Microprocessor Architecture:

Registers
• The micro processor as a programmable device
• Internal programming model
• How its memory space is addressed
The Microprocessor and Its •
•
Basic Architecture
Outline
 Before a program is written, the internal configuration of the µp
Architecture must be known.
 Program-visible architecture of the 8086 through Core 2 will be
detailed. Program visible architecture, e.g. registers .
 The adressing mode of this family of µps are described for
both the real and protected modes.
􀁑􀁑 Real Mode Addressing:
Real Mode Memory: 00000H-FFFFFH (the first 1MB of main memory).It
is present on all versions of the microprocessor.
􀁑􀁑 Protected Mode memory is available to 80286-Core 2.(80286, 16MB;
80386-Pentium, 4G; Pentium pro-core2 4G-64GB.
Programmer invisible registers to control and operate the protected
memory system.

The Programming Model

• 8086-80286 contain 16-bit internal architectures
• The 80386-Core2 contain 32-bit internal architecture
• P4 and Core2 also contain 64-bit registers when
operated in the 64-bit mode
• 8086-80286 fully upward compatible to the 80386-
Core2(Registers: AX…..SP)
• The programming model of 8086 through the Core2 :
program visible since its registers are used during
application programming and specified by the
instructions. (e.g. MOV CX, [BX+DI])
• Some registers can not!
– Program invisible , 80286 and above.
– Used to control and operate the protected memory system
 • REGISTER SIZE OVERRIDE BITS ACCESSED EXAMPLE
• 8 BITS B 7-0 MOV R9B, R10B
• 16 BITS W 15-0 MOV R10W, AX
• 32 BITS D 31-0 MOV R14D, R15D
• 64 BITS - 63-0 MOV R13, R12
….B is low-order byte……W low-order word

Some registers are general purpose regs., some registers are special purpose regs.

General Purpose Registers: The main functions are listed.

􀁐􀁐 RAX: Accumulator: Referenced as RAX, EAX, AX, AL or AH.
Used for mult, div, etc.
Used to hold an offset adress of a location in the memory system in the 80386 and above.
In the 64 bit P4 and Core 2 RAX holds a 64-bit offset address( 1T(terra) byte of memory can be
accessed.
􀁐􀁐 RBX: Base Index: Referenced as RBX, EBX, BX, BL or BH.
Used to adress memory data.
(for BX) Used to hold an offset adress of a location in the memory system.
􀁐􀁐 RCX: Count: Referenced as RCX, ECX, CX, CL or CH.
Used to hold the count for some instructions, shift, rotate, REP and LOOP.
Used to adress memory data.
􀁐􀁐 RDX: Data:Referenced as RDX, EDX, DX, DL or DH.
Used to hold a portion of the result for mult, of the operand for div.
Used to adress memory data.
􀁐􀁐 RBP: Base Pointer: Referenced as RBP, EBP, BP.
Points to memory location for memory data transfers.
􀁐􀁐 RDI: Destination Index:
Addresses destination string data for string instructions.
􀁐􀁐 RSI: Source Index:
Addresses source string data for string instructions.

Special Purpose Registers:EIP,ESP,EFLAGS,and

Special Purpose Registers:
segment regs. CS;DS;ES;SS;FS;GS EFLAGS Register (Counts for the entire 8086 and Pentium Microproc. familiy):
􀁐􀁐 RIP: Instruction Pointer:
Points to the next instruction in a code segment.
16-bits (IP) in real mode and 32-bits (EIP) in protected
mode.In the 64 bit mode, RIP contains 40 bit adress to The rightmost 5 flag bits and overflow change after many of the arithmetic
address 1Tbyte memory. and logic instructions execute. Data transfer and control instructions never
change the flags.
􀁐􀁐 RSP: Stack Pointer: 􀁑􀁑 C (Carry):
Holds the carry out after addition or the borrow after subtraction.
Used by the stack. Stack stores data through this Also indicates error conditions.
pointer.(covered later). SP is a16-bit register, ESP a 􀁑􀁑 P (Parity):
32-bit register. 0 for odd parity and 1 for even.(1110:odd parity ; 1111000:even parity)
􀁑􀁑 A (Auxiliary Carry):
􀁐􀁐 RFLAGS: 8086-80286 FLAG register, 80386 and Holds the half carry after addition or the borrow after subtraction between 3.
above->EFLAG in the 32-bit version bit and 4. bit of he result. Highly specialized flag used by DAA and DAS (to
adjust AL) instructions after BCD addition or subtraction.
Store conditions of the microprocessor and control its
operation.
 􀁑􀁑 Z (Zero):
1 if the result of an arithmetic or logic instruction is 0.
􀁑􀁑 S (Sign):
1 if the sign of the result of an arith. or logic instruction is negative.
􀁑􀁑 T (Trap):
Trap enable. The microprocessor interrupts the flow of instructions on
conditions indicated by the debug and control registers.
􀁑􀁑 I (Interrupt):
Controls the operation of the INTR (Interrupt request) input pin. If 1, interrupts
are enabled. Set by STI (set I flag) and CLI (clear I flag) instructions.
􀁑􀁑 D (Direction):
Selects with increment or decrement mode for the DI(destination index) and/or
SI registers during string instructions. If 1, registers are automatically
decremented. Set by STD(set direction) and CLD (clear direction) instructions.
􀁑􀁑 O (Overflow):
Set for addition and subtraction instructions. Overflow occurs when signed
numbers are added or subtracted.

80286 and up:

80486SX and up:
􀁑􀁑 IOPL (I/O privilege level):
􀁑􀁑 AC (Alignment Check):
It holds the privilege level for I/O devices. Used in the protected mode
Specialized instruction for the 80486SX. If a word or doubleword is
operation. 00 is the highest. adressed on a non word or non double word boundary this bit is
􀁑􀁑 NT (Nested Task): activated.
Indicates that the current task is nested within another task in protected Pentium and up:
Mode operation. This flag is set when the task is nested by software. 􀁑􀁑 VIF (Virtual Interrupt Flag):
80386 and up: Copy of the interrupt flag bit.
􀁑􀁑 RF (Resume): 􀁑􀁑 VIP (Virtual Interrupt Pending):
Used with debugging to control resumption of execution after the next Provides information about a virtual mode interrupt. This is used in
instr. multitasking environments to provides the system with VIF and
􀁑􀁑 VM (Virtual Mode): interrupt pending information.
The VM flag selects virtual mode operation in a protected mode 􀁑􀁑 ID (Identification):
operation. This allows multiple DOS memory partitions to coexist in the provides the system with information about the microprocessor such as
version number and manufacturer information
memory system.
 Real Mode Addressing
• Real mode:Only mode available to the 8086 and 8088.
Segment Registers:
􀁐􀁐 CS (Code Segment):
• Allow the processor to address only the first 1MB of
The code segment is a section of memory that holds code. The code segment memory (real memory).
reg. defines starting adress of the code segment. In real mode, this specifies • DOS requires real mode.
the start of a 64KB memory segment.
In protected mode, it selects a descriptor that defines the starting adress and • Segments and Offsets:
the length of a section of a memory. The code segment is limited to 64KB in the • Effective address = Segment address register’s content
8086-80286 and 4 GB in the 386 and above. x10H + an offset. (accessing a memory location in real
􀁐􀁐 DS (Data Segment):
Similar to the CS except this segment holds data.
mode)
􀁐􀁐 ES (Extra Segment): • A real mode segment of memory 64K in length.
Data segment used by some string instructions to hold destination data.
• Once the beginning address known, the ending adress is
􀁐􀁐 SS (Stack Segment):
Similar to the CS except this segment holds the stack. found by adding FFFFh.
ESP and EBP hold offsets into this segment.
􀁐􀁐 FS and GS: 80386 and up.

Effective address = Segment address register’s

contentx10H + an offset. (accessing a memory
location in real mode)
 Segments and Offsets
Syntax is usually given as seg_addr:offset, e.g. 1000:F000 in the previous
example to specify 1F000H.

The microp.has some rules that apply to segments whenever memory is

addressed:
Implicit combinations of segment registers and offsets are defined for memory
references.
For example, the code segment (CS) is always used with the instruction pointer
(IP for real mode or EIP for protected mode).
􀁑􀁑 CS:EIP: if CS=1400h and IP=1200H next instr in the location
14000h+1200h=15200h
􀁑􀁑 SS:ESP, SS:EBP: stack data referenced through ESP and EBP
If SS=2000h and BP=3000h then the memory location addressed 23000h.
􀁑􀁑 DS:EAX, DS:EBX, DS:ECX, DS:EDX, DS:EDI, DS:ESI
􀁑􀁑 ES:EDI
􀁑􀁑 FS and GS have no default.
(Table 2.3- 2-4 next page. )

Addressing Modes
 Introduction
• Efficient software development for the µps
familarity with addressig modes.
• Tha data adressing modes: register,
immediate , direct, register indirect, base-plus-
index, register relative,and base relative-plus-
index in the 8086-80286. The 80386 and
above also include a scaled-index mode. The
program memory addressing : relative, direct,
indirect .
• MOV inst. for data addressing modes: It
transfers data between registers or between
register and memory.
• Program memory addressing : jump
• Operation of the stack memory: Push and pop
Data Addressing Modes
• Cover the data addressing modes using the mov
instruction.
• Data movement instructions move data (bytes, words
and doublewords) between registers and between
registers and memory.

MOV AX , BX
• Copies the word content of the BX into AX.
MOV opcode (operation code)
BX source, AX destination (operands).
The source never changes but the destination changes.
• Only the movs (strings) instruction can have both
operands in memory.
• Most data transfer instructions do not change the
EFLAGS register.
DATA ADDRESSING MODES

Register addressing

Note: MOV really COPIES data from the source to destination register.

􀁑􀁑 Never mix an 16-bit register with a 32-bit, etc. For example:

mov eax, bx ; ERROR: NOT permitted.

􀁑􀁑 None of the mov instructions affect the EFLAGS register. Using a

segment to segment register MOV instruction is not allowed.
For example:
Mov cs, ds
􀁑􀁑 The code segment register may not be a destination register.
MOV CS, AX; causes problems
See the table 3.1 on the next page.
 MOV BX, CX Example 3.1

Example 3.1 and 3.3 (Register

Immediate addressing addressing mode needs 2
􀁑􀁑 It transfers a copy of the immediate data into a register or memory
location.
􀁑􀁑 The value of the operand is given as a constant in the instruction stream.
bytes, Immediate Addressing
For example:
mov eax, 0x13456H mode needs 3 bytes)

􀁑􀁑 In the 80386 through the p4 the immediate data can be a double word
data.
􀁑􀁑 Use b for binary, q for octal and nothing for decimal.
􀁑􀁑 ASCII data requires a set of apostrophes:mov eax, ‘A’ ;Moves ASCII
value 0x41H into eax. Immediate addressing examples:
MOV EAX, 12230000H MOV EAX,100B
MOV BL, 44 MOV RCX, 100H
MOV CL, 11001010B MOV ESI, 12
MOV AL, ‘A’
MOV ECX, 0
MOV SI, 0
MOV CH,100
Direct addressing: Direct addressing
Transfers data between memory location and al, • MOV AL, DATA1 ;Copies a byte from DATA1.
ax and eax. – 0000 DATA1 DB 10H
Usually encoded in 3 bytes, sometimes 4: MOV AL, DATA1

• MOV AL, [1234h] ; DS=1000H (effective • MOV DATA2, AX;Copies a word to DATA2.
addres=1000x10H+1234H=11234H • MOV HOME, EAX;
• MOV ES:[2000H],AL
• MOV RAX, WATER ; Copies 8 bytes from memory
location
;WATER into RAX.

MOV AL,[1234H] WHEN • Displacement:

• Displacement instructions are encoded with up
DS=1000H to 7 bytes (32 bit register and a 32 bit
displacement).
• Direct addressing (using al) requires 3 bytes to
encode while Displacement(using bx) requires
4. Some examples:
• MOV CL, DATA1 ;Copies a byte from DATA1.
• MOV EDI, SUM ;Copies a doubleword from SUM.
• MOV CH, [1000]
• MOV DATA7, BP
• MOV ES, DATA6
Register Indirect addressing:
• Offset stored in a register (bp,bx,dı,sı) is added to the segment
register*10h.
• Any register EXCEPT esp for the 80386 and up. MOV AX, [BX]
For eax, ebx, ecx, edx, edi and esi: The data segment is the default.
For ebp: The stack segment is the default.
• Use:
MOV CX, [BX]
MOV [BP], DL
MOV DI, [BH]
MOV [DI] [BX] ; not allowed
MOV AL, [EDX]
MOV RAX,[RDX]
MOV ECX, [EBX]
• Does [edi] address a byte, a word or a double-word?
MOV AL, [EDI] ; Clearly a byte-sized move.
Some versions of register indirect require special assembler directives
byte, word, or dword
MOV [EDI], 10H ;Ambiguous, assembler can’t size.
MOV BYTE PTR [EDI], 10H ;A byte transfer. (BYTE PTR, Word ptr,
DWORD PTR)

Base-Plus-Index addressing: Figure 3.8: MOV DX,[BX+DI]

Effective address computed as:
seg_base*10H + base + index. DS=0100H, BX=1000H, AND
Base registers: Holds starting location of an array.
􀁑􀁑 ebp (stack) DI=0010H
􀁑􀁑 ebx (data)
􀁑􀁑 Any 32-bit register except esp.
Index registers: Holds offset location.
􀁑􀁑 edi
􀁑􀁑 esi
􀁑􀁑 Any 32-bit register except esp.
mov dl, [eax+ebx] ;EAX as base, EBX as index.
mov ecx,[ebx+edi] ;Data segment copy.
mov ch, [ebp+esi] ;Stack segment copy.
Mov cx, [bx+di]
Mov ch, [bp+si] ; stack segment!!!
Mov [bp+di], ah
MOV [RSI+RBX],RAX
Register Relative addressing:
Effective address computed as: the data in segment are addressed by adding the
displacement to the contents of a base or an index register (see next page)
MOV AX,[BX+1000H] when
seg_base *10h+ base or index(bp,bx,dı,sı) + constant.
Same default segment rules apply with respect to ebp, ebx, edi and esi. Bp addresses the
stack segment and bx,dı,sı adress the data segment.
BX=0100H and DS=0200H
Table 3.7 page 94

MOV EDX, LIST[ESI+2] ;Both LIST and 2 are constants.

MOV EAX, [EBX+1000H] ;Data segment copy.
MOV EDX, LIST[ESI-2] ;Subtraction.
MOV LIST[SI+2], CL
MOV DI,[EAX+10H]
MOV ARRAY[EBX],EAX
MOV ARRAY[RBX], AL
MOV ARRAY[RCX],EAX
MOV ARRAY[SI],BL
Displacement constant is any 32-bit signed value (in the 80386 and above) .

Base Relative-Plus-Index
addressing: • Figure 3.12 : MOV AX, [BX+SI+100H]
Effective address computed as: DS=1000H
seg_base *10h+ base + index + constant.

Some EXAMPLES:
MOV LIST[EBP+ESI+4], DH ;Stack
segment copy.
MOV DH, [EBX+EDI+20H] ;Data segment
copy.
MOV AX, FILE[EBX+EDI] ;Constant is
FILE.
MOV EAX, FILE[EBX+ECX+2] ;32-bit
 addressing:
Designed to be used as a mechanism to Scaled-Index addressing:
address a two-dimensional array.
(Suppose that a file of many records
exists in a memory. Disp. Addresses the • It is unique to the 80386-Core2
file , the base reg. addresses a record, • Effective address computed as:
the index reg. Addresses an element of seg_base*10h + base + constant*index.
the record. )
• The scaling factor (constant) can 1x,2x,4x,8x
• Some examples:
mov eax, [ebx+4*ecx] ;Data segment DWORD
copy.
mov [eax+2*edi-100H], cx; copies cx into the DS
mem. Loc. addressed by eax+e*edi-100H
mov eax, array[4*ecx]; copies the DW content of
DS mem. loc. addressed by array+4*ecx

Direct Program Memory

Code Memory-Addressing Modes
Addressing
• Used in jmp and call instructions. • JMP [10000H]
• Three forms:
Direct, Relative, Indirect

Direct
• Absolute jump address is stored in the
instruction following the opcode.
• If a program jumps to memory location 10000h
for the next instruction, the adress 10000h is
stored following the opcode in the memory. • A direct jump is often called a far jump
because it can jump to any memory
location.
 Indirect Program Memory
Relative Program Memory • Addressing
Jump location is specified by a register.
Addressing • There are three forms:
Register:
ax, bx, cx, dx, sp, bp, di or si
• Relative means “relative to the IP”. Any register can be used: eax, ebx, ecx, edx, esp, ebp, edi or esi.
• A displacement is added to the IP register. (80386 and above)
• This constant is encoded into the instruction itself, as above. JMP BX; if bx=1000H the microp. Jumps to 1000H offset in the code
• Intrasegment jumps: segment.
• Short jumps use a 1-byte signed displacement. (+127, -128) Register Indirect:
• Near jumps use a 2-byte signed displacement. (+,- 32Kbytes) Any relative register [bp], [bx], [di], or [si]
• In the 80386 and above, the displacement can also be a 32-bit Register Relative:
value (+,- 2 Gbytes) Any relative register with a displacement
• The assembler usually computes the displacement and selects the • Some examples
appropriate form. JMP EAX ; Jump within the code seg. Jump to (CS*10h+eax)
JMP [EBX] ; Jump to the current code segment location addressed by
10000 eb ebx
10001 02 jmp [2] JMP [EDİ+2]
10002 JMP TABLE[bx] ; Jump table. It jumps to the code segment’ memory
location addressed by the content of the data segment memory
10003 location addressed by Table plus bx.
10004 JMP RDI (64 bit mode)

Figure 3.17 a) push bx b) pop

STACK MEMORY adressing modes cx
• The stack is used to hold temporary variables and stores return addresses for
procedures. A LIFO (Last-in, First-out) policy is used.

• push and pop instructions are used to manipulate it.(8086-286 word never bytes,
80386 word , doubleword))
call and ret also refer to the stack implicitly.
• There are six forms of the push and pop instructions.
Register, memory , immediate, segment register, flags, and all registers. The PUsH-
POP immediate and PUshA-POPa are not available in 8086/8088.
• Two registers maintain the stack, esp and ss.

• Push: High Order bits -> SS:[SP-1]

Low order bits->SS:[SP-2]
Sp=SP-2
• Pop: SS:[SP]->low order bits
SS:[SP+1]->high order bits
sp=SP+2
See figure 3.17 on page 103.
• Data may be pushed from any of the registers or segment registers.
Data may be popped into any register except cs.
Popf; removes a Word from the stack and places it into the flag
popfd ;Pop doubleword for stack to EFLAG.
pushfd ;Pushes EFLAG register.
pUsh ax,
pop ax
• Ex3-14:
pop cs; illegal MOV AX,1000H
push 1234H ;Pushes 1234H.
push word ptr [bx] ;Pushes word in data seg. MOV BX,2000H
pushad ;eax,ecx,edx,ebx,esp,ebp,esi,edi; (except segment registers)
pop eax ;Pops 4 bytes. MOV CX, 3000H
pushf; push flag reg. To the stack
pop bx; PUSH AX
push ds;
Push rsi PUSH BX
Pop rax
The pusha and popa instructions either push or pop all of the registers, PUSH CX
except the segment registers.
POP AX;3000H to AX
POP CX; 2000H to CX
POP BX; 1000 to BX

Intel Assembly
Arithmetic Operations:

Arithmetic, Logic and Addition

Subtraction
Multiplication

Control Instructions Division

Comparison
Negation
Increment
Decrement
Logic Operations:
AND
OR
XOR
NOT
shift
rotate
compare (test)
 z The following example uses register addition…
Arithmetic Operations
; a procedure that sums ax,bx,cx and dx the result is returned in ax
z Addition (8,16, and 32 bit), Increment, Add-with-carry
adds proc near
z Contents of the rightmost 8 bits of the FLAGS register and
(+Overflow) can change for arithmetic and logic instructions. add ax, bx
z Flags include: Z ,C, A, S ,P ,O add ax, cx
z Examples: add ax, dx
add al, bl ret
add cl, 44h adds endp
add cl, [bp] z In the following example , immediate addition is employed.
add [bx],al mov dl,12h
add [bx+di], dl add dl, 33h
add byte ptr [dı],3 z Memory to register addition
add al, ARRAY [esi] ;a procedure that sums data in locations numb and numb+1
Add rax,rbx Sums proc near
Add edx, [rax+rcx] Mov di, offset numb
Add bx, [eax+2ecx] Mov al,0
z The adressing modes include almost all those mentioned in Chap 3. Add al, [di]
The only types of addition not allowed are memory-to-memory and Add al, [di+1]
segment register. Ret
Sums endp

z Increment addition (INC): adds 1 to a register or the content of a

memory location, except a segment register. z Addition-with-carry: adds the bit in the carry flag to the
z The increment indirect memory data instructions require byte ptr, operand data. (Mainly appears in software that adds
word ptr or dword ptr. numbers that are wider than 16 bits or 32 bits)
z Examples: z It affects the flags after addition.
inc bl ; bl=bl+1 z Examples
inc sp ;sp=sp+1 adc al, ah ;al=al+ah+carry
inc byte ptr [bx] ; adds 1 to the byte contents of the data segment memory loc. adc cx, bx ; cx=cx+bx+carry
Addressed by bx adc edx, ebx ; edx=edx+ebx+carry
inc word ptr [si] Adc rbx,0
inc data1 adc dh, [bx]
inc byte ptr [edi] ;Adds 1 to any reg/mem except seg adc bx, [bp+2]
İnc rcx; adc ecx, [ebx] ;Adds register and data pointed by ebx + Carry flag.
z Increment is used to point to the next memory element in a byte-sized array
z ; a procedure that sums bx-ax and dx-cx; the result
of data only.
z For word-sized data it is better to use an add di, 2
; is returned in bx-ax (written for 8086-80286) page 161
z Increment inst. Do not affect the carry flag. Example:
Sum32 proc near
Mov di, offset numb add ax, cx
Mov al,0 adc bx, dx
Add al, [di] Ret
İnc di Sum32 endp
Add al, [di]
 32-bit Addition with 16-bit Arithmetic Operations
Subtraction, Decrement and Subtract-with-borrow.
Registers Subtraction:
z Forms of subtraction use any addressing mode with
8,16, and 32 bit data.
z Memory-to-memory and segment register subtractions
are not allowed.
z It affects the flag bits. (Z, c,a,s,p,o)
z Examples
sub eax, ebx ; eax=eax-ebx
sub ax,sp ; ax=ax-sp
sub dh, 6fh; dh=dh-6fh
sub [di], ch ; sub rdx, r8
sub ch, [bp];
Sub ecx, data1;
Sub rcx,16;
Sub ah, temp; sub di, temp[esi]

Decrement subtraction:
z It subtracts a 1 from a register or the contents of a
Register subtraction: memory location.
z Example: This example subtracts the 16-bit contents of z The decrement indirect memory data instructions require
registers cx and dx from the contents of register bx. byte ptr, word ptr or dword ptr.( e.g. dec byte ptr [si] )
sub bx,cx
z Examples
Dec bh; bh=bh-1
sub bx, dx Dec cx ; cx=cx-1
Immediate Subtraction: The micropr. allows Dec r14;
Dec edx;
immediate operands for subtraction. Dec byte ptr [di] ; data segment
z Example: Subtract a 44h from a 22h. Dec word ptr [bp]; stack segment
mov ch, 22h Dec dword ptr[ebx]
Dec qword ptr[rsi] ; dec numb
sub ch, 44h ; c=deh
Z=0
C=1
A=1
s=1
P=1
O=0
 Subtraction-with-borrow
z It functions as a regular subtraction, 32-bit Subtraction with 16-bit
except that the carry flag subtracts from
the difference. It is for subtractions that are registers
wider than16 bits in (8086-80286 )or 32
bits in 80386 and above .
sbb ah, al ; ah=ah-al-carry
sbb ax, bx
sbb cl,2; cl=cl-2-carry
sbb byte ptr [di],3
sbb ecx, ebx ;Subs registers - borrow.
Sbb rbp,8
Sbb al, [ebx+ecx]
Sbb [di], al
SUB AX,DI
Sbb di, [BP+2] SBB BX, SI

Multiplication and Division:

Comparison (cmp): Multiplication:
z A subtraction z performed on bytes, words or doublewords.
z Changes only the flag bits. Destination never changes. z Only the 80386 –P4 multiply 32 bit doublewords.
z Useful for checking the entire contents of a register or a z imul/idiv: Signed integer multiplication/division.
memory location against another value.
z It is normally followed by a conditional jump instruction, mul/div: Unsigned.
which tests the condition of the flag bits. z The product after a multiplication is always a double-
z Disallowed forms are comparison of memory –to width product.
memory and segment registers z C and O bits are cleared if most significant 8 bits of the
z Examples 16-bit product are zero
cmp al, 10H ; al-10 z al always holds the multiplicand (or ax or eax).
cmp ax, sp ; ax-sp Result is placed in ax (or dx and ax or edx or eax).
cmp [di],ch z mul bl;ax=al*bl (unsigned)
cmp cl, [bp] z imul bx;dx|ax=ax*bx (signed) dx gets the most
jae LABEL1 ;Jump if equal or above. significant byte.
jbe LABEL2 ;Jump if equal or below.
z imul cx, dx, 12H ;Special, cx=dx*12H (signed only)
z mul ecx ;edx|eax=eax*ecx
z imul byte ptr[bx]
 8-bit multiplication 16-bit multiplication
z In an 8-bit multiplication, the multiplicand
must always be in the AL register. z The AX register contains the multiplicand.
z The multiplier can be any 8-bit register or z The 32-bit product is written to the DX –
memory. AX registers.
z The result is written to the AX register. z DX register contains high-order 16 bits, AX
z Example: dx=blxcl register contains 16 low-order bits
mov bl, 5
mov cl,10, z MUL CX; IMUL DI;MUL WORD PTR[SI]
mov al, cl
mul bl
mov dx,ax

Special Immediate 16 Bit Multplication

z 80186-Core2 have a special multiplication 32-bit Multiplication

instruction. z 32-bit multiplication is possible on 80386
z Immediate multiplication should be signed and higher versions.
multiplication. z IMUL and MUL instr. can be used with 32
z The instr. contains 3 operands. bit registers. ,The EAX register is
z The first operand is a 16-bit dest. register, multiplied by the specified operand
the second is a 16-bit register or memory z The high-order 32-bit of the product is
location, the third is an 8 or 16 bit written to the EDX low-order 32-bit EAX
immediate data. register.
z IMUL CX,DX, 12H z MUL ECX, IMUL EDI,MUL DWORD
z IMUL BX, NUMBER, 1000H PTR[ESI]
 64-bit Multiplication Division:
z İdiv for signed integers, div for unsigned integers
z The dividend (bölünen) is always a double –width of divider
z Multiply the 64-bit register or memory data z There is no immediate division

with the RAX register. z None of the flags change predictably for a division
z Division by zero and overflow generate errors.Overflow occurs when
a small number divides a large dividend.
z The result is written to the RDX and RAX
z Examples:
registers with high-order bits in the RDX div cl; ah|al=ax/cl, unsigned quotient (bölüm) in al, remainder in
ah. (8-bit division)
register. idiv cx ;dx|ax=(dx|ax)/cx (16-bit signed division. dx-ax 32-bit dividend.
quotient in ax, remainder in dx)
z Signed and unsigned numbers can be div byte pointer [bp](8-bit unsigned division)
multiplied
z MUL RCX, IMUL RDI, MUL QWORD
PTR[RSI]

8-bit Division 8-bit Division

z An 8-bit division uses the AX register to z The dividend must be convered to a 16-bit
store the dividend is divided by the wide in AX.
contents of any 8-bit register or memory
z For unsigned numbers, the most
location.
significant bits are cleared to zero.
z The quotİent moves into AL, the remainder
z For signed numbers, the least significant
moves into AH
bits are sign extended into the most
z For signed division, the quotient is significant high bits.
negative or positive. The sign of remainder
z The CBW (convert byte to word)
assumes the sign of dividend.
performs conversion of 8 bit signned
number in AL to 16-bit signed number in
AX
 16-bit Division 32 Bit Division
z The 80386 through the Pentium 4 perfrom
z DX-AX, 32-bit dividend is divided by 16-bit 32 bit division on signed and unsigned
number. numbers
z The quotient appears in AX and the • EDX - EAX is divided by the register or
remainder appears in DX after a 16-bit memory data.
division. • The 32-bit quotient is written to the EAX
z 16-bit signed number in AX converted into register. The remainder 32 bits are written to
32 bit signed number by using CWD. the EDX register. DIV ECX, IDIV DATA4,
z DIV CX, IDIV DI, DIV WORD PTR[SI] DIV DWORD PTR[ESI]
z Example:
Mov ax, -100 z The CDQ is used before a signed division
Mov cx, 9 to convert the 32bit contents of EAX into a
Cwd; sign-extend (cbw for “convert word to doubleword)
İdiv cx 64-bit signed number in EDX-EAX

LOGIC INSRUCTIONS
Allow bits to be set, cleared and complemented.

64-Bit Division Commonly used to control I/O devices.

Logic operations always clear the carry and overflow flags, changes
PF, SF, ZF.
z The Pentium 4 performs 64 bit division on AND:

signed and unsigned numbers.

z RDX:RAX hold dividend.
z After the division, the quotient moves into
RAX, The remainder moves into RDX. z Commonly used with a MASK to clear bits:
XXXX XXXX Operand
0000 1111 Mask
z DIV RCX, IDIV DATA4, 0000 XXXX Result
z Examples: and al, bl ;al=al AND bl
DIV QWORD PTR[RSI] and cx,dx ;
and cl, 33H
And ecx,edi
; and di, 4fffh ; and esi, 34h; and rax,1
and ax, [di]
and array[si], al; and [eax],cl
z The and inst. Uses any addressing modes except memory-memory
and segment register adressing.
OR: XOR Logic Operations
z Performs logical addition

XOR: Commonly used with a MASK to complement bits:

XXXX XXXX Operand
z The OR operation sets any bit 0000 1111 Mask
XXXX XXXX Operand
XXXX X’X’X’X’ Result
0000 1111 Mask
XXXX 1111 Result
XOR AH, CH ;ah=ah XOR ch
z examples
XOR SI, BX; XOR EBX,EDI; XOR RAX,RBX
or eax, 10 ; eax=eax OR 0000000AH XOR AH, 0EEH
OR AH,BL; OR SI, DX XOR DI, 00DDH; XOR ESI,100; XOR R12, 20
XOR DX, [SI]; XOR DATES[DI+2], AL
OR EAX, EBX; OR R9,R10
z A common use for XOR is to clear a register zero. (XOR CH,CH inst. Of
OR SP, 990DH ; Or ebp, 10 mov ch,00h)
Or rbp, 1000h; OR DX, [BX] z Example: set bits 9 and 10 of cx, clear bits 0 and 1 of cx, and inverts bit 12
of cx.
OR DATES[DI+2], AL or cx, 0600h ;set bits 9 and 10
z The OR instruction uses any addressing modes except and cx, 0ffch; clear bits 0 and 1
segment register addressing and memory-to-memory. xor cx, 1000h; invert bit 12

TEST: Operates like the AND but doesn't affect the destination. It affect
the flag register. It uses the same addressing modes as the AND Shift and rotate instructions manipulate binary
instruction. numbers at the binary bit level . They are used
Sets the Z flag to the complement of the bit being tested: to shift or rotate any memory data or register.
test al, 4;Tests bit 2 in al – 00000100. Bit=1 z=0 They are used control I/o devices.
jz LABEL ;Jump to LABEL if bit 2 is zero.
jz (jump if zero) and jnz (jump if not zero) Shift:
TEST DL, DH, DL ANDED WİTH DH z Moves numbers to the left or right within a
TEST CX, BX; CX ANDED WİTH BX register or memory location.
TEST EDX,ECX
TEST RDX,R15 z They also perform simple arithmetic such as
TEST AH, 4 multiplication and divison.
TEST EAX,256
NOT (logical one's complement)
NEG (arithmetic two's complement - sign of number inverted)
not ebx,
neg TEMP
Neg ax
Not byte ptr [bx]
Not rax
Neg ecx
z Not and neg can use any addressing mode except segment register
addressing!!!
z The arithmetic and logical left shifts are z Logical shifts function with unsigned numbers, and arithmetic shifts
function with signed numbers. Logical shifts multiply or divide
identical. unsigned numbers. Arithmetic shifts multiply or divide signed
numbers.
z The arithmetic and logical right shifts are z Example shift instructions:
different. (Logical shifts insert 0, arithmetic SHL EAX, 1 ; eax is logically shifted left 1 bit pos.
right shifts insert sign bit.) SHR BX, 12;
SHL AX,1
SHR ECX, 10
SAL DATA1, CL; CL HOLDS THE SHIFT COUNT
SAR SI, 2
SAL DATA1,CL
SHL RAX, CL
z Updates cf,of,pf,zf and sf, and leaves af undefined
z Example
Shl dx,14
Or
Mov cl,14
Shl dx, cl

z Example 5.31
; multiply ax by 10 Rotate:
SHL AX,1 z Rotates bits from one end to the other or
through the carry flag.
MOV BX,AX
z Commonly used to operate on numbers
SHL AX, 2 wider than 32-bits in the 386-p4 or wider
ADD AX, BX than 16 bits in the 8086-80286.
z A rotate count can be immediate or
;multiply ax by 5 located in register CL.
MOV BX, AX z Figure 5.10 page page 185
SHL AX,2
ADD AX,BX
 ROL SI, 14 ;si rotated left 14 places.
RCL BL, 6; bl rotates left through carry 6 places.
ROL ECX, 18
ROL RDX, 40
RCR BL, CL; bl rotated right cl places through carry.
RCL DX, 1 ;Rotate carry bit from previous rcl in dx.
ROR WORD PTR [BP], 2; word contents of the memory location addressed by bp
in the stack segment rotated right 2 places.
z Affects only cf and of

Program Control Instructions Unconditional Jumps

z Transfer program execution from
one part of memory to another. zThe JMP instruc. has the general form:
z Conditional transfer, unconditional JMP target
transfer, and iteration control. z Target can be short or near, or far
z Direct or indirect
z They do not affect the flags. z Direct jumps are 2 bytes long with the SHORT
label, 3 bytes long with the NEAR label and 5
z Jumps, Calls, Returns, Interrupts bytes long with the FAR label
z e.g. JMP THERE
3 byte instr. if THERE is in the same segment
5 byte instr. if THERE is in the different segment
Short jump: PC-relative using two bytes if Near jump:
the label lies within +127/-128 bytes of the Within segment (+/- 32K).
JMP. jmp near eax ;Jump to address given by eax.
z (PC-relative: constant added to eip). jmp [eax] ;Jump to address given by [eax].
NEXT: add ax, bx Far jump:
2 bytes give the offset and two bytes give a new
jmp short NEXT segment address.
It executes in the same amount of time as jmp far LABEL ;Jump to address given by LABEL.
JMP NEXT; But takes up one less byte in
memory.

z Conditional Jumps:
z EB Disp z Let the microproc. make an execution decision based on
z E9 Displow DispHigh some prescribed condition. If the condition is satisfied
proccesor makes the jump
z EA Iplow IpHigh Cslow CsHigh z Test flag bits S, Z, C, P and O.
z The general form
Jx short_label
where x a modifier.The target (short_label) must be no
more than -128 or 127 bytes away from the instr.
z Cont. transfer inst.s occupy 2 bytes in memory. The First
byte holds opcode and the second one holds the relative
displacement.
z For unsigned numbers: z For either signed or unsigned:
ja ;Jump if above (Z=0 and C=0) jne ;Jump if != (Z=0)
jbe ;Jump if below or equal (Z=1 or C=1) je or jz ;Jump if ==; or jump if zero (Z=1)
z For signed numbers jc ;Jump if carry set (C=1)
jl ;Jump if < (S not=O)
jge ;Jump if >= (S=O) Test cx instead of flags:
jcxz ;Jump if cx==0
jecxz ;Jump if ecx==0

Iteration Control Instructions loop LABEL ;Jump if ecx != 0

Decrement ecx
z These are conditional transfers used to set
up repetitive loops. If ecx != 0, jump to label
z The count register (CX) is the counter for else fall through.
loops. Example:
z Each of them decrements cx by 1, then MOV cx, 100
makes a jump/no-jump decision based on the
result. Start:……
LOOP Instruction: Loop start ; if cx is not zero , jump to
z Loop until count complete ; start otherwise , continue
Combination of decrement ecx and jnz ; here
conditional jump.
 
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