0% found this document useful (0 votes)

19 views816 pages

Lib Guide

Uploaded by

mohamedshehabeldin79

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

19 views816 pages

Lib Guide

Uploaded by

mohamedshehabeldin79

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 816

Libraries Guide Xilinx Unified Libraries

Selection Guide

Design Elements (ACC1 to BYPOSC)

Design Elements (CAPTURE_VIRTEX to

DECODE64)

Design Elements (F5MAP to FTSRLE)

Design Elements (GCLK to KEEPER)

Design Elements (LD to NOR16)

Design Elements (OAND2 to OXOR2)

Design Elements (PULLDOWN to

ROM32X1)

Design Elements (SOP3 to XORCY_L)

Design Elements (X74_42 to X74_521)

Attributes, Constraints, and Carry

Logic

Libraries Guide, Release 1.5 — Printed in U.S.A.

Libraries Guide, Release 1.5

The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE, XACT, XILINX, XC2064,
XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

All XC-prefix product designations, Alliance Series, AllianceCORE, BITA, CLC, Configurable Logic Cell, Dual Block, EZTag, FastCLK,
FastCONNECT, FastFLASH, FastMap, Foundation, HardWire, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroVia, Plus Logic,
PLUSASM, Plustran, P+, PowerGuide, PowerMaze, SelectI/O, Select-RAM, Select-RAM+, Smartguide, SmartSearch, Smartspec, Spartan,
TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex, WebLINX, XABEL, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-
Floorplanner, XACT-Performance, XAM, XAPP, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, Xilinx Foundation Series, XPP, XSI, and
ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array Company are service marks of
Xilinx, Inc.
All other trademarks are the property of their respective owners.
Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any
license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in
order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any
circuitry described herein other than circuitry entirely embodied in its products. Xilinx, Inc. devices and products are protected under one or more
of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418;
4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390;
5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704;
5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153;
5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377;
5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,455,525; 5,466,117;
5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196;
5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124;
5,517,135; 5,521,835; 5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322; 5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018;
5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751; 5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528; 5,563,529; 5,563,827;
5,565,792; 5,566,123; 5,570,051; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199; 5,581,738; 5,583,450; 5,583,452; 5,592,105;
5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597; 5,608,342; 5,610,536; 5,610,790; 5,610,829; 5,612,633; 5,617,021;
5,617,041; 5,617,327; 5,617,573; 5,623,387; 5,627,480; 5,629,637; 5,629,886; 5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106;
5,642,058; 5,646,545; 5,646,547; 5,646,564; 5,646,903; 5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,656,950;
5,657,290; 5,659,484; 5,661,660; 5,661,685; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270; 5,675,589; 5,677,638;
5,682,107; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,056; 5,724,276; 5,694,399; 5,696,454; 5,701,091; 5,701,441;
5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,715,197; 5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584; Re.
34,363, Re. 34,444, and Re. 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products
described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors
contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or
correctness of any engineering or software support or assistance provided to a user.
Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the
written consent of the appropriate Xilinx officer is prohibited.
Copyright 1991-1998 Xilinx, Inc. All Rights Reserved.

Xilinx Development System

Preface

About This Manual

This manual describes Xilinx’s Unified Libraries and the attributes/constraints that
can be used with the components.
Before using this manual, you should be familiar with the operations that are common
to all Xilinx software tools: how to bring up the system, select a tool for use, specify
operations, and manage design data. These topics are covered in the Quick Start Guide.
You must consult The Programmable Logic Data Book for device-specific information on
Xilinx device characteristics, including readback, boundary scan, configuration,
length count, and debugging. The Programmable Logic Data Book is available in hard
copy and on the Xilinx web site (http://www.xilinx.com). See http://
www.xilinx.com/partinfo/databook.htm for the current version of this book.
For specific design issues or problems, use the Answers Search function on the Web
(http://www.xilinx.com/support/searchtd.htm) to access the following.
• Answers Database: current listing of solution records for the Xilinx software tools
• Applications Notes: descriptions of device-specific design techniques and
approaches
• Data Sheets: pages from The Programmable Logic Data Book
• XCELL Journal: quarterly journals for Xilinx programmable logic users
• Expert Journals: the latest news, design tips, and patch information on the Xilinx
design environment
If you cannot access the Web, you can install and access the Answers book with the
DynaText online browser in the same manner as the Xilinx book collection. The
Answers book includes information in the Answers Database at the time of this
release.

Manual Contents
Online Manual
If you are viewing this manual online, it is divided into twelve chapters.
• Chapter 1, “Xilinx Unified Libraries”
• Chapter 2, “Selection Guide”
• Chapter 3, “Design Elements (ACC1 to BYPOSC)”
• Chapter 4, “Design Elements (CAPTURE_VIRTEX to DECODE64)”

Libraries Guide, Release M1.5 — i

Libraries Guide, Release M1.5

• Chapter 5, “Design Elements (F5MAP to FTSRLE)”

• Chapter 6, “Design Elements (GCLK to KEEPER)”
• Chapter 7, “Design Elements (LD to NOR16)”
• Chapter 8, “Design Elements (OAND2 to OXOR2)”
• Chapter 9, “Design Elements (PULLDOWN to ROM32X1)”
• Chapter 10, “Design Elements (SOP3 to XORCY_L)”
• Chapter 11, “Design Elements (X74_42 to X74_521)”
• Chapter 12, “Attributes, Constraints, and Carry Logic”
Chapter 1, ”Xilinx Unified Libraries,” discusses the unified libraries, applicable device
architectures for each library, contents of the other chapters, general naming conven-
tions, and performance issues.
Chapter 2, “Selection Guide,” describes then lists design elements by function that are
explained in detail in the “Design Elements” chapters.
Chapters 3 through 11, “Design Elements,” provide a graphic symbol, functional
description, primitive versus macro table, truth table (when applicable), topology
(when applicable), and schematics for macros of the design elements.
Chapter 12, “Attributes, Constraints, and Carry Logic,” provides information on all
attributes, logical constraints, placement and timing constraints, relationally placed
macros (RPMs), and carry logic.

ii Xilinx Development System

Conventions

Typographical
This manual uses the following conventions. An example illustrates each convention.
• Courier font indicates messages, prompts, and program files that the system
displays.
speed grade: -100
• Courier bold indicates literal commands that you enter in a syntactical state-
ment.
rpt_del_net=
Courier bold also indicates commands that you select from a menu.
File → Open
• Italic font denotes the following items.
• Variables in a syntax statement for which you must supply values
edif2ngd design_name
• References to other manuals
See the Development System Reference Guide for more information.
• Emphasis in text
If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not
connected.
• Square brackets “[ ]” indicate an optional entry or parameter. However, in bus
specifications, such as bus [7:0], they are required.
edif2ngd [option_name] design_name
• Braces “{ }” enclose a list of items from which you choose one or more.
lowpwr = {on | off}
• A vertical bar “|” separates items in a list of choices.
symbol editor_name [bus|pins]
• A vertical ellipsis indicates repetitive material that has been omitted.
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.

Libraries Guide, Release M1.5 — iii

Libraries Guide, Release M1.5

• A horizontal ellipsis “. . .” indicates that an item can be repeated one or more

times.
allow block block_name loc1 loc2 ... locn;

Online Document
Xilinx has created several conventions for use within the DynaText online docu-
ments.
• Red-underlined text indicates an interbook link, which is a cross-reference to
another book. Click on the red-underlined text to open the specified cross-refer-
ence.
• Blue-underlined text indicates an intrabook link, which is a cross-reference within
a book. Click on the blue-underlined text to open the specified cross-reference.
• There are several types of icons.
Iconized figures are identified by the figure icon.

Iconized tables are identified by the table icon.

The Copyright icon displays in the upper-left hand corner on the first page of
every Xilinx online document.

The DynaText footnote icon displays next to the footnoted text.

Double-click on these icons to display figures, tables, copyright information, or

footnotes in a separate window.
• Inline figures display within the text of a document. You can display these figures
in a separate window by clicking on the figure.

iv Xilinx Development System

Contents

Preface
About This Manual ............................................................................................................... i
Manual Contents .................................................................................................................. i
Online Manual................................................................................................................. i
Conventions
Typographical....................................................................................................................... iii
Online Document ................................................................................................................. iv
Chapter 1 Xilinx Unified Libraries
Overview .............................................................................................................................. 1–1
Applicable Architectures....................................................................................................... 1–2
XC3000 Library ............................................................................................................... 1–2
XC4000E Library............................................................................................................. 1–2
XC4000X Library............................................................................................................. 1–2
XC4000 References........................................................................................................ 1–2
XC5200 Library ............................................................................................................... 1–2
XC9000 Library ............................................................................................................... 1–2
Spartan Library ............................................................................................................... 1–2
SpartanXL Library ........................................................................................................... 1–3
Spartans and Spartan Series References ...................................................................... 1–3
Virtex Library................................................................................................................... 1–3
Selection Guide.................................................................................................................... 1–3
Design Elements .................................................................................................................. 1–3
Schematic Examples............................................................................................................ 1–3
Naming Conventions............................................................................................................ 1–4
Attributes, Constraints, and Carry Logic .............................................................................. 1–4
Flip-Flop, Counter, and Register Performance .................................................................... 1–5
Chapter 2 Selection Guide
CLB Count............................................................................................................................ 2–1
Relationally Placed Macros.................................................................................................. 2–10
Functional Categories .......................................................................................................... 2–12
Arithmetic Functions ....................................................................................................... 2–13
Buffers............................................................................................................................. 2–14
Comparators ................................................................................................................... 2–16
Counters ......................................................................................................................... 2–17
Data Registers ................................................................................................................ 2–22
Decoders......................................................................................................................... 2–22
Edge Decoders ............................................................................................................... 2–23
Encoders......................................................................................................................... 2–24
Flip-Flops ........................................................................................................................ 2–24

Libraries Guide, M1.5 Release — v

Libraries Guide, M1.5 Release

General ........................................................................................................................... 2–31

Input/Output Flip-Flops ................................................................................................... 2–35
Input/Output Functions.................................................................................................... 2–39
Input Latches .................................................................................................................. 2–41
Latches ........................................................................................................................... 2–43
Logic Primitives............................................................................................................... 2–45
Map Elements ................................................................................................................. 2–48
Memory Elements ........................................................................................................... 2–48
Multiplexers..................................................................................................................... 2–52
Shift Registers................................................................................................................. 2–55
Shifters............................................................................................................................ 2–57
Chapter 3 Design Elements (ACC1 to BYPOSC)
ACC1.................................................................................................................................... 3-2
1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and
Synchronous Reset......................................................................................................... 3-2
ACC4, 8, 16.......................................................................................................................... 3-4
4-, 8-, 16-Bit Loadable Cascadable Accumulators with Carry-In, Carry-Out,
and Synchronous Reset.................................................................................................. 3-4
ACLK.................................................................................................................................... 3-13
Alternate Clock Buffer ..................................................................................................... 3-13
ADD1.................................................................................................................................... 3-14
1-Bit Full Adder with Carry-In and Carry-Out .................................................................. 3-14
ADD4, 8, 16.......................................................................................................................... 3-15
4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and Overflow............... 3-15
ADSU1 ................................................................................................................................. 3-24
1-Bit Cascadable Adder/Subtracter with Carry-In and Carry-Out ................................... 3-24
ADSU4, 8, 16 ....................................................................................................................... 3-26
4-, 8-, 16-Bit Cascadable Adders/Subtracters with Carry-In, Carry-Out, and Overflow .. 3-26
AND2-9 ................................................................................................................................ 3-35
2- to 9-Input AND Gates with Inverted and Non-Inverted Inputs .................................... 3-35
AND12, 16............................................................................................................................ 3-39
12- and 16-Input AND Gates with Non-Inverted Inputs .................................................. 3-39
BRLSHFT4, 8....................................................................................................................... 3-43
4-, 8-Bit Barrel Shifters.................................................................................................... 3-43
BSCAN................................................................................................................................. 3-45
Boundary Scan Logic Control Circuit .............................................................................. 3-45
BSCAN_VIRTEX.................................................................................................................. 3-46
Virtex Boundary Scan Logic Control Circuit.................................................................... 3-46
BUF ...................................................................................................................................... 3-47
General-Purpose Buffer ................................................................................................. 3-47
BUF4, 8, 16 .......................................................................................................................... 3-48
General-Purpose Buffers ............................................................................................... 3-48
BUFCF ................................................................................................................................. 3-49
Fast Connect Buffer ........................................................................................................ 3-49
BUFE, 4, 8, 16...................................................................................................................... 3-50
Internal 3-State Buffers with Active High Enable ............................................................ 3-50
BUFFCLK............................................................................................................................. 3-52
Global Fast Clock Buffer ................................................................................................. 3-52
BUFG ................................................................................................................................... 3-53
Global Clock Buffer ......................................................................................................... 3-53
BUFGDLL............................................................................................................................. 3-54
Clock Delay Locked Loop Buffer..................................................................................... 3-54

vi Xilinx Development System

xiv Xilinx Development System

Contents

OFDEXI_1............................................................................................................................ 8-23
D Flip-Flop with Active-High Enable Output Buffer, Inverted Clock, and
Clock Enable (Asynchronous Preset) ............................................................................. 8-23
OFDI..................................................................................................................................... 8-24
Output D Flip-Flop (Asynchronous Preset) ..................................................................... 8-24
OFDI_1................................................................................................................................. 8-25
Output D Flip-Flop with Inverted Clock (Asynchronous Preset)...................................... 8-25
OFDT, 4, 8, 16 ..................................................................................................................... 8-26
Single and Multiple D Flip-Flops with Active-Low 3-State Output Enable Buffers .......... 8-26
OFDT_1 ............................................................................................................................... 8-28
D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock .......................... 8-28
OFDTI .................................................................................................................................. 8-29
D Flip-Flop with Active-Low 3-State Output Buffer (Asynchronous Preset).................... 8-29
OFDTI_1 .............................................................................................................................. 8-30
D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock
(Asynchronous Preset) ................................................................................................... 8-30
OFDTX, 4, 8, 16 ................................................................................................................... 8-31
Single and Multiple D Flip-Flops with Active-Low 3-State Output Buffers and
Clock Enable................................................................................................................... 8-31
OFDTX_1 ............................................................................................................................. 8-33
D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock, and
Clock Enable................................................................................................................... 8-33
OFDTXI ................................................................................................................................ 8-34
D Flip-Flop with Active-Low 3-State Output Buffer and Clock Enable
(Asynchronous Preset) ................................................................................................... 8-34
OFDTXI_1 ............................................................................................................................ 8-35
D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock, and
Clock Enable (Asynchronous Preset) ............................................................................. 8-35
OFDX, 4, 8, 16 ..................................................................................................................... 8-36
Single- and Multiple-Output D Flip-Flops with Clock Enable .......................................... 8-36
OFDX_1 ............................................................................................................................... 8-38
Output D Flip-Flop with Inverted Clock and Clock Enable .............................................. 8-38
OFDXI .................................................................................................................................. 8-39
Output D Flip-Flop with Clock Enable (Asynchronous Preset) ....................................... 8-39
OFDXI_1 .............................................................................................................................. 8-40
Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset) ........ 8-40
OMUX2 ................................................................................................................................ 8-41
2-to-1 Multiplexer ............................................................................................................ 8-41
ONAND2 .............................................................................................................................. 8-42
2-Input NAND Gate with Invertible Inputs ....................................................................... 8-42
ONOR2 ................................................................................................................................ 8-43
2-Input NOR Gate with Invertible Inputs ......................................................................... 8-43
OOR2 ................................................................................................................................... 8-44
2-Input OR Gate with Invertible Inputs............................................................................ 8-44
OPAD, 4, 8, 16 ..................................................................................................................... 8-45
Single- and Multiple-Output Pads ................................................................................... 8-45
OR2-9................................................................................................................................... 8-46
2- to 9-Input OR Gates with Inverted and Non-Inverted Inputs....................................... 8-46
OR12, 16.............................................................................................................................. 8-49
12- and 16-Input OR Gates with Non-Inverted Inputs..................................................... 8-49
OSC ..................................................................................................................................... 8-51
Crystal Oscillator Amplifier.............................................................................................. 8-51
OSC4 ................................................................................................................................... 8-52
Internal 5-Frequency Clock-Signal Generator ................................................................ 8-52

Libraries Guide, M1.5 Release xv

Libraries Guide, M1.5 Release

OSC5 ................................................................................................................................... 8-53

Internal Multiple-Frequency Clock-Signal Generator ...................................................... 8-53
OSC52 ................................................................................................................................. 8-54
Internal Multiple-Frequency Clock-Signal Generator ...................................................... 8-54
OXNOR2 .............................................................................................................................. 8-55
2-Input Exclusive-NOR Gate with Invertible Inputs......................................................... 8-55
OXOR2................................................................................................................................. 8-56
2-Input Exclusive-OR Gate with Invertible Inputs ........................................................... 8-56
Chapter 9 Design Elements (PULLDOWN to ROM32X1)
PULLDOWN......................................................................................................................... 9-2
Resistor to GND for Input Pads ...................................................................................... 9-2
PULLUP ............................................................................................................................... 9-3
Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs ............................... 9-3
RAM16X1............................................................................................................................. 9-4
16-Deep by 1-Wide Static RAM ...................................................................................... 9-4
RAM16X1D .......................................................................................................................... 9-5
16-Deep by 1-Wide Static Dual Port Synchronous RAM ................................................ 9-5
RAM16X1D_1 ...................................................................................................................... 9-6
16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock...... 9-6
RAM16X1S .......................................................................................................................... 9-7
16-Deep by 1-Wide Static Synchronous RAM ................................................................ 9-7
RAM16X1S_1 ...................................................................................................................... 9-8
16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock...................... 9-8
RAM16X2............................................................................................................................. 9-9
16-Deep by 2-Wide Static RAM ...................................................................................... 9-9
RAM16X2D .......................................................................................................................... 9-10
16-Deep by 2-Wide Static Dual Port Synchronous RAM ................................................ 9-10
RAM16X2S .......................................................................................................................... 9-11
16-Deep by 2-Wide Static Synchronous RAM ................................................................ 9-11
RAM16X4............................................................................................................................. 9-12
16-Deep by 4-Wide Static RAM ...................................................................................... 9-12
RAM16X4D .......................................................................................................................... 9-14
16-Deep by 4-Wide Static Dual Port Synchronous RAM ................................................ 9-14
RAM16X4S .......................................................................................................................... 9-15
16-Deep by 4-Wide Static Synchronous RAM ................................................................ 9-15
RAM16X8............................................................................................................................. 9-16
16-Deep by 8-Wide Static RAM ...................................................................................... 9-16
RAM16X8D .......................................................................................................................... 9-18
16-Deep by 8-Wide Static Dual Port Synchronous RAM ................................................ 9-18
RAM16X8S .......................................................................................................................... 9-20
16-Deep by 8-Wide Static Synchronous RAM ................................................................ 9-20
RAM32X1............................................................................................................................. 9-22
32-Deep by 1-Wide Static RAM ...................................................................................... 9-22
RAM32X1S .......................................................................................................................... 9-23
32-Deep by 1-Wide Static Synchronous RAM ................................................................ 9-23
RAM32X1S_1 ...................................................................................................................... 9-24
32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock...................... 9-24
RAM32X2............................................................................................................................. 9-25
32-Deep by 2-Wide Static RAM ...................................................................................... 9-25
RAM32X2S .......................................................................................................................... 9-26
32-Deep by 2-Wide Static Synchronous RAM ................................................................ 9-26
RAM32X4............................................................................................................................. 9-27
32-Deep by 4-Wide Static RAM ...................................................................................... 9-27

xvi Xilinx Development System

Contents

Chapter 1

Xilinx Unified Libraries

This chapter describes the Unified Libraries and the applicable device architectures
for each library. It also briefly discusses the contents of the other chapters, the general
naming conventions, and performance issues.
This chapter consists of the following major sections.
• “Overview”
• “Applicable Architectures”
• “Selection Guide”
• “Design Elements”
• “Schematic Examples”
• “Naming Conventions”
• “Attributes, Constraints, and Carry Logic”
• “Flip-Flop, Counter, and Register Performance”

Overview
Xilinx maintains software libraries with thousands of functional design elements
(primitives and macros) for different device architectures. New functional elements
are assembled with each release of development system software. The catalog of
design elements is known as the “Unified Libraries.” Elements in these libraries are
common to all Xilinx device architectures. This “unified” approach means that you
can use your circuit design created with “unified” library elements across all current
Xilinx device architectures that recognize the element you are using.
Elements that exist in multiple architectures look and function the same, but their
implementations might differ to make them more efficient for a particular architec-
ture. A separate library still exists for each architecture (or architectural group) and
common symbols are duplicated in each one, which is necessary for simulation (espe-
cially board level) where timing depends on a particular architecture.
If you have active designs that were created with former Xilinx library primitives or
macros, you may need to change references to the design elements that you were
using to reflect the Unified Libraries’ elements.
The Libraries Guide describes the primitive and macro logic elements available in the
Unified Libraries for XC3000A, XC3000L, XC3100A, XC3100L, XC4000E, XC4000L,
XC4000EX, XC4000XL, XC4000XV, XC400XLA, XC5200, XC9500, XC9500XL, Spartan,
SpartanXL, and Virtex architectures. Common logic functions can be implemented
with these elements and more complex functions can be built by combining macros
and primitives. Several hundred design elements (primitives and macros) are avail-

Libraries Guide, Release M1.5 — 1-1

Libraries Guide, Release M1.5

able across multiple device architectures, providing a common base for program-
mable logic designs.
This libraries guide provides a functional selection guide, describes the design
elements, and addresses attributes, constraints, and carry logic.

Applicable Architectures
Design elements for the XC3000, XC4000E, XC4000X, XC5200, XC9000, Spartan, Spar-
tanXL, and Virtex libraries are included in the Xilinx Unified Libraries. Each library
supports specific device architectures. For detailed information on the architectural
families referenced below and the devices in each, refer to the current Programmable
Logic Data Book. (For Virtex device information, refer to the Xilinx web site, http://
www.xilinx.com.)

XC3000 Library
Information appearing under the title of XC3000 pertains to the XC3000A, XC3100A,
XC3000L, and XC3100L families. The XC3000L and XC3100L are identical in architec-
ture and features to the XC3000A and XC3100A, respectively, but operate at a nominal
supply voltage of 3.3 V.

XC4000E Library
Information appearing under the title XC4000E pertains to the XC4000E and XC4000L
families. The XC4000L is identical in architecture and features to the XC4000E but
operates at a nominal supply voltage of 3.3 V.

XC4000X Library
Information appearing under the title XC4000X pertains to the XC4000EX, XC4000XL,
XC4000XV, and XC4000XLA families. The XC4000XL is identical in architecture and
features to the XC4000EX but operates at a nominal supply voltage of 3.3 V. The
XC4000XV has identical library symbols to the XC4000EX and XC4000XL but operates
at a nominal supply voltage of 2.5 V and includes additional features.

XC4000 References
Wherever XC4000 is mentioned, the information applies to all architectures supported
by the XC4000E and XC4000X libraries.

XC5200 Library
The information appearing under the title XC5200 pertains to the XC5200 family.

XC9000 Library
The information appearing under the title XC9000 pertains to the XC9500 and
XC9500XL CPLD families.

Spartan Library
The information appearing under the title Spartan pertains to the Spartan family XCS*
devices.

1-2 Xilinx Development System

Xilinx Unified Libraries

SpartanXL Library
The information appearing under the title SpartanXL pertains to the SpartanXL
family XCS*XL devices.

Spartans and Spartan Series References

Wherever Spartans and Spartan series is mentioned, the information applies to all
architectures supported by the Spartan and SpartanXL libraries.

Virtex Library
The information appearing under the title Virtex pertains to the Virtex family XCV*
devices.

Selection Guide
The “Selection Guide” chapter briefly describes, then tabularly lists the logic
elements that are explained in detail in the “Design Elements” sections. The tables
included in this section are organized into functional categories. They list the avail-
able elements in each category along with a brief description of each element and an
applicability table identifying which libraries (XC3000, XC4000E, XC4000X, XC5200,
XC9000, Spartan, SpartanXL, Virtex) contain the element.

Design Elements
Design elements are organized in alphanumeric order, with all numeric suffixes in
ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8,
which precedes ADD16.
The following information is provided for each library element.
• Graphic symbol
• Applicability table (with primitive versus macro identification)
• Functional description
• Truth table (when applicable)
• Topology (when applicable)
• Schematic for macros

Schematic Examples
Schematics are included for each library if the implementation differs.
Design elements with bused or multiple I/O pins (2-, 4-, 8-, 16-bit versions) typically
include just one schematic — generally the 8-bit version. When only one schematic is
included, implementation of the smaller and larger elements differs only in the
number of sections. In cases where an 8-bit version is very large, an appropriate
smaller element serves as the schematic example.

Libraries Guide, Release M1.5 1-3

Libraries Guide, Release M1.5

Naming Conventions
Examples of the general naming conventions for the unified library elements are
shown in the following figures.

Example 1

FUNCTION SIZE CONTROL PINS

Counter, Binary 4-Bit
Clear (Asynchronous)
Load
Clock Enable
Bi-Directional

CB4CLED
Precedence of Control Pins

Example 2
FUNCTION SIZE CONTROL PINS
Flip-Flop, D-type 16-Bit
Reset (Synchronous)
Clock Enable

FD16RE
X7764 Precedence of Control Pins

Figure 1-1 Naming Conventions

AND3B2
Logic Function
Number of Inputs
Inverting (Bubble) Inputs
Number of Inverting Inputs

X4316

Figure 1-2 Combinatorial Naming Conventions

Refer to the “Selection Guide” chapter for examples of functional component naming
conventions.

Attributes, Constraints, and Carry Logic

Attributes are instructions placed on symbols or nets in a schematic to indicate their
placement, implementation, naming, directionality, and so forth. Constraints are a
type of attribute used only to limit where an element should be placed. The
“Attributes, Constraints, and Carry Logic” chapter provides information on all
attributes and constraints.

1-4 Xilinx Development System

Xilinx Unified Libraries

Flip-Flop, Counter, and Register Performance

All counter, register, and storage functions are derived from the flip-flops (and latches
in XC4000X and SpartanXL) available in the Configurable Logic Blocks (CLBs).
The D flip-flop is the basic building block for all architectures. Differences occur from
the availability of asynchronous Clear (CLR) and Preset (PRE) inputs, and the source
of the synchronous control signals, such as, Clock Enable (CE), Clock (C), Load enable
(L), synchronous Reset (R), and synchronous Set (S). The basic flip-flop configuration
for each architecture follows.
The XC3000 and XC5200 have a direct-connect Clock Enable input and a Clear input.

FDCE
D Q
CE
C

CLR X3717

The XC4000, XC9500XL, and Spartans have a direct-connect Clock Enable input and a
choice of either the Clear or the Preset inputs, but not both.
PRE

FDPE
D Q
CE
C

X3721

FDCE
D Q
CE
C

CLR X3717

The basic XC9000 flip-flops have both Clear and Preset inputs.
PRE

D FDCP
Q
C

CLR
X4397

Libraries Guide, Release M1.5 1-5

Libraries Guide, Release M1.5

Virtex has two basic flip-flop types. One has both Clear and Preset inputs and one has
both asynchronous and synchronous control functions.
PRE

D FDCPE
CE Q
C

CLR

X4389
S

D FDRSE Q
CE
C

R X3732

The asynchronous and synchronous control functions, when used, have a priority that
is consistent across all devices and architectures. These inputs can be either active-
High or active-Low as defined by the macro. The priority, from highest to lowest is as
follows.
• Asynchronous Clear (CLR)
• Asynchronous Preset (PRE)
• Synchronous Set (S)
• Synchronous Reset (R)
• Clock Enable (CE)
Note: The asynchronous CLR and PRE inputs, by definition, have priority over all the
synchronous control and clock inputs.
For FPGA families, the Clock Enable (CE) function is implemented using two
different methods in the Xilinx Unified Libraries; both are shown in the “Clock
Enable Implementation Methods” figure.
• In method 1, CE is implemented by connecting the CE pin of the macro directly to
the dedicated Enable Clock (EC) pin of the internal Configurable Logic Block
(CLB) flip-flop. This allows one CE per CLB. CE takes precedence over the L, S,
and R inputs. All flip-flops with asynchronous clear or preset use this method.
• In method 2, CE is implemented using function generator logic. This allows two
CEs per CLB. CE has the same priority as the L, S, and R inputs. All flip-flops with
synchronous set or reset use this method.
The method used in a particular macro is indicated by the inclusion of asynchronous
clear, asynchronous preset, synchronous set, or synchronous reset in the macro’s
description.

1-6 Xilinx Development System

Xilinx Unified Libraries

C1 X
D Q
C1 D Q C2 Function
Function EC Generator
CE
Generator C
C2
C
X=(CE * C2)+(CE * C1)

C1 D Q C1 Y
D Q
Function EC C2 Function
Generator Generator
C2 CE
C C

Y=(CE * C1)+(CE * C2)

Method 1 Method 2
CE implemented CE implemented as a
using dedicated EC pin. function generator input.
X4675

Figure 1-3 Clock Enable Implementation Methods

Libraries Guide, Release M1.5 2-11

Libraries Guide, Release M1.5

Functional Categories
This section categorizes, by function, the logic elements that are described in detail in
the “Design Elements” sections. Each category is briefly described. Tables under each
category identify all the available elements for the function and indicate which
libraries include the element.
Elements are listed in alphanumeric order under each category. There are a number of
standard TTL 7400-type functions in the different libraries. All 7400-type functions
start with a “X74” prefix and are listed after all other elements. The numeric sequence
following the “X74” prefix uses ascending numbers, for example, X74_42 precedes
X74_138.
A check mark (√) in the column under the library name means that the element
applies to the devices that use that library. (Refer to the “Applicable Architectures”
section of the “Xilinx Unified Libraries” chapter for information on the specific device
families that use each library.) A blank column means that the element does not apply.
The categories are as follows.
• Arithmetic Functions
• Buffers
• Comparators
• Counters
• Data Registers
• Decoders
• Edge Decoders
• Encoders
• Flip-Flops
• General
• Input/Output Flip-Flops
• Input/Output Functions
• Input Latches
• Latches
• Logic Primitives
• Map Elements
• Memory Elements
• Multiplexers
• Shift Registers
• Shifters
Note: When converting your design between FPGA families, use elements that have
equivalent functions in each of the architectural families (libraries) to minimize re-
designing.

2-12 Xilinx Development System

Selection Guide

Arithmetic Functions
There are three types of arithmetic functions: accumulators (ACC), adders (ADD), and
adder/subtracters (ADSU). With an ADSU, either unsigned binary or twos-comple-
ment operations cause an overflow. If the result crosses the overflow boundary, an
overflow is generated. Similarly, when the result crosses the carry-out boundary, a
carry-out is generated. The following figure shows the ADSU carry-out and overflow
boundaries.

Overflow

-127 127

128 127

TW
D
NE

OS
SIG

CO
UN
Y
ED BI NAR
E N T OR

MPL E MENT O
SIGN
ED BIN
LEM

G N

AR
I
MP

S N

R
Y
U
CO

SI
G
S

N
255
O ED
TW 0
-1 0

Carry-Out
X4720

Figure 2-1 ADSU Carry-Out and Overflow Boundaries

ACC1 1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous
Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

ACC4, 8, 16 4-, 8-, 16-Bit Loadable Cascadable Accumulators with Carry-In, Carry-Out, and
Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

ADD1 1-Bit Full Adder with Carry-In and Carry-Out

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

ADD4, 8, 16 4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and Overflow
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

Libraries Guide, Release M1.5 2-13

Libraries Guide, Release M1.5

ADSU1 1-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

ADSU4, 8, 16 4-, 8-, 16-Bit Cascadable Adders/Subtracters with Carry-In, Carry-Out and Over-
flow
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

X74_280 9-Bit Odd/Even Parity Generator/Checker

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_283 4-Bit Full Adder with Carry-In and Carry-Out

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Buffers
The buffers in this section route high fan-out signals, 3-state signals, and clocks inside
a PLD device. The “Input/Output Functions” section later in this chapter covers off-
chip interface buffers.

ACLK Alternate Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUF General-Purpose Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

BUF4, 8, 16 General-Purpose Buffers

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

2-14 Xilinx Development System

Selection Guide

BUFCF Fast Connect Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUFE, 4, 8, 16 Internal 3-State Buffers with Active High Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √∗ √ √ √
* not supported for XC9500XL devices

BUFFCLK Global Fast Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUFG Global Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

BUFGDLL Clock Delay Locked Loop Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUFGE Global Low Early Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUFGLS Global Low Skew Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

BUFGP Primary Global Buffer for Driving Clocks or Longlines (Four per PLD Device)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

Libraries Guide, Release M1.5 2-15

Libraries Guide, Release M1.5

BUFGS Secondary Global Buffer for Driving Clocks or Longlines (Four per PLD Device)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √

BUFGSR Global Set/Reset Input Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUFGTS Global Three-State Input Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BUFOD Open-Drain Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

BUFT, 4, 8, 16 Internal 3-State Buffers with Active-Low Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √∗ √ √ √
* not supported for XC9500XL devices

GCLK Global Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Comparators
There are two types of comparators, identity (COMP) and magnitude (COMPM).

COMP2, 4, 8, 16 2-, 4-, 8-, 16-Bit Identity Comparators

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

COMPM2, 4, 8, 16 2-, 4-, 8-, 16-Bit Magnitude Comparators

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-16 Xilinx Development System

Selection Guide

COMPMC8, 16 8-, 16-Bit Magnitude Comparators

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

X74_L85 4-Bit Expandable Magnitude Comparator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_518 8-Bit Identity Comparator with Active-Low Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_521 8-Bit Identity Comparator with Active-Low Enable and Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Counters
There are six types of counters with various synchronous and asynchronous inputs.
The name of the counter defines the modulo or bit size, the counter type, and which
control functions are included. The counter naming convention is shown in the
following figure.

CB16CLED
Counter

Binary (B)
BCD (D)
Binary, Carry Logic (C)
Johnson (J)
Ripple (R)

Modulo (Bit Size)

Synchronous Reset (R)

Asynchronous Clear (C)

Loadable

Clock Enable

Directional

X4577

Figure 2-2 Counter Naming Convention

Libraries Guide, Release M1.5 2-17

Libraries Guide, Release M1.5

A carry-lookahead design accommodates large counters without extra gating. On TTL

7400-type counters with trickle clock enable (ENT), parallel clock enable (ENP), and
ripple carry-out (RCO), both the ENT and ENP inputs must be High to count. ENT is
propagated forward to enable RCO, which produces a High output with the approxi-
mate duration of the QA output. The following figure illustrates a carry-lookahead
design.

RCO
ENP
ENT

Vcc RCO
ENP
ENT

Vcc
RCO
ENP
CE ENT

X4719

Figure 2-3 Carry-Lookahead Design

The RCO output of the first stage of the ripple carry is connected to the ENP input of
the second stage and all subsequent stages. The RCO output of the second stage and
all subsequent stages is connected to the ENT input of the next stage. The ENT of the
second stage is always enabled/tied to VCC. CE is always connected to the ENT input
of the first stage. This cascading method allows the first stage of the ripple carry to be
built as a prescaler. In other words, the first stage is built to count very fast.

CB2CE, CB4CE, CB8CE, 2-, 4-, 8-, 16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous
CB16CE Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CB2CLE, CB4CLE, 2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asyn-
CB8CLE, CB16CLE chronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-18 Xilinx Development System

Selection Guide

CB2CLED, CB4CLED, 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock
CB8CLED, CB16CLED Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CB2RE, CB4RE, CB8RE, 2-, 4-, 8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous
CB16RE Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CB2RLE, CB4RLE, 2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and
CB8RLE, CB16RLE Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CB2X1, CB4X1, CB8X1, 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock
CB16X1 Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CB2X2, CB4X2, CB8X2, 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock
CB16X2 Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CC8CE, CC16CE 8-, 16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

CC8CLE, CC16CLE 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchro-
nous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

Libraries Guide, Release M1.5 2-19

Libraries Guide, Release M1.5

CC8CLED, CC16CLED 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and
Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

CC8RE, CC16RE 8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

CD4CE 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CD4CLE 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous
Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CD4RE 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CD4RLE 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CJ4CE, CJ5CE, CJ8CE 4-, 5-, 8-Bit Johnson Counters with Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CJ4RE, CJ5RE, CJ8RE 4-, 5-, 8-Bit Johnson Counters with Clock Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-20 Xilinx Development System

Selection Guide

CR8CE, CR16CE 8-, 16-Bit Negative-Edge Binary Ripple Counters with Clock Enable and Asynchro-
nous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

X74_160 4-Bit BCD Counter with Parallel and Trickle Enables, Active-Low Load Enable, and
Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_161 4-Bit Binary Counter with Parallel and Trickle Enables, Active-Low Load Enable,
and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_162 4-Bit BCD Counter with Parallel and Trickle Enables, Active-Low Load Enable, and
Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_163 4-Bit Binary Counter with Parallel and Trickle Enables, Active-Low Load Enable,
and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_168 4-Bit BCD Bidirectional Counter with Parallel and Trickle Clock Enables and Active-
Low Load Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_390 4-Bit BCD/Bi-Quinary Ripple Counter with Negative-Edge Clocks and Asynchro-
nous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Libraries Guide, Release M1.5 2-21

Libraries Guide, Release M1.5

Data Registers
There are three TTL 7400-type data registers designed to function exactly as the TTL
elements for which they are named.

X74_174 6-Bit Data Register with Active-Low Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_273 8-Bit Data Register with Active-Low Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_377 8-Bit Data Register with Active-Low Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Decoders
Decoder names, shown in the following figure, indicate the number of inputs and
outputs and if an enable is available. Decoders with an enable can be used as multi-
plexers. This group includes some standard TTL 7400-type decoders whose names
have an “X74” prefix.

D2_4E
Decoder
Number of Inputs
Number of Outputs
Output Enable

X4619

Figure 2-4 Decoder Naming Convention

D2_4E 2- to 4-Line Decoder/Demultiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

D3_8E 3- to 8-Line Decoder/Demultiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-22 Xilinx Development System

Selection Guide

D4_16E 4- to 16-Line Decoder/Demultiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

DEC_CC4, 8, 16 4-, 8-, 16-Bit Active Low Decoders

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

X74_42 4- to 10-Line BCD-to-Decimal Decoder with Active-Low Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_138 3- to 8-Line Decoder/Demultiplexer with Active-Low Outputs and Three Enables

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_139 2- to 4-Line Decoder/Demultiplexer with Active-Low Outputs and Active-Low

Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_154 4- to 16-Line Decoder/Demultiplexer with Two Enables and Active-Low Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Edge Decoders
Edge decoders are open-drain wired-AND gates that are available in different bit
sizes.

DECODE4, 8, 16 4-, 8-, 16-Bit Active-Low Decoders

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

DECODE32, 64 32- and 64-Bit Active-Low Decoders

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

Libraries Guide, Release M1.5 2-23

Libraries Guide, Release M1.5

Encoders
There are two priority encoders (ENCPR) that function like the TTL 7400-type
elements they are named after. There is a 10- to 4-line BCD encoder and an 8- to 3-line
binary encoder.

X74_147 10- to 4-Line Priority Encoder with Active-Low Inputs and Outputs
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_148 8- to 3-Line Cascadable Priority Encoder with Active-Low Inputs and Outputs
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Flip-Flops
There are three types of flip-flops (D, J-K, toggle) with various synchronous and asyn-
chronous inputs. Some are available with inverted clock inputs and/or the ability to
set in response to global set/reset rather than reset. The naming convention shown in
the following figure provides a description for each flip-flop. D-type flip-flops are
available in multiples of up to 16 in one macro.

FDPE_1
Flip-Flop

D-Type (D)
JK-Type (JK)
Toggle-Type (T)

Asynchronous Preset (P)

Asynchronous Clear (C)
Synchronous Set (S)
Synchronous Reset (R)

Clock Enable

Inverted Clock

X4579

Figure 2-5 Flip-Flop Naming Convention

FD D Flip-Flop
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FD_1 D Flip-Flop with Negative-Edge Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

2-24 Xilinx Development System

Selection Guide

FD4, 8, 16 Multiple D Flip-Flops

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FD4CE, FD8CE, FD16CE 4-, 8-, 16-Bit Data Registers with Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FD4RE, FD8RE, FD16RE 4-, 8-, 16-Bit Data Registers with Clock Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDC D Flip-Flop with Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDC_1 D Flip-Flop with Negative-Edge Clock and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FDCE D Flip-Flop with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDCE_1 D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FDCP D Flip-Flop with Asynchronous Preset and Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

FDCP_1 D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-25

Libraries Guide, Release M1.5

FDCPE D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

FDCPE_1 D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and
Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDE D Flip-Flop with Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDE_1 D Flip-Flop with Negative-Edge Clock and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDP D Flip-Flop with Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FDP_1 D Flip-Flop with Negative-Edge Clock and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

FDPE D Flip-Flop with Clock Enable and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FDPE_1 D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

2-26 Xilinx Development System

Selection Guide

FDR D Flip-Flop with Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDR_1 D Flip-Flop with Negative-Edge Clock and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDRE D Flip-Flop with Clock Enable and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDRE_1 D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDRS D Flip-Flop with Synchronous Reset and Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDRS_1 D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDRSE D Flip-Flop with Synchronous Reset and Set and Clock Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDRSE_1 D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, and Clock
Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-27

Libraries Guide, Release M1.5

FDS D Flip-Flop with Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDS_1 D Flip-Flop with Negative-Edge Clock and Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDSE D Flip-Flop with Clock Enable and Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FDSE_1 D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FDSR D Flip-Flop with Synchronous Set and Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FDSRE D Flip-Flop with Synchronous Set and Reset and Clock Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FJKC J-K Flip-Flop with Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FJKCE J-K Flip-Flop with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FJKCP J-K Flip-Flop with Asynchronous Clear and Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

2-28 Xilinx Development System

Selection Guide

FJKCPE J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FJKP J-K Flip-Flop with Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FJKPE J-K Flip-Flop with Clock Enable and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FJKRSE J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FJKSRE J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FTC Toggle Flip-Flop with Toggle Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FTCE Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FTCLE Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FTCLEX Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

Libraries Guide, Release M1.5 2-29

Libraries Guide, Release M1.5

FTCP Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FTCPE Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FTCPLE Loadable Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
and Preset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FTP Toggle Flip-Flop with Toggle Enable and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FTPE Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Preset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FTPLE Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Preset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

FTRSE Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FTRSLE Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset
and Set
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-30 Xilinx Development System

Selection Guide

FTSRE Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

FTSRLE Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and
Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

General
General elements include FPGA configuration functions, oscillators, boundary scan
logic, and other functions not classified in other sections.

BSCAN Boundary Scan Logic Control Circuit

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

BSCAN_VIRTEX Virtex Boundary Scan Logic Control Circuit

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BYPOSC Bypass Oscillator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CAPTURE_VIRTEX Virtex Register State Capture for Bitstream Readback

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CK_DIV Internal Multiple-Frequency Clock Divider

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CLB CLB Configuration Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-31

Libraries Guide, Release M1.5

CLKDLL Clock Delay Locked Loop

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CLKDLLHF High Frequency Clock Delay Locked Loop

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CONFIG Repository for Schematic-Level (Global) Attributes

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

CY_INIT Initialization Stage for Carry Chain

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

GND Ground-Connection Signal Tag

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

GXTL Crystal Oscillator with ACLK Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

IOB IOB Configuration Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

KEEPER KEEPER Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LUT1, 2, 3, 4 1-, 2-, 3-, 4-Bit Look-Up-Table with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

2-32 Xilinx Development System

Selection Guide

LUT1_D, LUT2_D, 1-, 2-, 3-, 4-Bit Look-Up-Table with Dual Output
LUT3_D, LUT4_D
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LUT1_L, LUT2_L, 1-, 2-, 3-, 4-Bit Look-Up-Table with Local Output
LUT3_L, LUT4_L
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MD0 Mode 0, Input Pad Used for Readback Trigger Input

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √

MD1 Mode 1, Output Pad Used for Readback Data Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √

MD2 Mode 2, Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √

OSC Crystal Oscillator Amplifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

OSC4 Internal 5-Frequency Clock-Signal Generator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OSC5 Internal Multiple-Frequency Clock-Signal Generator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-33

Libraries Guide, Release M1.5

OSC52 Internal Multiple-Frequency Clock-Signal Generator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

PULLDOWN Resistor to GND for Input Pads

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

PULLUP Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

READBACK FPGA Bitstream Readback Controller

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

STARTUP User Interface to Global Clock, Reset, and 3-State Controls

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

STARTUP_VIRTEX Virtex User Interface to Global Clock, Reset, and 3-State Controls
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

TCK Boundary Scan Test Clock Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

TDI Boundary Scan Test Data Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

TDO Boundary Scan Data Output Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

2-34 Xilinx Development System

Selection Guide

TIMEGRP Schematic-Level Table of Basic Timing Specification Groups

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

TIMESPEC Schematic-Level Timing Requirement Table

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

TMS Boundary Scan Test Mode Select Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

VCC VCC-Connection Signal Tag

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

Input/Output Flip-Flops
Input/Output flip-flops are configured in IOBs. They include flip-flops whose
outputs are enabled by 3-state buffers, flip-flops that can be set upon global set/reset
rather than reset, and flip-flops with inverted clock inputs. The naming convention
specifies each flip-flop function and is illustrated in the following figure.

OFDEI_1
Output (O), Input (I)
Flip-Flop
D-Type

Active High Enable (E)

Active Low Enable (T)

Inverse of Normal Initial State

Inverted Clock

X4580

Figure 2-6 Input/Output Flip-Flop Naming Convention

IFD, 4, 8, 16 Single- and Multiple-Input D Flip-Flops

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

IFD_1 Input D Flip-Flop with Inverted Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Libraries Guide, Release M1.5 2-35

Libraries Guide, Release M1.5

IFDI Input D Flip-Flop (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

IFDI_1 Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

IFDX, 4, 8, 16 Single- and Multiple-Input D Flip-Flops with Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

IFDX_1 Input D Flip-Flop with Inverted Clock and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

IFDXI Input D Flip-Flop with Clock Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

IFDXI_1 Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

OFD, 4, 8, 16 Single- and Multiple-Output D Flip-Flops

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OFD_1 Output D Flip-Flop with Inverted Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

OFDE, 4, 8, 16 D Flip-Flops with Active-High Enable Output Buffers

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-36 Xilinx Development System

Selection Guide

OFDE_1 D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

OFDEI D Flip-Flop with Active-High Enable Output Buffer (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDEI_1 D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock (Asynchro-
nous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDEX, 4, 8, 16 D Flip-Flops with Active-High Enable Output Buffers and Clock Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDEX_1 D Flip-Flop with Active-High Enable Output Buffer, Inverted Clock, and Clock
Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDEXI D Flip-Flop with Active-High Enable Output Buffer and Clock Enable (Asynchro-
nous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDEXI_1 D Flip-Flop with Active-High Enable Output Buffer, Inverted Clock, and Clock
Enable (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDI Output D Flip-Flop (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

Libraries Guide, Release M1.5 2-37

Libraries Guide, Release M1.5

OFDI_1 Output D Flip-Flop with Inverted Clock (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

OFDT, 4, 8, 16 Single and Multiple D Flip-Flops with Active-Low 3-State Output Buffers
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OFDT_1 D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

OFDTI D Flip-Flop with Active-Low 3-State Output Buffer (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDTI_1 D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock (Asynchro-
nous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDTX, 4, 8, 16 Single and Multiple D Flip-Flops with Active-Low 3-State Output Buffers and Clock
Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDTX_1 D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock, and Clock
Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDTXI D Flip-Flop with Active-Low 3-State Output Buffer and Clock Enable (Asynchro-
nous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

2-38 Xilinx Development System

Selection Guide

OFDTXI_1 D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock, and Clock
Enable (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

OFDX, 4, 8, 16 Single- and Multiple-Output D Flip-Flops with Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

OFDX_1 Output D Flip-Flop with Inverted Clock and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

OFDXI Output D Flip-Flop with Clock Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

OFDXI_1 Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

Input/Output Functions
Input/Output Block (IOB) resources are configured into various I/O primitives and
macros for convenience, such as, output buffers (OBUFs) and output buffers with an
enable (OBUFEs). Pads used to connect the circuit to PLD device pins are also
included.
Virtex has multiple variants (primitives) to choose from for each selectI/O buffer. The
I/O interface for each variant corresponds to a specific I/O standard.

IBUF, 4, 8, 16 Single- and Multiple-Input Buffers

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

IBUF_selectIO Single Input Buffer with Selectable I/O Interface (16 primitives)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-39

Libraries Guide, Release M1.5

IBUFG_selectIO Dedicated Input Buffer with Selectable I/O Interface (16 primitives)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

IOBUF_selectIO Bi-Directional Buffer with Selectable I/0 Interface (30 primitives)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

IOPAD, 4, 8, 16 Single- and Multiple-Input/Output Pads

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

IPAD, 4, 8, 16 Single- and Multiple-Input Pads

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OBUF, 4, 8, 16 Single- and Multiple-Output Buffers

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OBUF_selectIO Single Output Buffer with Selectable I/O Interface (30 primitives)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

OBUFE, 4, 8, 16 3-State Output Buffers with Active-High Output Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OBUFT, 4, 8, 16 Single and Multiple 3-State Output Buffers with Active Low Output Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-40 Xilinx Development System

Selection Guide

OBUFT_selectIO Single 3-State Output Buffer with Active-Low Output Enable and Selectable I/O
Interface (30 primitives)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

OPAD, 4, 8, 16 Single- and Multiple-Output Pads

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

UPAD Connects the I/O Node of an IOB to the Internal PLD Circuit
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Input Latches
Single and multiple input latches can hold transient data entering a chip. Input
latches use the same naming convention as I/O flip-flops.

ILD, 4, 8, 16 Transparent Input Data Latches

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

ILD_1 Transparent Input Data Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

ILDI Transparent Input Data Latch (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

ILDI_1 Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

ILDX, 4, 8, 16 Transparent Input Data Latches

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

Libraries Guide, Release M1.5 2-41

Libraries Guide, Release M1.5

ILDX_1 Transparent Input Data Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

ILDXI Transparent Input Data Latch (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

ILDXI_1 Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

ILFFX Fast Capture Input Latch

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

ILFFXI Fast Capture Input Latch (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

ILFLX Fast Capture Transparent Input Latch

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

ILFLX_1 Fast Capture Input Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

ILFLXI_1 Fast Capture Input Latch with Inverted Gate (Asynchronous Preset)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

2-42 Xilinx Development System

Selection Guide

Latches
Latches (LD) are only available in the XC4000X, XC5200, XC9000, SpartanXL, and
Virtex architectures. XC3000 and XC4000E latches that existed in previous macro
libraries are not recommended for new designs.

LD Transparent Data Latch

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

LD_1 Transparent Data Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

LD4, 8, 16 Multiple Transparent Data Latches

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

LDC Transparent Data Latch with Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

LDC_1 Transparent Data Latch with Asynchronous Clear and Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

LDCE Transparent Data Latch with Asynchronous Clear and Gate Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

LDCE_1 Transparent Data Latch with Asynchronous Clear, Gate Enable, and Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

LD4CE, LD8CE, LD16CE Transparent Data Latches with Asynchronous Clear and Gate Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

Libraries Guide, Release M1.5 2-43

Libraries Guide, Release M1.5

LDCP Transparent Data Latch with Asynchronous Clear and Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDCP_1 Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDCPE Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDCPE_1 Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable, and
Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDE Transparent Data Latch with Gate Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDE_1 Transparent Data Latch with Gate Enable and Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDP Transparent Data Latch with Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

LDP_1 Transparent Data Latch with Asynchronous Preset and Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

2-44 Xilinx Development System

Selection Guide

LDPE Transparent Data Latch with Asynchronous Preset and Gate Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √

LDPE_1 Transparent Data Latch with Asynchronous Preset, Gate Enable, and Inverted Gate
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √

Logic Primitives
Combinatorial logic gates that implement the basic Boolean functions are available in
all architectures with up to five inputs in all combinations of inverted and non-
inverted inputs, and with six to nine inputs non-inverted.

AND2-9 2- to 9-Input AND Gates with Inverted and Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

AND12, 16 12- and 16-Input AND Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

INV, 4, 8, 16 Single and Multiple Inverters

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

MULT_AND Fast Multiplier AND

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

NAND2-9 2- to 9-Input NAND Gates with Inverted and Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

NAND12, 16 12- and 16-Input NAND Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

Libraries Guide, Release M1.5 2-45

Libraries Guide, Release M1.5

NOR2-9 2- to 9-Input NOR Gates with Inverted and Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

NOR12, 16 12 and 16-Input NOR Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

OAND2 2-Input AND Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

ONAND2 2-Input NAND Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

ONOR2 2-Input NOR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

OOR2 2-Input OR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

OR2-9 2- to 9-Input OR Gates with Inverted and Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OR12, 16 12- and 16-Input OR Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

OXNOR2 2-Input Exclusive-NOR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

2-46 Xilinx Development System

Selection Guide

OXOR2 2-Input Exclusive-OR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

SOP3-4 Sum of Products

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

WAND1, 4, 8, 16 Open-Drain Buffers

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

WOR2AND 2-Input OR Gate with Wired-AND Open-Drain Buffer Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

XNOR2-9 2- to 9-Input XNOR Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

XOR2-9 2- to 9-Input XOR Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

XORCY XOR for Carry Logic with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

XORCY_D XOR for Carry Logic with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

XORCY_L XOR for Carry Logic with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-47

Libraries Guide, Release M1.5

Map Elements
Map elements are used in conjunction with logic symbols to constrain the logic to
particular CLBs or particular F or H function generators.

CLBMAP Logic-Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

F5MAP 5-Input Function Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FMAP F Function Generator Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

HMAP H Function Generator Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

Memory Elements
The XC4000 and Spartan series architectures have a number of static RAM configura-
tions defined as macros. In the Virtex architecture, they are defined as primitives.
These 16- or 32-word RAMs are 1, 2, 4, and 8 bits wide. There are two ROMs in the
XC4000 and Spartan series architectures, 16X1 and 32X1.
The Virtex series has dedicated blocks of on-chip 4096-bit single-port and dual-port
synchronous RAM. Each port is configured to a specific data width. There are five
single-port block RAM primitives and 30 dual-port block RAM primitives.

RAM16X1 16-Deep by 1-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM16X1D 16-Deep by 1-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

2-48 Xilinx Development System

Selection Guide

RAM16X1D_1 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

RAM16X1S 16-Deep by 1-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM16X1S_1 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

RAM16X2 16-Deep by 2-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM16X2D 16-Deep by 2-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM16X2S 16-Deep by 2-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM16X4 16-Deep by 4-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM16X4D 16-Deep by 4-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM16X4S 16-Deep by 4-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

Libraries Guide, Release M1.5 2-49

Libraries Guide, Release M1.5

RAM16X8 16-Deep by 8-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM16X8D 16-Deep by 8-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM16X8S 16-Deep by 8-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM32X1 32-Deep by 1-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM32X1S 32-Deep by 1-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM32X1S_1 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

RAM32X2 32-Deep by 2-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM32X2S 32-Deep by 2-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM32X4 32-Deep by 4-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

2-50 Xilinx Development System

Selection Guide

RAM32X4S 32-Deep by 4-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAM32X8 32-Deep by 8-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

RAM32X8S 32-Deep by 8-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

RAMB4_Sn 4096-Bit Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2,
4, 8, or 16 Bits (5 primitives)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

RAMB4_Sn_Sn 4096-Bit Dual-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2,
4, 8, or 16 Bits (30 primitives)
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

ROM16X1 16-Deep by 1-Wide ROM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

ROM32X1 32-Deep by 1-Wide ROM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

Libraries Guide, Release M1.5 2-51

Libraries Guide, Release M1.5

Multiplexers
The multiplexer naming convention shown in the following figure indicates the
number of inputs and outputs and if an enable is available. There are a number of TTL
7400-type multiplexers that have active-Low or inverted outputs.

M8_1E
Multiplexer
Number of Inputs
Number of Outputs
Output Enable

X4620

Figure 2-7 Multiplexer Naming Convention

CY_MUX 2-to-1 Multiplexer for Carry Logic

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

F5_MUX 2-to-1 Lookup Table Multiplexer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

M2_1 2-to-1 Multiplexer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

M2_1B1 2-to-1 Multiplexer with D0 Inverted

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

M2_1B2 2-to-1 Multiplexer with D0 and D1 Inverted

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

M2_1E 2-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

2-52 Xilinx Development System

Selection Guide

M4_1E 4-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

M8_1E 8-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

M16_1E 16-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

MUXCY 2-to-1 Multiplexer for Carry Logic with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXCY_D 2-to-1 Multiplexer for Carry Logic with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXCY_L 2-to-1 Multiplexer for Carry Logic with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXF5 2-to-1 Lookup Table Multiplexer with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXF5_D 2-to-1 Lookup Table Multiplexer with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXF5_L 2-to-1 Lookup Table Multiplexer with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 2-53

Libraries Guide, Release M1.5

MUXF6 2-to-1 Lookup Table Multiplexer with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXF6_D 2-to-1 Lookup Table Multiplexer with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

MUXF6_L 2-to-1 Lookup Table Multiplexer with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

OMUX2 2-to-1 Multiplexer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

X74_150 16-to-1 Multiplexer with Active-Low Enable and Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_151 8-to-1 Multiplexer with Active-Low Enable and Complementary Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_152 8-to-1 Multiplexer with Active-Low Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_153 Dual 4-to-1 Multiplexer with Active-Low Enables and Common Select Input
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_157 Quadruple 2-to-1 Multiplexer with Common Select and Active-Low Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

2-54 Xilinx Development System

Selection Guide

X74_158 Quadruple 2-to-1 Multiplexer with Common Select, Active-Low Enable, and Active-
Low Outputs
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_298 Quadruple 2-Input Multiplexer with Storage and Negative-Edge Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_352 Dual 4-to-1 Multiplexer with Active-Low Enables and Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Shift Registers
Shift registers are available in a variety of sizes and capabilities. The naming conven-
tion shown in the following figure illustrates available features.

SR8RLED
Shift Register

Bit Size

Synchronous Reset (R)

Asynchronous Clear (C)

Loadable

Clock Enable

Directional

X4578

Figure 2-8 Shift Register Naming Convention

SR4CE, SR8CE, SR16CE 4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock Enable and Asynchro-
nous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

SR4CLE, SR8CLE, 4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock
SR16CLE Enable and Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

Libraries Guide, Release M1.5 2-55

Libraries Guide, Release M1.5

SR4CLED, SR8CLED, 4-, 8-, 16-Bit Shift Registers with Clock Enable and Asynchronous Clear
SR16CLED
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

SR4RE, SR8RE, SR16RE 4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock Enable and Synchro-
nous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

SR4RLE, SR8RLE, 4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock
SR16RLE Enable and Synchronous Reset
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

SR4RLED, SR8RLED, 4-, 8-, 16-Bit Shift Registers with Clock Enable and Synchronous Reset
SR16RLED
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

SRL16 16-Bit Shift Register Look-Up-Table (LUT)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

SRL16_1 16-Bit Shift Register Look-Up-Table (LUT) with Negative-Clock Edge

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

SRL16E 16-Bit Shift Register Look-Up-Table (LUT) with Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

SRL16E_1 16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock and Clock
Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

2-56 Xilinx Development System

Selection Guide

X74_164 8-Bit Serial-In Parallel-Out Shift Register with Active-Low Asynchronous Clear
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_165S 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_194 4-Bit Loadable Bidirectional Serial/Parallel-In Parallel-Out Shift Register

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

X74_195 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Shifters
Shifters are barrel shifters (BRLSHFT) of four and eight bits.

BRLSHFT4, 8 4-, 8-Bit Barrel Shifters

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

Libraries Guide, Release M1.5 2-57

Libraries Guide, Release M1.5

2-58 Xilinx Development System

Chapter 3

Design Elements (ACC1 to BYPOSC)

This chapter describes design elements included in the Unified Libraries. The
elements are organized in alphanumeric order with all numeric suffixes in ascending
order.
Information on the specific architectures supported by each of the following libraries
is contained under the Applicable Architectures section of the Unified Libraries
Chapter.
• XC3000 Library
• XC4000E Library
• XC4000X Library
• XC5200 Library
• XC9000 Library
• Spartan Library
• SpartanXL Library
• Virtex Library
Note: Wherever XC4000 is mentioned, the information applies to all architectures
supported by the XC4000E and XC4000X libraries.
Note: Wherever Spartans or Spartan series is mentioned, the information applies to all
architectures supported by the Spartan and SpartanXL libraries.
Schematics are included for each library if the implementation differs. Design
elements with bused or multiple I/O pins (2-, 4-, 8-, 16-bit versions) typically include
just one schematic — generally the 8-bit version. When only one schematic is
included, implementation of the smaller and larger elements differs only in the
number of sections. In cases where an 8-bit version is very large, an appropriate
smaller element serves as the schematic example.

Libraries Guide, Release M1.5 — 3-1

Libraries Guide, Release M1.5

ACC1
1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out,
and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

ACC1 can add or subtract a 1-bit unsigned-binary word to or from the contents of a 1-
CI ACC1 Q0
B0 CO
bit data register and store the results in the register. The register can be loaded with a
D0 1-bit word. The synchronous reset (R) has priority over all other inputs and, when
L High, causes the output to go to logic level zero during the Low-to-High clock (C)
ADD
transition. Clock (C) transitions are ignored when clock enable (CE) is Low.
CE
C
The accumulator is asynchronously cleared, outputs Low, when power is applied. For
CPLDs the power-on condition can be simulated by applying a High-level pulse on
R X3862 the PRLD global net.

Load
When the load input (L) is High, CE is ignored and the data on the input D0 is loaded
into the 1-bit register during the Low-to-High clock (C) transition.

Add
When control inputs ADD and CE are both High, the accumulator adds a 1-bit word
(B0) and carry-in (CI) to the contents of the 1-bit register. The result is stored in the
register and appears on output Q0 during the Low-to-High clock transition. The
carry-out (CO) is not registered synchronously with the data output. CO always
reflects the accumulation of input B0 and the contents of the register, which allows
cascading of ACC1s by connecting CO of one stage to CI of the next stage. In add
mode, CO acts as a carry-out, and CO and CI are active-High.

Subtract
When ADD is Low and CE is High, the 1-bit word B0 and CI are subtracted from the
contents of the register. The result is stored in the register and appears on output Q0
during the Low-to-High clock transition. The carry-out (CO) is not registered
synchronously with the data output. CO always reflects the accumulation of input B0
and the contents of the register, which allows cascading of ACC1s by connecting CO
of one stage to CI of the next stage. In subtract mode, CO acts as a borrow, and CO
and CI are active-Low.

3-2 Xilinx Development System

Design Elements (ACC1)

VCC
+5

CE
CI AND2
ADD
L

OR2

GND

INV

INV
B0 INV
AND6

INV
INV
INV
INV
INV AND6

OR4

INV
INV
INV AND6

INV
INV
INV AND6
D0
FD
Q0
D Q
AND3B1
XOR2
OR2 C

Q0
AND3B2

AND3

AND3B2
OR5

AND3B2

AND2

X7688

Figure 3-1 ACC1 Implementation XC9000

Libraries Guide, Release M1.5 3-3

Libraries Guide, Release M1.5

ACC4, 8, 16
4-, 8-, 16-Bit Loadable Cascadable Accumulators with Carry-In,
Carry-Out, and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

ACC4, ACC8, ACC16 can add or subtract a 4-, 8-, 16-bit unsigned-binary, respectively
CI ACC4
B0 Q0
or twos-complement word to or from the contents of a 4-, 8-, 16-bit data register and
B1 Q1 store the results in the register. The register can be loaded with the 4-, 8-, 16-bit word.
B2 Q2
B3 Q3 In the XC4000 and Spartans, these accumulators are implemented using carry logic
D0 CO and relative location constraints, which assure most efficient logic placement.
D1 OFL
D2 The synchronous reset (R) has priority over all other inputs, and when High, causes
D3 all outputs to go to logic level zero during the Low-to-High clock (C) transition. Clock
L
(C) transitions are ignored when clock enable (CE) is Low.
ADD
CE The accumulator is asynchronously cleared, outputs Low, when power is applied. For
C
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
R
X3863 reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
CI ACC8 Q[7:0]
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
B[7:0] CO
D[7:0] OFL
Load
L When the load input (L) is High, CE is ignored and the data on the D inputs is loaded
ADD into the register during the Low-to-High clock (C) transition. ACC4 loads the data on
CE inputs D3 – D0 into the 4-bit register. ACC8 loads the data on D7 – D0 into the 8-bit
C
register. ACC16 loads the data on inputs D15 – D0 into the 16-bit register.

R X4374
Unsigned Binary Versus Twos Complement
ACC4, ACC8, ACC16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary
numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as
CI ACC16 Q[15:0]
unsigned binary, the result can be interpreted as unsigned binary. If the inputs are
B[15:0] CO
interpreted as twos complement, the output can be interpreted as twos complement.
D[15:0] OFL The only functional difference between an unsigned binary operation and a twos-
L complement operation is how they determine when “overflow” occurs. Unsigned
ADD binary uses CO, while twos complement uses OFL to determine when “overflow”
CE occurs.
C
Unsigned Binary Operation
R X4375 For unsigned binary operation, ACC4 can represent numbers between 0 and 15, inclu-
sive; ACC8 between 0 and 255, inclusive; and ACC16 between 0 and 65535, inclusive.
In add mode, CO is active (High) when the sum exceeds the bounds of the adder/
subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low when the
difference exceeds the bounds. The carry-out (CO) is not registered synchronously

3-4 Xilinx Development System

Design Elements (ACC4, 8, 16)

with the data outputs. CO always reflects the accumulation of the B inputs (B3 – B0
for ACC4, B7 – B0 for ACC8, B15 – B0 for ACC16) and the contents of the register,
which allows cascading of ACC4s, ACC8s, or ACC16s by connecting CO of one stage
to CI of the next stage. An unsigned binary “overflow” that is always active-High can
be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD
OFL should be ignored in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ACC4 can represent numbers between -8 and +7,
inclusive; ACC8 between -128 and +127, inclusive; ACC16 between -32768 and
+32767, inclusive. If an addition or subtraction operation result exceeds this range, the
OFL output goes High. The overflow (OFL) is not registered synchronously with the
data outputs. OFL always reflects the accumulation of the B inputs (B3 – B0 for ACC4,
B7 – B0 for ACC8, B15 – B0 for ACC16) and the contents of the register, which allows
cascading of ACC4s, ACC8s, or ACC16s by connecting OFL of one stage to CI of the
next stage.
CO should be ignored in twos-complement operation.

Topology for XC4000 and Spartans

This is the ACC4 (4-bit), ACC8 (8-bit), and ACC16 (16-bit) topology for XC4000 and
Spartan series devices.
CO

OFL
A 15 B 15 Q 15
A 14 B 14 Q 14
CO
A 13 B 13 Q 13
OFL
A 12 B 12 Q 12
CO A 7B 7 Q7
A 11 B 11 Q 11
OFL A 6B 6 Q6
A 10 B 10 Q 10
A3B3 Q3 A 5B 5 Q5 A 9 B9 Q9
A2B2 Q2 A 4B 4 Q4 A 8 B8 Q8
A1B1 Q1 A 3B 3 Q3 A 7 B7 Q7

A0B0 Q0 A 2B 2 Q2 A 6 B6 Q6

CI A 1B 1 Q1 A 5 B5 Q5
A 4 B4 Q4
A 0B 0 Q0
A 3 B3 Q3
4-Bit CI
A 2 B2 Q2
A 1 B1 Q1
8-Bit A 0 B0 Q0
CI

X8216 16-Bit

Libraries Guide, Release M1.5 3-5

Libraries Guide, Release M1.5

Topology for XC5200

This is the ACC8 (8-bit) and ACC16 (16-bit) topology for XC5200 devices.
OFL*
LC0

D 15 CO Q 15
LC3 LC3 LC3
B 15
D 14 Q 14
LC2 LC2 LC2
B 14
D 13 Q 13
LC1 LC1 LC1
B 13
OFL* D 12 Q 12
LC0 LC0 LC0 LC0
B 12

D7 CO Q7 D 11 Q 11
LC3 LC3 LC3 LC3 LC3 LC3
B7 B 11
D6 Q6 D 10 Q 10
LC2 LC2 LC2 LC2 LC2 LC2
B6 B 10
D5 Q5 D9 Q9
LC1 LC1 LC1 LC1 LC1 LC1
B5 B9
D4 Q4 D8 Q8
LC0 LC0 LC0 LC0 LC0 LC0
B4 B8

D3 Q3 D7 Q7
LC3 LC3 LC3 LC3 LC3 LC3
B3 B7
D2 Q2 D6 Q6
LC2 LC2 LC2 LC2 LC2 LC2
B2 B6
D1 Q1 D5 Q5
LC1 LC1 LC1 LC1 LC1 LC1
B1 B5
D0 Q0 D4 Q4
LC0 LC0 LC0 LC0 LC0 LC0
B0 B4

CY_INIT D3 Q3
LC3 LC3 LC3 LC3
B3
D2 Q2
LC2 LC2 LC2
8-Bit B2
D1 Q1
LC1 LC1 LC1
B1
D0 Q0
LC0 LC0 LC0
B0

CY_INIT
LC3

X8211 16-Bit

3-6 Xilinx Development System

Design Elements (ACC4, 8, 16)

Design Elements (ACC4, 8, 16)

OFL_POS_ADD

AND4B2
OFL_NEG_ADD
CI
CI_0
OFL_OUT
AND4B1
AND2 OFL

OR4

R
R_0 AND4B2
Q3 OFL_POS_SUB
OR2 S3
B3
ADD_1 AND4B3
L L_0
OFL_NEG_SUB

OR2

GND
VCC
+5
AND2
CE CE_1
S0 FD
D
Q0
ADD
ADD_1
NOR2 C
AND2 AND3B2 AND2
Q0

S1 FD
AND3
D
Q1
AND3B2
D0
NOR2 C
OR2
AND3
Q1
AND3B1 KEEP
X0

NOR2
OR4
AND4B2

AND3
B0 S2 FD
BX0
D
Q2
XNOR2
NOR2 C
AND4 OR3
Q2

AND4

AND3B2
D1

AND3B1 KEEP
X1

NOR2
OR4
AND4B2 AND3

B1 S3 FD
AND4
Q3
BX1 D
XNOR2
NOR2 C
OR4
Q3
AND5

AND3B2
D2

AND3B1 AND5
KEEP
X2

OR4 NOR2
AND4B2
AND3

B2
BX2 AND4
XNOR2

AND5 OR5

AND3B2
D3

AND6
AND3B1 KEEP
X3

NOR2
OR4
AND4B2

AND6

B3
BX3

C XNOR2

X7607

Figure 3-6 ACC4 Implementation XC9000

Libraries Guide, Release M1.5 3-11

Libraries Guide, Release M1.5

ACC4X2
CI
CI
B0 QO
B0 QO
B1 Q1
B1 Q1
B2 Q2
B2 Q2
B3 Q3
B[7:0] B3 Q3
D0
D0 CO
D1
D1 Q3_0
D2
D2
D3
D3
L
ADD
C3
CE
C
R Q[7:0]

ACC4
CI
B4 Q4
B0 QO
B5 Q5
B1 Q1
B6 Q6
B2 Q2
B7 Q7
B3 Q3
D4 CO
D0 CO
D5 OFL
D1 Q7_4 OFL
D[7:0] D6
D2
D7
D3
L
L
ADD
ADD
CE
CE
C
C
R X7766
R

Figure 3-7 ACC8 Implementation XC9000

3-12 Xilinx Development System

Design Elements (ACLK)

ACLK
Alternate Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive N/A N/A N/A N/A N/A N/A N/A

ACLK, the alternate clock buffer, is used to distribute high fan-out clock signals
throughout a PLD device. One ACLK buffer on each device provides direct access to
X3883 every Configurable Logic Block (CLB) and Input Output Block (IOB) clock pin. The
ACLK buffer is slightly slower than the global clock buffer (GCLK) but otherwise
similar. Unlike GCLK, the routing resources used for the ACLK network can be used
to route other signals if it is not used. For this reason, if only one of the GCLK and
ACLK buffers is used, GCLK is preferred. The ACLK input (I) can come from one of
the following sources.
• A CMOS-level signal on the dedicated BCLKIN pin. BCLKIN is a direct CMOS-
only input to the ACLK buffer. To use the BCLKIN pin, connect the input of the
ACLK element to IBUF and IPAD elements.
• A CMOS- or TTL-level external signal. To connect an external input to the ACLK
buffer, connect the input of the ACLK element to the output of the IBUF for that
signal. Unless the corresponding IPAD element is constrained otherwise, PAR
typically places that IOB directly adjacent to the ACLK buffer.
• The on-chip crystal oscillator. The output of the XTAL oscillator on XC3000
devices is directly adjacent to the ACLK buffer input. If the GXTL element is used,
the output of the XTAL oscillator is automatically connected to the ACLK buffer;
do not use the ACLK element for anything else.
• An internal signal. To drive the ACLK buffer with an internal signal, connect that
signal directly to the input of the ACLK element.
For a negative-edge clock, insert an INV (inverter) element between the ACLK output
and the clock input. Inversion is performed inside the CLB, or in the case of IOB clock
pins, on the IOB clock line (that controls the clock sense for the IOBs on an entire edge
of the chip).

Libraries Guide, Release M1.5 3-13

Libraries Guide, Release M1.5

ADD1
1-Bit Full Adder with Carry-In and Carry-Out

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

CI ADD1, a cascadable 1-bit full adder with carry-in and carry-out, adds two 1-bit words
A0 (A and B) and a carry-in (CI), producing a binary sum (S0) output and a carry-out
S0
B0 (CO).
CO
X4034

Inputs Outputs

A0 B0 CI S0 CO
0 0 0 0 0
1 0 0 1 0
0 1 0 1 0
1 1 0 0 1
0 0 1 1 0
1 0 1 0 1
0 1 1 0 1
1 1 1 1 1

A0
S0
B0
CI XOR2
AND2B1

OR2

AND2B1

AND2
CO

AND2 OR3

AND2

X7689

Figure 3-8 ADD1 Implementation XC9000

3-14 Xilinx Development System

Design Elements (ADD4, 8, 16)

ADD4, 8, 16
4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and
Overflow

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CI ADD4, ADD8, and ADD16 add two words and a carry-in (CI), producing a sum
A0
output and carry-out (CO) or overflow (OFL). ADD4 adds A3 – A0, B3 – B0, and CI
A1 ADD4 producing the sum output S3 – S0 and CO (or OFL). ADD8 adds A7 – A0, B7 – B0, and
A2
A3
S0 CI, producing the sum output S7 – S0 and CO (or OFL). ADD16 adds A15 – A0, B15 –
S1
B0
S2 B0 and CI, producing the sum output S15 – S0 and CO (or OFL).
S3
B1
B2 ADD4, ADD8, and ADD16 are implemented in the XC4000 and Spartans using carry
B3
OFL
logic and relative location constraints, which assure most efficient logic placement.
CO
X4376 Unsigned Binary Versus Twos Complement
ADD4, ADD8, ADD16 can operate on either 4-, 8-, 16-bit unsigned binary numbers or
CI
A[7:0]
4-, 8-, 16-bit twos-complement numbers, respectively. If the inputs are interpreted as
ADD8
S[7:0] unsigned binary, the result can be interpreted as unsigned binary. If the inputs are
B[7:0] interpreted as twos complement, the output can be interpreted as twos complement.
OFL The only functional difference between an unsigned binary operation and a twos-
CO complement operation is how they determine when “overflow” occurs. Unsigned
X4377
binary uses CO, while twos-complement uses OFL to determine when “overflow”
occurs.
CI

A[15:0] Unsigned Binary Operation

ADD16
S[15:0]
For unsigned binary operation, ADD4 can represent numbers between 0 and 15,
B[15:0]
inclusive; ADD8 between 0 and 255, inclusive; ADD16 between 0 and 65535, inclu-
OFL sive. CO is active (High) when the sum exceeds the bounds of the adder.
CO
X4378 OFL is ignored in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ADD4 can represent numbers between -8 and +7,
inclusive; ADD8 between -128 and +127, inclusive; ADD16 between -32768 and
+32767, inclusive. OFL is active (High) when the sum exceeds the bounds of the
adder.
CO is ignored in twos-complement operation.

Libraries Guide, Release M1.5 3-15

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the ADD4 (4-bit), ADD8 (8-bit), and ADD16 (16-bit) topology for XC4000 and
Spartan series devices.
CO

OFL
A 15 B 15 S 15

A 14 B 14 S 14
CO A 13 B 13 S 13

OFL A 12 B 12 S 12
CO A 7B 7 S7 A 11 B 11 S 11

OFL A 6B 6 S6 A 10 B 10 S 10
A3B3 S3 A 5B 5 S5 A 9B 9 S9

A2B2 S2 A 4B 4 S4 A 8B 8 S8
A1B1 S1 A 3B 3 S3 A 7B 7 S7
A0B0 S0 A 2B 2 S2 A 6B 6 S6
CI A 1B 1 S1 A 5B 5 S5
A 0B 0 S0 A 4B 4 S4
CI A 3B 3 S3
4-Bit
A 2B 2 S2
A 1B 1 S1
8-Bit
A 0B 0 S0
CI

X8215 16-Bit

3-16 Xilinx Development System

Design Elements (ADD4, 8, 16)

Topology for XC5200

This is the ADD8 (8-bit) and ADD16 (16-bit) topology for XC5200 devices.

OFL*
LC0

A 15 S 15
LC3 LC3
B 15 CO
A 14 S 14
LC2 LC2
B 14
A 13 S 13
LC1 LC1
B 13
OFL* A 12 S 12
LC0 LC0 LC0
B 12

A7 S7 A 11 S 11
LC3 LC3 LC3 LC3
B7 B 11
A6 S6 A 10 S 10
LC2 LC2 LC2 LC2
B6 B 10
A5 S5 A9 S9
LC1 LC1 LC1 LC1
B5 B9
A4 S4 A8 S8
LC0 LC0 LC0 LC0
B4 B8

A3 S3 A7 S7
LC3 LC3 LC3 LC3
B3 B7
A2 S2 A6 S6
LC2 LC2 LC2 LC2
B2 B6
A1 S1 A5 S5
LC1 LC1 LC1 LC1
B1 B5
A0 S0 A4 S4
LC0 LC0 LC0 LC0
B0 B4

CY_INIT A3 S3
LC3 LC3 LC3
B3
A2 S2
LC2 LC2
8-Bit B2
A1 S1
LC1 LC1
B1
A0 S0
LC0 LC0
B0

CY_INIT
LC3

X8210 16-Bit

Libraries Guide, Release M1.5 3-17

Libraries Guide, Release M1.5

S[7:0]
CI

A0 A4
AB0 AB4
B0 B4
AND2 AND2
A0CI C0 A4C3 C4

AND2 AND2
B0CI OR3 B4C3 OR3

AND2 AND2
S0 S4

XOR3 XOR3
A1 A5
AB1 AB5
B1 B5
AND2 AND2
A1C0 C1 A5C4 C5

AND2 AND2
B1C0 OR3 B5C4 OR3

AND2 AND2
S1 S5

XOR3 XOR3
A2 A6
AB2 AB6
B2 B6
AND2 AND2
A2C1 C2 A6C5 C6

AND2 AND2
B2C1 OR3 B6C5 OR3

AND2 AND2
S2 S6

XOR3 XOR3
A3 A7
AB3 AB7
B3 B7
AND2 AND2
A3C2 C3 A7C6 C7

AND2 AND2
B3C2 OR3 B7C6 OR3

AND2 AND2
S3 S7

XOR3 XOR3
A[7:0] CO
AXB

XNOR2
B[7:0] OFL
AABXS
AAB
AND2
AND2 XOR2

X6495

Figure 3-9 ADD8 Implementation XC3000

3-18 Xilinx Development System

Design Elements (ADD4, 8, 16)

FMAP

OFOR1 I4
RLOC=R0C0 B7 OFL
I3
CY4 A7 O
AND2 I2
COUT OFOR2 C7_M
B1 (G1) I1
A1 (G4) COUT0
AND2 OR3 RLOC=R0C0.G
B0 (F2) OFOR3
A0 (F1)
OFL
ADD (F3) AND2
CARRY MODE
CIN COR1 XOR2

AND2
COR2 CO
EXAMINE-CI

CY4_42 AND2 FMAP

C7_M COR3 OR3
B7 I4
A7 B7 CO
AND2 I3
A7 O
I2
C7_M
I1

RLOC=R0C0.F

C7 S[7:0]
S7

S7 FMAP
CY4
B7 XOR3 I4
COUT
B1 (G1)
C6 B7 S7
A7 I3
A1 (G4) COUT0 A7 O
B6 I2
B0 (F2) C6
A6 I1
A0 (F1)
ADD (F3)
CARRY MODE
FMAP
I4
B6 S6
ADDSUB-F-CI I3
C5 A6 O
CY4_12 S6 I2
C5
I1
S6
XOR3
S5

S5
CY4
B5 XOR3
COUT FMAP
B1 (G1)
A5 C4
A1 (G4) COUT0 I4
B4 B0 (F2) B5 S5
I3
A4 A0 (F1) A5 O
I2
ADD (F3) C4
I1
CARRY MODE
CIN

FMAP
ADDSUB-FG-CI
C3 I4
CY4_13 S4 B4 S4
I3
A4 O
I2
S4 C3
I1
XOR3
S3

CY4 S3
B3 XOR3 FMAP
COUT
B1 (G1)
A3 C2
A1 (G4) COUT0 I4
B2 B3 S3
B0 (F2) I3
A2 A0 (F1)
A3 O
I2
ADD (F3)
C2
I1
CARRY MODE
CIN

FMAP
ADDSUB-FG-CI
C1 I4
CY4_13 S2 B2 S2
I3
A2 O
I2
S2 C1
I1
XOR3
S1

CY4 S1
B1 XOR3
B1 (G1) COUT
A1 C0 FMAP
A1 (G4) COUT0
B0 B0 (F2) I4
A0 B1 S1
A0 (F1) I3
A1 O
ADD (F3) I2
C0
CARRY MODE
CIN I1

ADDSUB-FG-CI
FMAP
C_IN
CY4_13 S0 I4
B0 S0
I3
A0 O
S0 I2
C_IN
CY4 XOR3 I1
A[7:0]
COUT
B1(G1)
B[7:0]
A1 (G4) COUT0
B0 (F2)
CI A0 (F1)
ADD (F3)

CARRY MODE
CIN
X4333

FORCE-F1

CY4_39

Figure 3-10 ADD8 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 3-19

Libraries Guide, Release M1.5

OFL

XOR2

CO RLOC=R0C0.LC3
B7 CY_MUX
FMAP
I7 S FMAP
A7 0 1 I4
DI CI I4 I3 0
S7
XOR2
ADD I3 0
I7 I2
B7 I2
C6 I1
S7 A7 I1
RLOC=R0C1.LC3
XOR2
C6 RLOC=R0C0.LC3

CO RLOC=R0C0.LC2
B6 CY_MUX
FMAP
I6 S FMAP
A6 0 1 I4
DI CI I4 I3 0
S6
XOR2
ADD I3 0
I6 I2
B6 I2
C5 I1
S6 A6 I1
RLOC=R0C1.LC2
XOR2
C5 RLOC=R0C0.LC2

CO RLOC=R0C0.LC1
B5 CY_MUX
FMAP
I5 S FMAP
A5 0 1 I4
CI I4 I3 0
S5
XOR2 DI
ADD I3 0
I5 I2
B5 I2
C4 I1
S5 A5 I1
RLOC=R0C1.LC1
XOR2 RLOC=R0C0.LC1
C4

CO RLOC=R0C0.LC0 FMAP
B4 CY_MUX
I4 S FMAP
A4 0 1 I4
CI I4 I3 0
S4
XOR2 DI
ADD I3 0
I4 I2
B4 I2
C3 I1
S4 A4 I1
RLOC=R0C1.LC0
XOR2 RLOC=R0C0.LC0
C3

CO RLOC=R1C0.LC3 FMAP
B3 CY_MUX
I3 S FMAP
A3 0 1 I4
CI I4 I3 0
S3
XOR2 DI
ADD I3 0
I3 I2
B3 I2
C2 I1
S3 A3 I1
RLOC=R1C1.LC3
XOR2 RLOC=R1C0.LC3
C2

CO RLOC=R1C0.LC2
B2 CY_MUX
FMAP
I2 S FMAP
A2 0 1 I4
CI I4 I3 0
S2
XOR2 DI
ADD I3 0
I2 I2
B2 I2
C1 I1
S2 A2 I1
RLOC=R1C1.LC2
XOR2 RLOC=R1C0.LC2
C1

CO RLOC=R1C0.LC1
B1
FMAP
I1 CY_MUX
A1
S FMAP I4
0 1
I4 I3 0
S1
XOR2 DI CI
ADD I3 0
I1 I2
B1 I2
C0 I1
S1 A1 I1
RLOC=R1C1.LC1
XOR2 RLOC=R1C0.LC1
C0

CO RLOC=R1C0.LC0
B0 FMAP
I0 CY_MUX
A0 S FMAP I4
0 1
I4 I3 0
S0
XOR2 DI CI
ADD I3 0
I0 I2
B0 I2
C_IN I1
A[7:0] S0 A0 I1
RLOC=R1C1.LC0
B[7:0] XOR2
C_IN RLOC=R1C0.LC0
S[7:0]

COUT
CI
INIT
CY_INIT
RLOC=R2C0.LC3

X7677

Figure 3-11 ADD8 Implementation XC5200

3-20 Xilinx Development System

Design Elements (ADD4, 8, 16)

OFL

XORCY

O RLOC=R0C0.S1
B7 I7 MUXCY
A7
S FMAP
0 1
DI CI I4
XOR2 I7
I3 0
B7 I2
S7 A7 I1

XORCY
C6 RLOC=R0C0.S1

LO RLOC=R0C0.S1
B6 I6 MUXCY_L FMAP
S
A6 0 1 I4
XOR2
DI CI
I3 0
I6
B6 I2
S6 A6 I1

XORCY RLOC=R0C0.S1
C5

LO RLOC=R1C0.S1
B5 FMAP
I5 MUXCY_L
S
A5 0 1 I4
CI I3 0
I5
DI
XOR2 B5 I2
A5 I1
S5
RLOC=R1C0.S1
XORCY
C4

LO RLOC=R1C0.S1 FMAP
B4 I4 S MUXCY_L I4
A4 0 1 I4
I3 0
DI CI B4
XOR2 I2
A4 I1
S4
RLOC=R1C0.S1
XORCY
C3

FMAP
LO RLOC=R2C0.S1
B3 I3 MUXCY_L I4
S I3
A3 0 1 I3 0
DI CI B3
XOR2 I2
A3 I1

S3 RLOC=R2C0.S1
XORCY
C2

FMAP
LO RLOC=R2C0.S1 I4
B2 I2 MUXCY_L I2
S I3 0
A2 0 1 B2 I2
DI CI A2
XOR2 I1

S2 RLOC=R2C0.S1

XORCY
C1

FMAP
LO RLOC=R3C0.S1 I4
B1 MUXCY_L I3 0
I1
I1 S B1
A1 0 1 I2
DI CI A1 I1
XOR2

RLOC=R3C0.S1
S1

XORCY
C0
FMAP
I4
LO RLOC=R3C0.S1 I0
B0 I3 0
I0 MUXCY_L B0
S I2
A0 0 1 A0 I1
DI CI
XOR2
RLOC=R3C0.S1
A[7:0] S0
B[7:0] XORCY
S[7:0]

CI X8687

Figure 3-12 ADD8 Implementation Virtex

Libraries Guide, Release M1.5 3-21

Libraries Guide, Release M1.5

S3
A3
B3
AND3B2 OFL
OR2

AND3B1

XOR2

S1
AND2
OR2 XOR2

AND2

OR3 XOR2
AND3
CI CI_ORO

OR2
AND3
GND

A0
KEEP AND2
X0

B0 XOR2 S3
AND3
XOR2
OR4

A1
KEEP AND4
X1

B1 XOR2

AND4
A2

KEEP AND2
X2

XOR2
B2 AND3

AND4
OR5

KEEP
X3 AND5

XOR2
B3

AND5

X7613

Figure 3-13 ADD4 Implementation XC9000

3-22 Xilinx Development System

Design Elements (ADD4, 8, 16)

S3_0
CI ADD4X2
CI
A0 A0
A1 A1 S[7:0]
A2 A2 S0
A[7:0] A3 S0
A3
S1
S1
S2
B0 S2
B0 S3
B1 B1
S3
B2
B[7:0] B2
B3 B3
CO

ADD4

CI
A4 A0
A5 A1
A6 A2 S4
A7 S0
A3
S1
S5
S6
B4 S2
B0 S7
B5 B1
S3
B6 B2
B7 B3 CO
CO OFL
CO

X7771
S7_4

Figure 3-14 ADD8 Implementation XC9000

Libraries Guide, Release M1.5 3-23

Libraries Guide, Release M1.5

ADSU1
1-Bit Cascadable Adder/Subtracter with Carry-In and Carry-Out

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

CI When the ADD input is High, two 1-bit words (A0 and B0) are added with a carry-in
A0 (CI), producing a 1-bit output (S0) and a carry-out (CO). When the ADD input is Low,
S0 B0 is subtracted from A0, producing a result (S0) and borrow (CO). In add mode, CO
B0 represents a carry-out, and CO and CI are active-High. In subtract mode, CO repre-
ADD CO sents a borrow, and CO and CI are active-Low.
X4035

Inputs Outputs

A0 B0 CI S0 CO
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
Add Function, ADD=1

Inputs Outputs
A0 B0 CI S0 CO
0 0 0 1 0
0 1 0 0 0
1 0 0 0 1
1 1 0 1 0
0 0 1 0 1
0 1 1 1 0
1 0 1 1 1
1 1 1 0 1
Subtract Function, ADD=0

3-24 Xilinx Development System

Design Elements (ADSU1)

A0
B0
ADD
AND3

AND3

AND3B2
OR5

AND3B2

AND2
SO

XOR2

AND3B3

AND3B1

OR4

AND3B1

AND3B1 X8144

Figure 3-15 ADSU1 Implementation XC9000

Libraries Guide, Release M1.5 3-25

Libraries Guide, Release M1.5

ADSU4, 8, 16
4-, 8-, 16-Bit Cascadable Adders/Subtracters with Carry-In, Carry-
Out, and Overflow

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CI When the ADD input is High, ADSU4, ADSU8, and ADSU16 add two words and a
A0 carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADSU4
A1 ADSU4
adds two 4-bit words (A3 – A0 and B3 – B0) and a CI, producing a 4-bit sum output
A2
A3
S0 (S3 – S0) and CO or OFL. ADSU8 adds two 8-bit words (A7 – A0 and B7 – B0) and a CI
S1
producing, an 8-bit sum output (S7 – S0) and CO or OFL. ADSU16 adds two 16-bit
S2
B0
S3 words (A15 – A0 and B15 – B0) and a CI, producing a 16-bit sum output (S15 – S0) and
B1
B2
CO or OFL.
B3
OFL When the ADD input is Low, ADSU4, ADSU8, and ADSU16 subtract Bz – B0 from
ADD
CO Az– A0, producing a difference output and CO or OFL. ADSU4 subtracts B3 – B0 from
X4379 A3 – A0, producing a 4-bit difference (S3 – S0) and CO or OFL. ADSU8 subtracts B7 –
B0 from A7 – A0, producing an 8-bit difference (S7 – S0) and CO or OFL. ADSU16
CI
subtracts B15 – B0 from A15 – A0, producing a 16-bit difference (S15 – S0) and CO or
OFL.
A[7:0]
ADSU8
S[7:0] In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low.
B[7:0] OFL is active-High in add and subtract modes.
OFL
ADD ADSU4, ADSU8, and ADU16 are implemented in the XC4000 and Spartans using
CO
carry logic and relative location constraints, which assure most efficient logic place-
X4380 ment.
ADSU4, ADSU8, and ADSU16 CI and CO pins do not use the CPLD carry chain.
CI

A[15:0]
ADSU16
Unsigned Binary Versus Twos Complement
S[15:0]
B[15:0] ADSU4, ADSU8, ADSU16 can operate, respectively, on either 4-, 8-, 16-bit unsigned
OFL binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are inter-
ADD
CO preted as unsigned binary, the result can be interpreted as unsigned binary. If the
inputs are interpreted as twos complement, the output can be interpreted as twos
X4381
complement. The only functional difference between an unsigned binary operation
and a twos-complement operation is how they determine when “overflow” occurs.
Unsigned binary uses CO, while twos complement uses OFL to determine when
“overflow” occurs.
With adder/subtracters, either unsigned binary or twos-complement operations
cause an overflow. If the result crosses the overflow boundary, an overflow is gener-
ated. Similarly, when the result crosses the carry-out boundary, a carry-out is gener-
ated. The following figure shows the ADSU carry-out and overflow boundaries.

3-26 Xilinx Development System

Design Elements (ADSU4, 8, 16)

Overflow

-127 127

128 127

TW
D
NE

OS
SIG

CO
UN
Y
ED BI NAR
E N T OR

MPL E MENT O
SIGN
ED BIN
LEM

IGN

AR
MP

R
Y
U
CO

SI
G
S
N
255
O ED
TW 0
-1 0

Carry-Out
X4720

Figure 3-16 ADSU Carry-Out and Overflow Boundaries

Unsigned Binary Operation

For unsigned binary operation, ADSU4 can represent numbers between 0 and 15,
inclusive; ADSU8 between 0 and 255, inclusive; ADSU16 between 0 and 65535, inclu-
sive. In add mode, CO is active (High) when the sum exceeds the bounds of the
adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low
when the difference exceeds the bounds.
An unsigned binary “overflow” that is always active-High can be generated by gating
the ADD signal and CO as follows.
unsigned overflow = CO XNOR ADD
OFL is ignored in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ADSU4 can represent numbers between -8 and +7,
inclusive; ADSU8 between -128 and +127, inclusive; ADSU16 between -32768 and
+32767, inclusive. If an addition or subtraction operation result exceeds this range, the
OFL output goes High.
CO is ignored in twos-complement operation.

Libraries Guide, Release M1.5 3-27

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the ADSU4 (4-bit), ADSU8 (8-bit), and ADSU16 (16-bit) topology for XC4000
and Spartan series devices.

OFL
A 15 B 15 S 15

A 14 B 14 S 14
CO A 13 B 13 S 13

OFL A 12 B 12 S 12
CO A 7B 7 S7 A 11 B 11 S 11

OFL A 6B 6 S6 A 10 B 10 S 10
A3B3 S3 A 5B 5 S5 A 9B 9 S9

A2B2 S2 A 4B 4 S4 A 8B 8 S8
A1B1 S1 A 3B 3 S3 A 7B 7 S7
A0B0 S0 A 2B 2 S2 A 6B 6 S6
CI A 1B 1 S1 A 5B 5 S5
A 0B 0 S0 A 4B 4 S4
CI A 3B 3 S3
4-Bit
A 2B 2 S2
A 1B 1 S1
8-Bit
A 0B 0 S0
CI

X8215 16-Bit

3-28 Xilinx Development System

Design Elements (ADSU4, 8, 16)

XC5200 Topology
This is the ADSU8 (8-bit) and ADSU16 (16-bit) topology for XC5200 devices.

OFL*
LC0

A 15 S 15
LC3 LC3
B 15 CO
A 14 S 14
LC2 LC2
B 14
A 13 S 13
LC1 LC1
B 13
OFL* A 12 S 12
LC0 LC0 LC0
B 12

A7 S7 A 11 S 11
LC3 LC3 LC3 LC3
B7 B 11
A6 S6 A 10 S 10
LC2 LC2 LC2 LC2
B6 B 10
A5 S5 A9 S9
LC1 LC1 LC1 LC1
B5 B9
A4 S4 A8 S8
LC0 LC0 LC0 LC0
B4 B8

A3 S3 A7 S7
LC3 LC3 LC3 LC3
B3 B7
A2 S2 A6 S6
LC2 LC2 LC2 LC2
B2 B6
A1 S1 A5 S5
LC1 LC1 LC1 LC1
B1 B5
A0 S0 A4 S4
LC0 LC0 LC0 LC0
B0 B4

CY_INIT A3 S3
LC3 LC3 LC3
B3
A2 S2
LC2 LC2
8-Bit B2
A1 S1
LC1 LC1
B1
A0 S0
LC0 LC0
B0

CY_INIT
LC3

X8210 16-Bit

Libraries Guide, Release M1.5 3-29

Libraries Guide, Release M1.5

S[7:0]

ADD
CI
S0 S4

A0 A0_0 XNOR4 A4 A0_4 XNOR4

B0 B4
AND2B1 AND2B1
M2_1 M2_1
A1_0 SUB_C0 D0 A1_4 SUB_C4 D0
A1CI O C0 A1C3 O C4
D1 D1
OR2B1 OR2 OR2B1 OR2
AND2 S0 C0 AND2 S0 C4
A2_0 A2_4
A2CI A2C3
OR2 OR2
AND2 ADD_C0 AND2 ADD_C4
OR2 OR2
A3_0 A3_4
AND2 AND2

S1 S5

A1 A0_1 XNOR4 A5 A0_5 XNOR4

B1 B5
AND2B1 AND2B1
M2_1 M2_1
A1_1 SUB_C1 D0 A1_5 SUB_C5 D0
A1C0 O C1 A1C4 O C5
D1 D1
OR2B1 OR2 OR2B1 OR2
AND2 S0 C1 AND2 S0 C5
A2_1 A2_5
A2C0 A2C4
OR2 OR2
AND2 ADD_C1 AND2 ADD_C5
A3_1 OR2 OR2
A3_5
AND2 AND2

S2 S6

A2 A0_2 XNOR4 A6 A0_6 XNOR4

B2 B6
AND2B1 AND2B1
M2_1 M2_1
A1_2 SUB_C2 D0 A1_6 SUB_C6 D0
A1C1 O C2 A1C5 O C6
D1 D1
OR2B1 OR2 OR2B1 OR2
AND2 S0 C2 AND2 S0 C6
A2_2 A2_6
A2C1 A2C5
OR2 OR2
AND2 ADD_C2 AND2 ADD_C6
OR2 OR2
A3_2 A3_6
AND2 AND2

S3 S7

A3 A0_3 XNOR4 A7 A0_7 XNOR4

B3 B7
AND2B1 AND2B1
M2_1 M2_1
A1_3 SUB_C3 D0 A1_7 SUB_CO D0
A1C2 O C3 A1C6 O C0
D1 D1
OR2B1 OR2 OR2B1 OR2
AND2 S0 C3 AND2 S0 C0
A2_3 A2_7
A2C2 A2C6
OR2 OR2
AND2 ADD_C3 AND2 ADD_CO
OR2 OR2
A3_3 A3_7
AND2 AND2
A[7:0]

B[7:0] B_M
XNOR2
AXB
XNOR2 OFL
AABXS
AAB
X7617 AND2
XOR2
AND2

Figure 3-17 ADSU8 Implementation XC3000

3-30 Xilinx Development System

Design Elements (ADSU4, 8, 16)

OFOR1 FMAP
A7
ADD
I4
B7 AND2
B7_M1 B7
OFOR2 I3 OFL
O
A7
I2
XNOR2
AND2 OR3 C7
I1
OFOR3

RLOC=R0C0.F
AND2 OFL

B7
B7_M2
XOR2
COR1

XNOR2
RLOC=R0C0 AND2
CY4 COR2 CO
COUT
B1(G1)
AND2
A1(G4)
OR3 FMAP
COUT0 COR3
ADD
B0(F2) I4
AND2 B7
A0(F1) I3 CO
O
A7
ADD(F3) I2
C7
CARRY MODE
I1
CIN
C7 RLOC=R0C0.G

EXAMINE-CI

A7 CY4_42
S[7:0]
B7
S7

RLOC=R1C0
S7
CY4 XNOR4 FMAP
COUT ADD
B1(G1) I4
C6 B7
A1(G4) I3 S7
COUT0 O
B6 A7
I2
B0(F2)
A6 C6
I1
A0(F1)

ADD(F3)
RLOC=R1C0.G
CARRY MODE
CIN
FMAP
ADD
I4

ADDSUB-FG-CI C5 B6
I3 S6
O
CY4_12 A6
I2
S6
C5
I1
S6
XNOR4
RLOC=R1C0.F

RLOC=R2C0
S5
XNOR4
CY4
COUT
B5
B1(G1) FMAP
A5 C4
A1(G4) COUT0 ADD
I4
B4
B0(F2) B5
I3 S5
A4 O
A0(F1) A5
I2
ADD(F3) C4
I1
CARRY MODE
CIN
RLOC=R2C0.G

FMAP
ADDSUB-FG-CI C3
ADD
I4
CY4_13
S4 B4
I3 S4
O
A4
I2
S4
C3
XNOR4 I1

S3 RLOC=R2C0.F

RLOC=R3C0 S3
CY4 XNOR4

COUT
B3
B1(G1) FMAP
A3 C2
A1(G4) COUT0 ADD
I4
B2
B0(F2) B3
I3 S3
A2 O
A0(F1) A3
I2
ADD(F3) C2
I1
CARRY MODE
CIN
RLOC=R3C0.G

FMAP
ADDSUB-FG-CI C1
ADD
I4
CY4_13 B2
S2 I3 S2
O
A2
I2
S2
C1
XNOR4 I1

S1 RLOC=R3C0.F

RLOC=R4C0 S1
CY4 XNOR4

COUT
B1
B1(G1)
A1
A1(G4) COUT0
C0 FMAP
B0
B0(F2) ADD
I4
A0
A0(F1) B1
I3 S1
O
ADD(F3) A1
I2
CARRY MODE C0
I1
CIN

RLOC=R4C0.G

C_IN
ADDSUB-FG-CI
FMAP
CY4_13
S0 ADD
I4
B0
I3 S0
S0 O
A0
A[7:0] RLOC=R5C0 XNOR4 I2
C_IN
CY4 I1

COUT
B[7:0] B1(G1) RLOC=R4C0.F

A1(G4) COUT0
ADD
B0(F2)
CI
A0(F1)

ADD(F3)

CARRY MODE
CIN

FORCE-F1

CY4_39 X7429

Figure 3-18 ADSU8 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 3-31

Libraries Guide, Release M1.5

OFL

XOR2

CO RLOC=R0C0.LC3
CY_MUX
FMAP
B7 I7 S FMAP
0 1 I4
A7 S7
DI CI I4 I3 0
XOR3 ADD I7
I3 0 I2
B7 I2
C6 I1
S7 A7 I1
RLOC=R0C1.LC3
XOR2
C6 RLOC=R0C0.LC3

CO RLOC=R0C0.LC2
CY_MUX
FMAP
B6 I6 S FMAP
0 1 I4
A6 S6
DI CI I4 I3 0
XOR3 ADD I6
I3 0 I2
B6 I2
C5 I1
S6 A6 I1
RLOC=R0C1.LC2
XOR2
C5 RLOC=R0C0.LC2

CO RLOC=R0C0.LC1
CY_MUX
FMAP
B5 I5 S FMAP
0 1 I4
A5 S5
DI CI I4 I3 0
XOR3 ADD I5
I3 0 I2
B5 I2
C4 I1
S5 A5 I1
RLOC=R0C1.LC1
XOR2 RLOC=R0C0.LC1
C4

CO RLOC=R0C0.LC0 FMAP
I4 CY_MUX
B4 S FMAP
0 1 I4
A4 S4
DI CI I4 I3 0
XOR3 ADD I4
I3 0 I2
B4 I2
C3 I1
S4 A4 I1
RLOC=R0C1.LC0
XOR2 RLOC=R0C0.LC0
C3

CO RLOC=R1C0.LC3 FMAP
I3 CY_MUX
B3 S FMAP
0 1 I4
A3 S3
DI CI I4 I3 0
XOR3 ADD I3
I3 0 I2
B3 I2
C2 I1
S3 A3 I1
RLOC=R1C1.LC3
XOR2 RLOC=R1C0.LC3
C2

CO RLOC=R1C0.LC2
CY_MUX
FMAP
B2 I2 S FMAP
0 1 I4
A2 S2
DI CI I4 I3 0
XOR3 ADD I2
I3 0 I2
B2 I2
C1 I1
S2 A2 I1
RLOC=R1C1.LC2
XOR2 RLOC=R1C0.LC2
C1

CO RLOC=R1C0.LC1 FMAP
CY_MUX
B1 I1 S FMAP
0 1 I4
A1 I4 S1
DI CI I3 0
XOR3 ADD I3 0
I1 I2
B1 I2
C0 I1
S1 A1 I1
RLOC=R1C1.LC1
XOR2 RLOC=R1C0.LC1
C0

CO RLOC=R1C0.LC0
SUB FMAP
CY_MUX
B0 INV I0 S FMAP
0 1 I4
A0 I4 S0
DI CI I3 0
XOR3 ADD I3 0
I0 I2
B0 I2
C_IN I1
A[7:0] S0 A0 I1
RLOC=R1C1.LC0
B[7:0] XOR2
C_IN RLOC=R1C0.LC0
S[7:0]

ADD

COUT
CI
INIT
CY_INIT
RLOC=R2C0.LC3

X7676

Figure 3-19 ADSU8 Implementation XC5200

3-32 Xilinx Development System

Design Elements (ADSU4, 8, 16)

OFL

XORCY

O RLOC=R0C0.S1
SUB7
B7 INV I7 S MUXCY_L FMAP
A7 0 1
DI CI I4
XOR3 ADD I7
I3 0
B7 I2
S7 A7 I1

XORCY
C6 RLOC=R0C0.S1

LO RLOC=R0C0.S1
SUB6
B6 INV I6 S
MUXCY_L FMAP
0 1
A6 I4
XOR3
DI CI ADD I3 0
I6
B6 I2
S6 A6 I1

XORCY RLOC=R0C0.S1
C5

LO RLOC=R1C0.S1
SUB5 FMAP
B5 INV I5 MUXCY_L
S
0 1 I4
A5 ADD I5
DI CI I3 0
XOR3 B5 I2
A5 I1
S5
RLOC=R1C0.S1
XORCY
C4

SUB4
LO RLOC=R1C0.S1 FMAP
B4 INV I4 S MUXCY_L I4
A4 0 1 ADD I3 0
I4
DI CI B4
XOR3 I2
A4 I1
S4
RLOC=R1C0.S1
XORCY
C3

FMAP
SUB3
LO RLOC=R2C0.S1
I3 MUXCY_L I4
B3 INV S
ADD I3
0 1 I3 0
A3 B3
DI CI I2
XOR3
A3 I1

S3 RLOC=R2C0.S1
XORCY
C2

FMAP
LO RLOC=R2C0.S1
SUB2 I4
B2 INV I2 MUXCY_L ADD I2
S I3 0
A2 0 1 B2 I2
DI CI A2
XOR3 I1

S2 RLOC=R2C0.S1

XORCY
C1

FMAP
LO RLOC=R3C0.S1 I4
SUB1 ADD I1
B1 INV I1 MUXCY_L I3 0
S B1
0 1 I2
A1 A1
DI CI I1
XOR3

RLOC=R3C0.S1
S1

XORCY
C0
FMAP
I4
SUB0
LO RLOC=R3C0.S1 ADD I0
I3 0
I0 MUXCY_L B0
B0 INV S I2
A0 0 1 A0 I1
DI CI
XOR3
RLOC=R3C0.S1
A[7:0] S0
B[7:0] XORCY
S[7:0]
ADD
CI X8686

Figure 3-20 ADSU8 Implementation Virtex

Libraries Guide, Release M1.5 3-33

Libraries Guide, Release M1.5

CI ADSU1
CI
A0 A0
S0
S0
B0 B0
ADD CO
S0

ADSU1
CI
A1 A0
S0
S1
B1 B0
ADD CO
S1

ADSU1

CI
A2 A0
S0
S2
B2 B0 OFL_POS_ADD
ADD CO
S2

AND4B2

ADSU1 OFL_NEG_ADD

CI
A3 A0 OFL_OUT
S0
S3
B3 AND4B1 OFL
B0
ADD CO
OR4
S3 CO

AND4B2
OFL_POS_SUB

ADD
AND4B3
OFL_NEG_SUB
X7615

Figure 3-21 ADSU4 Implementation XC9000

S3_0
CI ADSU4X2
CI
A0 A0
A1 A1 S[7:0]
A2 A2 S0
A[7:0] A3 S0
A3
S1
S1
S2
B0 S2
B0 S3
B1 B1
S3
B2
B[7:0] B2
B3 B3
CO
ADD

ADSU4

CI
A4 A0
A5 A1
A6 A2 S4
A7 S0
A3
S1
S5
S6
B4 S2
B0 S7
B5 B1
S3
B6 B2
B7 B3 OFL
ADD
CO OFL
ADD CO
S7_4
X7774

Figure 3-22 ADSU8 Implementation XC9000

3-34 Xilinx Development System

Design Elements (AND2-9)

AND2-9
2- to 9-Input AND Gates with Inverted and Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

AND2, Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
AND2B1,
AND2B2,
AND3,
AND3B1,
AND3B2,
AND3B3,
AND4
AND4B1,
AND4B2,
AND4B3,
AND4B4
AND5, Primitive Primitive Primitive Macro Primitive Primitive Primitive Primitive
AND5B1,
AND5B2,
AND5B3,
AND5B4,
AND5B5
AND6, Macro Macro Macro Macro Primitive Macro Macro Macro
AND7,
AND8,
AND9

Libraries Guide, Release M1.5 3-35

Libraries Guide, Release M1.5

AND2 AND3 AND4 AND5 AND6

AND2B1 AND3B1 AND4B1 AND5B1 AND7

AND2B2 AND3B2 AND4B2 AND5B2

AND3B3 AND4B3 AND5B3 AND8

AND4B4 AND5B4

X8030 AND5B5 AND9

Figure 3-23 AND Gate Representations

The AND function is performed in the Configurable Logic Block (CLB) function
generators for XC3000, XC4000, XC5200, and Spartans.
AND functions of up to five inputs are available in any combination of inverting and
non-inverting inputs. AND functions of six to nine inputs are available with only non-
inverting inputs. To make some or all inputs inverting, use external inverters. Because
each input uses a CLB resource in FPGAs, replace functions with unused inputs with
functions having the appropriate number of inputs.
Refer to “AND12, 16” for information on additional AND functions for the XC5200
and Virtex.

3-36 Xilinx Development System

Design Elements (AND2-9)

I4
I3 I35
I2
I1 AND3 O
I0
AND3

X8113

Figure 3-24 AND5 Implementation XC5200

I7
I6
I47
I5
I4
I3 AND4
I2 O
I1
I0
AND5

Figure 3-25 AND8 Implementation XC3000

I7
I6
I47
I5
I4
AND4 O
I3
I2 I13
AND3
I1
AND3
I0

X8115

Figure 3-26 AND8 Implementation XC4000, Spartans

FMAP
I7 CO I7 I4
I6 CY MUX I6 S1
S1 S I3 O
I5 0 1 I5
I2
I4 DI CI I4
I1
AND4

FMAP
I3 CO I3 I4
I2 CY MUX I2 S0
S0 S I3 O
I1 0 1 I1
I2
I0 DI CI I0
I1
AND4

CIN
GND

VCC
COUT
INIT
CY INIT X8116

Figure 3-27 AND8 Implementation XC5200

Libraries Guide, Release M1.5 3-37

Libraries Guide, Release M1.5

FMAP
I4
I3 O
S1 O
I2
S0
I1
I7
I6 RLOC=R0C0.S0
S1
I5
I4
AND4 FMAP
I7
I4
I6
O I3 S1
I5 O
I2
I4
AND2 I1
I3
RLOC=R0C0.S1
I2
S0
I1
I0 FMAP
AND4 I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8702 RLOC=R0C0.S1

Figure 3-28 AND8 Implementation Virtex

3-38 Xilinx Development System

Design Elements (AND12, 16)

AND12, 16
12- and 16-Input AND Gates with Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

AND12, N/A N/A N/A Macro N/A N/A N/A Macro
AND16

AND12 and AND16 functions are performed in the Configurable Logic Block (CLB)
function generator.
The 12- and 16-input AND functions are available only with non-inverting inputs. To
invert all of some inputs, use external inverters.
Refer to “AND2-9” for information on more AND functions.

AND12 I11 CO
CY_MUX
X8192 I10 RLOC=R0C0.LC3
S2 S
I9 0 1
FMAP
I8 DI CI
I11
I4
AND4
C1 I10
I3 S2
I9 O
I2
I8
I1
I7 CO
CY_MUX
RLOC=R0C0.LC3
I6 RLOC=R0C0.LC2
S1 S
I5 0 1
FMAP
I4 DI CI
I7
AND4 I4
C0 I6
I3 S1
I5 O
I2
I4
I1
I3 CO
AND16 CY_MUX
RLOC=R0C0.LC2
I2 RLOC=R0C0.LC1
X8193 S0 S
I1 0 1

I0 DI CI FMAP

AND4 I3
I4
I2
I3 S0
I1 O
I2
CIN I0
I1
GND
RLOC=R0C0.LC1
VCC

COUT

INIT

CY_INIT
RLOC=R0C0.LC0

X6445

Figure 3-29 AND12 Implementation XC5200

Libraries Guide, Release M1.5 3-39

Libraries Guide, Release M1.5

FMAP
I4
S2
I3 O
S1 O
I2
S0
I1

RLOC=R0C0.S0

I11
I10 FMAP
S2 I11
I9 I4
I10
I8 I3 S2
I9 O
AND4 I2
I8
I1
I7
I6 RLOC=R0C0.S0
S1 O
I5
I4
AND3 FMAP
AND4
I7
I4
I3 I6
I3 S1
I2 I5 O
S0 I2
I1 I4
I1
I0
AND4 RLOC=R0C0.S1

FMAP
I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8705 RLOC=R0C0.S1

Figure 3-30 AND12 Implementation Virtex

3-40 Xilinx Development System

Design Elements (AND12, 16)

FMAP

I15 CO I15
CY_MUX I4
I14 RLOC=R0C0.LC3 I14
S3 S I3 S3
I13 0 1 I13 O
I2
I12 DI CI I12 I1
AND4
C2 RLOC=R0C0.LC3

FMAP

I11 CO I11
CY_MUX I4
I10 RLOC=R0C0.LC2 I10
S2 S I3 S2
I9 0 1 I9 O
I2
I8 DI CI I8
I1
AND4
RLOC=R0C0.LC2
C1

FMAP

I7 CO I7
CY_MUX I4
I6 RLOC=R0C0.LC1 I6
S1 S I3 S1
I5 0 1 I5 O
I2
I4 DI CI I4
I1
AND4
RLOC=R0C0.LC1
C0

FMAP
I3 CO
CY_MUX I3
I2 RLOC=R0C0.LC0 I4
S0 S I2
I1 0 1 I3 S0
I1 O
I0 DI CI I2
I0
AND4 I1

RLOC=R0C0.LC0
CIN
GND
VCC

COUT
INIT
CY_INIT
RLOC=R1C0.LC3 X6450

Figure 3-31 AND16 Implementation XC5200

Libraries Guide, Release M1.5 3-41

Libraries Guide, Release M1.5

FMAP

I15
I15 O I4
MUXCY I14
I14 RLOC=R0C0.S1 I3 S3
S3 S I13 O
I13 0 1 I2
DI CI I12
I12 I1
AND4
RLOC=R0C0.S1
C2

FMAP

I11
I11 LO I4
MUXCY_L I10
I10 RLOC=R0C0.S1 I3 S2
S2 S I9 O
I9 0 1 I2
I8
I8 DI CI I1
AND4
RLOC=R0C0.S1
C1

FMAP

I7
I7 LO I4
MUXCY_L I6
I6 RLOC=R1C0.S1 I3 S1
S1 S I5 O
I5 0 1 I2
I4
I4 DI CI I1
AND4
RLOC=R1C0.S1
C0

FMAP
I3 LO I3
MUXCY_L I4
I2 RLOC=R1C0.S1 I2
S0 S I3 S0
I1 0 1 I1 O
I2
I0 DI CI I0
I1
AND4

RLOC=R1C0.S1

CIN

GND
VCC

X8708

Figure 3-32 AND16 Implementation Virtex

3-42 Xilinx Development System

Design Elements (BRLSHFT4, 8)

BRLSHFT4, 8
4-, 8-Bit Barrel Shifters

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

I0 BRLSHFT4 O0
BRLSHFT4, a 4-bit barrel shifter, can rotate four inputs (I3 – I0) up to four places. The
I1 O1 control inputs (S1 and S0) determine the number of positions, from one to four, that
I2 O2 the data is rotated. The four outputs (O3 – O0) reflect the shifted data inputs.
I3 O3
BRLSHFT8, an 8-bit barrel shifter, can rotate the eight inputs (I7 – I0) up to eight
S0 places. The control inputs (S2 – S0) determine the number of positions, from one to
S1
eight, that the data is rotated. The eight outputs (O7 – O0) reflect the shifted data
inputs.
X3856

I0 BRLSHFT8 O0
I1
Inputs Outputs
O1
I2 O2
I3 O3
S1 S0 I0 I1 I2 I3 O0 O1 O2 O3
I4 O4
I5
0 0 a b c d a b c d
O5
I6 O6 0 1 a b c d b c d a
I7 O7
1 0 a b c d c d a b
S0
1 1 a b c d d a b c
S1
S2
BRLSHFT4 Truth Table
X3857

Inputs Output

S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 a b c d e f g h a b c d e f g h
0 0 1 a b c d e f g h b c d e f g h a
0 1 0 a b c d e f g h c d e f g h a b
0 1 1 a b c d e f g h d e f g h a b c
1 0 0 a b c d e f g h e f g h a b c d
1 0 1 a b c d e f g h f g h a b c d e
1 1 0 a b c d e f g h g h a b c d e f
1 1 1 a b c d e f g h h a b c d e f g
BRLSHFT8 Truth Table

Libraries Guide, Release M1.5 3-43

Libraries Guide, Release M1.5

M2_1
I0 D0 M2_1
O M01 D0 M2_1
D1 O MO0 D0
D1 O O0
S0 M01 D1
S0 MO0
S0 O0

M2_1
I1 D0 M2_1
O M12 D0 M2_1
D1 O MO1 D0
D1 O O1
S0 M12 D1
S0 MO1
S0 O1

M2_1
I2 D0 M2_1
O M23 D0 M2_1
D1 O MO2 D0
D1 O O2
S0 M23 D1
S0 MO2
S0 O2

M2_1
I3 D0 M2_1
O M34 D0 M2_1
D1 O MO3 D0
D1 O O3
S0 M34 D1
S0 MO3
S0 O3

M2_1
I4 D0 M2_1
O M45 D0 M2_1
D1 O MO4 D0
D1 O O4
S0 M45 D1
S0 MO4
S0 O4

M2_1
I5 D0 M2_1
O M56 D0 M2_1
D1 O MO5 D0
D1 O O5
S0 M56 D1
S0 MO5
S0 O5

M2_1
I6 D0 M2_1
O M67 D0 M2_1
D1 O MO6 D0
D1 O O6
S0 M67 D1
S0 MO6
S0 O6

M2_1
I7 D0 M2_1
O M70 D0 M2_1
D1 O MO7 D0
D1 O O7
S0 S0 M70 D1
S0 MO7
S1 S0 O7
S2
X8143

Figure 3-33 BRLSHFT8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

3-44 Xilinx Development System

Design Elements (BSCAN)

BSCAN
Boundary Scan Logic Control Circuit

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive N/A

XC4000, Spartans The BSCAN symbol indicates that boundary scan logic should be enabled after the
TDI BSCAN TDO programmable logic device (PLD) configuration is complete. It also provides optional
TMS DRCK access to some special features of the XC5200 boundary scan logic.
TCK IDLE
TDO1 SEL1 Note: For specific information on boundary scan for each architecture, refer to The
TDO2 SEL2 Programmable Logic Data Book.

X3910 To indicate that boundary scan remains enabled after configuration, connect the
BSCAN symbol to the TDI, TMS, TCK, and TDO pads. The other pins on BSCAN do
not need to be connected, unless those special functions are needed. A signal on the
XC5200
TDO1 input is passed to the external TDO output when the USER1 instruction is
BSCAN UPDATE executed; the SEL1 output goes High to indicate that the USER1 instruction is active.
SHIFT
The TDO2 and SEL2 pins perform a similar function for the USER2 instruction. The
RESET
TDI TDO DRCK output provides access to the data register clock (generated by the TAP
TMS DRCK controller). The IDLE output provides access to a version of the TCK input, which is
TCK IDLE only active while the TAP controller is in the Run-Test-Idle state. The RESET,
TDO1 SEL1
TDO2 SEL2
UPDATE, and SHIFT pins of the XC5200 BSCAN symbol represent the decoding of
the corresponding state of the boundary scan internal state machine. These functions
are not available in the XC4000 and Spartans.
X4984 If boundary scan is used only before configuration is complete, do not include the
BSCAN symbol in the design. The TDI, TMS, TCK, and TDO pins can be reserved for
user functions.

XC4000, Spartans

TDI BSCAN TDO

TMS DRCK
TCK IDLE To
TDO1 SEL1 User
From Logic
User TDO2 SEL2
Logic

X4323
XC5200

BSCAN UPDATE
SHIFT
RESET
TDI TDO
TMS DRCK
TCK IDLE
TDO1 SEL1
TDO2 SEL2

X6961

Libraries Guide, Release M1.5 3-45

Libraries Guide, Release M1.5

BSCAN_VIRTEX
Virtex Boundary Scan Logic Control Circuit

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

BSCAN_VIRTEX The BSCAN_VIRTEX symbol indicates that boundary scan logic should be enabled
UPDATE
after the programmable logic device (PLD) configuration is complete. The 4-pin JTAG
SHIFT interface (TDI, TDO, TCK, and TMS) are dedicated pins in Virtex. To use normal JTAG
RESET for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins
TDI
SEL1
on the BSCAN_VIRTEX symbol do not need to be connected, unless those special
DRCK1 functions are needed to drive an internal scan chain.
TDO1 SEL2
TDO2 DRCK2 A signal on the TDO1 input is passed to the external TDO output when the USER1
instruction is executed; the SEL1 output goes High to indicate that the USER1 instruc-
X8679 tion is active.The DRCK1 output provides USER1 access to the data register clock
(generated by the TAP controller). The TDO2 and SEL2 pins perform a similar func-
tion for the USER2 instruction and the DRCK2 output provides USER2 access to the
data register clock (generated by the TAP controller). The RESET, UPDATE, and
SHIFT pins represent the decoding of the corresponding state of the boundary scan
internal state machine. The TDI pin provides access to the TDI signal of the JTAG port
in order to shift data into an internal scan chain.
Note: For detailed information on boundary scan for Virtex, refer to the Xilinx web
site, http://www.xilinx.com.

3-46 Xilinx Development System

Design Elements (BUF)

BUF
General-Purpose Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

BUF is a general purpose, non-inverting buffer.

In FPGA architectures, BUF is usually not necessary and is removed by the parti-
X3830 tioning software (MAP). The BUF element can be preserved for reducing the delay on
a high fan-out net, for example, by splitting the net and reducing capacitive loading.
In this case, the buffer is preserved by attaching an X (explicit) attribute to both the
input and output nets of the BUF.
In CPLD architecture, BUF is usually removed, unless you inhibit optimization by
applying the OPT=OFF attribute to the BUF symbol or by using the
LOGIC_OPT=OFF global attribute.

Libraries Guide, Release M1.5 3-47

Libraries Guide, Release M1.5

BUF4, 8, 16
General-Purpose Buffers

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

BUF4, 8, 16 are general purpose, non-inverting buffers.

BUF4
In CPLD architecture, BUF4, BUF8, and BUF16 are usually removed, unless you
inhibit optimization by applying the OPT=OFF attribute to the BUF4, BUF8, or BUF16
symbol or by using the LOGIC_OPT=OFF global attribute.

O[ 7: 0]

I0 0 O1
X4614 BUF
I1 1 O1

BUF
BUF8 I2 2 O2

BUF
I3 3 O3

X4615 BUF
I4 4 O4

BUF
BUF16 I5 5 O5

BUF
I6 6 O6

BUF
X4616 I7 7 O7

BUF
I[ 7: 0]
X7776

Figure 3-34 BUF8 Implementation XC9000

3-48 Xilinx Development System

Design Elements (BUFCF)

BUFCF
Fast Connect Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

BUFCF is a single fast connect buffer used to connect the outputs of the LUTs and
some dedicated logic directly to the input of another LUT. Using this buffer implies
CLB packing. No more than four LUTs may be connected together as a group.
X3830

Libraries Guide, Release M1.5 3-49

Libraries Guide, Release M1.5

BUFE, 4, 8, 16
Internal 3-State Buffers with Active High Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

BUFE Macro Macro Macro Macro Primitive* Macro Macro Primitive
BUFE4, Macro Macro Macro Macro Macro* Macro Macro Macro
BUFE8,
BUFE16
* not supported for XC9500XL devices

BUFE BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple tristate buffers with inputs
I, I3 – I0, I7 – I0, and I15 – I0, respectively; outputs O, O3 – O0, O7 – O0, and O15 – O0,
E
respectively; and active-High output enable (E). When E is High, data on the inputs of
the buffers is transferred to the corresponding outputs. When E is Low, the output is
high impedance (Z state or Off). The outputs of the buffers are connected to horizontal
longlines in FPGA architectures.
X3790
The outputs of separate BUFE symbols can be tied together to form a bus or a multi-
plexer. Make sure that only one E is High at any one time. If none of the E inputs is
BUFE4
active-High, a “weak-keeper” circuit (FPGAs) keeps the output bus from floating but
E
does not guarantee that the bus remains at the last value driven onto it.
In XC3000, XC4000, and Spartans, the E signal in BUFE macros is implemented by
using a BUFT with an inverter on the active-Low enable (T) pin. This inverter can add
an extra level of logic to the data path. Pull-up resistors can be used to establish a
High logic level if all BUFE elements are Off.
In the XC5200 architecture, pull-ups cannot be used in conjunction with BUFT or
BUFE macros because there are no pull-ups available at the ends of the horizontal
X3797 longlines.
For XC9500 devices, BUFE output nets assume the High logic level when all
BUFE8 connected BUFE/BUFT buffers are disabled. On-chip 3-state multiplexing is not avail-
E able in XC9500XL devices.
For Virtex, BUFE elements need a PULLUP element connected to their output.
NGDBuild inserts a PULLUP element if one is not connected.

X3809
Inputs Outputs
BUFE16 E I O
E
0 X Z
1 1 1
1 0 0
X3821

3-50 Xilinx Development System

Design Elements (BUFE, 4, 8, 16)

E T T

I O

BUFT
RLOC=R0C0

X4716

Figure 3-35 BUFE Implementation XC3000, XC4000, XC5200, Spartans

O[ 7: 0]

T
I0 O0
T BUFT

I1 O1
T BUFT
I2 O2
T BUFT
I3 O3
T BUFT
I4 O4
T BUFT
I5 O5
T BUFT
I6 O6
T BUFT
I7 O7
BUFT
I[ 7: 0]
X8120
E T

INV

Figure 3-36 BUFE8 Implementation XC3000, XC4000, XC5200, Spartans

O[ 7: 0]

E
I0 O0
E BUFE

I1 O1
E BUFE
I2 O2
E BUFE
I3 O3
E BUFE
I4 O4
E BUFE
I5 O5
E BUFE
I6 O6
E BUFE
I7 O7
BUFE
I[ 7: 0]
X8119
E

Figure 3-37 BUFE8 Implementation XC9000, Virtex

Libraries Guide, Release M1.5 3-51

Libraries Guide, Release M1.5

BUFFCLK
Global Fast Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A N/A N/A

BUFFCLK (FastCLK buffer) provides the fastest way to bring a clock into the
XC4000X device. Four of these buffers are present on those devices — two on the left
X4210 edge of the die and two on the right edge.
Using BUFFCLK, you can create a very fast pin-to-pin path by driving the F input of
the CLB function generator with BUFFCLK output.
You can use BUFFCLK to minimize the setup time of input devices if positive hold
time is acceptable. Use BUFFCLK to clock the Fast Capture latch and a slower clock
buffer to capture the standard IOB flip-flop or latch. Either the Global Early buffer
(BUFGE) or the Global Low-Skew buffer (BUFGLS) can be used for the second storage
element (the one used should be the same clock as the internal related logic).
You can also use BUFFCLK to provide a fast Clock-to-Out on device output pins.
These buffers can access IOBs on one half of the die edge only. They can each drive
two of the four vertical lines accessing the IOBs on the left edge of the device or two of
the eight vertical lines accessing the IOBs on the right edge of the device. They can
only access the CLB array through single and double-length lines.
BUFFCLKs must be driven by the semi-dedicated IOBs. They are not accessible from
internal nets.

3-52 Xilinx Development System

Design Elements (BUFG)

BUFG
Global Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

BUFG, an architecture-independent global buffer, distributes high fan-out clock

signals throughout a PLD device. The Xilinx implementation software converts each
X3831 BUFG to an appropriate type of global buffer for the target PLD device.
For XC9000 designs, consult the device data sheet for the number of available global
pins.
For an XC3000 design, you can use a maximum of two BUFG symbols (assuming that
no specific GCLK or ACLK buffer is specified). For an XC4000 or Spartan series
design, you can use a maximum of eight BUFG symbols (assuming that no specific
BUFGP or BUFGS buffers are specified). For XC3000 designs, MAP always selects an
ACLK, then a GCLK. For XC4000 or Spartan series designs, it always selects a BUFGS
before a BUFGP. If you want to use a specific type of buffer, instantiate it manually.
To use a BUFG in a schematic, connect the input of the BUFG symbol to the clock
source. Depending on the target PLD family, the clock source can be an external PAD
symbol, an IBUF symbol, or internal logic. In Virtex, the BUFG cannot be driven
directly from a pad; it can be driven from an IBUFG instead. For a negative-edge clock
input, insert an INV (inverter) symbol between the BUFG output and the clock input.
The inversion is implemented at the Configurable Logic Block (CLB) or Input Output
Block (IOB) clock pin.
For XC9000 designs, BUFG is always implemented using an IOB. Connect the input of
BUFG to an IPAD or an IOPAD that represents an external signal source. Each BUFG
can drive any number of register clocks in a designs.
For XC9000 designs, the output of a BUFG may also be used as an ordinary input
signal to other logic elsewhere in the design.

Libraries Guide, Release M1.5 3-53

Libraries Guide, Release M1.5

BUFGDLL
Clock Delay Locked Loop Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

BUFGDLL BUFGDLL is a special purpose clock delay locked loop buffer for clock skew manage-
O ment. It is provided as a user convenience for the most frequently used configuration
I of elements for clock skew management. It consists of an IBUFG followed by a
CLKDLL followed by a BUFG.

X8719

3-54 Xilinx Development System

Design Elements (BUFGE)

BUFGE
Global Low Early Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A N/A N/A

Eight Global Early buffers (BUFGE), two on each corner of the device, provide an
earlier clock access than the potentially heavily loaded Global Low-Skew buffers
X4210 (BUFGLS).
BUFGE can facilitate the fast capture of device inputs using the Fast Capture latches
ILFFX and ILFLX. For fast capture, take a single clock signal and route it through both
a BUFGE and a BUFGLS. Use the BUFGE to clock the fast capture latch and the
BUFGLS to clock the normal input flip-flop or latch.
You can also use BUFGE to provide a fast Clock-to-Out on device output pins.

Libraries Guide, Release M1.5 3-55

Libraries Guide, Release M1.5

BUFGLS
Global Low Skew Clock Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

Each corner of the XC4000X or SpartanXL device has two Global Low-Skew buffers
(BUFGLS). Any of the eight buffers can drive any of the eight vertical global lines in a
X4210 column of CLBs. In addition, any of the buffers can drive any of the four vertical lines
accessing the IOBs on the left edge of the device and any of the eight vertical lines
accessing the IOBs on the right edge of the device.
IOBs at the top and bottom edges of the device are accessed through the vertical
global lines in the CLB array. Any global low-skew buffer can, therefore, access every
IOB and CLB in the device.
The global low-skew buffers can be driven by either semi-dedicated pads or internal
logic.

3-56 Xilinx Development System

Design Elements (BUFGP)

BUFGP
Primary Global Buffer for Driving Clocks or Longlines (Four per
PLD Device)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive N/A Macro N/A Primitive N/A Primitive

BUFGP, a primary global buffer, is used to distribute high fan-out clock or control
signals throughout PLD devices. In Virtex, BUFGP is equivalent to an IBUFG driving
X3902 a BUFG. In CPLD designs, BUFGP is treated like BUFG. A BUFGP provides direct
access to Configurable Logic Block (CLB) and Input Output Block (IOB) clock pins
and limited access to other CLB inputs. Four BUFGPs are available on each XC4000E
and Spartan device, one in each corner. The input to a BUFGP comes only from a
dedicated IOB.
Alongside each column of CLBs in an XC4000E or Spartan device are four global
vertical lines, which are in addition to the standard vertical longlines. Each one of the
four global vertical lines can drive the CLB clock (K) pin directly. In addition, one of
the four lines can drive the F3 pin, a second line can drive the G1 pin, a third can drive
the C3 pin, and a fourth can drive the C1 pin. Each of the four BUFGPs drives one of
these global vertical lines. These same vertical lines are also used for the secondary
global buffers (refer to the “BUFGS” section for more information).
Because of its structure, a BUFGP can always access a clock pin directly. However, it
can access only one of the F3, G1, C3, or C1 pins, depending on the corner in which
the BUFGP is placed. When the required pin cannot be accessed directly from the
vertical line, PAR feeds the signal through another CLB and uses general purpose
routing to access the load pin.
To use a BUFGP in a schematic, connect the input of the BUFGP element directly to
the PAD symbol. Do not use any IBUFs, because the signal comes directly from a
dedicated IOB. The output of the BUFGP is then used throughout the schematic. For a
negative-edge clock, insert an INV (inverter) element between the output of the
BUFGP and the clock input. This inversion is performed inside each CLB or IOB.
A Virtex BUFGP must be sourced by an external signal. Other BUFGPs can be sourced
by an internal signal, but PAR must use the dedicated IOB to drive the BUFGP, which
means that the IOB is not available for use by other signals. If possible, use a BUFGS
instead, because they can be sourced internally without using an IOB.
The dedicated inputs for BUFGPs are identified by the names PGCK1 through PGCK4
in pinouts in XC4000E and Spartan. The package pin that drives the BUFGP depends
on which corner the BUFGP is placed by PAR.

I O

BUFG

X8117

Figure 3-38 BUFGP Implementation XC5200

Libraries Guide, Release M1.5 3-57

Libraries Guide, Release M1.5

BUFGS
Secondary Global Buffer for Driving Clocks or Longlines (Four per
PLD Device)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive N/A Macro N/A Primitive N/A N/A

BUFGS, a secondary global buffer, distributes high fan-out clock or control signals
throughout a PLD device. In CPLD designs, BUFGS is treated like BUFG. BUFGS
X3904
provides direct access to Configurable Logic Block (CLB) clock pins and limited access
to other CLB inputs. Four BUFGSs are available on each XC4000E and Spartan device,
one in each corner. The input to a BUFGS comes either from a dedicated Input Output
Block (IOB) or from an internal signal.
Alongside each column of CLBs in an XC4000E or Spartan device are four global
vertical lines, which are in addition to the standard vertical longlines. Each one of the
four global vertical lines can drive the CLB clock (K) pin directly. In addition, one of
the four lines can drive the F3 pin, a second line can drive the G1 pin, a third can drive
the C3 pin, and a fourth can drive the C1 pin. Each of the four BUFGSs can drive any
of these global vertical lines and are also used as the primary global buffers (refer also
to the “BUFGP” section for more information).
Because of its structure, a BUFGS can always access a clock pin directly. Because the
BUFGS is more flexible than the BUFGP, it can use additional global vertical lines to
access the F3, G1, C3, and C1 pins but requires multiple vertical lines in the same
column. If the vertical lines in a given column are already used for BUFGPs or another
BUFGS, PAR might have to feed signals through other CLBs to reach the load pins.
To use a BUFGS in a schematic, connect the input of the BUFGS element either
directly to the PAD symbol (for an external input) or to an internally sourced net. For
an external signal, do not use any IBUFs, because the signal comes directly from the
dedicated IOB. The output of the BUFGS is then used throughout the schematic. For a
negative-edge clock, insert an INV (inverter) element between the output of the
BUFGS and the clock input. This inversion is performed inside each CLB or IOB.
The dedicated inputs for BUFGSs are identified by the names SGCK1 through SGCK4
in pinouts in XC4000E and Spartan. The package pin that drives the BUFGS depends
on which corner the BUFGS is placed by PAR.

I O

BUFG

X8117

Figure 3-39 BUFGS Implementation XC5200

3-58 Xilinx Development System

Design Elements (BUFGSR)

BUFGSR
Global Set/Reset Input Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Primitive N/A N/A N/A

BUFGSR, an XC9000-specific global buffer, distributes global set/reset signals

throughout selected flip-flops of an XC9000 device. Global Set/Reset (GSR) control
X3831 pins are available on XC9000 devices; consult device data sheets for availability.
BUFGSR always acts as an input buffer. To use it in a schematic, connect the input of
the BUFGSR symbol to an IPAD or an IOPAD representing the GSR signal source.
GSR signals generated on-chip must be passed through an OBUF-type buffer before
they are connected to BUFGSR.
For global set/reset control, the output of BUFGSR normally connects to the CLR or
PRE input of a flip-flop symbol, like FDCP, or any registered symbol with asynchro-
nous clear or preset. The global set/reset control signal may pass through an inverter
to perform an active-low set/reset. The output of BUFGSR may also be used as an
ordinary input signal to other logic elsewhere in the design. Each BUFGSR can control
any number of flip-flops in a design.

Libraries Guide, Release M1.5 3-59

Libraries Guide, Release M1.5

BUFGTS
Global Three-State Input Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Primitive N/A N/A N/A

BUFGTS, an XC9000-specific global buffer, distributes global output-enable signals

throughout the output pad drivers of an XC9000 device. Global Three-State (GTS)
X3831 control pins are available on XC9000 devices; consult device data sheets for avail-
ability.
BUFGTS always acts as an input buffer. To use it in a schematic, connect the input of
the BUFGTS symbol to an IPAD or an IOPAD representing the GTS signal source. GTS
signals generated on-chip must be passed through an OBUF-type buffer before they
are connected to BUFGTS.
For global 3-state control, the output of BUFGTS normally connects to the E input of a
3-state output buffer symbol, OBUFE. The global 3-state control signal may pass
through an inverter or control an OBUFT symbol to perform an active-low output-
enable. The same 3-state control signal may even be used both inverted and non-
inverted to enable alternate groups of device outputs. The output of BUFGTS may
also be used as an ordinary input signal to other logic elsewhere in the design. Each
BUFGTS can control any number of output buffers in a design.

3-60 Xilinx Development System

Design Elements (BUFOD)

BUFOD
Open-Drain Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A N/A N/A N/A

BUFOD is a buffer with input (I) and open-drain output (O). When the input is Low,
the output is Low. When the input is High, the output is off. To establish an output
X3903 High level, a pull-up resistor is tied to output O. One pull-up resistor uses the least
power; two pull-up resistors achieve the fastest Low-to-High speed.
To indicate two pull-up resistors, append a DOUBLE parameter to the pull-up symbol
attached to the output (O) node. Refer to the appropriate CAE tool interface user
guide for details.

WAND1
I O

X7777

Figure 3-40 BUFOD Implementation XC4000

Libraries Guide, Release M1.5 3-61

Libraries Guide, Release M1.5

BUFT, 4, 8, 16
Internal 3-State Buffers with Active-Low Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

BUFT Primitive Primitive Primitive Primitive Primitive* Primitive Primitive Primitive
BUFT4, Macro Macro Macro Macro Macro* Macro Macro Macro
BUFT8,
BUFT16
* not supported for XC9500XL devices

BUFT BUFT, BUFT4, BUFT8, and BUFT16 are single or multiple 3-state buffers with inputs I,
T I3 – I0, I7 – I0, and I15 – 10, respectively; outputs O, O3 – O0, O7 – O0, and O15 – O0,
respectively; and active-Low output enable (T). When T is Low, data on the inputs of
the buffers is transferred to the corresponding outputs. When T is High, the output is
high impedance (Z state or off). The outputs of the buffers are connected to horizontal
X3789 longlines in FPGA architectures.
The outputs of separate BUFT symbols can be tied together to form a bus or a multi-
BUFT4
plexer. Make sure that only one T is Low at one time. If none of the T inputs is active
T
(Low), a “weak-keeper” circuit (FPGAs) prevents the output bus from floating but
does not guarantee that the bus remains at the last value driven onto it.
Pull-up resistors can be used to establish a High logic level if all BUFT elements are off
in XC3000, XC4000, and Spartans.
In the XC5200 architecture, pull-ups cannot be used in conjunction with BUFT or
BUFE macros because there are no pull-ups available at the ends of the horizontal
X3796 longlines.
For XC9500 devices, BUFT output nets assume the High logic level when all
BUFT8
connected BUFE/BUFT buffers are disabled. On-chip 3-state multiplexing is not avail-
T
able in XC9500XL devices.
For Virtex, when all BUFTs on a net are disabled, the net is High. For correct simula-
tion of this effect, a PULLUP element must be connected to the net. NGDBuild inserts
X3808
a PULLUP element if one is not connected so that back-annotation simulation reflects
the true state of the Virtex chip.
BUFT16
T

Inputs Outputs

T I O
X3820
1 X Z
0 1 1
0 0 0

3-62 Xilinx Development System

Design Elements (BUFT, 4, 8, 16)

T
I0 O0
T BUFT

I1 O1
T BUFT
I2 O2
T BUFT
I3 O3
T BUFT
I4 O4
T BUFT
I5 O5
T BUFT
I6 O6
T BUFT
I7 O7
BUFT
I[ 7: 0]
X8118
T

Figure 3-41 BUFT8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 3-63

Libraries Guide, Release M1.5

BYPOSC
Bypass Oscillator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

BYPOSC BYPOSC provides for definition of a user clock for the charge pump via its I pin.
When the BYPOSC symbol is not used or its I pin is not connected, the charge pump
uses an internal clock.
I

X8236

3-64 Xilinx Development System

Chapter 4

Design Elements (CAPTURE_VIRTEX to DECODE64)

Libraries Guide, Release M1.5 — 4-1

Libraries Guide, Release M1.5

CAPTURE_VIRTEX
Virtex Register State Capture for Bitstream Readback

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

CAPTURE_VIRTEX CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and
CAP latch) information for readback. Virtex provides the readback function through dedi-
cated configuration port instructions, instead of with a READBACK component as in
CLK other FPGA architectures. The CAPTURE_VIRTEX symbol is optional. Without it
readback is still performed, but the asynchronous capture function it provides for
X8681 register states is not available.
Note: Virtex only allows for capturing register (flip-flop and latch) states. Although
LUT RAM, SRL, and block RAM states are read back, they cannot be captured.
An asserted High CAP signal indicates that the registers in the device are to be
captured at the next Low-to-High clock transition. The Low-to-High clock transition
triggers the capture clock (CLK) which clocks out the readback data.
Two BitGen options control when capture can occur.
• When ONESHOT mode is set, only a single capture of registers for readback is
allowed. After a trigger (transition on CLK while CAP is asserted), all register
information is captured and no additional captures can occur until the readback
operation is completed.
• When CONTINUOUS mode is set, data is captured after every trigger (transition
on CLK while CAP is asserted).
For details on the Virtex readback function, refer to the Xilinx web site, http://
www.xilinx.com.

4-2 Xilinx Development System

Design Elements (CB2CE, CB4CE, CB8CE, CB16CE)

CB2CE, CB4CE, CB8CE, CB16CE

2-, 4-, 8-,16-Bit Cascadable Binary Counters with Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CB2CE
CB2CE, CB4CE, CB8CE, and CB16CE are, respectively, 2-, 4-, 8-, and 16-bit (stage),
Q0 asynchronous, clearable, cascadable binary counters. The asynchronous clear (CLR) is
Q1
CE CEO
the highest priority input. When CLR is High, all other inputs are ignored; the Q
C TC outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, inde-
pendent of clock transitions. The Q outputs increment when the clock enable input
CLR (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock
X4353
transitions when CE is Low. The TC output is High when all Q outputs are High.
Larger counters are created by connecting the CEO output of the first stage to the CE
CB4CE Q0
Q1
input of the next stage and connecting the C and CLR inputs in parallel. CEO is active
Q2 (High) when TC and CE are High. The maximum length of the counter is determined
Q3 by the accumulated CE-to-TC propagation delays versus the clock period. The clock
CE CEO
period must be greater than n(tCE-TC), where n is the number of stages and the time
C TC
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
CLR
X4357
The counter is asynchronously cleared, outputs Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
CB8CE Q[7:0] the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
CE CEO reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
C TC Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
CLR
X4361

Inputs Outputs
CB16CE Q[15:0]

CE CEO CLR CE C Qz – Q0 TC CEO

C TC
1 X X 0 0 0
CLR
X4365 0 0 X No Chg No Chg 0
0 1 ↑ Inc TC CEO
z= 1 for CB2CE; z = 3 for CB4CE; z = 7 for CB8CE; z = 15 for CB16CE
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE

Libraries Guide, Release M1.5 4-3

Libraries Guide, Release M1.5

Q[7:0]
VCC
FTCE
Q0
T Q
CE
C
CLR
Q0

FTCE
Q1
T Q
CE
C T2
CLR
Q1 AND2

FTCE
Q2
T Q
CE
C T3
CLR
Q2 AND3

FTCE
Q3
T Q
CE
C T4
CLR
Q3
AND4

FTCE
Q4
T Q
CE
C T5
CLR
Q4 AND2

FTCE
Q5
T Q
CE
C T6
CLR
Q5 AND3

FTCE
Q6
T Q
CE
C T7
CLR
Q6
AND4

FTCE
Q7
T Q
CE
CE
C
C
CLR TC
CLR Q7

AND5

CEO
X8136
AND2

Figure 4-1 CB8CE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

4-4 Xilinx Development System

Design Elements (CB2CE, CB4CE, CB8CE, CB16CE)

VCC
+5

CE
Q0
AND2
Q1

FDC

D Q

XOR2 CEO
C
CLR
AND3
Q0

AND2
FDC

D Q

AND2 XOR2
C
C CLR
CLR Q1
X7779

Figure 4-2 CB2CE Implementation XC9000

CB2CE
Q0
Q0
Q1
Q1
CE
CE CEO
C
C TC
CLR
CLR CB0

CB2CE
Q2
Q0
Q3
Q1
CE CEO
C TC
CLR
CB2

CB2CE
Q4
Q0
Q5
Q1
CE CEO
C TC
CLR
CB4

CB2CE
Q6
Q0
Q7
Q1
CEO
CE CEO
C TC
CLR
CB6

X7783 AND4

Figure 4-3 CB8CE Implementation XC9000

Libraries Guide, Release M1.5 4-5

Libraries Guide, Release M1.5

CB2CLE, CB4CLE, CB8CLE, CB16CLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock
Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

D0 Q0
CB2CLE, CB4CLE, CB8CLE, and CB16CLE are, respectively, 2-, 4-, 8-, and 16-bit
CB2CLE
D1 Q1 (stage) synchronously loadable, asynchronously clearable, cascadable binary
counters. The asynchronous clear (CLR) is the highest priority input. When CLR is
L
High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
CE CEO
C TC
enable out (CEO) go to logic level zero, independent of clock transitions. The data on
the D inputs is loaded into the counter when the load enable input (L) is High during
CLR
the Low-to-High clock transition, independent of the state of clock enable (CE). The Q
X4354 outputs increment when CE is High during the Low-to-High clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when all Q
D0 CB4CLE Q0
outputs are High.
D1 Q1
D2 Q2
Larger counters are created by connecting the CEO output of the first stage to the CE
D3 Q3 input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is
active (High) when TC and CE are High. The maximum length of the counter is deter-
L mined by the accumulated CE-to-TC propagation delays versus the clock period. The
CE CEO
C TC
clock period must be greater than n(tCE-TC), where n is the number of stages and the
time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading
CLR counters, use the CEO output if the counter uses the CE input; use the TC output if it
X4358
does not.
D[7:0] Q[7:0] The counter is asynchronously cleared, output Low, when power is applied. For
CB8CLE
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
L the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
CE CEO
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
C TC
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
CLR
X4362

D[15:0]
CB16CLE
Q[15:0] Inputs Outputs
L CLR L CE C Dz – D0 Qz – Q0 TC CEO
CE CEO
C TC 1 X X X X 0 0 0
0 1 X ↑ Dn dn TC CEO
CLR
X4366
0 0 0 X X No Chg No Chg 0
0 0 1 ↑ X Inc TC CEO
z= 1 for CB2CLE; z = 3 for CB4CLE; z = 7 for CB8CLE; z = 15 for CB16CLE
dn = state of referenced input (Dn) one setup time prior to active clock transition.
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE

4-6 Xilinx Development System

Design Elements (CB2CLE, CB4CLE, CB8CLE, CB16CLE)

VCC
FTCLE
D0 Q[7:0]
D
L
Q0
T Q
CE
C
CLR
Q0

FTCLE
D1
D
L
Q1
T Q
CE
C T2
CLR
Q1 AND2

FTCLE
D2
D
L
Q2
T Q
CE
C T3
CLR
Q2 AND3

FTCLE
D3
D
L
Q3
T Q
CE
C T4
CLR
Q3
AND4
FTCLE
D4
D
L
Q4
T Q
CE
C T5
CLR
Q4 AND2

FTCLE
D5
D
L
Q5
T Q
CE
C T6
CLR
Q5 AND3

FTCLE
D6
D
L
Q6
T Q
CE
C T7
CLR
Q6
AND4
FTCLE
D[7:0] D7
D
L
L
Q7
T Q
CE
CE
C
C
CLR TC
CLR Q7

AND5

CEO
X8134
AND2

Figure 4-4 CB8CLE Implementation XC3000

Libraries Guide, Release M1.5 4-7

Libraries Guide, Release M1.5

VCC
FTCLEX
D0 Q[7:0]
D
L
Q0
T Q
CE
C
CLR
Q0

FTCLEX
D1
D
L
Q1
T Q
CE
C T2
CLR
Q1 AND2

FTCLEX
D2
D
L
Q2
T Q
CE
C T3
CLR
Q2 AND3

FTCLEX
D3
D
L
Q3
T Q
CE
C T4
CLR
Q3
AND4
FTCLEX
D4
D
L
Q4
T Q
CE
C T5
CLR
Q4 AND2

FTCLEX
D5
D
L
Q5
T Q
CE
C T6
CLR
Q5 AND3

FTCLEX
D6
D
L
Q6
T Q
CE
C T7
CLR
Q6
AND4
FTCLEX
D[7:0] D7
D
L
L
Q7
T Q
CE
CE
C
C
CLR TC
CLR Q7

AND5

OR_CE_L
OR2 CEO

AND2
X8135

Figure 4-5 CB8CLE Implementation XC4000, XC5200, Spartans, Virtex

4-8 Xilinx Development System

Design Elements (CB2CLE, CB4CLE, CB8CLE, CB16CLE)

VCC
+5

CE
Q0
AND2
Q1

L CEO
FDC
AND2B1 AND3
OR2 D Q TC
AND2B1 XOR2
GND AND2
C
CLR
OR2 Q0
D0
AND2

FDC
AND2B1
D Q
XOR2
AND3B1 C
CLR
OR2 Q1
D1
AND2
C
CLR
X7780

Figure 4-6 CB2CLE Implementation XC9000

CB2CLE
D0 Q0
D0 Q0
D1 Q1
D1 Q1
L
L
CE
CE CEO
C
C TC
CLR
CLR CB0

CB2CLE
D2 Q2
D0 Q0
D3 Q3
D1 Q1
L
CE CEO
C TC
CLR
D[7:0] Q[7:0]
CB2

CB2CLE
D4 Q4
D0 Q0
D5 Q5
D1 Q1
L
CE CEO
C TC
CLR
CB4

CB2CLE
D6 Q6
D0 Q0
D7 Q7
D1 Q1
L
CEO
CE CEO
C TC
CLR
CB6

X8130 AND4

Figure 4-7 CB8CLE Implementation XC9000

Libraries Guide, Release M1.5 4-9

Libraries Guide, Release M1.5

CB2CLED, CB4CLED, CB8CLED, CB16CLED

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary
Counters with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CB2CLED, CB4CLED, CB8CLED, and CB16CLED are, respectively, 2-, 4-, 8- and 16-bit
D0 CB2CLED Q0
(stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional
D1 Q1
binary counters. The asynchronous clear (CLR) is the highest priority input. When
UP CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and
L clock enable out (CEO) go to logic level zero, independent of clock transitions. The
CE CEO
C TC
data on the D inputs is loaded into the counter when the load enable input (L) is High
during the Low-to-High clock (C) transition, independent of the state of clock enable
CLR
(CE). The Q outputs decrement when CE is High and UP is Low during the Low-to-
X4355
High clock transition. The Q outputs increment when CE and UP are High. The
counter ignores clock transitions when CE is Low.
D0 CB4CLED Q0 For counting up, the TC output is High when all Q outputs and UP are High. For
D1 Q1
D2
counting down, the TC output is High when all Q outputs and UP are Low. To
Q2
D3 Q3 cascade counters, the CEO output of each counter is connected to the CE pin of the
next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active
UP (High) when TC and CE are High. The maximum length of the counter is determined
L
CE CEO
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
C TC period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage.
CLR
X4359 When cascading counters, use the CEO output if the counter uses the CE input; use
the TC output if it does not. For CPLD designs, refer to the “CB2X1, CB4X1, CB8X1,
D[7:0]
CB8CLED
Q[7:0] CB16X1” section for high-performance cascadable, bidirectional counters.

UP The counter is asynchronously cleared, output Low, when power is applied. For
L CPLDs, the power-on condition can be simulated by applying a High-level pulse on
CEO
CE the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
C TC
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
CLR X4363 front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

D[15:0] CB16CLED Q[15:0] Inputs Outputs

UP
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
L
CE CEO
1 X X X X X 0 0 0
C TC 0 1 X ↑ X Dn dn TC CEO

CLR
0 0 0 X X X No Chg No Chg 0
X4367
0 0 1 ↑ 1 X Inc TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = 1 for CB2CLED; z = 3 for CB4CLED; z = 7 for CB8CLED; z = 15 for CB16CLED
dn = state of referenced input (Dn), one setup time prior to active clock transition
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE

4-10 Xilinx Development System

Design Elements (CB2CLED, CB4CLED, CB8CLED, CB16CLED)

D[7:0]
VCC
+5
FTCLE
D0
D
L
Q0
T Q
CE
M2_1B1
C D0
O T1
CLR D1
Q0 S0 T1

FTCLE
D1
D
L
Q1
T Q
CE
T2_DN
C
CLR AND2B2
M2_1
D0
Q1 O T2
D1
S0 T2
T2_UP

AND2

FTCLE
D2
D
L
Q2
T Q
CE
C T3_DN
CLR
Q2 AND3B3 M2_1
D0
O T3
D1
S0 T3
T3_UP

AND3

FTCLE
D3
D
L
Q3
T Q
CE
T4_DN
C
CLR AND2B1
M2_1
D0
Q3 O T4
D1
S0 T4
T4_UP

AND2

FTCLE
D4
D
L
Q4
T Q
CE
C T5_DN
CLR
Q4 AND3B2
M2_1
D0
O T5
D1
S0 T5
T5_UP

AND3

FTCLE
D5
D
L
Q5
T Q
CE
C
T6_DN
CLR
Q5
AND4B3
M2_1
D0
O T6
D1
S0 T6

T6_UP

AND4

FTCLE
D6
D
L
Q6
T Q
CE
T7_DN
C
CLR AND2B2
M2_1
D0
Q6 O T7
D1
S0 T7
T7_UP

AND2B1

FTCLE
D7
D
L
L Q[7:0]
Q7
T Q
CE
CE
C TC_DN
C
CLR
CLR Q7 AND3B2 M2_1
D0
O TC
D1
S0 TC
TC_UP

AND3
UP

CEO
X7622
AND2

Figure 4-8 CB8CLED Implementation XC3000

Libraries Guide, Release M1.5 4-11

Libraries Guide, Release M1.5

D[7:0]
FTCLEX
D0 VCC
D
L Q0
T Q
CE M2_1B1
D0
C O T1
CLR D1
Q0 S0 T1

FTCLEX
D1
D
L Q1
T Q
CE T2_DN
C M2_1
CLR D0
AND2B2 O T2
Q1 D1
T2_UP S0 T2

AND2
FTCLEX
D2
D
L Q2
T Q
CE
T3_DN
C
CLR M2_1
Q2 AND3B3 D0
O T3
D1
S0 T3
T3_UP

AND3
FTCLEX
D3
D
L Q3
T Q
CE
C T4_DN
CLR
M2_1
Q3
D0
AND4B4 O T4
D1
S0 T4
T4_UP

AND4
FTCLEX
D4
D
L
T Q4
Q
CE T5_DN
C M2_1
CLR D0
AND2B1 O T5
Q4 D1
T5_UP S0 T5

AND2
FTCLEX
D5
D
L
Q5
T Q
CE T6_DN
C
CLR M2_1
Q5 AND3B2 D0 O T6
D1
S0 T6
T6_UP

AND3
FTCLEX
D6
D
L
Q6
T Q
CE
C T7_DN
CLR
M2_1
Q6
D0
AND4B3 O T7
D1
S0
T7
T7_UP

AND4
D7 FTCLEX
D
L L
CE T Q Q7
CE Q[7:0]
C C
CLR TC_DN
CLR
Q7 M2_1
D0 O TC
AND5B4 D1
S0 CEO
TC
OR_CE_L TC_UP
OR2 AND2

AND5
UP
X4046

Figure 4-9 CB8CLED Implementation XC4000, XC5200, Spartans, Virtex

4-12 Xilinx Development System

Design Elements (CB2CLED, CB4CLED, CB8CLED, CB16CLED)

VCC
+5

CE
AND2
UP

OR2
AND3B2
GND FDC
L Q0
D Q
AND3B1 OR3
OR2 XOR2 C
CLR
GND
D0 Q0

AND2

AND2B1

AND4B3

FDC
Q1
D Q
OR3
AND4B1 XOR2
C
CLR
D1 Q1
AND2

AND2B1

AND5B4

FDC
Q2
D Q
OR3
XOR2
AND5B1 C
CLR
D2 Q2

AND2

AND2B1

INV
INV
INV
INV
INV AND6

FDC
INV Q3
D Q
OR3 XOR2
C
AND6 CLR
Q3
D3
AND2

AND2B1

AND5 TC

OR2

AND5B5

INV
INV
INV
INV
INV AND6 CEO

OR2

AND6
C

CLR

X7625

Figure 4-10 CB4CLED Implementation XC9000

Libraries Guide, Release M1.5 4-13

Libraries Guide, Release M1.5

CB2RE, CB4RE, CB8RE, CB16RE

2-, 4-, 8-, 16-Bit Cascadable Binary Counters with Clock Enable
and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CB2RE
CB2RE, CB4RE, CB8RE, and CB16RE are, respectively, 2-, 4-, 8-, and 16-bit (stage),
Q0 synchronous, resettable, cascadable binary counters. The synchronous reset (R) is the
Q1
CE CEO
highest priority input. When R is High, all other inputs are ignored; the Q outputs,
C TC terminal count (TC), and clock enable out (CEO) go to logic level zero during the
Low-to-High clock transition. The Q outputs increment when the clock enable input
R
X4356
(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock
transitions when CE is Low. The TC output is High when both Q outputs are High.

CB4RE Q0 Larger counters are created by connecting the CEO output of the first stage to the CE
Q1 input of the next stage and connecting the C and R inputs in parallel. CEO is active
Q2
(High) when TC and CE are High. The maximum length of the counter is determined
Q3
CE CEO
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
C TC period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
R
X4360
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
CB8RE Q[7:0]
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
CE CEO
C TC
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
R
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
X4364

CB16RE Q[15:0] Inputs Outputs

CE CEO
C TC R CE C Qz – Q0 TC CEO
1 X ↑ 0 0 0
R
X4368
0 0 X No Chg No Chg 0
0 1 ↑ Inc TC CEO
z = 1 for CB2RE; z = 3 for CB4RE; z = 7 for CB8RE; z = 15 for CB16RE
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE

4-14 Xilinx Development System

Design Elements (CB2RE, CB4RE, CB8RE, CB16RE)

FTRSE Q[7:0]
VCC

S Q0
T Q
CE
C
R
Q0

FTRSE

S Q1
T Q
CE
C T2
R
Q1 AND2

FTRSE

S Q2
T Q
CE
C T3
R
Q2 AND3

FTRSE

S Q3
T Q
CE
C T4
R
Q3
AND4

FTRSE

S Q4
T Q
CE
C T5
R
Q4 AND2

FTRSE

S Q5
T Q
CE
C T6
R
Q5 AND3

FTRSE

S Q6
T Q
CE
C T7
R
Q6
AND4

FTRSE

S Q7
T Q
CE
CE
C
C
R TC
R Q7

AND5
GND

CEO
X8137
AND2

Figure 4-11 CB8RE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Libraries Guide, Release M1.5 4-15

Libraries Guide, Release M1.5

VCC
+5

CE
AND2

CEO

AND3
FD

D Q TC
AND2B1
XOR2
AND2
C

Q0
AND2B1

FD Q0
Q1
D Q
AND3B1 XOR2
C

Q1
AND2B1 X7781
C

Figure 4-12 CB2RE Implementation XC9000

CB2RE
Q0
Q0
Q1
Q1
CE
CE CEO
C
C TC
R
R CB0

CB2RE
Q2
Q0
Q3
Q1
CE CEO
C TC
R
CB2

CB2RE
Q4
Q0
Q5
Q1
CE CEO
C TC
R
CB4

CB2RE
Q6 Q[7:0]
Q0
Q7
Q1
CEO
CE CEO
C TC
R
CB6

X8129

AND4

Figure 4-13 CB8RE Implementation XC9000

4-16 Xilinx Development System

Design Elements (CB2RLE, CB4RLE, CB8RLE, CB16RLE)

CB2RLE, CB4RLE, CB8RLE, CB16RLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock
Enable and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

CB2RLE
CB2RLE, CB4RLE, CB8RLE, and CB16RLE are, respectively, 2-, 4-, 8-, and 16-bit
D0 Q0
D1 Q1
(stage), synchronous, loadable, resettable, cascadable binary counter. The synchro-
nous reset (R) is the highest priority input. The synchronous R, when High, overrides
L all other inputs and resets the Q outputs, terminal count (TC), and clock enable out
CE CEO (CEO) outputs to Low on the Low-to-High clock (C) transition.
C TC
The data on the D inputs is loaded into the counter when the load enable input (L) is
High during the Low-to-High clock (C) transition, independent of the state of CE. The
R X4513
Q outputs increment when CE is High during the Low-to-High clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when all Q
D0 CB4RLE Q0 outputs are High. The CEO output is High when all Q outputs and CE are High to
D1 Q1 allow direct cascading of counters.
D2 Q2
D3 Q3 Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and by connecting the C, L, and R inputs in parallel. The
L
CE CEO
maximum length of the counter is determined by the accumulated CE-to-CEO propa-
C TC gation delays versus the clock period. When cascading counters, use the CEO output
if the counter uses the CE input; use the TC output if it does not.
R
X4514 The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
D[7:0] Q[7:0]
the PRLD global net.
CB8RLE

L
CE CEO
C
Inputs Outputs
TC

R L CE C Dz – D0 Qz – Q0 TC CEO
R
X4515
1 X X ↑ X 0 0 0
0 1 X ↑ Dn dn TC CEO
D[15:0]
CB16RLE Q[15:0]
0 0 0 X X No Chg No Chg 0
L 0 0 1 ↑ X Inc TC CEO
CE CEO
C TC
z = 1 for CB2RLE; z = 3 for CB4RLE; z = 7 for CB8RLE; z = 15 for CB16RLE
dn = state of referenced input (Dn) one setup time prior to active clock transition
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
R X4516 CEO = TC•CE

Libraries Guide, Release M1.5 4-17

Libraries Guide, Release M1.5

VCC
+5

CE
AND2
L

OR2
CEO

GND
R AND3

Q1
AND3B2 Q0
D0

FD
OR2 TC
AND3B1 D Q
AND2
XOR2
C

Q0
AND3B2

AND4B2
D1

FD
OR2
AND3B1 D Q
XOR2
C

Q1
AND3B2
C
X7782

Figure 4-14 CB2RLE Implementation XC9000

CB2RLE
D0 Q0
D0 Q0
D1 Q1
D1 Q1
L
L
CE
CE CEO
C C TC
R
R
CB0

CB2RLE
D2 Q2
D0 Q0
D3 D1 Q3
Q1
L
CE CEO
C TC
R
CB2

CB2RLE
D4 Q4
D0 Q0
D5 Q5
D1 Q1
L
CE CEO
C TC
R
CB4

CB2RLE
D6 Q6
D0 Q0
D7 Q7
D1 Q1
L
CE CEO CEO
C TC
R
D[7:0] CB6

Q[7:0]

AND4

X7621

Figure 4-15 CB8RLE Implementation XC9000

4-18 Xilinx Development System

Design Elements (CB2X1, CB4X1, CB8X1, CB16X1)

CB2X1, CB4X1, CB8X1, CB16X1

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary
Counters with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

CB2X1, CB4X1, CB8X1, and CB16X1 are, respectively, 2-, 4-, 8-, and 16-bit (stage),
D0 CB2X1 QO
synchronously loadable, asynchronously clearable, bidirectional binary counters.
D1 Q1
TCU
These counters have separate count-enable inputs and synchronous terminal-count
L TCD
outputs for up and down directions to support high-speed cascading in the CPLD
CEU CEOU architecture.
CED CEOD
C
The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
other inputs are ignored; data outputs (Q) go to logic level zero, terminal count
outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU
CLR X4194 and CEOD go to Low and High, respectively, independent of clock transitions. The
data on the D inputs loads into the counter on the Low-to-High clock (C) transition
when the load enable input (L) is High, independent of the CE inputs.
D0 CB4X1 Q0
D1 Q1 The Q outputs increment when CEU is High, provided CLR and L are Low, during
D2 Q2
D3 Q3
the Low-to-High clock transition. The Q outputs decrement when CED is High,
TCU provided CLR and L are Low. The counter ignores clock transitions when CEU and
CEU TCD CED are Low. Both CEU and CED should not be High during the same clock transi-
CED CEOU
tion; the CEOU and CEOD outputs might not function properly for cascading when
L CEOD
C
CEU and CED are both High.
For counting up, the CEOU output is High when all Q outputs and CEU are High. For
CLR
X4196 counting down, the CEOD output is High when all Q outputs are Low and CED is
High. To cascade counters, the CEOU and CEOD outputs of each counter are
connected directly to the CEU and CED inputs, respectively, of the next stage. The
D[7:0]
CB8X1
Q[7:0] clock, L, and CLR inputs are connected in parallel.
TCU
L TCD In Xilinx CPLD devices, the maximum clocking frequency of these counter compo-
CEU CEOU nents is unaffected by the number of cascaded stages for all counting and loading
CED CEOD
functions. The TCU terminal count output is High when all Q outputs are High,
C
regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of
CLR
CED.
X4198
When cascading counters, the final terminal count signals can be produced by AND
wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the
D[15:0]
CB16X1 Q[15:0] down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable
TCU AND gates within the component, resulting in zero propagation from the CEU and
L TCD
CEU
CED inputs and from the Q outputs, provided all connections from each such output
CEOU
CED CEOD remain on-chip. Otherwise, a macrocell buffer delay is introduced.
C
The counter is initialized to zero (TCU Low and TCD High) when power is applied.
For CPLDs, the power-on condition can be simulated by applying a High-level pulse
CLR
X4200 on the PRLD global net.

Libraries Guide, Release M1.5 4-19

Libraries Guide, Release M1.5

Inputs Outputs

CLR L CEU CED C Dz–D0 Qz–Q0 TCU TCD CEOU CEOD

1 X X X X X 0 0 1 0 CEOD
0 1 X X ↑ Dn dn TCU TCD CEOU CEOD
0 0 0 0 X X No Chg No Chg No Chg 0 0
0 0 1 0 ↑ X Inc TCU TCD CEOU 0
0 0 0 1 ↑ X Dec TCU TCD 0 CEOD
0 0 1 1 ↑ X Inc TCU TCD Invalid Invalid
z = 1 for CB2X1; z = 3 for CB4X1; z = 7 for CB8X1; z = 15 for CB16X1
dn = state of referenced input (Dn) one setup time prior to active clock transition
TCU = Qz•Q(z-1)•Q(z-2)•...•Q0
TCD = Qz•Q(z-1)•Q(z-2)•...•Q0
CEOU = TCU•CEU
CEOD = TCD•CED

4-20 Xilinx Development System

Design Elements (CB2X1, CB4X1, CB8X1, CB16X1)

OR2

CEU

OR2
AND2B1
FDC
Q0
D Q
CED
AND3B2 OR3
XOR2 C
OR2 CLR
Q0
AND2B1
GND
D0
AND2

AND4B3
FDC
Q1
D Q
AND3B1 OR3
XOR2 C
CLR
Q1
AND2B1

D1
AND2

AND5B4

FDC
Q2
D Q
OR3
AND4B1 XOR2 C
CLR
Q2
AND2B1

D2
AND2

INV
INV
INV
INV
INV AND6

FDC
Q3
D Q
OR3
XOR2 C
AND5B1
CLR
Q3
AND2B1

D3
AND2

TCU

AND4

INV
INV
INV
INV
INV
INV
INV AND7

INV
INV

INV
FDC
INV
INV AND7 TCDINV
D Q

NOR4 C
CLR
TCDINV

AND5B4

AND3B1

CEQU

AND2

CEQD

AND3B1
TCD
INV
C
CLR

X7624

Figure 4-16 CB4X1 Implementation XC9000

Libraries Guide, Release M1.5 4-21

Libraries Guide, Release M1.5

CB2X2, CB4X2, CB8X2, CB16X2

2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Binary
Counters with Clock Enable and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

CB2X2, CB4X2, CB8X2, and CB16X2 are, respectively, 2-, 4-, 8-, and 16-bit (stage),
D0 CB2X2 QO
D1
synchronous, loadable, resettable, bidirectional binary counters. These counters have
Q1
TCU separate count-enable inputs and synchronous terminal-count outputs for up and
L TCD down directions to support high-speed cascading in the CPLD architecture.
CEU CEOU
CED CEOD
The synchronous reset (R) is the highest priority input. When R is High, all other
C inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs
TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and
CEOD go to Low and High, respectively, on the Low-to-High clock (C) transition. The
R X4195
data on the D inputs loads into the counter on the Low-to-High clock (C) transition
when the load enable input (L) is High, independent of the CE inputs.
D0 CB4X2 Q0 All Q outputs increment when CEU is High, provided R and L are Low during the
D1 Q1
D2 Q2
Low-to-High clock transition. All Q outputs decrement when CED is High, provided
D3 Q3 R and L are Low. The counter ignores clock transitions when CEU and CED are Low.
TCU Both CEU and CED should not be High during the same clock transition; the CEOU
L TCD
CEU CEOU
and CEOD outputs might not function properly for cascading when CEU and CED
CED CEOD are both High.
C
For counting up, the CEOU output is High when all Q outputs and CEU are High. For
counting down, the CEOD output is High when all Q outputs are Low and CED is
R X4197
High. To cascade counters, the CEOU and CEOD outputs of each counter are, respec-
tively, connected directly to the CEU and CED inputs of the next stage. The C, L, and
D[7:0]
CB8X2
Q[7:0] R inputs are connected in parallel.
TCU
L
In Xilinx CPLD devices, the maximum clocking frequency of these counter compo-
TCD
CEU CEOU nents is unaffected by the number of cascaded stages for all counting and loading
CED CEOD functions. The TCU terminal count output is High when all Q outputs are High,
C regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of
CED.
R X4199
When cascading counters, the final terminal count signals can be produced by AND
wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the
D[15:0] Q[15:0]
CB16X2 down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable
TCU AND gates within the component, resulting in zero propagation from the CEU and
L TCD
CEU
CED inputs and from the Q outputs, provided all connections from each such output
CEOU
CED CEOD remain on-chip. Otherwise, a macrocell buffer delay is introduced.
C
The counter is initialized to zero (TCU Low and TCD High) when power is applied.
For CPLDs, the power-on condition can be simulated by applying a High-level pulse
R X4201
on the PRLD global net.

4-22 Xilinx Development System

Design Elements (CB2X2, CB4X2, CB8X2, CB16X2)

Inputs Outputs

R L CEU CED C Dz – D0 Qz – Q0 TCU TCD CEOU CEOD

1 X X X ↑ X 0 0 1 0 CEOD
0 1 X X ↑ Dn dn TCU TCD CEOU CEOD
0 0 0 0 X X No Chg No Chg No Chg 0 0
0 0 1 0 ↑ X Inc TCU TCD CEOU 0
0 0 0 1 ↑ X Dec TCU TCD 0 CEOD
0 0 1 1 ↑ X Inc TCU TCD Invalid Invalid
z = 1 for CB2X2; z = 3 for CB4X2; z = 7 for CB8X2; z = 15 for CB16X2
d = state of referenced input (Dn) one setup time prior to active clock transition
TCU = Qz•Q(z-1)•Q(z-2)•...•Q0
TCD = Qz•Q(z-1)•Q(z-2)•...•Q0
CEOU = TCU•CEU
CEOD = TCD•CED

Libraries Guide, Release M1.5 4-23

Libraries Guide, Release M1.5

Q3
L
Q2
Q1
OR2
Q0

CED
OR2 TCU
R
AND4B3 AND4
TCD
INV
FD
CEQD
AND3B2 OR3
D Q
XOR2 AND3B1
C
CEQU
AND3B2
Q0 AND2
D0

AND3B1

CEU

OR2

GND AND5B4

FD
OR3
AND4B2 D Q

XOR2
C

AND3B2 Q1
D1

AND3B1

INV
INV
INV
INV
INV AND6

FDC
OR3

AND5B2 D Q

XOR2
C

Q2
AND3B2
D2

AND3B1

INV
INV
INV
INV
INV
INV AND7

INV
INV

OR3
FDC

AND6 D Q

XOR2
C

Q3
AND3B2
D3

AND3B1

INV
INV
INV
INV
INV
INV
INV AND7

INV
INV

INV
INV
INV AND7 FDC

D Q

C
NOR5
INV
TCDINV

AND6

AND5B4
C

X7623

Figure 4-17 CB4X2 Implementation XC9000

4-24 Xilinx Development System

Design Elements (CC8CE, CC16CE)

CC8CE, CC16CE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro Macro

CC8CE and CC16CE are, respectively, 8- and 16-bit (stage), asynchronous, clearable,
CC8CE Q[7:0]
cascadable binary counters. These counters are implemented using carry logic with
CEO
CE relative location constraints to ensure efficient placement of logic. The asynchronous
C TC
clear (CLR) is the highest priority input. When CLR is High, all other inputs are
ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic
CLR
X4290 level zero, independent of clock transitions. The Q outputs increment when the clock
enable input (CE) is High during the Low-to-High clock (C) transition. The counter
Q[15:0]
ignores clock transitions when CE is Low. The TC output is High when all Q outputs
CC16CE
are High.
CE CEO
C TC Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the C and CLR inputs in
CLR
X4286
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, with Low outputs, when power is applied.
FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active.
GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR CE C Qz – Q0 TC CEO
1 X X 0 0 0
0 0 X No Chg No Chg 0
0 1 ↑ Inc TC CEO
z = 7 for CC8CE; z = 15 for CC16CE
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE

Libraries Guide, Release M1.5 4-25

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the CC8CE (8-bit) and CC16CE (16-bit) topology for XC4000 and Spartan series
devices.
TC*

CEO*
D 15 Q 15

D 14 Q 14
TC* D 13 Q 13

CEO* D 12 Q 12
D7 Q7 D 11 Q 11

D6 Q6 D 10 Q 10
D5 Q5 D9 Q9

D4 Q4 D8 Q8
D3 Q3 D7 Q7

D2 Q2 D6 Q6
D1 Q1 D5 Q5

D0 Q0 D4 Q4
D3 Q3
8-Bit
D2 Q2
D1 Q1

D0 Q0

X8214 16-Bit

4-26 Xilinx Development System

Design Elements (CC8CE, CC16CE)

Topology for XC5200

This is the CC8CE (8-bit) and CC16CE (16-bit) topology for XC5200 devices.
CEO*
LC0

D 15 Q 15
LC3 LC3
TC
D 14 Q 14
LC2 LC2

D 13 Q 13
LC1 LC1

CEO* D 12 Q 12
LC0 LC0 LC0

D7 Q7 D 11 Q 11
LC3 LC3 LC3 LC3
B7
D6 Q6 D 10 Q 10
LC2 LC2 LC2 LC2
B6
D5 Q5 D9 Q9
LC1 LC1 LC1 LC1
B5
D4 Q4 D8 Q8
LC0 LC0 LC0 LC0
B4

D3 Q3 D7 Q7
LC3 LC3 LC3 LC3
B3
D2 Q2 D6 Q6
LC2 LC2 LC2 LC2
B2
D1 Q1 D5 Q5
LC1 LC1 LC1 LC1
B1
D0 Q0 D4 Q4
LC0 LC0 LC0 LC0
B0

CY_INIT D3 Q3
LC3 LC3 LC3

D2 Q2
LC2 LC2
8-Bit Q1
D1
LC1 LC1

D0 Q0
LC0 LC0

CY_INIT
LC3

x8209 16-Bit

Libraries Guide, Release M1.5 4-27

Libraries Guide, Release M1.5

RLOC=R0C0
CY4
COUT
B1 (G1)
A1 (G4) COUT0
B0 (F2)
A0 (F1)
ADD (F3)
CARRY MODE CEO
CIN

AND2
TC
EXAMINE-CI
CY4_42 Q[7:0]

RLOC=R1C0
CY4
COUT
B1 (G1) TQ7
C6
A1 (G4) COUT0
XOR2 FMAP
B0 (F2) FDCE
A0 (F1) Q7 I4
D Q
ADD (F3) I3 TQ7
CE Q7 O
CARRY MODE I2
CIN C C6
CLR I1
Q7
C5 RLOC=R1C0.FFY RLOC=R1C0.G
TQ6
INC-FG-CI
CY4_18 XOR2 FDCE FMAP
Q6
D Q I4
CE I3 TQ6
Q6 O
C I2
CLR C5
I1
Q6
RLOC=R1C0.FFX
RLOC=R1C0.F
RLOC=R2C0
CY4
COUT
B1 (G1) TQ5
C4
A1 (G4) COUT0
B0 (F2) XOR2 FDCE FMAP
A0 (F1) Q5
D Q I4
ADD (F3)
CE I3 TQ5
CARRY MODE Q5 O
CIN C I2
CLR C4
I1
C3 RLOC=R2C0.FFY Q5
TQ4 RLOC=R2C0.G
INC-FG-CI
XOR2 FDCE
CY4_18 FMAP
Q4
D Q
I4
CE
I3 TQ4
C Q4 O
CLR I2
C3
Q4 I1
RLOC=R2C0.FFX
RLOC=R2C0.F
RLOC=R3C0
CY4
COUT
B1 (G1) TQ3
C2
A1 (G4) COUT0 FMAP
B0 (F2) XOR2 FDCE
I4
A0 (F1) Q3
D Q I3 TQ3
ADD (F3) Q3 O
CE I2
CARRY MODE C2
CIN C I1
CLR
Q3 RLOC=R3C0.G
C1 RLOC=R3C0.FFY
TQ2
INC-FG-CI
FMAP
XOR2 FDCE
CY4_18
Q2 I4
D Q
I3 TQ2
CE Q2 O
I2
C C1
CLR I1
Q2
RLOC=R3C0.FFX RLOC=R3C0.F

RLOC=R4C0
CY4
COUT
B1 (G1) TQ1
C0
A1 (G4) COUT0 FMAP
B0 (F2) XOR2 FDCE
I4
A0 (F1) Q1
D Q I3 TQ1
ADD (F3) Q1 O
CE I2
CARRY MODE CIN C0
C I1
CLR
Q1 RLOC=R4C0.G
RLOC=R4C0.FFY
INC-FG-I
FMAP
CY4_19
I4
I3 TQ0
Q0 O
I2
FDCE
I1
TQ0 Q0
D Q
CE INV RLOC=R4C0.F
CE
C
C
CLR
CLR
Q0
RLOC=R4C0.FFX X6497

Figure 4-18 CC8CE Implementation XC4000, Spartans

4-28 Xilinx Development System

Design Elements (CC8CE, CC16CE)

CEO

AND2 Q[7:0]

CY_MUX CO
Q7 S RLOC=R0C0.LC3
0 1 FMAP
DI CI
FDCE I4
C7
TQ7 Q7 I3 TQ7
D Q C7 O
I2
CE Q7
XOR2 I1
C
CY_MUX CO CLR
RLOC=R0C1.LC3
Q6 S RLOC=R0C0.LC2
0 1 RLOC=R0C1.LC3 FMAP
DI CI FDCE
C6 I4
TQ6 Q6 I3 TQ6
D Q C6 O
I2
CE Q6
XOR2 I1
C
CLR
CY_MUX CO RLOC=R0C1.LC2
Q5 S RLOC=R0C0.LC1 RLOC=R0C1.LC2
0 1 FMAP
DI CI
C5 FDCE I4
TQ5 Q5 I3 TQ5
D Q C5 O
I2
CE Q5
XOR2 I1
C
CY_MUX CO CLR
RLOC=R0C1.LC1
Q4 S RLOC=R0C0.LC0
0 1 RLOC=R0C1.LC1 FMAP
DI CI I4
C4 FDCE
TQ4 Q4 I3 TQ4
D Q C4 I2 O
CE Q4 I1
XOR2
C
CLR
CY_MUX CO RLOC=R0C1.LC0
Q3 S RLOC=R1C0.LC3 RLOC=R0C1.LC0
0 1 FMAP
DI CI I4
FDCE
C3
TQ3 Q3 I3 TQ3
D Q C3 I2 O
CE Q3 I1
XOR2
C
CLR
CY_MUX CO RLOC=R1C1.LC3
Q2 S RLOC=R1C0.LC2
0 1 RLOC=R1C1.LC3 FMAP
DI CI FDCE I4
C2
TQ2 Q2 I3 TQ2
D Q C2 I2 O
CE Q2
XOR2 I1
C
CLR
CY_MUX CO RLOC=R1C1.LC2
Q1 S RLOC=R1C0.LC1 RLOC=R1C1.LC2
0 1 FMAP
DI CI FDCE I4
C1
TQ1 Q1 I3 TQ1
D Q C1 I2 O
CE Q1
XOR2 I1
C
CLR
CY_MUX CO RLOC=R1C1.LC1
Q0 S RLOC=R1C0.LC0
0 1 RLOC=R1C1.LC1 FMAP
DI CI
FDCE I4
C0
TQ0 Q0 I3 TQ0
D Q C0 O
I2
CE Q0
XOR2 I1
GND C
CLR
VCC RLOC=R1C1.LC0
COUT
RLOC=R1C1.LC0
INIT
CY_INIT
RLOC=R2C0.LC3
CE
C
CLR
X6400

Figure 4-19 CC8CE Implementation XC5200

Libraries Guide, Release M1.5 4-29

Libraries Guide, Release M1.5

CEO

AND2 Q[7:0]

MUXCY LO
Q7 S RLOC=R0C0.S1
0 1 FMAP
DI CI
FDCE I4
C7
TQ7 Q7 I3 TQ7
D Q C7 O
I2
CE Q7
XORCY I1
C
MUXCY_L LO CLR
RLOC=R0C0.S0
Q6 S RLOC=R0C0.S1
0 1 RLOC=R0C0.S0 FMAP
DI CI FDCE
C6 I4
TQ6 Q6 I3 TQ6
D Q C6 O
I2
CE Q6
XORCY I1
C
CLR
MUXCY_L LO RLOC=R0C0.S0
Q5 S RLOC=R1C0.S1 RLOC=R0C0.S0
0 1 FMAP
DI CI
C5 FDCE I4
TQ5 Q5 I3 TQ5
D Q C5 O
I2
CE Q5
XORCY I1
C
MUXCY_L LO CLR
RLOC=R1C0.S0
Q4 S RLOC=R1C0.S1
0 1 RLOC=R1C0.S0 FMAP
DI CI I4
C4 FDCE
TQ4 Q4 I3 TQ4
D Q C4 I2 O
CE Q4 I1
XORCY
C
CLR
MUXCY_L LO RLOC=R1C0.S0
Q3 S RLOC=R2C0.S1 RLOC=R1C0.S0
0 1 FMAP
DI CI I4
FDCE
C3
TQ3 Q3 I3 TQ3
D Q C3 I2 O
CE Q3 I1
XORCY
C
CLR
MUXCY_L LO RLOC=R2C0.S0
Q2 S RLOC=R2C0.S1
0 1 RLOC=R2C0.S0 FMAP
DI CI FDCE I4
C2
TQ2 Q2 I3 TQ2
D Q C2 I2 O
CE Q2
XORCY I1
C
CLR
MUXCY_L LO RLOC=R2C0.S0
Q1 S RLOC=R3C0.S1 RLOC=R2C0.S0
0 1 FMAP
DI CI FDCE I4
C1
TQ1 Q1 I3 TQ1
D Q C1 I2 O
CE Q1
XORCY I1
C
CLR
MUXCY_L LO RLOC=R3C0.S0
Q0 S RLOC=R3C0.S1
0 1 RLOC=R3C0.S0 FMAP
DI CI
FDCE I4
C0
TQ0 Q0 I3 TQ0
D Q C0 O
I2
CE Q0
XORCY I1
GND C
CLR
VCC RLOC=R3C0.S0
RLOC=R3C0.S0

CE
C
CLR
X8710

Figure 4-20 CC8CE Implementation Virtex

4-30 Xilinx Development System

Design Elements (CC8CLE, CC16CLE)

CC8CLE, CC16CLE
8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable
and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro Macro

D[7:0] Q[7:0]
CC8CLE and CC16CLE are, respectively, 8- and 16-bit (stage), synchronously load-
CC8CLE
able, asynchronously clearable, cascadable binary counter. These counters are imple-
CEO
L TC
mented using carry logic with relative location constraints to ensure efficient
CE placement of logic.
C
The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
CLR
other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out
X4289
(CEO) go to logic level zero, independent of clock transitions. The data on the D
inputs is loaded into the counter when the load enable input (L) is High during the
D[15:0] CC16CLE Q[15:0] Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q
CEO outputs increment when CE is High during the Low-to-High clock transition. The
L TC counter ignores clock transitions when CE is Low. The TC output is High when all Q
CE
C
outputs are High.
Larger counters are created by connecting the count enable out (CEO) output of the
CLR
X4284 first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, with Low output, when power is applied.
FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active.
GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn dn TC CEO
0 0 0 X X No Chg No Chg 0
0 0 1 ↑ X Inc TC CEO
z = 7 for CC8CLE; z = 15 for CC16CLE
dn = state of referenced input (Dn) one setup time prior to active clock transition
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE

Libraries Guide, Release M1.5 4-31

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the CC8CLE (8-bit) and CC16CLE (16-bit) topology for XC4000 and Spartan
series devices.

TC*

CEO*
D 15 Q 15

D 14 Q 14
TC* D 13 Q 13

CEO* D 12 Q 12
D7 Q7 D 11 Q 11

D6 Q6 D 10 Q 10
D5 Q5 D9 Q9

D4 Q4 D8 Q8
D3 Q3 D7 Q7

D2 Q2 D6 Q6
D1 Q1 D5 Q5

D0 Q0 D4 Q4
D3 Q3
8-Bit
D2 Q2
D1 Q1

D0 Q0

X8214 16-Bit

In the process of combining the logic that loads CEO and TC, the place and route soft-
ware might map the logic that generates CEO and TC to different function generators.
If this mapping occurs, the CEO and TC logic cannot be placed in the uppermost CLB
as indicated in the illustration.

4-32 Xilinx Development System

Design Elements (CC8CLE, CC16CLE)

Topology for XC5200

This is the CC8CLE (8-bit) and CC16CLE (16-bit) topology for XC5200 devices.

CEO*
LC0

D 15 Q 15
LC3 LC3
TC
D 14 Q 14
LC2 LC2

D 13 Q 13
LC1 LC1

CEO* D 12 Q 12
LC0 LC0 LC0

D7 Q7 D 11 Q 11
LC3 LC3 LC3 LC3
B7
D6 Q6 D 10 Q 10
LC2 LC2 LC2 LC2
B6
D5 Q5 D9 Q9
LC1 LC1 LC1 LC1
B5
D4 Q4 D8 Q8
LC0 LC0 LC0 LC0
B4

D3 Q3 D7 Q7
LC3 LC3 LC3 LC3
B3
D2 Q2 D6 Q6
LC2 LC2 LC2 LC2
B2
D1 Q1 D5 Q5
LC1 LC1 LC1 LC1
B1
D0 Q0 D4 Q4
LC0 LC0 LC0 LC0
B0

CY_INIT D3 Q3
LC3 LC3 LC3

D2 Q2
LC2 LC2
8-Bit Q1
D1
LC1 LC1

D0 Q0
LC0 LC0

CY_INIT
LC3

x8209 16-Bit

Libraries Guide, Release M1.5 4-33

Libraries Guide, Release M1.5

CY4 RLOC=R0C0
COUT
B1 (G1)
A1 (G4) COUT0
B0 (F2)
A0 (F1)
ADD (F3)
CARRY MODE CEO
CIN

C0_UP AND2 TC
EXAMINE-CI
CY4_42

CY4 RLOC=R1C0
COUT XOR2 Q[7:0]
B1 (G1) TQ7 M2_1
C6
A1 (G4) COUT0 O MD7
D7 D1 FDCE
B0 (F2)
S0 MD7 Q7
A0 (F1) D Q FMAP
ADD (F3) CE L
I4
CARRY MODE C Q7
CIN CLR I3 MD7
Q7 D7 O
I2
RLOC=R1C0.FFY C6
I1
C5 XOR2
INC-FG-CI
TQ6 M2_1 RLOC=R1C1.G
CY4_18 D0
O MD6
D6 D1 FDCE
FMAP
S0 MD6 Q6
D Q L
I4
CE Q6
I3 MD6
C D6 O
CLR I2
C5
Q6 I1
RLOC=R1C0.FFX
RLOC=R1C1.F

CY4 RLOC=R2C0
COUT XOR2
B1 (G1) TQ5 M2_1
C4 D0
A1 (G4) COUT0 O MD5
D5 D1 FDCE
B0 (F2) FMAP
S0 MD5 Q5
A0 (F1) D Q L
I4
ADD (F3) CE Q5
I3 MD5
CARRY MODE C D5 O
CIN CLR I2
C4
Q5 I1
RLOC=R2C0.FFY
XOR2 RLOC=R2C1.G
INC-FG-CI C3
TQ4 M2_1
D0
CY4_18 O MD4
D4 D1 FDCE FMAP

S0 MD4 Q4 L
D Q I4
Q4
CE I3 MD4
D4 O
C I2
CLR C3
I1
Q4
RLOC=R2C0.FFX RLOC=R2C1.F

CY4 RLOC=R3C0
COUT XOR2
B1 (G1) TQ3 M2_1 FMAP
C2 D0
A1 (G4) COUT0 O MD3 L
D3 D1 FDCE I4
B0 (F2) Q3
S0 MD3 Q3 I3 MD3
A0 (F1) D Q D3 O
I2
ADD (F3) CE C2
I1
CARRY MODE C
CIN CLR
RLOC=R3C1.G
Q3
RLOC=R3C0.FFY
XOR2 FMAP
INC-FG-CI C1
TQ2 M2_1 L
CY4_18 D0 I4
O MD2 Q2
D2 D1 FDCE I3 MD2
D2 O
S0 MD2 Q2 I2
D Q C1
I1
CE
C RLOC=R3C1.F
CLR
Q2
RLOC=R3C0.FFX

CY4 RLOC=R4C0 FMAP

XOR2
COUT L
B1 (G1) TQ1 M2_1 I4
C0 D0 Q1
A1 (G4) COUT0 O MD1 I3 MD1
D1 D1 FDCE D1 O
B0 (F2) I2
S0 MD1 Q1 C0
A0 (F1) D Q I1
ADD (F3) CE
RLOC=R4C1.G
CARRY MODE C
CIN CLR
Q1 FMAP
RLOC=R4C0.FFY L
I4
INC-FG-1 Q0
I3 MD0
CY4_19 D0 O
D0 I2
M2_1 I1
D0
O MD0
INV D1 RLOC=R4C1.F
S0 MD0 FDCE
Q0
L D Q
L_CE
CE CE
FDCE C
C CLR
CLR Q0
RLOC=R4C0.FFX

X6539

Figure 4-21 CC8CLE Implementation XC4000, Spartans

4-34 Xilinx Development System

Design Elements (CC8CLE, CC16CLE)

CEO

AND2 Q[7:0]

CY_MUX CO
Q7 S RLOC=R0C0.LC3
0 1 FMAP
L
DI CI M2_1 I4
C7 FDCE D7
TQ7 D0 I3 MD7
O MD7 Q7 C7 O
D7 D1 D Q I2
XOR2 S0 CE Q7
I1
CY_MUX CO C CLR
RLOC=R0C0.LC2 RLOC=R0C1.LC3
Q6 S
0 1 RLOC=R0C1.LC3
FMAP
DI CI M2_1 L
C6 TQ6 FDCE I4
D0 D6
O MD6 Q6 I3 MD6
D6 D1 D Q O
C6
XOR2 S0 CE I2
C CLR Q6
I1
CY_MUX CO
Q5 S RLOC=R0C0.LC1 RLOC=R0C1.LC2
0 1 RLOC=R0C1.LC2

DI CI FMAP
C5 M2_1 FDCE L
TQ5 D0 I4
O MD5 Q5 D5
D5 D1 D Q I3 MD5
C5 O
XOR2 S0 CE I2
CY_MUX CO C CLR Q5
I1
Q4 S RLOC=R0C0.LC0
0 1 RLOC=R0C1.LC1 RLOC=R0C1.LC1
DI CI M2_1 FMAP
C4 FDCE
TQ4 D0 L
O MD4 Q4 I4
D4 D1 D Q D4
XOR2 S0 CE I3 MD4
C4 O
C CLR I2
CY_MUX CO Q4
I1
Q3 S RLOC=R1C0.LC3 RLOC=R0C1.LC0
0 1 RLOC=R0C1.LC0
DI CI M2_1
C3 FDCE FMAP
TQ3 D0
O MD3 Q3 L
D3 D1 D Q I4
D3
XOR2 S0 CE I3 MD3
C CLR C3 O
CY_MUX CO I2
Q2 RLOC=R1C0.LC2 Q3
S I1
0 1 RLOC=R1C1.LC3
DI CI RLOC=R1C1.LC3
C2 M2_1
FDCE
TQ2 D0 FMAP
O MD2 Q2
D2 D1 D Q L
I4
XOR2 S0 CE D2
C CLR I3 MD2
CY_MUX CO C2 O
I2
Q1 S RLOC=R1C0.LC1 Q2
0 1 RLOC=R1C1.LC2 I1
DI CI M2_1 RLOC=R1C1.LC2
C1 FDCE
TQ1 D0
O MD1 Q1 FMAP
D1 D1 D Q L
XOR2 S0 CE I4
C CLR D1
CY_MUX CO I3 MD1
C1 O
Q0 S RLOC=R1C0.LC0 I2
0 1 RLOC=R1C1.LC1 Q1
I1
DI CI M2_1
C0 FDCE RLOC=R1C1.LC1
TQ0 D0
O MD0 Q0
D0 D1 D Q FMAP
XOR2 S0 CE L
GND I4
C CLR
D0
VCC I3 MD0
COUT C0 O
RLOC=R2C0.LC3 RLOC=R1C1.LC0 I2
INIT
Q0
I1
D[7:0] CY_INIT
RLOC=R1C1.LC0

L L_CE
CE

C OR2
X6542
CLR

Figure 4-22 CC8CLE Implementation XC5200

Libraries Guide, Release M1.5 4-35

Libraries Guide, Release M1.5

CEO

AND2 Q[7:0]

MUXCY LO
Q7 S RLOC=R0C0.S1
0 1 FMAP
L
DI CI M2_1 I4
C7 FDCE D7
TQ7 D0 I3 MD7
O MD7 Q7 TQ7 O
D7 D1 D Q I2
XORCY S0 CE I1
MUXCY_L LO C CLR
RLOC=R0C0.S1 RLOC=R0C0.S0
Q6 S
0 1 RLOC=R0C0.S0
FMAP
DI CI M2_1 L
C6 FDCE I4
TQ6 D0 D6
O MD6 Q6 I3 MD6
D6 D1 D Q O
TQ6
XORCY S0 CE I2
C CLR I1
MUXCY_L LO
Q5 S RLOC=R1C0.S1 RLOC=R0C0.S0
0 1 RLOC=R0C0.S0

DI CI FMAP
C5 M2_1 FDCE L
TQ5 D0 I4
O MD5 Q5 D5
D5 D1 D Q I3 MD5
TQ5 O
XORCY S0 CE I2
MUXCY_L LO C CLR
I1
Q4 S RLOC=R1C0.S1
0 1 RLOC=R1C0.S0 RLOC=R1C0.S0
DI CI M2_1 FMAP
C4 FDCE
TQ4 D0 L
O MD4 Q4 I4
D4 D1 D Q D4
XORCY S0 CE I3 MD4
TQ4 O
C CLR I2
MUXCY_L LO
I1
Q3 S RLOC=R2C0.S1 RLOC=R1C0.S0
0 1 RLOC=R1C0.S0
DI CI M2_1
C3 FDCE FMAP
TQ3 D0
O MD3 Q3 L
D3 D1 D Q I4
D3
XORCY S0 CE I3 MD3
C CLR TQ3 O
MUXCY_L LO I2
Q2 S RLOC=R2C0.S1 I1
0 1 RLOC=R2C0.S0
DI CI RLOC=R2C0.S0
C2 M2_1
FDCE
TQ2 D0 FMAP
O MD2 Q2
D2 D1 D Q L
I4
XORCY S0 CE D2
C CLR I3 MD2
MUXCY_L LO TQ2 O
I2
Q1 S RLOC=R3C0.S1
0 1 RLOC=R2C0.S0 I1
DI CI M2_1 RLOC=R2C0.S0
C1 FDCE
TQ1 D0 O MD1 Q1 FMAP
D1 D1 D Q L
XORCY S0 CE I4
C CLR D1
MUXCY_L LO I3 MD1
TQ1 O
Q0 S RLOC=R3C0.S1 I2
0 1 RLOC=R3C0.S0
I1
DI CI M2_1
C0 FDCE RLOC=R3C0.S0
TQ0 D0
O MD0 Q0
D0 D1 D Q FMAP
XORCY S0 CE L
GND I4
C CLR
D0
VCC I3 MD0
TQ0 O
RLOC=R3C0.S0 I2
I1
D[7:0]
RLOC=R3C0.S0

L L_CE
CE
C OR2
CLR X8711

Figure 4-23 CC8CLE Implementation Virtex

4-36 Xilinx Development System

Design Elements (CC8CLED, CC16CLED)

CC8CLED, CC16CLED
8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with
Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro Macro

CC8CLED and CC16CLED are, respectively, 8- and 16-bit (stage), synchronously load-
D[7:0] CC8CLED Q[7:0]
able, asynchronously clearable, cascadable, bidirectional binary counters. These
CEO
counters are implemented using carry logic with relative location constraints, which
UP TC
L
assures most efficient logic placement.
CE
C
The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out
CLR
(CEO) go to logic level zero, independent of clock transitions. The data on the D
X4287
inputs is loaded into the counter when the load enable input (L) is High during the
Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q
D[15:0] CC16CLED Q[15:0] outputs decrement when CE is High and UP is Low during the Low-to-High clock
CEO
transition. The Q outputs increment when CE and UP are High. The counter ignores
UP TC clock transitions when CE is Low.
L
CE
For counting up, the TC output is High when all Q outputs and UP are High. For
C counting down, the TC output is High when all Q outputs and UP are Low. To
cascade counters, the count enable out (CEO) output of each counter is connected to
CLR
X4285 the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, outputs Low, when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000, Spartans, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn dn TC CEO
0 0 0 X X X No Chg No Chg 0
0 0 1 ↑ 1 X Inc TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = 7 for CC8CLED; z = 15 for CC16CLED
dn = state of referenced input (Dn) one setup time prior to active clock transition
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE

Libraries Guide, Release M1.5 4-37

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the CC8CLED (8-bit) and CC16CLED (16-bit) topology for XC4000 and Spartan
series devices.

TC*

CEO*

D 15 Q 15

D 14 Q 14

TC* D 13 Q 13

CEO* D 12 Q 12

D7 Q7 D 11 Q 11

D6 Q6 D 10 Q 10

D5 Q5 D9 Q9

D4 Q4 D8 Q8

D3 Q3 D7 Q7

D2 Q2 D6 Q6

D1 Q1 D5 Q5

D0 Q0 D4 Q4

D3 Q3
8-Bit
D2 Q2

D1 Q1

D0 Q0

X8213 16-Bit

4-38 Xilinx Development System

Design Elements (CC8CLED, CC16CLED)

Topology for XC5200

This is the CC8CLED (8-bit) and CC16CLED (16-bit) topology for XC5200 devices.

CEO*
LC0

D 15 Q 15
LC3 LC3
TC
D 14 Q 14
LC2 LC2

D 13 Q 13
LC1 LC1

CEO* D 12 Q 12
LC0 LC0 LC0

D7 Q7 D 11 Q 11
LC3 LC3 LC3 LC3
B7
D6 Q6 D 10 Q 10
LC2 LC2 LC2 LC2
B6
D5 Q5 D9 Q9
LC1 LC1 LC1 LC1
B5
D4 Q4 D8 Q8
LC0 LC0 LC0 LC0
B4

D3 Q3 D7 Q7
LC3 LC3 LC3 LC3
B3
D2 Q2 D6 Q6
LC2 LC2 LC2 LC2
B2
D1 Q1 D5 Q5
LC1 LC1 LC1 LC1
B1
D0 Q0 D4 Q4
LC0 LC0 LC0 LC0
B0

CY_INIT D3 Q3
LC3 LC3 LC3

D2 Q2
LC2 LC2
8-Bit Q1
D1
LC1 LC1

D0 Q0
LC0 LC0

CY_INIT
LC3

x8209 16-Bit

Libraries Guide, Release M1.5 4-39

4-40
AND2
RLOC=R0C1 CO_UP TC_UP
CY4 RLOC=R0C0 CY4
AND2
B1 (G1) COUT B1 (G1) COUT
A1 (G4) COUT0 A1 (G4) COUT0 CEO
OR2
B0 (F2) B0 (F2)
A0 (F1) A0 (F1) TC
ADD (F3) ADD(F3)
Q[7:0]
CARRY MODE CIN CARRY MODE CIN

CO_UP TC_DN
CO_DN
EXAMINE-CI EXAMINE-CI
CY4_42 CY4_42 AND2B2
FMAP FMAP
CY4 RLOC=R1C0 CY4 RLOC=R1C1
L I4 XOR2 L_UP I4
MD7_UP TQ7_DN MD7
Q7 I3 B1 (G1) COUT TQ7_UP B1 (G1) COUT M2_1 Q7 I3
O C6_UP M2_1 C6_DN O
D7 I2 A1 (G4) COUT0 D0 A1 (G4) COUT0 D0 MD7_UP I2
O MD7_UP O MD7
C6_UP I1 B0 (F2) D7 D1 B0 (F2) MD7_UP XNOR2 D1 FDCE C6_DN I1
A0 (F1) A0 (F1) Q7
S0 MD7_UP S0 MD7
RLOC=R1C0.G ADD (F3) ADD(F3) D Q RLOC=R1C1.G
CE
Libraries Guide, Release M1.5

FMAP CARRY MODE CIN CARRY MODE CIN C CLR FMAP

Q7
L I4 C5_DN L_UP I4
MD6_UP TQ6_DN RLOC=R1C1.FFY MD6
Q6 I3 M2_1 Q6 I3
O INC-FG-CI DEC-FG-CI D0 O
D6 I2 O MD6 MD6_UP I2
XOR2 CY4_25 MD6_UP D1 FDCE
C5_UP I1 CY4_18 C5_UP TQ6_UP Q6 C5_DN I1
M2_1 XNOR2 S0
D0 MD6 D Q
O MD6_UP
RLOC=R1C0.F D6 D1 CE RLOC=R1C1.F
S0 MD6_UP C
CLR Q6
RLOC=R1C1.FFX
RLOC=R2C0
FMAP FMAP

Figure 4-24
CY4 CY4 RLOC=R2C1
XOR2 XNOR2
L I4 TQ5_UP TQ5_DN L_UP I4
MD5_UP B1 (G1) COUT B1 (G1) COUT C4_DN M2_1 MD5
Q5 I3 C4_UP M2_1 Q5 I3
O A1 (G4) COUT0 D0 A1 (G4) COUT0 D0 O
D5 I2 O MD5_UP O MD5 MD5_UP I2
B0 (F2) D5 D1 B0 (F2) MD5_UP D1 FDCE
C4_UP I1 Q5 C4_DN I1
A0 (F1) S0 A0 (F1) S0
ADD (F3) MD5_UP ADD(F3) MD5 D Q
RLOC=R2C0.G CE RLOC=R2C1.G
CARRY MODE CIN CARRY MODE CIN C CLR
FMAP Q5 FMAP

L I4 C3_DN RLOC=R2C1.FFY L_UP I4

MD4_UP TQ4_DN M2_1 MD4
Q4 I3 INC-FG-CI DEC-FG-CI D0 MD4 Q4 I3 O
O MD4_UP O
D4 I2 XOR2 D1 FDCE MD4_UP I2
CY4_18 C3_UP TQ4_UP M2_1 CY4_25 Q4
C3_UP I1 XNOR2 S0 C3_DN I1
D0 MD4_UP MD4 D Q
O
RLOC=R2C0.F D4 D1 CE RLOC=R2C1.F
S0 MD4_UP C CLR
Q4
RLOC=R2C1.FFX
FMAP RLOC=R3C0 FMAP

L I4 CY4 CY4 RLOC=R3C1 L_UP I4

MD3_UP XOR2 XNOR2 MD3
Q3 I3 Q3 I3
O B1 (G1) COUT TQ3_UP M2_1 B1 (G1) COUT C2_DN TQ3_DN M2_1 O
D3 I2 C2_UP MD3_UP I2
A1 (G4) COUT0 D0 A1 (G4) COUT0 D0
C2_UP I1 O MD3_UP O MD3 C2_DN I1
B0 (F2) D3 D1 B0 (F2) MD3_UP D1 FDCE
A0 (F1) S0 A0 (F1) S0 Q3
RLOC=R3C0.G MD3_UP MD3 D Q RLOC=R3C1.G
ADD(F3) ADD(F3)
CE FMAP
FMAP CARRY MODE CIN
CIN CARRY MODE C CLR
Q3 L_UP
L I4 I4 MD2
MD2_UP C1_DN Q2
Q2 I3 TQ2_DN M2_1 RLOC=R3C1.FFY I3 O
O MD2_UP
D2 I2 INC-FG-CI DEC-FG-CI D0 O I2
MD2
C1_UP I1 CY4_18 XOR2 CY4_25 MD2_UP D1 FDCE C1_DN I1
C1_UP M2_1 Q2
TQ2_UP XNOR2 S0
RLOC=R3C0.F D0 MD2_UP MD2 D Q RLOC=R3C1.F
O
D2 D1 CE
S0 C
MD2_UP CLR Q2
RLOC=R4C0 RLOC=R3C1.FFX
FMAP FMAP
L I4 CY4 CY4 RLOC=R4C1 L_UP I4
MD1_UP XOR2 XNOR2 MD1
Q1 I3 B1 (G1) COUT TQ1_UP B1 (G1) COUT TQ1_DN Q1 I3 O
O C0_UP M2_1 C0_DN M2_1
D1 I2 A1 (G4) COUT0 MD1_UP I2
D0 O MD1_UP A1 (G4) COUT0 D0 O MD1
C0_UP I1 B0 (F2) B0 (F2) MD1_UP C0_DN I1
D1 D1 D1 FDCE
A0 (F1) S0 A0 (F1) S0 Q1
RLOC=R4C0.G MD1_UP MD1 D Q RLOC=R4C1.G
ADD(F3) ADD(F3)
CE FMAP
FMAP CIN
CIN CARRY MODE C
CLR Q1
L I4 L_UP I4
MD0_UP MD0
Q0 I3 RLOC=R4C1.FFY Q0 I3
O O

CC8CLED Implementation XC4000, Spartans

D0 I2 INC-FG-1 DEC-FG-0 MD0_UP I2
I1 CY4_26 I1
CY4_19
RLOC=R4C0.F RLOC=R4C1.F
TQ0_UP TQ0_DN M2_1
M2_1 D0
D0 O MD0
INV O MD0_UP MD0_UP INV D1 FDCE
D0 D1 Q0
S0
S0 MD0 D Q
MD0_UP
CE
D[7:0] C
CLR Q0
OR2 RLOC=R4C1.FFX
UP L_UP
UP

OR2
L L_CE
L
CE
CE
C
C
CLR
CLR X7599

Xilinx Development System

Design Elements (CC8CLED, CC16CLED)

CEO

AND2
Q[7:0]

CO RLOC=R0C0.LC3
INV DN7
SQ7 S CY_MUX
Q7 0 1
XOR2 DI CI

FMAP C7 M2_1 FDCE FMAP

TQ7 D0
O MD7 Q7 L
I4 D7 D1 D Q I4
I3 XOR2 D7 I3
O SQ7 S0 CE O MD7
UP I2 C7 I2
C
Q7 CLR Q7 Q7
I1 I1
RLOC=R0C1.LC3
RLOC=R0C0.LC3 CO RLOC=R0C0.LC2 RLOC=R0C1.LC3
INV DN6
SQ6 S CY_MUX
Q6 0 1
FMAP XOR2 DI CI FMAP
L
I4 C6 M2_1 FDCE I4
I3 TQ6 D0 D6 I3
UP O SQ6 O MD6 Q6
C6 O MD6
I2 D6 D1 D Q I2
Q6 XOR2 S0 CE Q6
I1 I1
C
CLR Q6
RLOC=R0C0.LC2 RLOC=R0C1.LC2
RLOC=R0C1.LC2
CO RLOC=R0C0.LC1
INV DN5
CY_MUX
FMAP SQ5 S FMAP
Q5 0 1
L
I4 XOR2 DI CI I4
I3 D5 I3
UP O SQ5 M2_1 C5 O MD5
I2 C5 FDCE I2
Q5 TQ5 D0 Q5
I1 O MD5 Q5 I1
D5 D1 D Q
XOR2 S0 CE
RLOC=R0C0.LC1 RLOC=R0C1.LC1
C
CLR Q5

RLOC=R0C1.LC1
FMAP CO
FMAP
INV DN4 RLOC=R0C0.LC0
L
I4 SQ4 S CY_MUX I4
Q4 0 1 D4
I3 I3
UP O SQ4 XOR2 DI CI C4 O MD4
I2 I2
Q4 Q4
I1 I1
C4 M2_1 FDCE
TQ4 D0
RLOC=R0C0.LC0 O MD4 Q4 RLOC=R0C1.LC0
D4 D1 D Q
XOR2 S0 CE
C CLR
FMAP Q4 FMAP
RLOC=R0C1.LC0 L
I4 I4
CO RLOC=R1C0.LC3 D3
I3 INV DN3 I3
UP O SQ3 SQ3 S CY_MUX C3 O MD3
I2 Q3 I2
Q3 0 1 Q3
I1 I1
XOR2 DI CI

RLOC=R1C0.LC3 M2_1 FDCE RLOC=R1C1.LC3

C3
TQ3 D0
O MD3 Q3
D3 D1 D Q
FMAP XOR2 S0 CE FMAP
C L
I4 CLR Q3 I4
I3 D2 I3
UP O SQ2 RLOC=R1C1.LC3 C2 O MD2
I2 CO RLOC=R1C0.LC2 I2
Q2 INV DN2 Q2
I1 SQ2 S CY_MUX I1
Q2 0 1
RLOC=R1C0.LC2 XOR2 DI CI RLOC=R1C1.LC2

C2 M2_1 FDCE
TQ2 D0
FMAP O MD2 Q2 FMAP
D2 D1 D Q
XOR2 CE L
I4 S0 I4
I3 C D1 I3
UP O SQ1 CLR Q2 C1 O MD1
I2 I2
Q1 Q1
I1 RLOC=R1C1.LC2 I1
CO RLOC=R1C0.LC1
INV DN1
RLOC=R1C0.LC1 SQ1 S CY_MUX RLOC=R1C1.LC1
Q1 0 1
XOR2 DI CI
FMAP FMAP
C1 M2_1 FDCE
TQ1 D0 L
I4 O MD1 Q1 I4
I3 D1 D1 D Q D0 I3
UP O SQ0 XOR2 S0 CE C0 O MD0
I2 I2
Q0 C Q0
I1 CLR Q1 I1

RLOC=R1C0.LC0 RLOC=R1C1.LC1 RLOC=R1C1.LC0

CO RLOC=R1C0.LC0
INV DN0
SQ0 S CY_MUX
Q0 0 1
XOR2 DI CI

C0 M2_1 FDCE
TQ0 D0
O MD0 Q0
D0 D1 D Q
XOR2 S0 CE
C
CLR Q0
GND
VCC RLOC=R1C1.LC0
+5
COUT
UP
INIT
CY_INIT
D[7:0] RLOC=R2C0.LC3

L L_CE
CE
C OR2
CLR

X8042

Figure 4-25 CC8CLED Implementation XC5200

Libraries Guide, Release M1.5 4-41

Libraries Guide, Release M1.5

CEO

AND2
Q[7:0]

LO RLOC=R0C0.S1
INV DN7 MUXCY
SQ7 S
Q7 0 1
XOR2 DI CI

FMAP C7 M2_1 FDCE FMAP

TQ7 D0
O MD7 Q7 L
I4 D7 D1 D Q I4
I3 XORCY D7 I3
O SQ7 S0 CE O MD7
UP I2 TQ7 I2
C
Q7 CLR
I1 I1
RLOC=R0C0.S0
RLOC=R0C0.S1 LO RLOC=R0C0.S1 RLOC=R0C0.S0
INV DN6
SQ6 MUXCY_L
S
Q6 0 1
FMAP XOR2 DI CI FMAP
L
I4 C6 M2_1 FDCE I4
I3 TQ6 D0 D6 I3
UP O SQ6 O MD6 Q6
TQ6 I2 O MD6
I2 D6 D1 D Q
Q6 XORCY S0 CE
I1 I1
C
CLR
RLOC=R0C0.S1 RLOC=R0C0.S0
RLOC=R0C0.S0
LO RLOC=R1C0.S1
INV DN5
MUXCY_L
FMAP SQ5 S FMAP
Q5 0 1
L
I4 XOR2 DI CI I4
I3 D5 I3
UP O SQ5 M2_1 TQ5 I2 O MD5
I2 C5 FDCE
Q5 TQ5 D0
I1 O MD5 Q5 I1
D5 D1 D Q
XORCY S0 CE
RLOC=R1C0.S1 RLOC=R1C0.S0
C
CLR

RLOC=R1C0.S0
FMAP LO FMAP
INV DN4 RLOC=R1C0.S1
MUXCY_L L
I4 SQ4 S I4
Q4 0 1 D4 I3
I3
UP O SQ4 XOR2 DI CI TQ4 I2 O MD4
I2
Q4
I1 I1
C4 M2_1 FDCE
TQ4 D0
RLOC=R1C0.S1 O MD4 Q4 RLOC=R1C0.S0
D4 D1 D Q
XORCY S0 CE
C CLR
FMAP FMAP
RLOC=R1C0.S0 L
I4 I4
LO RLOC=R2C0.S1 D3 I3
I3 INV DN3
UP O SQ3 SQ3 MUXCY_L TQ3 I2 O MD3
I2 S
Q3 0 1
Q3
I1 I1
XOR2 DI CI

RLOC=R2C0.S1 M2_1 FDCE RLOC=R2C0.S0

C3
TQ3 D0
O MD3 Q3
D3 D1 D Q
FMAP XORCY S0 CE FMAP
C L
I4 CLR I4
I3 D2 I3
UP O SQ2 RLOC=R2C0.S0 TQ2 I2 O MD2
I2 LO RLOC=R2C0.S1
Q2 INV DN2
I1 SQ2 MUXCY_L I1
S
Q2 0 1
RLOC=R2C0.S1 XOR2 DI CI RLOC=R2C0.S0

C2 M2_1 FDCE
TQ2 D0
FMAP O MD2 Q2 FMAP
D2 D1 D Q
XORCY CE L
I4 S0 I4
I3 C D1 I3
UP O SQ1 CLR TQ1 I2 O MD1
I2
Q1
I1 RLOC=R2C0.S0 I1
LO RLOC=R3C0.S1
INV DN1
RLOC=R3C0.S1 SQ1 S
MUXCY_L RLOC=R3C0.S0
Q1 0 1
XOR2 DI CI
FMAP FMAP
C1 M2_1 FDCE
TQ1 D0 L
I4 O MD1 Q1 I4
I3 D1 D1 D Q D0 I3
UP O SQ0 XORCY S0 CE TQ0 I2 O MD0
I2
Q0 C
I1 CLR I1

RLOC=R3C0.S1 RLOC=R3C0.S0 RLOC=R3C0.S0

LO RLOC=R3C0.S1
INV DN0
SQ0 MUXCY_L
S
Q0 0 1
XOR2 DI CI

C0 M2_1 FDCE
TQ0 D0
O MD0 Q0
D0 D1 D Q
XORCY S0 CE
C
CLR
GND
VCC RLOC=R3C0.S0
+5

D[7:0]

L L_CE
CE
C OR2
CLR X8714

Figure 4-26 CC8CLED Implementation Virtex

4-42 Xilinx Development System

Design Elements (CC8RE, CC16RE)

CC8RE, CC16RE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and
Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro Macro

CC8RE and CC16RE are, respectively, 8- and 16-bit (stage), synchronous, resettable,
CC8RE Q[7:0]
cascadable binary counters. These counters are implemented using carry logic with
CEO
CE relative location constraints to ensure efficient placement of logic. The synchronous
C TC
reset (R) is the highest priority input. When R is High, all other inputs are ignored; the
Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on
R
X4288 the Low-to-High clock (C) transition. The Q outputs increment when the clock enable
input (CE) is High during the Low-to-High clock transition. The counter ignores clock
CC16RE Q[15:0] transitions when CE is Low. The TC output is High when all Q outputs and CE are
CE CEO High.
C TC
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C and R inputs in parallel. CEO is active
R
X4283 (High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, with Low outputs, when power is applied.
FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active.
GR (XC5200) and GSR (XC4000, Spartans, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or
STARTUP_VIRTEX symbol.

Inputs Outputs

R CE C Qz – Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No Chg No Chg 0
0 1 ↑ Inc TC CEO
z = 7 for CC8RE; z = 15 for CC16RE
TC = Qz•Q(z-1)•Q(z-2)•...•Q0•CE
CEO = TC•CE

Libraries Guide, Release M1.5 4-43

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the CC8RE (8-bit) and CC16RE (16-bit) topology for XC4000 and Spartan series
devices.
TC*

CEO*
D 15 Q 15

D 14 Q 14
TC* D 13 Q 13

CEO* D 12 Q 12
D7 Q7 D 11 Q 11

D6 Q6 D 10 Q 10
D5 Q5 D9 Q9

D4 Q4 D8 Q8
D3 Q3 D7 Q7

D2 Q2 D6 Q6
D1 Q1 D5 Q5

D0 Q0 D4 Q4
D3 Q3
8-Bit
D2 Q2
D1 Q1

D0 Q0

X8214 16-Bit

4-44 Xilinx Development System

Design Elements (CC8RE, CC16RE)

Topology for XC5200

This is the CC8RE (8-bit) and CC16RE (16-bit) topology for XC5200 devices.

CEO*
LC0

D 15 Q 15
LC3 LC3
TC
D 14 Q 14
LC2 LC2

D 13 Q 13
LC1 LC1

CEO* D 12 Q 12
LC0 LC0 LC0

D7 Q7 D 11 Q 11
LC3 LC3 LC3 LC3
B7
D6 Q6 D 10 Q 10
LC2 LC2 LC2 LC2
B6
D5 Q5 D9 Q9
LC1 LC1 LC1 LC1
B5
D4 Q4 D8 Q8
LC0 LC0 LC0 LC0
B4

D3 Q3 D7 Q7
LC3 LC3 LC3 LC3
B3
D2 Q2 D6 Q6
LC2 LC2 LC2 LC2
B2
D1 Q1 D5 Q5
LC1 LC1 LC1 LC1
B1
D0 Q0 D4 Q4
LC0 LC0 LC0 LC0
B0

CY_INIT D3 Q3
LC3 LC3 LC3

D2 Q2
LC2 LC2
8-Bit Q1
D1
LC1 LC1

D0 Q0
LC0 LC0

CY_INIT
LC3

x8209 16-Bit

Libraries Guide, Release M1.5 4-45

Libraries Guide, Release M1.5

RLOC=R0C0
CY4

B1 (G1) COUT
A1 (G4) COUT0
B0 (F2) VCC
A0 (F1)
ADD (F3)
CEO
CARRY MODE CIN
AND2
C0
TC
EXAMINE-CI
CY4_42 AND2 Q[7:0]
RLOC=R1C0
CY4 M2_1 AND2B1
XOR2 D0 FDCE
COUT O CE_M7 R_TQ7
B1 (G1) TQ7 D1 Q7
C6 D Q
A1 (G4) COUT0 S0
CE FMAP
B0 (F2)
C CE
A0 (F1) CLR I4
R
ADD (F3) Q7 I3 R_TQ7
Q7 O
CARRY MODE RLOC=R1C0.FFY I2
CIN C6
I1

M2_1
XOR2 D0 AND2B1 FDCE RLOC=R1C0.G
INC-FG-CI C5 O CE_M6 R_TQ6
TQ6 D1 Q6
CY4_18 D Q FMAP
S0 CE
CE
I4
C R
CLR I3 R_TQ6
Q6 O
Q6 I2
RLOC=R1C0.FFX C5
I1

RLOC=R1C0.F
RLOC=R2C0
CY4 M2_1
XOR2 D0 AND2B1 FDCE
B1 (G1)
COUT O CE_M5 R_TQ5
C4 TQ5 D1 Q5
D Q
A1 (G4) COUT0 S0
CE
B0 (F2) FMAP
C
A0 (F1) CLR CE
I4
ADD (F3) Q5 R
I3 R_TQ5
RLOC=R2C0.FFY Q5 O
CARRY MODE CIN I2
M2_1 C4
I1
XOR2 D0 AND2B1 FDCE
C3 O CE_M4 R_TQ4
TQ4 D1 Q4 RLOC=R2C0.G
INC-FG-CI D Q
S0
CY4_18 CE
FMAP
C
CLR CE
I4
Q4 R
RLOC=R2C0.FFX I3 R_TQ4
Q4 O
I2
C3 I1

RLOC=R2C0.F
RLOC=R3C0
CY4 M2_1
XOR2 D0 AND2B1 FDCE
COUT O CE_M3
B1 (G1) TQ3 D1 R_TQ3 Q3
C2 D Q
A1 (G4) COUT0 S0 FMAP
CE
B0 (F2) CE
C I4
A0 (F1) CLR R
I3 R_TQ3
ADD (F3) Q3 Q3 O
RLOC=R3C0.FFY I2
CARRY MODE CIN C2
I1
M2_1
XOR2 D0 AND2B1 FDCE RLOC=R3C0.G
C1 O CE_M2
TQ2 D1 R_TQ2 Q2
INC-FG-CI D Q
S0 FMAP
CY4_18 CE
CE
C I4
CLR R
I3 R_TQ2
Q2 Q2 O
RLOC=R3C0.FFX I2
C1
I1

RLOC=R3C0.F

RLOC=R4C0
CY4 M2_1
XOR2 D0 AND2B1 FDCE
COUT O CE_M1
B1 (G1) TQ1 D1 R_TQ1 Q1
C0 D Q
A1 (G4) COUT0 S0 FMAP
CE
B0 (F2) CE
C I4
A0 (F1) CLR R
I3 R_TQ1
ADD (F3) Q1 Q1 O
RLOC=R4C0.FFY I2
CARRY MODE CIN C0
I1

RLOC=R4C0.G
INC-FG-1
FMAP
CY4_19
CE
I4
M2_1 R
I3 R_TQ0
D0 AND2B1 FDCE Q0 O
INV O CE_M0 I2
TQ0 D1 R_TQ0 Q0
D Q I1
CE S0
CE
C RLOC=R4C0.F
C
R CLR
Q0
RLOC=R4C0.FFX

X6498

GND

Figure 4-27 CC8RE Implementation XC4000, Spartans

4-46 Xilinx Development System

Design Elements (CC8RE, CC16RE)

CEO

AND2 Q[7:0]

CO
CY_MUX VCC
Q7 S RLOC=R0C0.LC3 FMAP
0 1
CE
DI CI I4
M2_1 Q7
C7 I3 R_TQ7
TQ7 D0 FDCE C7 O
O CE_M7 I2
Q7 D1 R_TQ7 Q7 R
D Q I1
XOR2 S0 CEB7
CO CE
INV AND2B1 RLOC=R0C1.LC3
CY_MUX C
RLOC=R0C0.LC2 CLR
Q6 S FMAP
0 1
RLOC=R0C1.LC3 CE
DI CI I4
M2_1 Q6
C6 I3 R_TQ6
TQ6 D0 FDCE C6 O
O CE_M6 I2
Q6 D1 R_TQ6 Q6 R
D Q I1
XOR2 S0 CEB6 CE
CO AND2B1 RLOC=R0C1.LC2
INV C
CY_MUX CLR
Q5 S RLOC=R0C0.LC1 FMAP
0 1 RLOC=R0C1.LC2
CE
DI CI I4
M2_1 Q5
C5 I3 R_TQ5
TQ5 D0 FDCE C5 O
O CE_M5 I2
Q5 D1 R_TQ5 Q5 R
D Q I1
XOR2 S0 CEB5
CO CE
INV
AND2B1 RLOC=R0C1.LC1
CY_MUX C
Q4 RLOC=R0C0.LC0 CLR
S FMAP
0 1
RLOC=R0C1.LC1 CE I4
DI CI
M2_1 Q4
C4 I3 R_TQ4
TQ4 D0 FDCE C4 O
O CE_M4 I2
Q4 D1 R_TQ4 Q4 R
D Q I1
XOR2 S0 CEB4 CE
CO INV
AND2B1 RLOC=R0C1.LC0
C
CY_MUX CLR
Q3 S RLOC=R1C0.LC3 FMAP
0 1 RLOC=R0C1.LC0
CE I4
DI CI
M2_1 Q3 R_TQ3
C3 I3
TQ3 D0 FDCE C3 O
O CE_M3 I2
Q3 D1 R_TQ3 Q3 R
D Q I1
XOR2 S0 CEB3
CO CE
AND2B1 RLOC=R1C1.LC3
CY_MUX INV C
RLOC=R1C0.LC2 CLR
Q2 S FMAP
0 1
RLOC=R1C1.LC3 CE
DI CI I4
M2_1 Q2
C2 I3 R_TQ2
TQ2 D0 FDCE C2 O
O CE_M2 I2
Q2 D1 R_TQ2 Q2 R
D Q I1
XOR2 S0 CEB2 CE
CO INV AND2B1 RLOC=R1C1.LC2
C
CY_MUX CLR
Q1 S RLOC=R1C0.LC1 FMAP
0 1 RLOC=R1C1.LC2
CE
DI CI I4
M2_1 Q1
C1 I3 R_TQ1
TQ1 D0 FDCE C1 O
O CE_M1 I2
Q1 D1 R_TQ1 Q1 R
D Q I1
XOR2 S0 CEB1
CO CE
AND2B1 RLOC=R1C1.LC1
CY_MUX INV C
RLOC=R1C0.LC0 CLR
Q0 S FMAP
0 1
RLOC=R1C1.LC1 CE
DI CI I4
M2_1 Q0
C0 I3 R_TQ0
TQ0 D0 FDCE C0 O
O CE_M0 I2
Q0 D1 R_TQ0 Q0 R
D Q I1
XOR2 S0 CEB0 CE
GND AND2B1 RLOC=R1C1.LC0
INV C
VCC CLR
COUT
INIT RLOC=R1C1.LC0
CY_INIT
RLOC=R2C0.LC3

CE
R
C X6366

GND

Figure 4-28 CC8RE Implementation XC5200

Libraries Guide, Release M1.5 4-47

Libraries Guide, Release M1.5

CEO

AND2
Q[7:0]

LO
MUXCY VCC
Q7 S RLOC=R0C0.S1 FMAP
0 1
DI CI CE
I4
M2_1 Q7
R_TQ7
C7 I3
TQ7 D0 FDCE TQ7 O
O CE_M7 R_TQ7
I2
Q7 D1 Q7 R
D Q I1
XORCY S0
LO CE
INV CEB7 AND2B1 RLOC=R0C0.S0
MUXCY_L C
CLR
Q6 S RLOC=R0C0.S1 FMAP
0 1
DI CI RLOC=R0C0.S0 CE
I4
M2_1 Q6
C6 I3 R_TQ6
TQ6 D0 FDCE TQ6 O
O CE_M6 I2
Q6 D1 R_TQ6 Q6 R
D Q I1
XORCY S0
CE
INV CEB6 AND2B1 RLOC=R0C0.S0
LO C
MUXCY_L CLR
Q5 S RLOC=R1C0.S1 FMAP
0 1 RLOC=R0C0.S0 CE
DI CI I4
M2_1 Q5
I3 R_TQ5
C5
TQ5 D0 FDCE TQ5 O
O CE_M5 R_TQ5
I2
Q5 D1 Q5 R
D Q I1
XORCY S0
LO CE
INV CEB5 AND2B1 RLOC=R1C0.S0
MUXCY_L C
CLR
Q4 S RLOC=R1C0.S1 FMAP
0 1
RLOC=R1C0.S0 CE
DI CI I4
M2_1 Q4
C4 I3 R_TQ4
TQ4 D0 FDCE TQ4 O
O CE_M4 R_TQ4
I2
Q4 D1 Q4 R
D Q I1
XORCY S0
CE
LO INV CEB4 AND2B1 RLOC=R1C0.S0
C
MUXCY_L CLR
Q3 S RLOC=R2C0.S1 FMAP
0 1 RLOC=R1C0.S0
DI CI CE
I4
M2_1 Q3
C3 I3 R_TQ3
TQ3 D0 FDCE TQ3 O
O CE_M3 R_TQ3
I2
Q3 D1 Q3 R
D Q I1
XORCY
S0 CE
LO CEB3 AND2B1
INV RLOC=R2C0.S0
MUXCY_L C
CLR
Q2 S RLOC=R2C0.S1 FMAP
0 1
RLOC=R2C0.S0 CE
DI CI I4
M2_1 Q2
C2 I3 R_TQ2
TQ2 D0 FDCE TQ2 O
O CE_M2 I2
Q2 D1 R_TQ2 Q2 R
D Q I1
XORCY S0
CE
LO INV CEB2 AND2B1 RLOC=R2C0.S0
C
MUXCY_L CLR
Q1 S RLOC=R3C0.S1 FMAP
0 1 RLOC=R2C0.S0
CE
DI CI I4
M2_1 Q1
C1 I3 R_TQ1
TQ1 D0 FDCE TQ1 O
O CE_M1 R_TQ1
I2
Q1 D1 Q1 R
D Q I1
XORCY S0
LO CE
INV CEB1 AND2B1 RLOC=R3C0.S0
MUXCY_L C
CLR
Q0 S RLOC=R3C0.S1 FMAP
0 1
RLOC=R3C0.S0 CE
DI CI I4
Q0
C0
M2_1 I3 R_TQ0
TQ0 D0 FDCE TQ0 O
O CE_M0 I2
Q0 D1 R_TQ0 Q0 R
D Q I1
XORCY S0
GND CE
INV CEB0 AND2B1 RLOC=R3C0.S0
VCC C
CLR

RLOC=R3C0.S0

CE
R
C X8712
GND

Figure 4-29 CC8RE Implementation Virtex

4-48 Xilinx Development System

Design Elements (CD4CE)

CD4CE
4-Bit Cascadable BCD Counter with Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

Q0
CD4CE is a 4-bit (stage), asynchronous, clearable, cascadable binary-coded-decimal
CD4CE
Q1 (BCD) counter. The asynchronous clear input (CLR) is the highest priority input.
Q2 When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC),
Q3
and clock enable out (CEO) go to logic level zero, independent of clock transitions.
CE CEO
C TC
The Q outputs increment when clock enable (CE) is High during the Low-to-High
clock (C) transition. The counter ignores clock transitions when CE is Low. The TC
CLR
output is High when Q3 and Q0 are High and Q2 and Q1 are Low.
X4369
The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for FPGA architectures, as shown in the
following state diagram. For XC9000, the counter resets to zero or recovers within the
first clock cycle.

0 1 2 3 4

F 5

E 6

D 7

C B A 9 8

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the CLR and clock inputs
in parallel. CEO is active (High) when TC and CE are High. The maximum length of
the counter is determined by the accumulated CE-to-TC propagation delays versus
the clock period. The clock period must be greater than n(tCE-TC), where n is the
number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage.
When cascading counters, use the CEO output if the counter uses the CE input; use
the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse to
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Libraries Guide, Release M1.5 4-49

Libraries Guide, Release M1.5

Inputs Outputs

CLR CE C Q3 Q2 Q1 Q0 TC CEO
1 X X 0 0 0 0 0 0
0 1 ↑ Inc Inc Inc Inc TC CEO
0 0 X No Chg No Chg No Chg No Chg TC 0
0 1 X 1 0 0 1 1 1
TC = Q3•Q2•Q1•Q0
CEO = TC•CE

FDCE
D0 Q0
D Q
INV CE
C
CLR
Q0

FDCE
AX1
D1 Q1
D Q
AND2B1 CE
XOR2
C
CLR
Q1

FDCE
AX2
D2 Q2
D Q
AND2 CE
AO3B XOR2
C
CLR
AND3 Q2

FDCE
OX3
AO3A D3 Q3
D Q
OR2 CE
AND2 XOR2
C
CLR
Q3

TC
C
CLR
AND4B2 CEO
CE
AND2
X7784

Figure 4-30 CD4CE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

4-50 Xilinx Development System

Design Elements (CD4CE)

vcc
+5

CE
AND2

CLR
C

Q0
Q1
Q2
Q3

AND3B2

FDC
AND5B2
Q0
D Q

OR3
AND4B3
C
CLR FDC
Q0 AND4B2 Q2
D Q
AND2B1 CEO

OR4 C
CLR
AND5B2
Q2
AND4B2
AND4B2
FDC
TC
Q1 AND2B1
D Q
OR3 AND4B2
AND4B2
C
CLR
Q1
AND2B1 AND5B1

FDC
Q3
D Q
OR3
AND5B3 C
CLR
Q3

AND2B1

X7629

Figure 4-31 CD4CE Implementation XC9000

Libraries Guide, Release M1.5 4-51

Libraries Guide, Release M1.5

CD4CLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CD4CLE
CD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, binary-
D0 Q0
D1 Q1
coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest
D2 Q2 priority input. When CLR is High, all other inputs are ignored; the Q outputs,
D3 Q3 terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of
clock transitions. The data on the D inputs is loaded into the counter when the load
L
CE CEO enable input (L) is High during the Low-to-High clock (C) transition. The Q outputs
C TC increment when clock enable input (CE) is High during the Low- to-High clock transi-
tion. The counter ignores clock transitions when CE is Low. The TC output is High
CLR
X4370 when Q3 and Q0 are High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for FPGAs, as shown in the following state
diagram. For XC9000, the counter resets to zero or recovers within the first clock cycle.

0 1 2 3 4

F 5

E 6

D 7

C B A 9 8

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

4-52 Xilinx Development System

Design Elements (CD4CLE)

Inputs Outputs

CLR L CE D3 – D0 C Q3 Q2 Q1 Q0 TC CEO
1 X X X X 0 0 0 0 0 0
0 1 X D3 – D0 ↑ d3 d2 d1 d0 TC CEO
0 0 1 X ↑ Inc Inc Inc Inc TC CEO
0 0 0 X X No Chg No Chg No Chg No Chg TC 0
0 0 1 X X 1 0 0 1 1 1
d = state of referenced input one setup time prior to active clock transition
TC = Q3•Q2•Q1•Q0
CEO = TC•CE

FTCLE
D0
D
L
L
T Q
CE
C
C
CLR
CLR
Q0
Q0

FTCLE
D1
D
L
T1 Q
T
CE
AND2B1
C
CLR
Q1 Q1

FTCLE
D2
D
L
T Q
CE
C
CLR
Q2 Q2

FTCLE
D3
D
TQ2 L
T2 T3 Q
T
AND2 CE
AND2 OR2
C
CLR
TQ03
Q3
AND2
Q3

AND4B2
CEO
CE
AND2
X8109

Figure 4-32 CD4CLE Implementation XC3000

Libraries Guide, Release M1.5 4-53

Libraries Guide, Release M1.5

FTCLEX
D0
D
L
L
T Q
CE
C
C
CLR
CLR
Q0
Q0

FTCLEX
D1
D
L
T1 Q
T
CE
AND2B1
C
CLR
OR_CE_L Q1 Q1

OR2 FTCLEX
D2
D
L
T Q
CE
C
CLR
Q2 Q2

FTCLEX
D3
D
TQ2 L
T2 T3 Q
T
AND2 CE
AND2 OR2
C
CLR
TQ03
Q3
AND2
Q3

AND4B2
CEO
CE
AND2
X7785

Figure 4-33 CD4CLE Implementation XC4000, XC5200, Spartans, Virtex

Q0
Q1
Q2
Q3

INV

INV
AND5B4 INV
AND6

CEO
FDC
AND4B3 D Q
AND5B2
OR4 C AND5B3
CLR TC
AND3B2 FDC
Q0
D0
D Q
AND4B2
AND2 C
AND5B3 OR5 CLR
Q2

AND3B2
AND5B3
D2
AND2

FDC
INV
AND5B3 D Q

OR4
C
CLR INV AND6
AND3B2 Q1

D1 INV
AND2 INV
vcc INV
+5 FDC
INV
AND6 D Q
CE
OR4
L C
CLR
AND3B2 Q3

GRD D3
AND2
C
CLR

X7628

Figure 4-34 CD4CLE Implementation XC9000

4-54 Xilinx Development System

Design Elements (CD4RE)

CD4RE
4-Bit Cascadable BCD Counter with Clock Enable and
Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CD4RE Q0
CD4RE is a 4-bit (stage), synchronous, resettable, cascadable binary-coded-decimal
Q1 (BCD) counter. The synchronous reset input (R) is the highest priority input. When R
Q2 is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
Q3
CE CEO
enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q
C TC
outputs increment when the clock enable input (CE) is High during the Low-to-High
clock transition. The counter ignores clock transitions when CE is Low. The TC output
R is High when Q3 and Q0 are High and Q2 and Q1 are Low.
X4371

The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for FPGAs, as shown in the following state
diagram. For XC9000, the counter resets to zero or recovers within the first clock cycle.

0 1 2 3 4

F 5

E 6

D 7

C B A 9 8

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the R and clock inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Libraries Guide, Release M1.5 4-55

Libraries Guide, Release M1.5

Inputs Outputs

R CE C Q3 Q2 Q1 Q0 TC CEO
1 X ↑ 0 0 0 0 0 0
0 1 ↑ Inc Inc Inc Inc TC CEO
0 0 X No Chg No Chg No Chg No Chg TC 0
0 1 X 1 0 0 1 1 1
TC = Q3•Q2•Q1•Q0
CEO = TC•CE

FDRE
D0 Q0
D Q
INV CE
C
R
Q0

FDRE
AX1
D1 Q1
D Q
AND2B1 CE
XOR2
C
R
Q1

FDRE
AX2
D2 Q2
D Q
AND2 CE
AO3B XOR2
C
R
AND3 Q2

FDRE
OX3
AO3A D3 Q3
D Q
OR2 CE
AND2 XOR2
C
R
Q3

C TC
R

AND4B2 CEO
R
AND2

X7786

Figure 4-35 CD4RE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

4-56 Xilinx Development System

Design Elements (CD4RE)

R
Q0
Q1
Q2
Q3

INV

AND5B4 INV
INV AND6
FD
D Q
OR3
AND4B3 C
CEO
FD
Q0 AND5B3
D Q
AND5B2
AND3B2
OR4 C

Q2
TC
AND5B3

AND5B3 AND4B2

FD AND3B2
D Q
OR3
INV
C
AND5B3
Q1

INV AND6
AND3B2

FD
INV
INV D Q
INV OR3
INV
VCC C
+5 AND6
Q3
CE
AND2
AND3B2

X7627

Figure 4-36 CD4RE Implementation XC9000

Libraries Guide, Release M1.5 4-57

Libraries Guide, Release M1.5

CD4RLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and
Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CD4RLE is a 4-bit (stage), synchronous, loadable, resettable, binary-coded-decimal

D0 CD4RLE Q0
D1 Q1
(BCD) counter. The synchronous reset input (R) is the highest priority input. When R
D2 Q2 is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
D3 Q3 enable out (CEO) go to logic level zero on the Low-to-High clock transitions. The data
on the D inputs is loaded into the counter when the load enable input (L) is High
L
CE CEO
during the Low-to-High clock (C) transition. The Q outputs increment when the clock
C TC enable input (CE) is High during the Low-to-High clock transition. The counter
ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are
R
X4372
High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for FPGAs, as shown in the following state
diagram. For XC9000, the counter resets to zero or recovers within the first clock cycle.

0 1 2 3 4

F 5

E 6

D 7

C B A 9 8

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the R, L, and C inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

4-58 Xilinx Development System

Design Elements (CD4RLE)

Inputs Outputs

R L CE D3 – D0 C Q3 Q2 Q1 Q0 TC CEO
1 X X X ↑ 0 0 0 0 0 0
0 1 X D3 – D0 ↑ d3 d2 d1 d0 TC CEO
0 0 1 X ↑ Inc Inc Inc Inc TC CEO
0 0 0 X X No Chg No Chg No Chg No Chg TC 0
0 0 1 X X 1 0 0 1 1 1
d = state of referenced input one setup time prior to active clock transition
TC = Q3•Q2•Q1•Q0
CEO = TC•CE

FTRSLE
D0
D S
L
L
T Q
CE
C
C
R
R
Q0
Q0

FTRSLE
D1
D S
L
T1
T Q
CE
AND2B1
C
R
Q1 Q1

FTRSLE
D2
D S
L
T Q
CE
C
R
Q2 Q2

FTRSLE
D3
D S
TQ2 L
T2 T3
T Q
AND2 CE
AND2 OR2
C
R
TQ03
Q3
AND2
Q3

AND4B2
CEO
CE
AND2

GND X7787

Figure 4-37 CD4RLE Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

Libraries Guide, Release M1.5 4-59

Libraries Guide, Release M1.5

C
VCC
Q0
+5 Q1
Q2
CE Q3
AND2

R INV CEO
L INV
INV
OR2 INV AND5B2
INV AND6

GND
TC

FD AND4B2

AND5B4 D Q
OR4
C

Q0
AND4B3

AND3B1

INV
INV

INV
INV AND6

INV
INV
INV FD

INV AND6 D Q
OR4
C

Q1
AND4B3

AND3B1

INV
INV

INV
INV AND7

INV
INV
INV

INV AND6

FD
INV
INV D Q
INV
OR5
C
INV AND6
Q2

AND4B3

AND3B1

INV
INV

INV AND7

INV
INV
INV
INV FD
INV
D Q
AND7
OR4
C

AND4B3

AND3B1

X7626

Figure 4-38 CD4RLE Implementation XC9000

4-60 Xilinx Development System

Design Elements (CJ4CE, CJ5CE, CJ8CE)

CJ4CE, CJ5CE, CJ8CE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CJ4CE, CJ5CE, and CJ8CE are clearable Johnson/shift counters. The asynchronous
CJ4CE
Q0 clear (CLR) input, when High, overrides all other inputs and causes the data (Q)
Q1 outputs to go to logic level zero, independent of clock (C) transitions. The counter
CE Q2
C Q3
increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE)
is High during the Low-to-High clock transition. Clock transitions are ignored when
CLR CE is Low.
X4112

For CJ4CE, the Q3 output is inverted and fed back to input Q0 to provide continuous
CJ5CE
counting operation. For CJ5CE, the Q4 output is inverted and fed back to input Q0.
Q0 For CJ8CE, the Q7 output is inverted and fed back to input Q0.
Q1
Q2 The counter is asynchronously cleared, output Low, when power is applied. For
CE Q3
C
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
Q4
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
CLR
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
X4114
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
CJ8CE Q[7:0]

CE
C
Inputs Outputs
CLR X4118 CLR CE C Q0 Q1 Q2 Q3
1 X X 0 0 0 0
0 0 X No Chg No Chg No Chg No Chg
0 1 ↑ q3 q0 q1 q2
q = state of referenced output one setup time prior to active clock transition

CJ4CE Truth Table

Inputs Outputs

CLR CE C Q0 Q1 Q2 Q3 Q4
1 X X 0 0 0 0 0
0 0 X No Chg No Chg No Chg No Chg No Chg
0 1 ↑ q4 q0 q1 q2 q3
q = state of referenced output one setup time prior to active clock transition

CJ5CE Truth Table

Libraries Guide, Release M1.5 4-61

Libraries Guide, Release M1.5

Inputs Outputs

CLR CE C Q0 Q1 – Q7
1 X X 0 0
0 0 X No Chg No Chg
0 1 ↑ q7 q0 – q6
q = state of referenced output one setup time prior to active clock transition

CJ8CE Truth Table

Q[7:0]
Q7
FDCE
FDCE Q3 Q4
D Q
Q7B Q0
D Q CE
INV CE C
C CLR
CLR Q4
Q0

FDCE
FDCE Q5
D Q
Q1
D Q CE
CE C
CLR
C
CLR Q5
Q1

FDCE
FDCE Q6
D Q
Q2
D Q CE
CE C
CLR
C
CLR Q6
Q2

FDCE
FDCE Q7
D Q
Q3
D Q CE
CE C
CLR
C
CLR Q7
Q3

CE
C
CLR
X7789

Figure 4-39 CJ8CE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

4-62 Xilinx Development System

Design Elements (CJ4RE, CJ5RE, CJ8RE)

CJ4RE, CJ5RE, CJ8RE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and
Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

CJ4RE, CJ5RE, and CJ8RE are resettable Johnson/shift counters. The synchronous
CJ4RE
Q0 reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs
Q1
CE
to go to logic level zero during the Low-to-High clock (C) transition. The counter
Q2
C Q3
increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE)
is High during the Low-to-High clock transition. Clock transitions are ignored when
R X4113
CE is Low.
For CJ4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous
CJ5RE counting operation. For CJ5RE, the Q4 output is inverted and fed back to input Q0.
Q0
For CJ8RE, the Q7 output is inverted and fed back to input Q0.
Q1
Q2 The counter is asynchronously cleared, output Low, when power is applied. For
CE Q3
C Q4
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
R
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
X4115
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
CJ8RE Q[7:0]

CE
C
Inputs Outputs
R
X4119 R CE C Q0 Q1 Q2 Q3
1 X ↑ 0 0 0 0
0 0 X No Chg No Chg No Chg No Chg
0 1 ↑ q3 q0 q1 q2
q = state of referenced output one setup time prior to active clock transition

CJ4RE Truth Table

Inputs Outputs

R CE C Q0 Q1 Q2 Q3 Q4
1 X ↑ 0 0 0 0 0
0 0 X No Chg No Chg No Chg No Chg No Chg
0 1 ↑ q4 q0 q1 q2 q3
q = state of referenced output one setup time prior to active clock transition

CJ5RE Truth Table

Libraries Guide, Release M1.5 4-63

Libraries Guide, Release M1.5

Inputs Outputs

R CE C Q0 Q1 – Q7
1 X ↑ 0 0
0 0 X No Chg No Chg
0 1 ↑ q7 q0 – q6
q = state of referenced output one setup time prior to active clock transition

CJ8RE Truth Table

Q[7:0]
Q7
FDRE
FDRE Q3 Q4
D Q
Q7B Q0
D Q CE
INV CE C
C R
R Q4
Q0

FDRE
FDRE Q5
D Q
Q1
D Q CE
CE C
R
C
R Q5
Q1

FDRE
FDRE Q6
D Q
Q2
D Q CE
CE C
R
C
R Q6
Q2

FDRE
FDRE Q7
D Q
Q3
D Q CE
CE C
R
C
R Q7
Q3

CE
C
R
X7790

Figure 4-40 CJ8RE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

4-64 Xilinx Development System

Design Elements (CK_DIV)

CK_DIV
Internal Multiple-Frequency Clock Divider

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

CK_DIV
CK_DIV divides a user-provided external clock signal with different divide factors on
OSC1
either or both of the outputs. Only one CK_DIV may be used per design. The CK_DIV
C OSC2 is not available if the OSC5 element is used.
The clock frequencies of the OSC1 and OSC2 outputs are determined by specifying
@DIVIDE1_BY=
@DIVIDE2_BY= the DIVIDE1_BY=n1 attribute for the OSC1 output and the DIVIDE2_BY=n2 attribute
X4970 for the OSC2 output. n1 and n2 are integer numbers by which the clock input (C) is
divided to produce the desired output clock frequency. The available values of n1 and
n2 are shown in the following table.

n1 n2
4 2
16 8
64 32
256 128
1,024
4,096
16,384
65,536

Libraries Guide, Release M1.5 4-65

Libraries Guide, Release M1.5

CLB
CLB Configuration Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive N/A N/A N/A N/A N/A N/A N/A

CLB
The CLB symbol enables you to manually specify a CLB configuration. It allows you
A to enter portions of a logic design directly in terms of the physical CLB, rather than
B schematically. Using the CLB symbol provides precise partitioning control and
X
C requires knowledge of the CLB architecture. Use it in place of the equivalent captured
D
E
logic and not in conjunction with it.
DI
A blank XC3000 CLB primitive symbol and its corresponding configured CLB primi-
EC Y
K
tive and circuit are shown in the following figure.
RD

A
X7560 B
C X
D
E
DI
EC Y
K
RD
CLB
AA
FG
X:QX Y:QY DX:F DY:G CLK:K ENCLK:EC
F=A*B*E*QY
G=A*B*D*QX

A U3 U4
B F X
E D Q

AND4
C
CE

FDCE

U6 U5
G Y
D Q
D
AND4
C
CE
K
FDCE
EC

X7234

Figure 4-41 XC3000 CLB Primitive Example and Equivalent Circuit

CLB symbol pins correspond to actual CLB pins. Signals connected to these pins in a
schematic are connected to the corresponding CLB pins in the design. You must
specify the BASE, CONFIG, and EQUATE commands for the CLB. It is not necessary
for the translator program to parse the commands specifying the CLB configuration.
The mapping program from the LCA Xilinx netlist to the LCA design checks these
commands for errors.

4-66 Xilinx Development System

Design Elements (CLB)

The configuration commands must be consistent with the connections. For example, if
you use the A input in an equation, connect a signal to the A pin. Refer to the appli-
cable CAE tool interface user guide for more information on specifying the CLB
configuration commands in the schematic.
You can specify the location of a CLB on the device using the LOC attribute. When
specifying the LOC attribute, a valid CLB name (AA, AB, and so forth) must be used.
Refer to the “LOC” section of the “Attributes, Constraints, and Carry Logic” chapter
for more information.

Libraries Guide, Release M1.5 4-67

Libraries Guide, Release M1.5

CLBMAP
Logic-Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive N/A N/A N/A N/A N/A N/A N/A

The CLBMAP symbol is used to control logic partitioning into XC3000 family CLBs.
A CLBMAP The CLBMAP symbol is not a substitute for logic. It is used in addition to combina-
B
C
tional gates, latches, and flip-flops for mapping control.
D
E
X At the schematic level, you can implement a portion of logic using gates, latches, and
DI
Y flip-flops and specify that the logic be grouped into a single CLB by using the
EC CLBMAP symbol. You must name the signals that are the inputs and outputs of the
K
CLB, then draw the signals to appropriate pins of the CLBMAP symbol, or name the
RD
CLBMAP signals and logic signals correspondingly. The symbol can have uncon-
nected pins, but all signals on the logic group to be mapped must be specified on a
X4651
symbol pin.
CLBMAP primitives and equivalent circuits are shown for XC3000 families in the
following figure.

U1 U2 U9
A0IN A0 U17
SUM0 S0
PAD IBUF
XOR2 OBUF

U3 U4 U10
B0IN B0 U12 U18
PAD SUM1 S1
IBUF
AND2 OBUF
XOR2
U5 U6 U11
A1IN A1
PAD IBUF
XOR2
U13
U7 U8
B1IN B1
PAD IBUF AND2
U14 U16 U19
SUM2 S2

AND2 XOR3 OBUF

U15

AND2

A0
A
A1
B
B0 SUM1
C X
B1
D
E
DI
SUM2
EC Y
K
RD
CLBMAP

X5022

Figure 4-42 XC3000 CLBMAP Primitive Example and Equivalent

4-68 Xilinx Development System

Design Elements (CLBMAP)

Use the MAP=type parameter with the CLBMAP symbol to further define how much
latitude you want to give the mapping program. The following table shows MAP
option characters and their meanings.

MAP Option
Function
Character
P Pins.
C Closed — Adding logic to or removing logic from the CLB
is not allowed.
L Locked — Locking CLB pins.
O Open — Adding logic to or removing logic from the CLB is
allowed.
U Unlocked — No locking on CLB pins.

Possible types of MAP parameters for FMAP are: MAP=PUC, MAP=PLC, MAP=PLO,
and MAP=PUO. The default parameter is PUO. If one of the “open” parameters is
used (PLO or PUO), only the output signals must be specified.
Note: Currently, only PUC and PUO are observed. PLC and PLO are translated into
PUC and PUO, respectively.
You can lock individual pins using the “P” (Pin lock) parameter on the CLBMAP pin
in conjunction with the PUC parameter. Refer to the appropriate CAE tool interface
user guide for information on changing symbol parameters for your schematic editor.

Libraries Guide, Release M1.5 4-69

Libraries Guide, Release M1.5

CLKDLL
Clock Delay Locked Loop

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

CLKDLL
CLKDLL is a clock delay locked loop used to minimize clock skew. CLKDLL synchro-
CLKIN CLK0 nizes the clock signal at the feed back clock input (CLKFB) to the clock signal at the
CLKFB CLK90 input clock (CLKIN). The locked output (LOCKED) is high when the two signals are
CLK180
in phase. The signals are considered to be in phase when their rising edges are within
CLK270
CLK2X 250 ps of each other.
CLKDV
RST LOCKED The frequency of the clock signal at the CLKIN input must be in the range 30 - 120
MHz.
X8678
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
global clock network driven by a BUFG, a global clock buffer. The BUFG input can
only be connected to the CLK0 or CLK2X output of CLKDLL. The BUFG connected to
the CLKFB input of the CLKDLL must be sourced from either the CLK0 or CLK2X
outputs of the same CLKDLL. The CLKIN input should be connected to the output of
an IBUFG, with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Only the CLK0 or CLK2X output
can be used. The CLK0 or CLK2X must be connected to the input of OBUF, an output
buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION
attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN
input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
the same as that of the CLK0 output. The duty cycle of the CLK2X and CLKDV
outputs is always 50-50. The frequency of the CLKDV output is determined by the
value assigned to the CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal
at the RST input is synchronized to the clock signal at the CLKIN input. The reset
becomes effective at the second Low-to-High transition of the clock signal at the
CLKIN input after assertion of the RST signal.

Table 4-1 CLKDLL Outputs

Output Description
CLK0 Clock at 1x CLKIN frequency
CLK90 Clock at 1x CLKIN frequency, shifted 90o with regards to CLK0
CLK180 Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0
CLK270 Clock at 1x CLKIN frequency, shifted 270o with regards to CLK0
CLK2X Clock at 2x CLKIN frequency
CLKDV Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value
LOCKED CLKDLL locked

4-70 Xilinx Development System

Design Elements (CLKDLLHF)

CLKDLLHF
High Frequency Clock Delay Locked Loop

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

CLKDLLHF
CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew.
CLKIN CLK0 CLKDLLHF synchronizes the clock signal at the feed back clock input (CLKFB) to the
CLKFB clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when
CLK180
the two signals are in phase. The signals are considered to be in phase when their
rising edges are within 250 ps of each other.
CLKDV
RST LOCKED The frequency of the clock signal at the CLKIN input must be in the range 60 - 180
MHz.
X8680
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
global clock network driven by a BUFG, a global clock buffer. The BUFG input can
only be connected to the CLK0 output of CLKDLLHF. The BUFG connected to the
CLKFB input of the CLKDLLHF must be sourced from the CLK0 output of the same
CLKDLLHF. The CLKIN input should be connected to the output of an IBUFG, with
the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Only the CLK0 output can be
used. CLK0 must be connected to the input of OBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION
attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN
input. The duty cycle of the phase shifted output (CLK180) is the same as that of the
CLK0 output. The frequency of the CLKDV output is determined by the value
assigned to the CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal
at the RST input is synchronized to the clock signal at the CLKIN input. The reset
becomes effective at the second Low-to-High transition of the clock signal at the
CLKIN input after assertion of the RST signal.

Table 4-2 CLKDLLHF Outputs

Output Description
CLK0 Clock at 1x CLKIN frequency
CLK180 Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0
CLKDV Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value
LOCKED CLKDLL locked

Libraries Guide, Release M1.5 4-71

Libraries Guide, Release M1.5

COMP2, 4, 8, 16
2-, 4-, 8-, 16-Bit Identity Comparators

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

COMP2, COMP4, COMP8, and COMP16 are, respectively, 2-, 4-, 8-, and 16-bit identity
COMP2
A0 comparators. The equal output (EQ) of the COMP2 2-bit, identity comparator is High
A1
EQ when the two words A1 – A0 and B1 – B0 are equal. EQ is high for COMP4 when A3 –
B0
B1
A0 and B3 – B0 are equal; for COMP8, when A7 – A0 and B7 – B0 are equal; and for
COMP16, when A15 – A0 and B15 – B0 are equal.
X4122
Equality is determined by a bit comparison of the two words. When any two of the
corresponding bits from each word are not the same, the EQ output is Low.
A0 COMP4
A1 A0
AB0
A2 B0
A3
EQ XNOR2
B0
A1
B1 AB1
B1
B2
B3 XNOR2 AB03
A2
AB2
X4126 B2 AND4

XNOR2

A[7:0] A3
COMP8 AB3
B3
EQ EQ
XNOR2
B[7:0] AND2
A4
AB4
B4

X4131 XNOR2
A5
AB5
B5
A[15:0] COMP16
XNOR2 AB47
EQ A6
AB6
B[15:0]
B6 AND4

XNOR2

X4133
A7
AB7
B7
A[7:0]
XNOR2

B[7:0] X7791

Figure 4-43 COMP8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

4-72 Xilinx Development System

Design Elements (COMPM2, 4, 8, 16)

COMPM2, 4, 8, 16
2-, 4-, 8-, 16-Bit Magnitude Comparators

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

COMPM2, COMPM4, COMPM8, and COMPM16 are, respectively, 2-, 4-, 8-, and 16-
COMPM2
A0 bit magnitude comparators that compare two positive binary-weighted words.
A1 GT
B0 LT COMPM2 compares A1 – A0 and B1 – B0, where A1 and B1 are the most significant
B1
bits. COMPM4 compares A3 – A0 and B3 – B0, where A3 and B3 are the most signifi-
cant bits. COMPM8 compares A7 – A0 and B7 – B0, where A7 and B7 are the most
X4123
significant bits. COMPM16 compares A15 – A0 and B15 – B0, where A15 and B15 are
the most significant bits.
COMPM4
A0 The greater-than output (GT) is High when A>B, and the less-than output (LT) is
A1
A2
High when A<B. When the two words are equal, both GT and LT are Low. Equality
A3 GT can be measured with this macro by comparing both outputs with a NOR gate.
B0 LT
B1
B2
B3 Inputs Outputs

X4127 A1 B1 A0 B0 GT LT
0 0 0 0 0 0
A[7:0] COMPM8 0 0 1 0 1 0
GT
0 0 0 1 0 1
LT
B[7:0] 0 0 1 1 0 0
1 1 0 0 0 0
X4132
1 1 1 0 1 0
1 1 0 1 0 1
A[15:0] COMPM16
GT
1 1 1 1 0 0
LT 1 0 X X 1 0
B[15:0]
0 1 X X 0 1
X4134
COMPM2 Truth Table

Libraries Guide, Release M1.5 4-73

Libraries Guide, Release M1.5

Inputs Outputs

A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A3>B3 X X X 1 0
A3<B3 X X X 0 1
A3=B3 A2>B2 X X 1 0
A3=B3 A2<B2 X X 0 1
A3=B3 A2=B2 A1>B1 X 1 0
A3=B3 A2=B2 A1<B1 X 0 1
A3=B3 A2=A2 A1=B1 A0>B0 1 0
A3=B3 A2=B2 A1=B1 A0<B0 0 1
A3=B3 A2=B2 A1=B1 A0=B0 0 0

COMPM4 Truth Table

Inputs Outputs

A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A7>B7 X X X X X X X 1 0
A7<B7 X X X X X X X 0 1
A7=B7 A6>B6 X X X X X X 1 0
A7=B7 A6<B6 X X X X X X 0 1
A7=B7 A6=B6 A5>B5 X X X X X 1 0
A7=B7 A6=B6 A5<B5 X X X X X 0 1
A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0
A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0

COMPM8 Truth Table (also representative of COMPM16)

4-74 Xilinx Development System

Design Elements (COMPM2, 4, 8, 16)

EQ_1 LE0_1
LT0_1

XNOR2 LTA
AND3B1 OR2
A0
GE0_1
AND4
B0

AND3B1 GTA
A1 GT0_1
GT_1
B1 AND4
OR2
AND2B1
LT_1

AND2B1

EQ_3 LE2_3
LT2_3
LTB
XNOR2 AND3B1 LT
OR2
A2
GE2_3 AND3
EQ2_3
OR4
B2

AND3B1 NOR2
GTB
A3 GT2_3
GT_3
A3 AND3
OR2
AND2B1
LT_3

AND2B1

EQ_5 LE4_5
LT4_5
LTC
XNOR2 AND3B1 OR2
A4 AND2
GE4_5 EQ4_5
B4

AND3B1 NOR2
GT
GTC
A5 GT4_5
GT_5
B5
AND2 OR4
OR2
AND2B1
LT_5

AND2B1

EQ_7 LE6_7
LTD

XNOR2 AND3B1 OR2

A6
GE6_7 EQ6_7
B6
NOR2
AND3B1
A[7:0]
A7 GTD
GT_7
B[7:0] B7
OR2
AND2B1
LT_7

AND2B1 X7793

Figure 4-44 COMPM8 Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

Libraries Guide, Release M1.5 4-75

Libraries Guide, Release M1.5

B0
A0
AND2B1
AND2
B1
A1 OR2
OR2B1

AND2
AND2B1
B2
A2 OR2
OR2B1

AND2
AND2B1
B3
A3 OR2
OR2B1

AND2
AND2B1
B4
A4 OR2
OR2B1

AND2
AND2B1
B5
A5
OR2
OR2B1

AND2
AND2B1
B6
A6
OR2
OR2B1

AND2
AND2B1
B7 LT
A7
OR2
OR2B1

AND2B1
A0
B0
AND2B1
AND2
A1
B1 OR2
OR2B1

AND2
AND2B1
A2
B2 OR2
OR2B1

AND2
AND2B1
A3
B3 OR2
OR2B1

AND2
AND2B1
A4
B4 OR2
OR2B1

AND2
AND2B1
A5
B5
OR2
OR2B1

AND2
AND2B1
A6
B6
OR2
OR2B1

AND2
AND2B1
A7 GT
B7
OR2
A[7:0] OR2B1

B[7:0] AND2B1

X7632

Figure 4-45 COMPM8 Implementation XC9000

4-76 Xilinx Development System

Design Elements (COMPMC8, 16)

COMPMC8, 16
8-, 16-Bit Magnitude Comparators

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro Macro

COMPMC8 is an 8-bit, magnitude comparator that compares two positive binary-

A[7:0] COMPMC8
GT
weighted words A7 – A0 and B7 – B0, where A7 and B7 are the most significant bits.
COMPMC16 is a 16-bit, magnitude comparator that compares two positive binary-
LT
B[7:0] weighted words A15 – A0 and B15 – B0, where A15 and B15 are the most significant
bits.
X4264 These comparators are implemented using carry logic with relative location
constraints to ensure efficient logic placement.
A[15:0] COMPMC16 The greater-than output (GT) is High when A>B, and the less-than output (LT) is
GT High when A<B. When the two words are equal, both GT and LT are Low. Equality
LT can be flagged with this macro by connecting both outputs to a NOR gate.
B[15:0]

X4265
Inputs Outputs

A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT

Libraries Guide, Release M1.5 4-77

Libraries Guide, Release M1.5

Topology for XC4000 and Spartans

This is the COMPMC8 (8-bit) and COMPMC16 (16-bit) topology for XC4000 and
Spartan series devices.

GT*

LT*

A 15 B 15

A 14 B 14

GT* A 13 B 13

LT* A 12 B 12

A 7B 7 A 11 B 11

A 6B 6 A 10 B 10

A 5B 5 A 9B 9

A 4B 4 A 8B 8

A 3B 3 A 7B 7

A 2B 2 A 6B 6

A 1B 1 A 5B 5

A 0B 0 A 4B 4

A 3B 3

A 2B 2

A 1B 1
8-Bit
A 0B 0

X8212 16-Bit

In the process of combining the logic that loads GT and LT, the place and route soft-
ware might map the logic that generates GT and LT to different function generators. If
this mapping occurs, the GT and LT logic cannot be placed in the uppermost CLB, as
indicated in the illustration.

4-78 Xilinx Development System

Design Elements (COMPMC8, 16)

CY4 RLOC-R0C0
COUT
B1 (G1)
A1 (G4) COUT0
B0 (F2)
A0 (F1)
ADD (F3)
CARRY MODE CIN
INV
CO LT
EXAMINE-CI

CY4_42
s7
s67
GT
CY4 RLOC-R1C0 EQ
XNOR2
B7 COUT AND2
B1 (G1)
A7 NOR2
A1 (G4) COUT0
B6 AND4
B0 (F2)
A6 FMAP
A0 (F1)
ADD (F3) I4
CARRY MODE CIN I3 s7
B7 O
I2
A7 HMAP
I1

SUB-FG-CI C6 I3 s67
RLOC-R1C0.G O
XNOR2 I2
CY4_07 s6 I1
FMAP

I4 RLOC-R1C0
s5
s45 I3 s6
B6 O
I2
CY4 RLOC-R2C0 A6
XNOR2 I1
COUT AND2
B5 B1 (G1)
A5 RLOC-R1C0.F
A1 (G4) COUT0
B4 B0 (F2)
A4 FMAP
A0 (F1)
ADD (F3) I4

CARRY MODE I3 s5
CIN B5 O
I2
A5 HMAP
I1
I3 s45
SUB-FG-CI C4 RLOC-R2C0.G O
I2
XNOR2
CY4_07 I1
s4 FMAP

I4 RLOC-R2C0
s3 I3 s4
s23 B4 O
I2
A4
I1
CY4 RLOC-R3C0 XNOR2
AND2
B3 COUT RLOC-R2C0.F
B1 (G1)
A3
A1 (G4) COUT0
B2 FMAP
B0 (F2)
A2
A0 (F1) I4
ADD (F3) I3 s3
B3 O
CARRY MODE I2
CIN A3 HMAP
I1
I3 s23
RLOC-R3C0.G O
I2
SUB-FG-CI C2
XNOR2 I1
FMAP
CY4_07
s2
I4 RLOC-R3C0
I3 s2
s1 B2 O
s01 I2
A2
I1
CY4 RLOC-R4C0
XNOR2
B1 COUT AND2 RLOC-R3C0.F
B1 (G1)
A1
A1 (G4) COUT0
B0 FMAP
B0 (F2)
A0 I4
A0 (F1)
ADD (F3) I3 s1
B1 O
I2
CARRY MODE CIN A1 HMAP
I1
I3 s01
RLOC-R4C0.G O
I2
SUB-FG-CI C_IN
I1
FMAP
CY4_07
s0
I4 RLOC-R4C0
I3 s0
B0 O
CY4 RLOC-R5C0 XNOR2 I2
A[7:0] A0
COUT I1
B1 (G1)
B[7:0] A1 (G4) COUT0 RLOC-R4C0.F
B0 (F2)
A0 (F1)
ADD (F3)

CARRY MODE CIN

X6499
FORCE-1

CY4_38

Figure 4-46 COMPMC8 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 4-79

Libraries Guide, Release M1.5

LT
GT

CO
CY_MUX CO
B7 RLOC=R0C0.LC3 CY_MUX
I7 S B7 RLOC=R0C1.LC3
A7 0 1 I7G S
0 1
XOR2 DI CI
XOR2 DI CI
A7
C8
C8G
CO
CY_MUX CO
B6 RLOC=R0C0.LC2 CY_MUX
I6 S B6 RLOC=R0C1.LC2
A6 0 1 I6G S
0 1
XOR2 DI CI
XOR2 DI CI
A6
C7
C7G
CO
CY_MUX CO
B5 RLOC=R0C0.LC1 CY_MUX
I5 S B5 RLOC=R0C1.LC1
A5 0 1 I5G S
0 1
XOR2 DI CI DI CI
A5 XOR2
C6
C6G
CO
CY_MUX CO
B4 RLOC=R0C0.LC0 CY_MUX
I4 S B4 RLOC=R0C1.LC0
A4 0 1 I4G S
0 1
DI CI
XOR2 DI CI
A4 XOR2
C5
C5G
CO
CY_MUX CO
B3 RLOC=R1C0.LC3 CY_MUX
I3 S B3 RLOC=R1C1.LC3
A3 0 1 I3G S
0 1
XOR2 DI CI
XOR2 DI CI
A3
C4
C4G
CO
CY_MUX CO
B2 RLOC=R1C0.LC2 CY_MUX
I2 S B2 RLOC=R1C1.LC2
A2 0 1 I2G S
0 1
XOR2 DI CI
XOR2 DI CI
A2
C2
C2G
CO
CY_MUX CO
B1 RLOC=R1C0.LC1 CY_MUX
I1 S B1 RLOC=R1C1.LC1
A1 0 1 I1G S
0 1
XOR2 DI CI
XOR2 DI CI
A1
C1
C1G
CO
CY_MUX CO
B0 CY_MUX
I0 S RLOC=R1C0.LC0 B0
A0 0 1 I0G S RLOC=R1C1.LC0
0 1
XOR2 DI CI
XOR2 DI CI
A0
C0
C0G

VCC
COUT
COUT
INIT
INIT
CY_INIT
RLOC=R2C0.LC3 CY_INIT
RLOC=R2C1.LC3
A[7:0]
GND
B[7:0]
X6363

Figure 4-47 COMPMC8 Implementation XC5200

4-80 Xilinx Development System

Design Elements (COMPMC8, 16)

LT
GT

LO
MUXCY LO
B7 RLOC=R0C0.S1 MUXCY
I7 S B7 RLOC=R0C0.S0
A7 0 1 I7G S
0 1
XNOR2 DI CI DI CI
A7 XNOR2
C8
C8G
LO
MUXCY_L LO
B6 RLOC=R0C0.S1 MUXCY_L
I6 S B6 RLOC=R0C0.S0
A6 0 1 I6G S
0 1
XNOR2 DI CI
A6 XNOR2 DI CI
C7
C7G
LO
MUXCY_L LO
B5 RLOC=R1C0.S1 MUXCY_L
I5 S B5 RLOC=R1C0.S0
A5 0 1 I5G S
0 1
XNOR2 DI CI DI CI
A5 XNOR2
C6 C6G
LO
MUXCY_L LO
B4 RLOC=R1C0.S1 MUXCY_L
I4 S B4 RLOC=R1C0.S0
A4 0 1 I4G S
0 1
XNOR2 DI CI
XNOR2 DI CI
A4
C5
C5G
LO
MUXCY_L LO
B3 RLOC=R2C0.S1 MUXCY_L
I3 S B3 RLOC=R2C0.S0
A3 0 1 I3G S
0 1
XNOR2 DI CI
XNOR2 DI CI
A3
C4 C4G
LO
MUXCY_L LO
B2 RLOC=R2C0.S1 MUXCY_L
I2 S B2 RLOC=R2C0.S0
A2 0 1 I2G S
0 1
XNOR2 DI CI
XNOR2 DI CI
A2
C2 C2G
LO
MUXCY_L LO
B1 RLOC=R3C0.S1 MUXCY_L
I1 S B1 RLOC=R3C0.S0
A1 0 1 I1G S
0 1
XNOR2 DI CI
XNOR2 DI CI
A1
C1
C1G
LO
MUXCY_L LO
B0 RLOC=R3C0.S1 MUXCY_L
I0 S B0 RLOC=R3C0.S0
A0 0 1 I0G S
0 1
XNOR2 DI CI
XNOR2 DI CI
A0
C0
C0G

GND
GND

A[7:0]

B[7:0]
X8713

Figure 4-48 COMPMC8 Implementation Virtex

Libraries Guide, Release M1.5 4-81

Libraries Guide, Release M1.5

CONFIG
Repository for Schematic-Level (Global) Attributes

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

The CONFIG primitive is a table that you can use to specify up to eight attributes that
affect the entire design (global attributes such as PART or PROHIBIT).
When using certain CAE software packages, global properties cannot be attached to
the “Schematic” or “Sheet.” Instead, they must be attached to the CONFIG symbol.
Enter attributes using the same syntax that you would use in a UCF file. The global
attributes can be any length, but only 30 characters are displayed in the CONFIG
window. The CONFIG table is shown in the following figure.

CONFIG

X7763

4-82 Xilinx Development System

Design Elements (CR8CE, CR16CE)

CR8CE, CR16CE
8-, 16-Bit Negative-Edge Binary Ripple Counters with Clock Enable
and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

Q[7:0]
CR8CE and CR16CE are 8-bit and 16-bit, cascadable, clearable, binary, ripple counters.
CR8CE
The asynchronous clear (CLR), when High, overrides all other inputs and causes the
CE
C Q outputs to go to logic level zero. The counter increments when the clock enable
input (CE) is High during the High-to-Low clock (C) transition. The counter ignores
CLR clock transitions when CE is Low.
X4116
Larger counters can be created by connecting the last Q output (Q7 for CR8CE, Q15
Q[15:0]
for CR16CE) of the first stage to the clock input of the next stage. CLR and CE inputs
CR16CE
are connected in parallel. The clock period is not affected by the overall length of a
CE
C ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the
number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage.
CLR
X4120 The counter is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR CE C Qz – Q0
1 X X 0
0 0 X No Chg
0 1 ↓ Inc
z = 7 for CR8CE; z = 15 for CR16CE.

Libraries Guide, Release M1.5 4-83

Libraries Guide, Release M1.5

Q[7:0]
Q7

FDCE_1 FDCE_1
TQ0 Q0 TQ4 Q4
D Q D Q
INV CE INV CE
C Q3
C C
CLR CLR
Q0 Q4

FDCE_1 FDCE_1
TQ1 Q1 TQ5 Q5
D Q D Q
INV INV
CE CE
C C
CLR CLR
Q1 Q5

FDCE_1 FDCE_1
TQ2 Q2 TQ6 Q6
D Q D Q
INV CE INV CE
C C
CLR CLR
Q2 Q6

FDCE_1 FDCE_1
TQ3 Q3 TQ7 Q7
D Q D Q
INV INV
CE CE
C C
CLR CLR
Q3 Q7

CLR
CE
X8141

Figure 4-49 CR8CE Implementation XC3000

Q[7:0]
Q7

FDCE_1 FDCE_1
TQ0 Q0 TQ4 Q4
D Q D Q
CE INV INV
CE CE
C Q3
C C
CLR CLR
Q0 Q4

FDCE_1 FDCE_1
TQ1 Q1 TQ5 Q5
D Q D Q
INV INV
CE CE
C C
CLR CLR
Q1 Q5

FDCE_1 FDCE_1
TQ2 Q2 TQ6 Q6
D Q D Q
INV CE INV CE
C C
CLR CLR
Q2 Q6

FDCE_1 FDCE_1
TQ3 Q3 TQ7 Q7
D Q D Q
INV INV
CE CE
C C
CLR CLR
Q3 Q7

CLR

VCC
X8142

Figure 4-50 CR8CE Implementation XC4000, XC5200, Spartans, Virtex

4-84 Xilinx Development System

Design Elements (CR8CE, CR16CE)

Q7 Q[7:0]
Q6
Q5
Q4
Q3
Q2
Q1
Q0

VCC
+5 FDC

D Q
CE
AND2 XOR2 C
CLR
Q0

FDC

D Q

AND2 XOR2 C
CLR
Q1

FDC

D Q

XOR2 C
AND3
CLR
Q2

FDC

D Q

XOR2 C
AND4 CLR
Q3

FDC

D Q

XOR2 C
AND5 CLR
Q4

FDC

D Q

XOR2 C
CLR
AND6
Q5

FDC

D Q

XOR2
C
CLR
AND7 Q6

FDC

D Q

XOR2
C
CLR
Q7
AND8

C
CLR INV
X7631

Figure 4-51 CR8CE Implementation XC9000

Libraries Guide, Release M1.5 4-85

Libraries Guide, Release M1.5

CY_INIT
Initialization Stage for Carry Chain

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Macro N/A N/A N/A N/A

CY_INIT is used to initialize the carry chain in the XC5200 architecture. It is used in
COUT conjunction with multiple CY_MUX elements to implement high speed carry-propa-
INIT
CY_INIT gate or high speed cascade logic. CY_INIT must be placed in the logic cell (LC) imme-
diately below the least-significant carry element (CY_MUX) in the carry/cascade
X4924
chain. The INIT input is driven from the direct input (DI) to LC. The CY_INIT carry-
out (COUT) drives the C in input of the first LC in the carry chain. The COUT output
reflects the state of the DI input. This figure represents the schematic implementation
of CY_INIT.

COUT

RLOC=R0C0
CO

CY_MUX
S
0 1 The select line is forced Low
so as to force the "INIT" signal
DI CI either High or Low and thereby
initialize the carry chain

GND

INIT

X6370

Figure 4-52 CY _INIT 4-Bit Adder Implementation XC5200

4-86 Xilinx Development System

Design Elements (CY_MUX)

CY_MUX
2-to-1 Multiplexer for Carry Logic

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

CY_MUX CY_MUX is used to implement a 1-bit high-speed carry propagate function. One such
function can be implemented per logic cell (LC), for a total of 4-bits per configurable
CO logic block (CLB). The direct input (DI) of an LC is connected to the DI input of the
S CY_MUX. The carry in (CI) input of an LC is connected to the CI input of the
0 1 CY_MUX. The select input (S) of the CY_MUX is driven by the output of the lookup
DI CI
table (LUT) and configured as an XOR function. The carry out (CO) of the CY_MUX
reflects the state of the selected input and implements the carry out function of each
X4923 LC. When Low, S selects DI; when High, S selects CI.

Inputs Outputs

S DI CI CO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

The following figure depicts the application of the CY_MUX for a 4-bit adder. Also
shown are the associated FMAP symbols and the CY_INIT function.

Libraries Guide, Release M1.5 4-87

Libraries Guide, Release M1.5

OFL

XOR2 FMAP
CY_MUX CO FMAP
B3 S RLOC=R0C0.LC3
I3 I4
A3 0 1 I4
I3 S3
DI CI I3 I3 O
XOR2 B3 O I2
I2 C2
S3 A3 I1
I1
C2 RLOC=R0C1.LC3
XOR2 RLOC=R0C0.LC3

CY_MUX FMAP FMAP

CO
B2 S RLOC=R0C0.LC2
I2 I4
A2 0 1 I4
I2 I3 S2
DI CI I3 O
XOR2 B2 I2 O I2
S2 C1 I1
A2 I1
C1 XOR2 RLOC=R0C1.LC2
RLOC=R0C0.LC2

CY_MUX FMAP
CO FMAP
B1 S RLOC=R0C0.LC1
I1 I4 I4
A1 0 1 I3 S1
DI CI I3 I1 O
B1 O I2
XOR2 I2 C0
S1 A1 I1
I1
C0 RLOC=R0C1.LC1
XOR2 RLOC=R0C0.LC1

CY_MUX FMAP
CO FMAP
B0 S RLOC=R0C0.LC0
I0 I4
A0 0 1 I4
I3 S0
DI CI I3 I0 I2 O
B0 O
XOR2 I2 C IN I1
S0 A0 I1

C_IN XOR2 RLOC=R0C1.LC0

RLOC=R0C0.LC0

COUT
CI INIT RLOC=R1C0.LC3

CY_INIT
X6430

Figure 4-53 CY_MUX 4-Bit Adder Schematic XC5200

4-88 Xilinx Development System

Design Elements (D2_4E)

D2_4E
2- to 4-Line Decoder/Demultiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

A0 D2_4E D0
When the enable (EN) input of the D2_4E decoder/demultiplexer is High, one of four
A1 D1 active-High outputs (D3 – D0) is selected with a 2-bit binary address (A1 – A0) input.
D2 The non-selected outputs are Low. Also, when the EN input is Low, all outputs are
E D3
Low. In demultiplexer applications, the EN input is the data input.

X3853

Inputs Outputs

A1 A0 E D3 D2 D1 D0
X X 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0

AND3B2

AND3B1

AND3B1
E
A0 D3
A1
AND3
X7794

Figure 4-54 D2_4E Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 4-89

Libraries Guide, Release M1.5

D3_8E
3- to 8-Line Decoder/Demultiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

When the enable (EN) input of the D3_8E decoder/demultiplexer is High, one of
A0 D3_8E D0
A1 D1 eight active-High outputs (D7 – D0) is selected with a 3-bit binary address (A2 – A0)
A2 D2 input. The non-selected outputs are Low. Also, when the EN input is Low, all outputs
D3 are Low. In demultiplexer applications, the EN input is the data input.
D4
D5
D6
E D7
Inputs Outputs

X3854 A2 A1 A0 E D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 1 0 0 0 0 0 0 1 0
0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 1 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0
1 0 1 1 0 0 1 0 0 0 0 0
1 1 0 1 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

4-90 Xilinx Development System

Design Elements (D3_8E)

AND4B3

AND4B2

AND4B1

AND4B2

AND4B1

AND4B1
E
A0
D7
A1
A2
AND4
X7795

Figure 4-55 D3_8E Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 4-91

Libraries Guide, Release M1.5

D4_16E
4- to 16-Line Decoder/Demultiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

When the enable (EN) input of the D4_16E decoder/demultiplexer is High, one of 16
A0 D4_16E D0
A1 D1
active-High outputs (D15 – D0) is selected with a 4-bit binary address (A3 – A0) input.
A2 D2 The non-selected outputs are Low. Also, when the EN input is Low, all outputs are
A3 D3 Low. In demultiplexer applications, the EN input is the data input.
D4
D5 Refer to the “D3_8E” section for a representative truth table derivation.
D6
D7
D8
D9
D10
D11
D12
D13
D14
E D15

X3855

4-92 Xilinx Development System

Design Elements (D4_16E)

AND5B4

AND5B3

AND5B2

AND5B3

AND5B2

AND5B1

AND5B3

AND5B2

D10

AND5B2

D11

AND5B1

D12

AND5B2

D13

AND5B1

D14

AND5B1
E
A0
A1 D15
A2
A3
AND5

X7638

Figure 4-56 D4_16E Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 4-93

Libraries Guide, Release M1.5

DEC_CC4, 8, 16
4-, 8-, 16-Bit Active Low Decoders

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Macro N/A N/A N/A Macro

These decoders are used to build wide-decoder functions. They are implemented by
A0 DEC_CC4
A1
cascading CY_MUX elements driven by lookup tables (LUTs). The C_IN pin can only
A2 be driven by a CY_INIT or by the output (O) of a previous decode stage. When one or
A3 O more of the inputs (A) are Low, the output is Low. When all the inputs are High and
C_IN the C_IN input is High, the output is High. You can decode patterns by adding
inverters to inputs.
X4927

A0 DEC_CC8 Inputs Outputs

A1
A2 A0 A1 … Az C_IN O
A3
A4 1 1 1 1 1 1
A5
A6 X X X X 0 0
A7 O
C_IN
0 X X X X 0
X 0 X X X 0
X4928
X X X 0 X 0
z = 3 for DEC_CC4; z = 7 for DECC_CC8; z = 15 for DECC_CC16
A0 DEC_CC16
A1
A2 O
A3
A4 A3 CY_MUX C0
A5 A2
S0 S
A6 A1 0 1
A7 A0 DI CI
A8 AND4
A9
A10
A11
GND
A12 C_IN
A13
A14
The C_IN pin can only be initialized
A15 O by a CY_INIT or by the output of a
C_IN previous decode stage. X6537

X4929
Figure 4-57 DEC_CC4 Implementation XC5200

4-94 Xilinx Development System

Design Elements (DEC_CC4, 8, 16)

A3
MUXCY O
A2
S0 S
A1 0 1
A0 DI CI
AND4

GND
C_IN

The C_IN pin can only be initialized

by a CY_INIT or by the output of a
previous decode stage. X8717

Figure 4-58 DEC_CC4 Implementation Virtex

DEC_CC4
A0
A0
A1
A1
A0
A2
A3 O
A3 O
C_IN

DEC_CC4
A4
A0
A5
A1
A6
A2
A7
A3 O
C_IN
C_IN

The C_IN pin can only be initialized

by a CY_INIT or by the output of a
previous decode stage.

X6396

Figure 4-59 DEC_CC8 Implementation XC5200, Virtex

Libraries Guide, Release M1.5 4-95

Libraries Guide, Release M1.5

DECODE4, 8, 16
4-, 8-, 16-Bit Active-Low Decoders

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A N/A N/A Macro

XC4000 XC4000 XC5200, Virtex XC5200, Virtex

A0 DECODE4 A0 DECODE16 A0 DECODE4 A0 DECODE16
A1 A1 A1 A1
A2 A2 A2 A2
A3 O A3 A3 O A3
A4 A4
A5 A5
A6 A6
XC4000 A7 XC5200, Virtex A7
A0 DECODE8 A8 A0 DECODE8 A8
A1 A9 A1 A9
A2 A10 A2 A10
A3 A11 A3 A11
A4 A12 A4 A12
A5 A13 A5 A13
A6 A14 A6 A14
A7 O A15 O A7 O A15 O

X6795

Figure 4-60 DECODE Representations

In the XC4000 architectures, decoders are open-drain, wired-AND gates. When one or
more of the inputs (A) are Low, output (O) is Low. When all the inputs are High, the
output is High or Off. A pull-up resistor must be connected to the output node to
achieve a true logic High. A double pull-up resistor can be used to achieve faster
performance; however, it uses more power. The software implements these macros
using the open-drain AND gates around the periphery of the devices. (Diamonds in
library symbols indicate an open-drain output.)
In XC5200, decoders are implemented by cascading CY_MUX elements driven by
lookup tables (LUTs). When one or more of the inputs are Low, the output is Low.
When all the inputs are High, the output is High. You can decode patterns by adding
inverters to inputs. Pull-ups cannot be used on XC5200 longlines.
In Virtex, decoders are implemented using combinations of LUTs and MUXCYs.

Inputs Outputs*

A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = 3 for DECODE4, z = 7 for DECODE8; z = 15 for DECODE16
*A pull-up resistor must be connected to the output to establish High-level drive current.

4-96 Xilinx Development System

Design Elements (DECODE4, 8, 16)

A0 O
WAND1
DECODE
A1
WAND1
DECODE
A2
WAND1
DECODE
A3
WAND1
DECODE
A4
WAND1
DECODE
A5
WAND1
DECODE
A6
WAND1
DECODE
A7
WAND1
DECODE
X6500

Figure 4-61 DECODE8 Implementation XC4000

A7
CY_MUX CO
A6 FMAP
S1 S RLOC=R0C0.LC3
A5 0 1 A7
I4
A4 DI CI A6
I3 S1
A5 O
AND4 I2
A4
I1

C_IN1 MAP=PUO
RLOC=R0C0.LC3

A3 CY_MUX CO FMAP
A2 RLOC=R0C0.LC2
S1 S
A1 0 1 A3
I4
A0 DI CI A2
I3 S0
A1 O
AND4 I2
A0
I1

MAP=PUO
RLOC=R0C0.LC2

GND C_IN0

VCC

COUT
INIT
CY_INIT
RLOC=R0C0.LC1
X6397

Figure 4-62 DECODE8 Implementation XC5200

Libraries Guide, Release M1.5 4-97

Libraries Guide, Release M1.5

FMAP
I4
I3 O
S1 O
I2
S0
I1
A7
A6 MAP=PUO
S1 RLOC=R0C0.S0
A5
A4
AND4 FMAP
A7
I4
A6
O I3 S1
A5 O
I2
A4
AND2 I1
A3 MAP=PUO
A2 RLOC=R0C0.S1
S0
A1
A0 FMAP
AND4 A3
I4
A2
I3 S0
A1 O
I2
A0
I1

X8703 MAP=PUO
RLOC=R0C0.S1

Figure 4-63 DECODE8 Implementation Virtex

4-98 Xilinx Development System

Design Elements (DECODE32, 64)

DECODE32, 64
32- and 64-Bit Active-Low Decoders

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Macro N/A N/A N/A Macro

A[31:0] DECODE32
DECODE32 and DECODE64 are 32- and 64-bit active-low decoders. In XC5200,
decoders are implemented by cascading CY_MUX elements driven by lookup tables
O (LUTs). When one or more of the inputs are Low, the output is Low. When all the
inputs are High, the output is High. You can decode patterns by adding inverters to
X8203 inputs. Pull-ups cannot be used on XC5200 longlines.
In Virtex, decoders are implemented using combinations of LUTs and MUXCYs.
A[63:0] DECODE64
Refer to the “DECODE4, 8, 16” section for a representative schematic.
O

X8204
Inputs Outputs

A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = 31 for DECODE32; z = 63 for DECODE64

Libraries Guide, Release M1.5 4-99

Libraries Guide, Release M1.5

4-100 Xilinx Development System

Chapter 5

Design Elements (F5MAP to FTSRLE)

Libraries Guide, Release M1.5 — 5-1

Libraries Guide, Release M1.5

F5MAP
5-Input Function Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

I5 F5MAP
The F5MAP symbol is used to control the logic partitioning of 5-input functions into
I4 the top or bottom half of a CLB. The F5MAP symbol is not a substitute for logic. It is
I3 used in addition to combinatorial gates for mapping control.
I2 O
I1 At the schematic level, any 5-input logic function can be implemented using gates and
mapped into half of a single CLB by using the F5MAP symbol. The signals that are the
X4925
inputs and outputs of the 5-input function must be labelled and connected to appro-
priate pins of the F5MAP symbol, or the F5MAP signals and logic signals must have
identical labels. The symbol can have unconnected pins, but all signals on the logic
group to be mapped must be specified on a symbol pin.
Using F5MAP forces any 5-input function to be implemented by two lookup tables
(LUTs), the direct input (DI), and the F5_MUX primitive, which are contained within
adjacent CLB logic cells LC0 and LC1 or LC2 and LC3.
The connections within a CLB are shown in the “Two LUTs in Parallel Combined to
Create a 5-Input Function” figure. An F5MAP primitive example is shown in the
“F5MAP Primitive Example” figure.
I1 F4
I2 F3 LUT
I3 F2 in F5_MUX
I4 F1 LC1
I1
O
O
I2

I5 DI DI
F4
F3 LUT
F2 in
F1 LC0
X6428

Figure 5-1 Two LUTs in Parallel Combined to Create a 5-Input Function

A0
B0
C0

AND3
O

A1 XOR2
B1

AND2

F5MAP
A0
I5
B0
I4
C0 O
I3
A1
I2
B1
I1

X6443

Figure 5-2 F5MAP Primitive Example

5-2 Xilinx Development System

Design Elements (F5_MUX)

F5_MUX
2-to-1 Lookup Table Multiplexer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

I1
F5_MUX provides a multiplexer function in one half of a CLB. The output from the
O lookup table (LUT) in LC1 is connected to the I1 input of the F5_MUX. The output
I2
DI from the LUT in LC0 is connected to the I2 input. The direct input (DI) of LC0 is
X4926 connected to the DI input of the F5_MUX. The output (O) reflects the state of the
selected input. When Low, DI selects I1; when High, DI selects I2. Similarly, the
F5_MUX can connect to the LUTs in LC2 and LC3. The F5_MUX can also implement
any 5-input function in the top or bottom half of a CLB when the mapping of the func-
tion is controlled by F5MAP.

Inputs Outputs

DI I1 I2 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

LUT
in F5_MUX
LC1
I1 O
O
I2
DI DI

LUT
in
LC0

X6427

Figure 5-3 F5_MUX Representation

Libraries Guide, Release M1.5 5-3

Libraries Guide, Release M1.5

FD
D Flip-Flop

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

D FD Q
FD is a single D-type flip-flop with data input (D) and data output (Q). The data on
the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition.
C
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
X3715
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Refer to the “FD4, 8, 16” section for information on multiple D flip-flops for the
XC9000.

Inputs Outputs

D C Q
0 ↑ 0
1 ↑ 1

VCC
FDCE
D Q
D Q
CE
C
C
CLR

GND X7796

Figure 5-4 FD Implementation XC3000, XC4000, XC5200, Spartans

FDCP

D PRE Q
D Q

C C
CLR
Q

X7797
GND

Figure 5-5 FD Implementation XC9000

5-4 Xilinx Development System

Design Elements (FD_1)

FD_1
D Flip-Flop with Negative-Edge Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Primitive

FD_1 is a single D-type flip-flop with data input (D) and data output (Q). The data on
D FD_1 Q
the D input is loaded into the flip-flop during the High-to-Low clock (C) transition.
C
The flip-flop is asynchronously cleared, output Low, when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for
X3726
XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to
active-High but can be inverted by adding an inverter in front of the GR/GSR input of
the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

D C Q
0 ↓ 0
1 ↓ 1

VCC
FDCE
D D Q
Q
CE
C CB
C
CLR
INV

X7798
GND

Figure 5-6 FD_1 Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 5-5

Libraries Guide, Release M1.5

FD4, 8, 16
Multiple D Flip-Flops

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

FD4
FD4, FD8, FD16 are multiple D-type flip-flops with data inputs (D) and data outputs
D0 Q0
D1 Q1
(Q). FD4, FD8, and FD16 are, respectively, 4-bit, 8-bit, and 16-bit registers, each with a
D2 Q2
common clock (C). The data on the D inputs is loaded into the flip-flop during the
D3 Q3 Low-to-High clock (C) transition.
C The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
X4608 the PRLD global net.

D[7:0] FD8 Q[7:0]

Inputs Outputs
C
Dz – D0 C Qz – Q0
X4609
0 ↑ 0
1 ↑ 1
D[15:0] FD16 Q[15:0]
z = 3 for FD4; z = 7 for FD8; z = 15 for FD16
C
Q[7:0]

X4610
FD FD
D0 Q0 D4 Q4
D Q D Q

C C

Q0 Q4

FD FD
D1 Q1 D5 Q5
D Q D Q

C C

Q1 Q5

FD FD
D2 Q2 D6 Q6
D Q D Q

C C

Q2 Q6

FD FD
D3 Q3 D7 Q7
D Q D Q

C C

D[7:0] Q3 Q7

C X8128

Figure 5-7 FD8 Implementation XC9000

5-6 Xilinx Development System

Design Elements (FD4CE, FD8CE, FD16CE)

FD4CE, FD8CE, FD16CE

4-, 8-, 16-Bit Data Registers with Clock Enable and Asynchronous
Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FD4CE, FD8CE, and FD16CE are, respectively, 4-, 8-, and 16-bit data registers with
D0 FD4CE Q0
D1 Q1
clock enable and asynchronous clear. When clock enable (CE) is High and asynchro-
D2 Q2 nous clear (CLR) is Low, the data on the data inputs (D) is transferred to the corre-
D3 Q3 sponding data outputs (Q) during the Low-to-High clock (C) transition. When CLR is
CE
C
High, it overrides all other inputs and resets the data outputs (Q) Low. When CE is
Low, clock transitions are ignored.
CLR
X3733 The flip-flops are asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
D[7:0] FD8CE Q[7:0]
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
CE
C
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
CLR
X3850

Inputs Outputs
D[15:0] FD16CE Q[15:0]

CE CLR CE Dz – D0 C Qz – Q0
C
1 X X X 0
CLR
X3736 0 0 X X No Chg
0 1 Dn ↑ dn
z = 3 for FD4CE; z = 7 for FD8CE; z = 15 for FD16CE.
dn = state of corresponding input (Dn) one setup time prior to active clock transition

Libraries Guide, Release M1.5 5-7

Libraries Guide, Release M1.5

Q[7:0]

FDCE
FDCE D4 Q4
D Q
D0 Q0
D Q CE
CE C
C CLR
CLR Q4
Q0

FDCE
FDCE D5 Q5
D Q
D1 Q1
D Q CE
CE C
CLR
C
CLR Q5
Q1

FDCE
FDCE D6 Q6
D Q
D2 Q2
D Q CE
CE C
CLR
C
CLR Q6
Q2

FDCE
FDCE D7 Q7
D Q
D3 Q3
D Q CE
CE C
CLR
C
CLR Q7
Q3
D[7:0]

CE
C
CLR
X7799

Figure 5-8 FD8CE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

5-8 Xilinx Development System

Design Elements (FD4RE, FD8RE, FD16RE)

FD4RE, FD8RE, FD16RE

4-, 8-, 16-Bit Data Registers with Clock Enable and Synchronous
Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FD4RE
FD4RE, FD8RE, and FD16RE are, respectively, 4-, 8-, and 16-bit data registers. When
D0 Q0
D1 Q1 the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the
D2 Q2 data on the data inputs (D) is transferred to the corresponding data outputs (Q0)
D3 Q3
CE during the Low-to-High clock (C) transition. When R is High, it overrides all other
C inputs and resets the data outputs (Q) Low on the Low-to-High clock transition.
When CE is Low, clock transitions are ignored.
R X3734
The flip-flops are asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
D[7:0] FD8RE Q[7:0] the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
CE reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
C Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
R
X3735

D[15:0] Q[15:0]
Inputs Outputs
FD16RE
CE R CE Dz – D0 C Qz – Q0
C

1 X X ↑ 0
R X3737 0 0 X X No Chg
0 1 Dn ↑ dn
z = 3 for FD4RE; z = 7 for FD8RE; z = 15 for FD16RE
dn = state of referenced input (Dn) one setup time prior to active clock transition

Libraries Guide, Release M1.5 5-9

Libraries Guide, Release M1.5

Q[7:0]

FDRE FDRE
D0 Q0 D4 Q4
D Q D Q
CE CE
C C
R R
Q0 Q4

FDRE FDRE
D1 Q1 D5 Q5
D Q D Q
CE CE
C C
R R
Q1 Q5

FDRE FDRE
D2 Q2 D6 Q6
D Q D Q
CE CE
C C
R R
Q2 Q6

FDRE FDRE
D3 Q3 D7 Q7
D Q D Q
CE CE
C C
R R
Q3 Q7
D[7:0]

CE
C
R
X8195

Figure 5-9 FD8RE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

5-10 Xilinx Development System

Design Elements (FDC)

FDC
D Flip-Flop with Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs
D FDC Q
and data output (Q). The asynchronous CLR, when High, overrides all other inputs
C and sets the Q output Low. The data on the D input is loaded into the flip-flop when
CLR is Low on the Low-to-High clock transition.
CLR
X3716 The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR D C Q
1 X X 0
0 1 ↑ 1
0 0 ↑ 0

VCC
+5
FDCE
D D Q
Q
CE
C
C
CLR
CLR
X7800

Figure 5-10 FDC Implementation XC3000, XC4000, XC5200, Spartans

FDCP

D PRE Q
D Q

C C
CLR
CLR Q

X7801

GND

Figure 5-11 FDC Implementation XC9000

Libraries Guide, Release M1.5 5-11

Libraries Guide, Release M1.5

FDC_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Primitive

FDC_1
FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input
D Q
(CLR), and data output (Q). The asynchronous CLR, when active, overrides all other
C inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop
during the High-to-Low clock (C) transition.
CLR
X3847 The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR D C Q
1 X X 0
0 1 ↓ 1
0 0 ↓ 0

VCC

FDCE
D Q
D Q
CE
C CB
C
INV CLR
CLR
X7810

Figure 5-12 FDC_1 Implementation XC3000, XC4000, XC5200, Spartans

5-12 Xilinx Development System

Design Elements (FDCE)

FDCE
D Flip-Flop with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

FDCE
FDCE is a single D-type flip-flop with clock enable and asynchronous clear. When
D Q
clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data
CE
input (D) of FDCE is transferred to the corresponding data output (Q) during the
C
Low-to-High clock (C) transition. When CLR is High, it overrides all other inputs and
resets the data output (Q) Low. When CE is Low, clock transitions are ignored.
CLR X3717
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
For XC9500XL devices, logic connected to the clock enable (CE) input is uncondition-
ally implemented using the clock enable product-term of the XC9500XL macrocell.
Only FDCE and FDPE flip-flops use the XC9500XL clock enable product-term.

Inputs Outputs

CLR CE D C Q
1 X X X 0
0 0 X X No Chg
0 1 1 ↑ 1
0 1 0 ↑ 0

Libraries Guide, Release M1.5 5-13

Libraries Guide, Release M1.5

FDCE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Primitive

FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
D FDCE_1 Q
CE
clear (CLR) inputs, and data output (Q). The asynchronous CLR input, when High,
C overrides all other inputs and sets the Q output Low. The data on the D input is
loaded into the flip-flop when CLR is Low and CE is High on the High-to-Low clock
CLR X3727
(C) transition. When CE is Low, the clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for
XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to
active-High but can be inverted by adding an inverter in front of the GR/GSR input of
the STARTUP or STARTUP_VIRTEX symbol.

N/A N/A N/A N/A Macro N/A N/A Primitive

PRE
FDCPE is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asyn-
FDCPE
chronous PRE, when High, sets the Q output High; CLR, when High, resets the
D
CE Q
output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are
C
Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the
clock transitions are ignored.
CLR The flip-flop is asynchronously cleared, output Low, when power is applied. For
X4389 CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. Virtex simulates power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_VIRTEX symbol.

Inputs Outputs

CLR PRE CE D C Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Chg
0 0 1 0 ↑ 0
0 0 1 1 ↑ 1

VCC
+5

CE
AND2B1
AND2

D
OR2
AND2
PRE FDCP

PRE Q
D Q

C
C
CLR
CLR Q

X7804

Figure 5-14 FDCPE Implementation XC9000

Libraries Guide, Release M1.5 5-17

Libraries Guide, Release M1.5

FDCPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and
Asynchronous Preset and Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asyn-
D FDCPE_1 chronous PRE, when High, sets the Q output High; CLR, when High, resets the
CE Q output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are
C Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the
clock transitions are ignored.
CLR
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
X8360
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR PRE CE D C Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Chg
0 0 1 0 ↓ 0
0 0 1 1 ↓ 1

5-18 Xilinx Development System

Design Elements (FDE)

FDE
D Flip-Flop with Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

D FDE FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data
CE Q
output (Q). When clock enable is High, the data on the D input is loaded into the flip-
C
flop during the Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
X8361 simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CE D C Q
0 X X No Chg
1 0 ↑ 0
1 1 ↑ 1

Libraries Guide, Release M1.5 5-19

Libraries Guide, Release M1.5

FDE_1
D Flip-Flop with Negative-Edge Clock and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

D FDE_1 FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data
CE Q
output (Q). When clock enable is High, the data on the D input is loaded into the flip-
C
flop during the High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
X8362 simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CE D C Q
0 X X No Chg
1 0 ↓ 0
1 1 ↓ 1

5-20 Xilinx Development System

Design Elements (FDP)

FDP
D Flip-Flop with Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro Macro Macro Macro Primitive

PRE
FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs
and data output (Q). The asynchronous PRE, when High, overrides all other inputs
FDP and presets the Q output High. The data on the D input is loaded into the flip-flop
D Q
when PRE is Low on the Low-to-High clock (C) transition.
C
For FPGAs, the flip-flop is asynchronously preset, output High, when global reset (GR
for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The active
X3720
level of the GR/GSR defaults to active-High but can be inverted by adding an inverter
in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is
applied. The power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

PRE C D Q
1 X X 1
0 ↑ 1 1
0 ↑ 0 0

VCC

PRE FDPE

D PRE Q
D Q
CE
C
C

RLOC=R0C0
X6393

Figure 5-15 FDP Implementation XC4000, XC5200, Spartans

PRE FDCP

D PRE Q
D Q

C C
CLR
Q

X7805
GND

Figure 5-16 FDP Implementation XC9000

Libraries Guide, Release M1.5 5-21

Libraries Guide, Release M1.5

FDP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and
FDR
D Q data output (Q). The synchronous reset (R) input, when High, overrides all other
C inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data
on the D input is loaded into the flip-flop when R is Low during the Low-to-High
R
clock transition.
X3718
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R D C Q
1 X ↑ 0
0 1 ↑ 1
0 0 ↑ 0

FD
D
D_R Q
R D Q
AND2B1
C
C
X7807

Figure 5-20 FDR Implementation XC3000, XC4000, XC5200, XC9000, Spartans

Libraries Guide, Release M1.5 5-25

Libraries Guide, Release M1.5

FDR_1
D Flip-Flop with Negative-Edge Clock and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

FDR_1
FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and
D
data output (Q). The synchronous reset (R) input, when High, overrides all other
Q
inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data
C
on the D input is loaded into the flip-flop when R is Low during the High-to-Low
clock transition.
R
X8363 The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

R D C Q
1 X ↓ 0
0 1 ↓ 1
0 0 ↓ 0

5-26 Xilinx Development System

Design Elements (FDRE)

FDRE
D Flip-Flop with Clock Enable and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous
D FDRE Q
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
CE
C
overrides all other inputs and resets the Q output Low on the Low-to-High clock (C)
transition. The data on the D input is loaded into the flip-flop when R is Low and CE
R is High during the Low-to-High clock transition.
X3719

The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R CE D C Q
1 X X ↑ 0
0 0 X X No Chg
0 1 1 ↑ 1
0 1 0 ↑ 0

R A0
QD
CR A1
AND3B2 OR2

FD
D
Q
D Q
AND3B1
C
C

RLOC=R0C0
X7935

Figure 5-21 FDRE Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 5-27

Libraries Guide, Release M1.5

VCC
+5

CE
AND2

R
AND3B2

D
FD
Q
OR2 D Q
AND3B1
C
C

Q
X7808

Figure 5-22 FDRE Implementation XC9000

5-28 Xilinx Development System

Design Elements (FDRE_1)

FDRE_1
D Flip-Flop with Negative-Clock Edge, Clock Enable, and
Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous
D FDRE_1
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
CE Q
overrides all other inputs and resets the Q output Low on the Low-to-High clock (C)
C
transition. The data on the D input is loaded into the flip-flop when R is Low and CE
is High during the High-to-Low clock transition.
R
X8364 The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

R CE D C Q
1 X X ↓ 0
0 0 X X No Chg
0 1 1 ↓ 1
0 1 0 ↓ 0

Libraries Guide, Release M1.5 5-29

Libraries Guide, Release M1.5

FDRS
D Flip-Flop with Synchronous Reset and Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

S FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
D FDRS Q overrides all other inputs and resets the Q output Low during the Low-to-High clock
(C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-
C
flop is set, output High, during the Low-to-High clock transition. When R and S are
Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock
R X3731 transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R S D C Q
1 X X ↑ 0
0 1 X ↑ 1
0 0 1 ↑ 1
0 0 0 ↑ 0

FDR
D D_S Q
S D Q
OR2
C
C
R
R
X7809

Figure 5-23 FDRS Implementation XC3000, XC4000, XC5200, Spartans

D
R
AND2B1

S FD
Q
OR2 D Q
AND2B1
C
C

Q
X7811

Figure 5-24 FDRS Implementation XC9000

5-30 Xilinx Development System

Design Elements (FDRS_1)

FDRS_1
D Flip-Flop with Negative-Clock Edge and Synchronous Reset and
Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

S FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchro-
nous reset (R) inputs and data output (Q). The synchronous reset (R) input, when
D FDRS_1 High, overrides all other inputs and resets the Q output Low during the High-to-Low
Q clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the
C flip-flop is set, output High, during the High-to-Low clock transition. When R and S
are Low, data on the (D) input is loaded into the flip-flop during the High-to-Low
R clock transition.
X8365
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

R S D C Q
1 X X ↓ 0
0 1 X ↓ 1
0 0 1 ↓ 1
0 0 0 ↓ 0

Libraries Guide, Release M1.5 5-31

Libraries Guide, Release M1.5

FDRSE
D Flip-Flop with Synchronous Reset and Set and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

S FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S),
and clock enable (CE) inputs and data output (Q). The reset (R) input, when High,
D FDRSE Q overrides all other inputs and resets the Q output Low during the Low-to-High clock
CE transition. (Reset has precedence over Set.) When the set (S) input is High and R is
C
Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition.
Data on the D input is loaded into the flip-flop when R and S are Low and CE is High
R X3732 during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R S CE D C Q
1 X X X ↑ 0
0 1 X X ↑ 1
0 0 0 X X No Chg
0 0 1 1 ↑ 1
0 0 1 0 ↑ 0

D
D_S
S
OR2
FDRE
CE_S Q
CE D Q
OR2 CE
C
C
R
R
X7812

Figure 5-25 FDRSE Implementation XC3000, XC4000, XC5200, Spartans

5-32 Xilinx Development System

Design Elements (FDRSE)

VCC
+5

AND2 AND2B1

OR3

D FD
AND2 Q
R D Q
AND2B1
C
C

X7813

Figure 5-26 FDRSE Implementation XC9000

Libraries Guide, Release M1.5 5-33

Libraries Guide, Release M1.5

FDRSE_1
D Flip-Flop with Negative-Clock Edge, Synchronous Reset and
Set, and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

S FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S),
and clock enable (CE) inputs and data output (Q). The reset (R) input, when High,
D FDRSE_1 overrides all other inputs and resets the Q output Low during the High-to-Low clock
CE Q transition. (Reset has precedence over Set.) When the set (S) input is High and R is
C Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition.
Data on the D input is loaded into the flip-flop when R and S are Low and CE is High
R during the High-to-Low clock transition.
X8366
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

R S CE D C Q
1 X X X ↓ 0
0 1 X X ↓ 1
0 0 0 X X No Chg
0 0 1 1 ↓ 1
0 0 1 0 ↓ 0

5-34 Xilinx Development System

Design Elements (FDS)

FDS
D Flip-Flop with Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

S FDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data
output (Q). The synchronous set input, when High, sets the Q output High on the
D FDS Q
Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop
when S is Low during the Low-to-High clock (C) transition.
C
The flip-flop is asynchronously cleared, output Low, when power is applied. For
X3722 CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

S D C Q
1 X ↑ 1
0 1 ↑ 1
0 0 ↑ 0

FD
D
Q
S D Q
OR2
C
C

Q
X7562

Figure 5-27 FDS Implementation XC3000, XC4000, XC5200, XC9000, Spartans

Libraries Guide, Release M1.5 5-35

Libraries Guide, Release M1.5

FDS_1
D Flip-Flop with Negative-Edge Clock and Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

S FDS_1 is a single D-type flip-flop with data (D) and synchronous set (S) inputs and
data output (Q). The synchronous set input, when High, sets the Q output High on
D FDS_1 the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-
Q flop when S is Low during the High-to-Low clock (C) transition.
C
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
X8367
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

S D C Q
1 X ↓ 1
0 1 ↓ 1
0 0 ↓ 0

5-36 Xilinx Development System

Design Elements (FDSE)

FDSE
D Flip-Flop with Clock Enable and Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Primitive

S
FDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set
(S) inputs and data output (Q). The synchronous set (S) input, when High, overrides
D FDSE Q
the clock enable (CE) input and sets the Q output High during the Low-to-High clock
CE (C) transition. The data on the D input is loaded into the flip-flop when S is Low and
C CE is High during the Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
X3723
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

S CE D C Q
1 X X ↑ 1
0 0 X X No Chg
0 1 1 ↑ 1
0 1 0 ↑ 0

AND2B1
A0
S A_S
A1
OR3

CE
D
AND2
FD
Q
D Q

C
C

X7814

Figure 5-28 FDSE Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 5-37

Libraries Guide, Release M1.5

VCC
+5

AND2 AND2B1

OR3

D FD
AND2 Q Q
D Q
C
C

Q
X7815

Figure 5-29 FDSE Implementation XC9000

5-38 Xilinx Development System

Design Elements (FDSE_1)

FDSE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and
Synchronous Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

S FDSE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous
set (S) inputs and data output (Q). The synchronous set (S) input, when High, over-
D FDSE_1 rides the clock enable (CE) input and sets the Q output High during the High-to-Low
CE Q clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low
C and CE is High during the High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex
X8368
simulates power-on when global set/reset (GSR) is active. GSR defaults to active-
High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

S CE D C Q
1 X X ↓ 1
0 0 X X No Chg
0 1 1 ↓ 1
0 1 0 ↓ 0

Libraries Guide, Release M1.5 5-39

Libraries Guide, Release M1.5

FDSR
D Flip-Flop with Synchronous Set and Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

S FDSR is a single D-type flip-flop with data (D), synchronous reset (R) and synchro-
nous set (S) inputs and data output (Q). When the set (S) input is High, it overrides all
D FDSR Q other inputs and sets the Q output High during the Low-to-High clock transition. (Set
has precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset,
C
output Low, on the Low-to-High clock transition. Data on the D input is loaded into
the flip-flop when S and R are Low on the Low-to-High clock transition.
R
X3729
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans) default to active-High but can be inverted by adding an inverter in front of
the GR/GSR input of the STARTUP symbol.

Inputs Outputs

S R D C Q
1 X X ↑ 1
0 1 X ↑ 0
0 0 1 ↑ 1
0 0 0 ↑ 0

S FDS

D
D_R S Q
R D Q
AND2B1
C
C

X7816

Figure 5-30 FDSR Implementation XC3000, XC4000, XC5200, Spartans

D
R
AND2B1 FD
D Q
S Q
OR2
C C

Q
X7817

Figure 5-31 FDSR Implementation XC9000

5-40 Xilinx Development System

Design Elements (FDSRE)

FDSRE
D Flip-Flop with Synchronous Set and Reset and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

S FDSRE is a single D-type flip-flop with synchronous set (S), synchronous reset (R),
and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High,
D FDSRE Q it overrides all other inputs and sets the Q output High during the Low-to-High clock
CE transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S
C
is Low, output Q is reset Low during the Low-to-High clock transition. Data is loaded
into the flip-flop when S and R are Low and CE is High during the Low-to-high clock
R
X3730 transition. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans) default to active-High but can be inverted by adding an inverter in front of
the GR/GSR input of the STARTUP symbol.

Inputs Outputs

S R CE D C Q
1 X X X ↑ 1
0 1 X X ↑ 0
0 0 0 X X No Chg
0 0 1 1 ↑ 1
0 0 1 0 ↑ 0

S FDSE

D
D_R S Q
R D Q
AND2B1 CE
C
CE_R
CE
OR2
CLR
X7818

Figure 5-32 FDSRE Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 5-41

Libraries Guide, Release M1.5

VCC
+5

CE
AND2

R
AND3B2 FD
S Q
D Q

OR3
D C

AND3B1
C

X7819

Figure 5-33 FDSRE Implementation XC9000

5-42 Xilinx Development System

Design Elements (FJKC)

FJKC
J-K Flip-Flop with Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FJKC is a single J-K-type flip-flop with J, K, and asynchronous clear (CLR) inputs and
J FJKC
data output (Q). The asynchronous clear (CLR) input, when High, overrides all other
K Q
inputs and resets the Q output Low. When CLR is Low, the output responds to the
C state of the J and K inputs, as shown in the following truth table, during the Low-to-
High clock (C) transition.
CLR
X3753 The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR J K C Q
1 X X X 0
0 0 0 ↑ No Chg
0 0 1 ↑ 0
0 1 0 ↑ 1
0 1 1 ↑ Toggle

AND3B2
A0
A1 AD
A2
OR3
AND3B1
FDC
J
K Q
D Q
AND2B1
C
C
CLR
CLR

X7820

Figure 5-34 FJKC Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Libraries Guide, Release M1.5 5-43

Libraries Guide, Release M1.5

K
AND2B1
FDC
J Q
D Q
OR2
AND2B1
C
C CLR
CLR Q

X7821

Figure 5-35 FJKC Implementation XC9000

5-44 Xilinx Development System

Design Elements (FJKCE)

FJKCE
J-K Flip-Flop with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FJKCE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous
FJKCE
J clear (CLR) inputs and data output (Q). The asynchronous clear (CLR), when High,
K Q
overrides all other inputs and resets the Q output Low. When CLR is Low and CE is
CE
C
High, Q responds to the state of the J and K inputs, as shown in the following truth
table, during the Low-to-High clock transition. When CE is Low, the clock transitions
CLR are ignored.
X3756
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR CE J K C Q
1 X X X X 0
0 0 X X X No Chg
0 1 0 0 X No Chg
0 1 0 1 ↑ 0
0 1 1 0 ↑ 1
0 1 1 1 ↑ Toggle

AND3B2
A0
A1 AD
A2
OR3
AND3B1
J
K
AND2B1
FDCE
Q
D Q
CE
CE
C
C
CLR
CLR
X7822

Figure 5-36 FJKCE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Libraries Guide, Release M1.5 5-45

Libraries Guide, Release M1.5

VCC
+5

CE
AND2

AND2B1

J
FDC
AND3B1 Q
D Q
K
OR3
AND2B1 C
CLR
C
CLR
X7823

Figure 5-37 FJKCE Implementation XC9000

5-46 Xilinx Development System

Design Elements (FJKCP)

FJKCP
J-K Flip-Flop with Asynchronous Clear and Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

PRE FJKCP is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and asynchro-
nous preset (PRE) inputs and data output (Q). The asynchronous clear input (CLR),
J FJKCP when High, overrides all other inputs and resets the Q output Low. The asynchronous
K Q preset (PRE) input, when High, overrides all other inputs and sets the Q output High.
When CLR and PRE are Low, Q responds to the state of the J and K inputs during the
C
Low-to-High clock transition, as shown in the following truth table.
CLR The flip-flop is asynchronously cleared, output Low, when power is applied. For
X4390
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

CLR PRE J K C Q
1 0 X X X 0
0 1 X X X 1
0 0 0 0 X No Chg
0 0 0 1 ↑ 0
0 0 1 0 ↑ 1
0 0 1 1 ↑ Toggle

AND2B1

PRE FDCP

PRE Q
D Q
K
OR2
AND2B1 C
CLR
C Q
CLR

X8124

Figure 5-38 FJKCP Implementation XC9000

Libraries Guide, Release M1.5 5-47

Libraries Guide, Release M1.5

FJKCPE
J-K Flip-Flop with Asynchronous Clear and Preset and Clock
Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

PRE FJKCPE is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), asynchro-
nous preset (PRE), and clock enable (CE) inputs and data output (Q). The asynchro-
J FJKCPE nous clear input (CLR), when High, overrides all other inputs and resets the Q output
K Q Low. The asynchronous preset (PRE) input, when High, overrides all other inputs and
CE sets the Q output High. When CLR and PRE are Low and CE is High, Q responds to
C the state of the J and K inputs, as shown in the following truth table, during the Low-
to-High clock transition. Clock transitions are ignored when CE is Low.
CLR
X4391 The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

CLR PRE CE J K C Q
1 X X X X X 0
0 1 X X X X 1
0 0 0 0 X X No Chg
0 0 1 0 0 X No Chg
0 0 1 0 1 ↑ 0
0 0 1 1 0 ↑ 1
0 0 1 1 1 ↑ Toggle

VCC
±5

FDCP
CE
AND2B1
AND2
J PRE Q
D Q
AND3B1 OR3
C
K CLR
Q
AND2B1
PRE

CLR
X7687

Figure 5-39 FJKCPE Implementation XC9000

5-48 Xilinx Development System

Design Elements (FJKP)

FJKP
J-K Flip-Flop with Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro Macro Macro Macro Macro

PRE FJKP is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and
data output (Q). The asynchronous preset (PRE) input, when High, overrides all other
J FJKP inputs and sets the Q output High. When PRE is Low, the Q output responds to the
K Q state of the J and K inputs, as shown in the following truth table, during the Low-to-
High clock transition.
C
For FPGAs, the flip-flop is asynchronously preset, output High, when global reset (GR
X3754 for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The GR/
GSR active level defaults to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is
applied. The power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

PRE J K C Q
1 X X X 1
0 0 0 X No Chg
0 0 1 ↑ 0
0 1 0 ↑ 1
0 1 1 ↑ Toggle

Libraries Guide, Release M1.5 5-49

Libraries Guide, Release M1.5

AND3B2
A0
A1 AD
A2
OR3
AND3B1
J
K
AND2B1
PRE FDP

PRE Q
D Q

C
C

RLOC=R0C0

X7824

Figure 5-40 FJKP Implementation XC4000, XC5200, Spartans, Virtex

AND2B1

PRE FDP

PRE Q
D Q
K
OR2
AND2B1 C

C Q

X8125

Figure 5-41 FJKP Implementation XC9000

5-50 Xilinx Development System

Design Elements (FJKPE)

FJKPE
J-K Flip-Flop with Clock Enable and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro Macro Macro Macro Macro

PRE FJKPE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous
preset (PRE) inputs and data output (Q). The asynchronous preset (PRE), when High,
J FJKPE overrides all other inputs and sets the Q output High. When PRE is Low and CE is
K Q High, the Q output responds to the state of the J and K inputs, as shown in the truth
CE
table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions
C
are ignored.
X3757 For FPGAs, the flip-flop is asynchronously preset, output High, when global reset (GR
for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The GR/
GSR active level defaults to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is
applied. The power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

PRE CE J K C Q
1 X X X X 1
0 0 X X X No Chg
0 1 0 0 X No Chg
0 1 0 1 ↑ 0
0 1 1 0 ↑ 1
0 1 1 1 ↑ Toggle

Libraries Guide, Release M1.5 5-51

Libraries Guide, Release M1.5

AND3B2
A0
A1 AD
A2
OR3
AND3B1
J
K
AND2B1
PRE FDPE

PRE Q
D Q
CE
CE
C
C

RLOC=R0C0

X7825

Figure 5-42 FJKPE Implementation XC4000, XC5200, Spartans, Virtex

VCC
+5

CE
AND2B1 FDP
AND2

PRE Q
K D Q
AND2B1 OR3
C
J
Q

AND3B1
C

PRE
X7826

Figure 5-43 FJKPE Implementation XC9000

5-52 Xilinx Development System

Design Elements (FJKRSE)

FJKRSE
J-K Flip-Flop with Clock Enable and Synchronous Reset and Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

S FJKRSE is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set
(S), and clock enable (CE) inputs and data output (Q). When synchronous reset (R) is
J FJKRSE High, all other inputs are ignored and output Q is reset Low. (Reset has precedence
K Q over Set.) When synchronous set (S) is High and R is Low, output Q is set High. When
CE R and S are Low and CE is High, output Q responds to the state of the J and K inputs,
C according to the following truth table, during the Low-to-High clock (C) transition.
When CE is Low, clock transitions are ignored.
R
X3760
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R S CE J K C Q
1 X X X X ↑ 0
0 1 X X X ↑ 1
0 0 0 X X X No Chg
0 0 1 0 0 X No Chg
0 0 1 0 1 ↑ 0
0 0 1 1 0 ↑ 1
0 0 1 1 1 ↑ Toggle

AND3B2
A0
A1
AD_S
A2
AND3B1
J OR4
K
FDRE
AND2B1
S Q
D Q
CE S_CE
CE
C OR2
C
R
R

RLOC=R0C0 X7827

Figure 5-44 FJKRSE Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

Libraries Guide, Release M1.5 5-53

Libraries Guide, Release M1.5

VCC
+5

K AND2
S
AND4B1

AND3B3 FD
Q
D Q
J
AND3B3 NOR4 C
R
Q
C
X8126

Figure 5-45 FJKRSE Implementation XC9000

5-54 Xilinx Development System

Design Elements (FJKSRE)

FJKSRE
J-K Flip-Flop with Clock Enable and Synchronous Set and Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

S FJKSRE is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset
(R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is
J FJKSRE High, all other inputs are ignored and output Q is set High. (Set has precedence over
K Q Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low. When
CE S and R are Low and CE is High, output Q responds to the state of the J and K inputs,
C
as shown in the following truth table, during the Low-to-High clock (C) transition.
When CE is Low, clock transitions are ignored.
R X3759
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

S R CE J K C Q
1 X X X X ↑ 1
0 1 X X X ↑ 0
0 0 0 X X X No Chg
0 0 1 0 0 X No Chg
0 0 1 0 1 ↑ 0
0 0 1 1 0 ↑ 1
0 0 1 1 1 ↑ Toggle

Libraries Guide, Release M1.5 5-55

Libraries Guide, Release M1.5

AND3B2
A0
A1 AD
AD_R
A2
OR3
AND3B1 AND2B1
J
K

S AND2B1 FDSE

S Q
R D Q
R_CE
CE CE

C OR2
C

X7828

Figure 5-46 FJKSRE Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

VCC
+5

CE
AND2B2
AND2

K
AND3

AND2B2 OR4 FD
R
Q
S D Q
NAND2B1
C
C

Q
X8127

Figure 5-47 FJKSRE Implementation XC9000

5-56 Xilinx Development System

Design Elements (FMAP)

FMAP
F Function Generator Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive Primitive

I4 FMAP
The FMAP symbol is used to control logic partitioning into XC4000 4-input function
I3 generators. For XC4000 and Spartans, the place and route software chooses an F or a
O
I2 G function generator as a default, unless you specify an F or G. The FMAP symbol is
I1 used in an XC5200 or a Virtex device to map logic to the function generator of a slice.
Refer to the appropriate CAE tool interface user guide for information about speci-
X4646
fying this attribute in your schematic design editor.
The FMAP symbol is usually used with the HMAP symbol, which partitions logic
into the 3-input generator of the Configurable Logic Block (CLB). You can implement
a portion of logic using gates, latches, and flip-flops and specify the logic to be
grouped into F, G, and H function generators by naming logic signals and FMAP/
HMAP signals correspondingly. These symbols are used for mapping control in addi-
tion to the actual gates, latches, and flip-flops, not as a substitute for them.
The following figure gives an example of how logic can be placed using FMAP and
HMAP symbols.

IN_F1 U1
IN_F2 U3
F_FUNC
IN_F3 D0
G_FUNC
IN_F4 D1 H_FUNC
AND4 O

SE
U2 M2-1 U4
IN_G1 IN_F1
D0 I1
IN_G2 IN_F2
D1 I2 F_FUNC
O IN_F3 O
IN_G3 I3
SE IN_F4
IN_G4 I4
EN
M2-1E FMAP
CLB_R*C*.F
IN_H1
U5
IN_G1
I1
IN_G2
IN_H1 I2 G_FUNC
IN_G3 O
I3
IN_F1 IN_G4
I4
IN_F2
IN_F3 F FMAP
CLB_R*C*.G
IN_F4
H_FUNC U6
IN_G1 H F_FUNC
I1
IN_G2 G_FUNC H_FUNC
I2 O
IN_G3 G IN_H1
I3
IN_G4
HMAP
X1882

Figure 5-48 Partitioning Logic Using FMAP and HMAP Symbols

Libraries Guide, Release M1.5 5-57

Libraries Guide, Release M1.5

The MAP=type parameter can be used with the FMAP symbol to further define how
much latitude you want to give the mapping program. The following table shows
MAP option characters and their meanings.

Possible types of MAP parameters for FMAP are MAP=PUC, MAP=PLC, MAP=PLO,
and MAP=PUO. The default parameter is PUO. If one of the “open” parameters is
used (PLO or PUO), only the output signals must be specified.
Note: Currently, only PUC and PUO are observed. PLC and PLO are translated into
PUC and PUO, respectively.
The FMAP symbol can be assigned to specific CLB locations using LOC attributes.
Refer to the “Mapping Constraint Examples” section of the “Attributes, Constraints,
and Carry Logic” chapter and to the appropriate CAE tool interface user guide for
more information on assigning LOC attributes.

5-58 Xilinx Development System

Design Elements (FTC)

FTC
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FTC FTC is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input,
T Q
when High, overrides all other inputs and resets the data output (Q) Low. The Q
C output toggles, or changes state, when the toggle enable (T) input is High and CLR is
Low during the Low-to-High clock transition.
CLR
X3761
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR T C Q
1 X X 0
0 0 X No Chg
0 1 ↑ Toggle

FDC
TQ Q
T D Q

XOR2
C
C
CLR
CLR

X7830

Figure 5-49 FTC Implementation XC3000, XC4000, XC5200, Spartans, Virtex

FTCP

T PRE Q
D Q

C C
CLR
CLR Q

X7831

GND

Figure 5-50 FTC Implementation XC9000

Libraries Guide, Release M1.5 5-59

Libraries Guide, Release M1.5

FTCE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous
Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FTCE is a toggle flip-flop with toggle and clock enable and asynchronous clear. When
T FTCE Q
CE
the asynchronous clear (CLR) input is High, all other inputs are ignored and the data
C output (Q) is reset Low. When CLR is Low and toggle enable (T) and clock enable (CE)
are High, Q output toggles, or changes state, during the Low-to-High clock (C) transi-
CLR X3764
tion. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

CLR CE T C Q
1 X X X 0
0 0 X X No Chg
0 1 0 X No Chg
0 1 1 ↑ Toggle

TQ FDCE
T
Q
D Q
CE XOR2
CE
C
C
CLR
CLR

X7832

Figure 5-51 FTCE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

FTCP

T PRE
T Q
CE Q
AND2
C C
CLR
CLR Q

X7833
GND

Figure 5-52 FTCE Implementation XC9000

5-60 Xilinx Development System

Design Elements (FTCLE)

FTCLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

FTCLE
FTCLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous
D
L
clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored
T Q
and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock
CE enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop
C during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High
and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High
CLR clock transition. When CE is Low, clock transitions are ignored.
X3769

Inputs Outputs

CLR L CE T D C Q
1 X X X X X 0
0 1 X X 1 ↑ 1
0 1 X X 0 ↑ 0
0 0 0 X X X No Chg
0 0 1 0 X X No Chg
0 0 1 1 X ↑ Toggle

TQ
T
XOR2
M2_1
D0
O MD
D D1
L S0 FDCE
Q
D Q
L_CE
CE CE
OR2 C
CLR

C
CLR
X8150

Figure 5-53 FTCLE Implementation XC3000

Libraries Guide, Release M1.5 5-61

Libraries Guide, Release M1.5

TQ
T
XOR2
M2_1
D0
O MD
D D1
L S0 FDCE
Q
D Q
L_CE
CE CE
OR2 C
CLR

C
CLR
RLOC=R0C0 X8147

Figure 5-54 FTCLE Implementation XC4000, XC5200, Spartans, Virtex

VCC
+5

CE
AND3
L
AND3B2
OR2

GRD
AND4B2

T OR4

AND3B2
FDC
Q
D D Q

AND2
C
C
CLR
Q
CLR

X7561

Figure 5-55 FTCLE Implementation XC9000

5-62 Xilinx Development System

Design Elements (FTCLEX)

FTCLEX
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro Macro

FTCLEX
FTCLEX is a toggle/loadable flip-flop with toggle and clock enable and asynchronous
D
clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored
L
and output Q is reset Low. When load enable input (L) is High, CLR is Low, and CE is
T Q
High, the data on data input (D) is loaded into the flip-flop during the Low-to-High
CE
clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low,
C
output Q toggles, or changes state, during the Low- to-High clock transition. When
CLR
CE is Low, clock transitions are ignored.
X7601 The flip-flop is asynchronously cleared, output Low, when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for
XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted
by adding an inverter in front of the GR/GSR input of the STARTUP or
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR L CE T D C Q
1 X X X X X 0
0 1 1 X 1 ↑ 1
0 1 1 X 0 ↑ 0
0 0 0 X X X No Chg
0 0 1 0 X X No Chg
0 0 1 1 X ↑ Toggle

TQ
T M2_1
XOR2 D0
0 MD
D D1
S0
L FDCE

CE D Q Q
CE
C C
CLR
CLR

X6995

Figure 5-56 FTCLEX Implementation XC4000, XC5200, Spartans, Virtex

Libraries Guide, Release M1.5 5-63

Libraries Guide, Release M1.5

FTCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and
Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Primitive N/A N/A N/A

PRE FTCP is a toggle flip-flop with toggle enable and asynchronous clear and preset.
When the asynchronous clear (CLR) input is High, all other inputs are ignored and
T FTCP the output (Q) is reset Low. When the asynchronous preset (PRE) input is High, all
Q other inputs are ignored and Q is set High. When the toggle enable input (T) is High
C and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-
High clock (C) transition.
CLR
The flip-flop is asynchronously cleared, output Low, when power is applied. For
X4392
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

CLR PRE T C Q
1 0 X X 0
0 1 X X 1
0 0 0 X No Chg
0 0 1 ↑ Toggle

5-64 Xilinx Development System

Design Elements (FTCPE)

FTCPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous
Clear and Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

PRE FTCPE is a toggle flip-flop with toggle and clock enable and asynchronous clear and
preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored
T FTCPE and the output (Q) is reset Low. When the asynchronous preset (PRE) input is High,
CE Q
all other inputs are ignored and Q is set High. When the toggle enable input (T) and
C the clock enable input (CE) are High and CLR and PRE are Low, output Q toggles, or
changes state, during the Low-to-High clock (C) transition. Clock transitions are
CLR ignored when CE is Low.
X4393
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

CLR PRE CE T C Q
1 0 X X X 0
0 1 X X X 1
0 0 0 X X No Chg
0 0 1 0 X No Chg
0 0 1 1 ↑ Toggle

PRE FTCP
T
PRE Q
CE T Q

C AND2
C
CLR
CLR
Q
X7681

Figure 5-57 FTCPE Implementation XC9000

Libraries Guide, Release M1.5 5-65

Libraries Guide, Release M1.5

FTCPLE
Loadable Toggle Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear and Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A Macro N/A N/A N/A

PRE FTCPLE is a loadable toggle flip-flop with toggle and clock enable and asynchronous
clear and preset. When the asynchronous clear (CLR) input is High, all other inputs
D
FTCPLE are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE)
L input is High, all other inputs are ignored and Q is set High. The load input (L) loads
T Q the data on input D into the flip-flop on the Low-to-High clock transition, regardless
CE of the state of the clock enable (CE). When the toggle enable input (T) and the clock
C enable input (CE) are High and CLR, PRE, and L are Low, output Q toggles, or
changes state, during the Low-to-High clock (C) transition. Clock transitions are
CLR X4394 ignored when CE is Low.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

CLR PRE L CE T C D Q
1 X X X X X X 0
0 1 X X X X X 1
0 0 1 X X ↑ 0 0
0 0 1 X X ↑ 1 1
0 0 0 0 X X X No Chg
0 0 0 1 0 X X No Chg
0 0 0 1 1 ↑ X Toggle

5-66 Xilinx Development System

Design Elements (FTCPLE)

VCC
+5

CE
AND2

AND3B2
OR2

GND

AND4B2

T FDCP

AND3B2 PRE Q
D Q

D
OR4 C
AND2 CLR
PRE
C
CLR
X7845

Figure 5-58 FTCPLE Implementation XC9000

Libraries Guide, Release M1.5 5-67

Libraries Guide, Release M1.5

FTP
Toggle Flip-Flop with Toggle Enable and Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro Macro Macro Macro Macro

PRE FTP is a toggle flip-flop with toggle enable and asynchronous preset. When the asyn-
chronous preset (PRE) input is High, all other inputs are ignored and output Q is set
T FTP Q High. When toggle-enable input (T) is High and PRE is Low, output Q toggles, or
changes state, during the Low-to-High clock (C) transition.
C
For FPGAs, the flip-flop is asynchronously preset to output High, when global reset
X3762 (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The
GR/GSR active level defaults to active-High but can be inverted by adding an
inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX
symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is
applied. The power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

PRE T C Q
1 X X 1
0 0 X No Chg
0 1 ↑ Toggle

PRE FDP

TQ PRE Q
T D Q

XOR2
C
C

RLOC=R0C0

X6371

Figure 5-59 FTP Implementation XC4000, XC5200, Spartans, Virtex

PRE FTCP

T PRE Q
T Q

C
C
CLR

GND X7680

Figure 5-60 FTP Implementation XC9000

5-68 Xilinx Development System

Design Elements (FTPE)

FTPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous
Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro Macro Macro Macro Macro

PRE FTPE is a toggle flip-flop with toggle and clock enable and asynchronous preset.
When the asynchronous preset (PRE) input is High, all other inputs are ignored and
T FTPE Q output Q is set High. When the toggle enable input (T) is High, clock enable (CE) is
CE High, and PRE is Low, output Q toggles, or changes state, during the Low-to-High
C
clock transition. When CE is Low, clock transitions are ignored.
X3765 For FPGAs, the flip-flop is asynchronously preset to output High, when global reset
(GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The
GR/GSR active level defaults to active-High but can be inverted by adding an
inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX
symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is
applied. The power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

PRE CE T C Q
1 X X X 1
0 0 X X No Chg
0 1 0 X No Chg
0 1 1 ↑ Toggle

PRE FDPE

TQ PRE Q
T D Q
XOR2 CE
CE C
C
RLOC=R0C0
X8694

Figure 5-61 FTPE Implementation XC4000, XC5200, Spartans, Virtex

PRE FTCP
T
PRE Q
CE T Q

C AND2
C
CLR
Q

GND X7683

Figure 5-62 FTPE Implementation XC9000

Libraries Guide, Release M1.5 5-69

Libraries Guide, Release M1.5

FTPLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro Macro Macro Macro Macro

PRE FTPLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous
preset. When the asynchronous preset input (PRE) is High, all other inputs are
D FTPLE ignored and output Q is set High. When the load enable input (L) is High and PRE is
L Low, the clock enable (CE) is overridden and the data (D) is loaded into the flip-flop
T Q during the Low-to-High clock transition. When L and PRE are Low and toggle-enable
CE input (T) and CE are High, output Q toggles, or changes state, during the Low-to-
C
High clock transition. When CE is Low, clock transitions are ignored.
X3770 For FPGAs, the flip-flop is asynchronously preset to output High, when global reset
(GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The
GR/GSR active level defaults to active-High but can be inverted by adding an
inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX
symbol.
For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is
applied. The power-on condition can be simulated by applying a High-level pulse on
the PRLD global net.

Inputs Outputs

PRE L CE T D C Q
1 X X X X X 1
0 1 X X 1 ↑ 1
0 1 X X 0 ↑ 0
0 0 0 X X X No Chg
0 0 1 0 X X No Chg
0 0 1 1 X ↑ Toggle

5-70 Xilinx Development System

Design Elements (FTPLE)

TQ
T
M2_1
XOR2 D0
O MD
D D1
L S0

PRE FDPE

PRE Q
CE D Q
CE
C OR2
C

RLOC=R0C0

X6372

Figure 5-63 FTPLE Implementation XC4000, XC5200, Spartans, Virtex

VCC
+5

CE
AND2

AND3B2
OR2

GND

AND4B2

T FDP

AND3B2 PRE Q
D Q

D
OR4 C
AND2
PRE
C
X7846

Figure 5-64 FTPLE Implementation XC9000

Libraries Guide, Release M1.5 5-71

Libraries Guide, Release M1.5

FTRSE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous
Reset and Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

S FTRSE is a toggle flip-flop with toggle and clock enable and synchronous reset and
set. When the synchronous reset input (R) is High, it overrides all other inputs and the
T FTRSE Q data output (Q) is reset Low. When the synchronous set input (S) is High and R is
CE Low, clock enable input (CE) is overridden and output Q is set High. (Reset has prece-
C
dence over Set.) When toggle enable input (T) and CE are High and R and S are Low,
output Q toggles, or changes state, during the Low-to-High clock transition.
R
X3768
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R S CE T C Q
1 X X X ↑ 0
0 1 X X ↑ 1
0 0 0 X X No Chg
0 0 1 0 X No Chg
0 0 1 1 ↑ Toggle

TQ
T
XOR2 D_S
S
FDRE
OR2
Q
D Q
CE_S
CE CE
OR2 C
C
R
R

RLOC=R0C0
X7658

Figure 5-65 FTRSE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

5-72 Xilinx Development System

Design Elements (FTRSE)

VCC
+5

CE
AND2B1
AND2
T

AND3B1
S

OR4

FD
AND3B1
Q
R D Q
AND2B1
C
C

X7847

Figure 5-66 FTRSE Implementation XC9000

Libraries Guide, Release M1.5 5-73

Libraries Guide, Release M1.5

FTRSLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Synchronous Reset and Set

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

S FTRSLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous
reset and set. The synchronous reset input (R), when High, overrides all other inputs
D FTRSLE and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low
L and synchronous set input (S) is High, the clock enable input (CE) is overridden and
T Q output Q is set High. When R and S are Low and load enable input (L) is High, CE is
CE overridden and data on data input (D) is loaded into the flip-flop during the Low-to-
C
High clock transition. When R, S, and L are Low and CE is High, output Q toggles, or
changes state, during the Low-to-High clock transition. When CE is Low, clock transi-
R
X3773 tions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

R S L CE T D C Q
1 0 X X X X ↑ 0
0 1 X X X X ↑ 1
0 0 1 X X 1 ↑ 1
0 0 1 X X 0 ↑ 0
0 0 0 0 X X X No Chg
0 0 0 1 0 X X No Chg
0 0 0 1 1 X ↑ Toggle

5-74 Xilinx Development System

Design Elements (FTRSLE)

TQ
T
M2_1
XOR2 D0
O MD
D D1

L S0
MD_S
S

OR2 FDRE
CE_S_L Q
D Q
CE
OR3 CE
C
C

R
RLOC=R0C0
X7641

Figure 5-67 FTRSLE Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

VCC
+5

CE
AND2 FD
L
Q
D Q
AND3B2
OR2
C

GND
T
AND4B2

AND2B1
OR5

AND4B2

R AND2
C
X7848

Figure 5-68 FTRSLE Implementation XC9000

Libraries Guide, Release M1.5 5-75

Libraries Guide, Release M1.5

FTSRE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous
Set and Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

S
FTSRE is a toggle flip-flop with toggle and clock enable and synchronous set and
reset. The synchronous set input, when High, overrides all other inputs and sets data
T FTSRE Q
output (Q) High. (Set has precedence over Reset.) When synchronous reset input (R)
CE is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low.
C
When toggle enable input (T) and CE are High and S and R are Low, output Q toggles,
or changes state, during the Low-to-High clock transition.
R X3767
The flip-flop is asynchronously cleared, output Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

S R CE T C Q
1 X X X ↑ 1
0 1 X X ↑ 0
0 0 0 X X No Chg
0 0 1 0 X No Chg
0 0 1 1 ↑ Toggle

TQ
T
XOR2 D_R
R

S AND2B1 FDSE

S Q
D Q
CE_R
CE CE
OR2 C
C

RLOC=R0C0
X7643

Figure 5-69 FTSRE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

5-76 Xilinx Development System

Design Elements (FTSRE)

VCC
+5

CE
AND2

R
AND3B2

AND4B2
FD
Q
D Q

AND3B2 OR4 C
S

C
X7849

Figure 5-70 FTSRE Implementation XC9000

Libraries Guide, Release M1.5 5-77

Libraries Guide, Release M1.5

FTSRLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Synchronous Set and Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

S FTSRLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous
set and reset. The synchronous set input (S), when High, overrides all other inputs
D
FTSRLE and sets data output (Q) High. (Set has precedence over Reset.) When synchronous
L reset (R) is High and S is Low, clock enable input (CE) is overridden and output Q is
T Q reset Low. When load enable input (L) is High and S and R are Low, CE is overridden
CE and data on data input (D) is loaded into the flip-flop during the Low-to-High clock
C transition. When the toggle enable input (T) and CE are High and S, R, and L are Low,
output Q toggles, or changes state, during the Low-to- High clock transition. When
R X3772 CE is Low, clock transitions are ignored.
For FPGAs, the flip-flop is asynchronously cleared, output Low, when global reset
(GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The
GR/GSR active level defaults to active-High but can be inverted by adding an
inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX
symbol. For CPLDs, the flip-flop is asynchronously preset when a High-level pulse is
applied on the PRLD global net.

Inputs Outputs

S R L CE T D C Q
1 0 X X X X ↑ 1
0 1 X X X X ↑ 0
0 0 1 X X 1 ↑ 1
0 0 1 X X 0 ↑ 0
0 0 0 0 X X X No Chg
0 0 0 1 0 X X No Chg
0 0 0 1 1 X ↑ Toggle

5-78 Xilinx Development System

Design Elements (FTSRLE)

TQ
T
M2_1
XOR2 D0
O MD
D D1
L S0
MD_S
R
AND2B1
S FDSE

D Q
Q
CE_R_L
CE
CE
C
OR3
C
RLOC=R0C0
X7642

Figure 5-71 FTSRLE Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

VCC
+5

CE
AND2

AND4B3

OR2
AND5B3

GND

FD
AND4B3
D Q
D Q

C
AND3B1 OR5
S Q
C
X7850

Figure 5-72 FTSRLE Implementation XC9000

Libraries Guide, Release M1.5 5-79

GXTL
Crystal Oscillator with ACLK Buffer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro N/A N/A N/A N/A N/A N/A N/A

The GXTL element drives an internal ACLK buffer with a frequency derived from an
external crystal-controlled oscillator. The GXTL (or ACLK) output is connected to an
internal clock net.
There are two dedicated input pins (XTAL 1 and XTAL 2) on each FPGA device that
X3886 are internally connected to pads and input/output blocks that are in turn connected
to the GXTL amplifier. The external components are connected as shown in the
following figure.

GXTL

ACLK

OSC

XTAL2 XTAL1

X8264

Refer to The Programmable Logic Data Book for details on component selection and
tolerances.

OSC

OSC_OUT O
ACLK

@PULSELO=@PULSEL
@PULSEHI=@PULSEH X8265

Figure 6-1 GXTL Implementation XC3000

6-4 Xilinx Development System

Design Elements (HMAP)

HMAP
H Function Generator Partitioning Control Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive N/A

The HMAP symbol is used to control logic partitioning into XC4000 and Spartan
I3 HMAP
I2 O series 3-input H function generators. It is usually used with FMAP, which partitions
I1 logic into F and G function generators. You can implement a portion of logic using
gates, latches, and flip-flops and specify the logic to be grouped into F, G, and H func-
X4659 tion generators by naming logic signals and HMAP/FMAP signals correspondingly.
These symbols are used for mapping control in addition to the actual gates, latches,
and flip-flops and not as a substitute for them. The following figure gives an example
of how logic can be placed using HMAP and FMAP symbols.

IN_F1 U1
IN_F2 U3
F_FUNC
IN_F3 D0
G_FUNC
IN_F4 D1 H_FUNC
AND4 O

Figure 6-2 Partitioning Logic Using FMAP and HMAP Symbols

The MAP=type parameter can only be set to the default value, PUC, for the HMAP
symbol. PUC means pins are not locked to the signals but the CLB is closed to addi-
tion or removal of logic.
The HMAP symbol can be assigned to specific CLB locations using LOC attributes.
Refer to the “LOC” section of the “Attributes, Constraints, and Carry Logic” chapter
for more information on assigning LOC attributes.

Libraries Guide, Release M1.5 6-5

Libraries Guide, Release M1.5

IBUF, 4, 8, 16
Single- and Multiple-Input Buffers

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

IBUF Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
IBUF4, Macro Macro Macro Macro Macro Macro Macro Macro
IBUF8,
IBUF16

IBUF IBUF, IBUF4, IBUF8, and IBUF16 are single- and multiple-input buffers. An IBUF
isolates the internal circuit from the signals coming into a chip. IBUFs are contained in
input/output blocks (IOBs). IBUF inputs (I) are connected to an IPAD or an IOPAD.
IBUF outputs (O) are connected to the internal circuit.
X3784
For Virtex, refer to the “IBUF_selectIO” section for information on IBUF variants with
selectable I/O interfaces. IBUF, 4, 8, and 16 use the LVTTL standard.
IBUF4

O[7:0]

IO O0

IBUF
I1 O1

IBUF
I2 O2
X3791 IBUF
I3 O3

IBUF
I4 O4
IBUF8
IBUF
I5 O5

IBUF
I6 O6
X3803 IBUF
I7 O7
I[7:0] IBUF
IBUF16
X7652

Figure 6-3 IBUF8 Implementation XC3000, XC4000, XC5200, XC9000, Spartans,

X3815 Virtex

6-6 Xilinx Development System

Design Elements (IBUF_selectIO)

IBUF_selectIO
Single Input Buffer with Selectable I/O Interface

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

For Virtex, IBUF and its variants (listed below) are single input buffers whose I/O
interface corresponds to a specific I/O standard. The name extensions (LVCMOS2,
X3830
PCI33_3, PCI33_5, etc.) specify the standard. For example, IBUF_SSTL3_II is a single
input buffer that uses the SSTL3_II I/O-signaling standard.
An IBUF isolates the internal circuit from the signals coming into a chip. IBUFs are
contained in input/output blocks (IOBs). IBUF inputs (I) are connected to an IPAD or
an IOPAD. IBUF outputs (O) are connected to the internal circuit.
The hardware implementation of the I/O standards requires that you follow a set of
usage rules for the SelectI/O buffer components. Refer to the “SelectI/O Usage
Rules” section below for information on using these components.

Component I/O Standard VREF

IBUF LVTTL N/A
IBUF_LVCMOS2 LVCMOS2 N/A
IBUF_PCI33_3 PCI33_3 N/A
IBUF_PCI33_5 PCI33_5 N/A
IBUF_PCI66_3 PCI66_3 N/A
IBUF_GTL GTL 0.80
IBUF_GTLP GTL+ 1.00
IBUF_HSTL_I HSTL_I 0.75
IBUF_HSTL_III HSTL_III 0.90
IBUF_HSTL_IV HSTL_IV 0.75
IBUF_SSTL2_I SSTL2_I 1.10
IBUF_SSTL2_II SSTL2_II 1.10
IBUF_SSTL3_I SSTL3_I 0.90
IBUF_SSTL3_II SSTL3_II 1.50
IBUF_CTT CTT 1.50
IBUF_AGP AGP 1.32

Libraries Guide, Release M1.5 6-7

Libraries Guide, Release M1.5

SelectI/O Usage Rules

The Virtex architecture includes a versatile SelectI/O interface to multiple voltage and
drive standards. To select an I/O standard, you must choose the appropriate compo-
nent from the Virtex library. Each standard has a full set of I/O buffer components
(input, in/out, output, 3-state output). For example, for an input buffer of the GTL
standard, you would choose IBUF_GTL. Refer to the “IBUF_selectIO”,
“IBUFG_selectIO”, “IOBUF_selectIO”, “OBUF_selectIO”, and “OBUFT_selectIO”
sections for information on the various input/output buffer components available to
implement the desired standard.
The hardware implementation of the various I/O standards requires that certain
usage rules be followed. As shown in the following table, each I/O standard has
voltage source requirements for input reference (VREF), output drive (VCCO), or
both. Each Virtex device has eight banks (two on each edge). Each bank has voltage
sources shared by all I/O in the bank. Therefore, in a particular bank, the voltage
source (for either input or output) must be of the same type. The Input Banking
(VREF) Rules section and the Output Banking (VCCO) Rules section below summa-
rize the SelectI/O component usage rules based on the hardware implementation.

I/O Standard VCCO VREF

LVTTL 3.3 N/A
LVCMOS2 2.5 N/A
PCI33_3 (PCI 33MHz 3.3V) 3.3 N/A
PCI33_5 (PCI 33MHZ 5.0V) 3.3 N/A
PCI66_3 (PCI 66MHz 3.3V) 3.3 N/A
GTL N/A 0.80
GTL+ N/A 1.00
HSTL_I 1.5 0.75
HSTL_III 1.5 0.90
HSTL_IV 1.5 0.75
SSTL2_I 2.5 1.10
SSTL2_II 2.5 1.10
SSTL3_I 3.3 0.90
SSTL3_II 3.3 1.50
CTT 3.3 1.50
AGP 3.3 1.32
Input Banking (VREF) Rules
The low-voltage I/O standards that have a differential amplifier input require a
voltage reference input (VREF). The VREF voltage source is provided as an external
signal to the chip that is banked internal to the chip.
• Any input buffer component that does not require a VREF source (LVTTL,
LVCMOS2, PCI*) can be placed in any bank.
• All input buffer components that require a VREF source (GTL*, HSTL*, SSTL*,
CTT, AGP) must be of the same I/O standard in a particular bank. For example,

6-8 Xilinx Development System

Design Elements (IBUF_selectIO)

IBUF_SSTL2_I and IBUFG_SSTL2_I are compatible since they are the same I/O
standard (SSTL2_I).
• If the bank contains any input buffer component that requires a VREF source:
• One or more VREF sources must be connected to the bank via an IOB.
• The number of VREF sources is dependent on the device and package.
• The locations of the VREF sources are fixed for each device/package.
• All VREF sources must be used in that bank.
• If the bank contains no input buffer component that requires a VREF source:
• The IOBs for VREF sources can be used for general I/O.
• Output buffer components of any type can be placed in the bank.
Output Banking (VCCO) Rules
Because Virtex has multiple low-voltage standards and also needs to be 5V tolerant,
some control is required over the distribution of VCCO, the drive source voltage for
output pins. To provide for maximum flexibility, the output pins are banked. In
comparison to the VREF sources described above, the VCCO voltage sources are dedi-
cated pins on the device and do not consume valuable IOBs.
• Any output buffer component that does not require a VCCO source (GTL, GTL+)
can be placed in any bank.
• To be placed in a particular bank, all output buffer components that require
VCCO must have the same supply voltage (VCCO). For example, OBUF_SSTL3_I
and OBUF_PCI33_3 are compatible in the same output bank since VCCO=3.3 for
both.
• Input buffer components of any type can be placed in the bank.
• The configuration pins on a Virtex device are on the right side of the chip. When
configuring the device through a serial prom, the user is required to use a VREF of
3.3V in the two banks on the right hand side of the chip. If the user is not config-
uring the device through a serial prom, the VREF requirement is dependent upon
the configuration source.
Banking Rules for OBUFT_selectIO with KEEPER
If a KEEPER symbol is attached to an OBUFT_selectIO component (3-state output
buffer) for an I/O standard that requires a VREF (for example, OBUFT_GTL,
OBUFT_SSTL3_I), then the OBUFT_selectIO component follows the same rules as an
IOBUF_selectIO component for the same standard. It must follow both the input
banking and output banking rules. The KEEPER element requires that the VREF be
properly driven.

Libraries Guide, Release M1.5 6-9

Libraries Guide, Release M1.5

IBUFG_selectIO
Dedicated Input Buffer with Selectable I/O Interface

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

IBUFG and its variants (listed below) are dedicated input buffers for connecting to the
clock buffer (BUFG) or CLKDLL. The name extensions (LVCMOS2, PCI33_3, PCI33_5,
etc.) specify the I/O interface standard used by the component. For example,
X3830
IBUFG_CTT is an input buffer that uses the CTT I/O- signaling standard.
The Xilinx implementation software converts each BUFG to an appropriate type of
global buffer for the target PLD device. The IBUFG output can only be connected to
the CLKIN input of a CLKDLL or to the input of a BUFG.
The hardware implementation of the I/O standards requires that you follow a set of
usage rules for the SelectI/O buffer components. Refer to the “SelectI/O Usage
Rules” section under the IBUF_selectIO section for information on using these compo-
nents.

Component I/O Standard VREF

IBUFG LVTTL N/A
IBUFG_LVCMOS2 LVCMOS2 N/A
IBUFG_PCI33_3 PCI33_3 N/A
IBUFG_PCI33_5 PCI33_5 N/A
IBUFG_PCI66_3 PCI66_3 N/A
IBUFG_GTL GTL 0.80
IBUFG_GTLP GTL+ 1.00
IBUFG_HSTL_I HSTL_I 0.75
IBUFG_HSTL_III HSTL_III 0.90
IBUFG_HSTL_IV HSTL_IV 0.75
IBUFG_SSTL2_I SSTL2_I 1.10
IBUFG_SSTL2_II SSTL2_II 1.10
IBUFG_SSTL3_I SSTL3_I 0.90
IBUFG_SSTL3_II SSTL3_II 1.50
IBUFG_CTT CTT 1.50
IBUFG_AGP AGP 1.32

6-10 Xilinx Development System

Design Elements (IFD, 4, 8, 16)

IFD, 4, 8, 16
Single- and Multiple-Input D Flip-Flops

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

IFD Primitive Macro Macro Macro Macro Macro Macro Macro
IFD4, Macro Macro Macro Macro Macro Macro Macro Macro
IFD8,
IFD16

The IFD D-type flip-flop is contained in an input/output block (IOB), except for
D IFD Q
XC5200 and XC9000. The input (D) of the flip-flop is connected to an IPAD or an
C IOPAD (without using an IBUF). The D input provides data input for the flip-flop,
which synchronizes data entering the chip. The data on input D is loaded into the flip-
X3776
flop during the Low-to-High clock (C) transition and appears at the output (Q). The
clock input can be driven by internal logic or through another external pin.

D0 IFD4 Q0
The flip-flops are asynchronously cleared with Low outputs when power is applied.
D1 Q1
For CPLDs, the power-on condition can be simulated by applying a High-level pulse
D2 Q2
on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global
D3 Q3
set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR
(XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an
C inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

X3799
For information on legal IFD, IFD_1, ILD, and ILD_1 combinations, refer to the “ILD,
4, 8, 16” section.

D[7:0] IFD8 Q[7:0]

C Inputs Outputs

X3811 D C Q
0 ↑ 0
D[15:0] IFD16 Q[15:0] 1 ↑ 1

C VCC
IFDX
D Q
X3833 D Q
CE
C
C

X7928

Figure 6-4 IFD Implementation XC4000, Spartans

VCC

FDCE
D D_IN Q
D Q
IBUF
CE
C
C
CLR

INREG (XC5200)
IOB=TRUE (VIRTEX)

GND X7938

Figure 6-5 IFD Implementation XC5200, Virtex

Libraries Guide, Release M1.5 6-11

Libraries Guide, Release M1.5

FDCP
IBUF
D D_IN PRE Q
D Q
IBUF
C
C
CLR
Q

GND X7852

Figure 6-6 IFD Implementation XC9000

Q[7:0]

IFD
D0 Q0
D Q

C
Q0

IFD
D1 Q1
D Q

C Q1

IFD
D2 Q2
D Q

C Q2

IFD
D3 Q3
D Q

C Q3

IFD
D4 Q4
D Q

C Q4

IFD
D5 Q5
D Q

C Q5

IFD
D6 Q6
D Q

C Q6

IFD
D7 Q7
D Q

C Q7
D[7:0]

C X6389

Figure 6-7 IFD8 Implementation XC3000, XC4000, XC5200, XC9000, Spartans,

Virtex

6-12 Xilinx Development System

Design Elements (IFD_1)

IFD_1
Input D Flip-Flop with Inverted Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Macro

The IFD_1 D-type flip-flop is contained in an input/output block (IOB) except for
D IFD_1 Q
XC5200. The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D
C input also provides data input for the flip-flop, which synchronizes data entering the
chip. The D input data is loaded into the flip-flop during the High-to-Low clock (C)
X3777 transition and appears at the output (Q). The clock input can be driven by internal
logic or through another external pin.
The flip-flop is asynchronously cleared with Low output when power is applied.
FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active.
GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex)
default to active-High but can be inverted by adding an inverter in front of the GR/
GSR input of the STARTUP or STARTUP_VIRTEX symbol.
For information on legal IFD, IFD_1, ILD, and ILD_1 combinations, refer to the “ILD,
4, 8, 16” section.

Inputs Outputs

D C Q
0 ↓ 0
1 ↓ 1

IFD
D Q
D Q

C CB
C
INV

X6398

Figure 6-8 IFD_1 Implementation XC3000, XC4000, Spartans

VCC
FDCE
D D_IN Q
D Q
IBUF
CE
C CB
C
CLR
INV

INREG (XC5200)
IOB=TRUE (VIRTEX)

GND X8122

Figure 6-9 IFD_1 Implementation XC5200, Virtex

Libraries Guide, Release M1.5 6-13

Libraries Guide, Release M1.5

IFDI
Input D Flip-Flop (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

IFDI
The IFDI D-type flip-flop is contained in an input/output block (IOB). The input (D)
D Q
of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input
C for the flip-flop, which synchronizes data entering the chip. The data on input D is
loaded into the flip-flop during the Low-to-High clock (C) transition and appears at
X4617 the output (Q). The clock input can be driven by internal logic or through another
external pin.
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.
For information on legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations, refer to the
“ILDI” section.

Inputs Outputs

D C Q
0 ↑ 0
1 ↑ 1

Vcc
IFDXI
D Q
D Q
CE
C
C

X7682

Figure 6-10 IFDI Implementation XC4000, Spartans

VCC

D D_IN PRE Q
D Q
IBUF CE
C
C

FDPE
IOB=TRUE

GND
X8740

Figure 6-11 IFDI Implementation Virtex

6-14 Xilinx Development System

Design Elements (IFDI_1)

IFDI_1
Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

The IFDI_1 D-type flip-flop is contained in an input/output block (IOB). The input
D IFDI_1 Q (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data
input for the flip-flop, which synchronizes data entering the chip. The data on input D
C
is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at
the output (Q). The clock input can be driven by internal logic or through another
X4386 external pin.
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.
For information on legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations, refer to the
“ILDI” section.

Inputs Outputs

D C Q
0 ↓ 0
1 ↓ 1

IFDI
D Q
D Q

C CB
C
INV
X7657

Figure 6-12 IFDI_1 Implementation XC4000, Spartans

VCC

D D_IN PRE Q
D Q
IBUF
CE
C CB
C
INV
FDPE
IOB=TRUE

GND X8741

Figure 6-13 IFDI_1 Implementation Virtex

Libraries Guide, Release M1.5 6-15

Libraries Guide, Release M1.5

IFDX, 4, 8, 16
Single- and Multiple-Input D Flip-Flops with Clock Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

IFDX N/A Primitive Primitive N/A N/A Primitive Primitive Macro
IFDX4, N/A Macro Macro N/A N/A Macro Macro Macro
IFDX8,
IFDX16

IFDX
The IFDX D-type flip-flop is contained in an input/output block (IOB). The input (D)
D Q
of the flip-flop is connected to an IPAD or an IOPAD (without using an IBUF). The D
CE
C
input provides data input for the flip-flop, which synchronizes data entering the chip.
The data on input D is loaded into the flip-flop during the Low-to-High clock (C) tran-
X6009 sition and appears at the output (Q). The clock input can be driven by internal logic or
through another external pin. When CE is Low, flip-flop outputs do not change.
D0 IFDX4 Q0 The flip-flops are asynchronously cleared with Low outputs when power is applied.
D1 Q1 FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
D2 Q2 tans) default to active-High but can be inverted by adding an inverter in front of the
D3 Q3 GSR input of the STARTUP symbol.
CE
For information on legal IFDX, IFDX_1, ILDX, and ILDX_1 combinations, refer to the
C
“ILDX, 4, 8, 16” section.
X6010

Inputs Outputs
D[7:0] IFDX8 Q[7:0]

CE CE Dn C Qn
C
1 Dn ↑ dn
X6011 0 X X No Chg
dn = state of referenced input (Dn) one setup time prior to active clock transition
D[15:0] IFDX16 Q[15:0]

CE FDCE
C D D_IN Q
D Q
CE IBUF
CE
X6012 C
C
CLR

IOB=TRUE

GND
X8742

Figure 6-14 IFDX Implementation Virtex

6-16 Xilinx Development System

Design Elements (IFDX, 4, 8, 16)

Q[7:0]

IFDX
D0 Q0
D Q
CE
C

IFDX
D1 Q1
D Q
CE
C

IFDX
D2 Q2
D Q
CE
C

IFDX
D3 Q3
D Q
CE
C

IFDX
D4 Q4
D Q
CE
C

IFDX
D5 Q5
D Q
CE
C

IFDX
D6 Q6
D Q
CE
C

IFDX
D7 Q7
D Q
CE
C

D[7:0] Q7

C X7635

Figure 6-15 IFDX8 Implementation XC4000, Spartans, Virtex

Libraries Guide, Release M1.5 6-17

Libraries Guide, Release M1.5

IFDX_1
Input D Flip-Flop with Inverted Clock and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

IFDX_1
The IFDX_1 D-type flip-flop is contained in an input/output block (IOB). The input
D Q
CE
(D) of the flip-flop is connected to an IPAD or an IOPAD. The D input also provides
C
data input for the flip-flop, which synchronizes data entering the chip. The data on
input D is loaded into the flip-flop during the High-to-Low clock (C) transition and
X6014 appears at the output (Q). The clock input can be driven by internal logic or through
another external pin. When the CE pin is Low, the output (Q) does not change.
The flip-flop is asynchronously cleared with Low output, when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.
For information on legal IFDX, IFDX_1, ILDX, and ILDX_1 combinations, refer to the
“ILDX, 4, 8, 16” section.

Inputs Outputs

CE D C Q
1 D ↓ d
0 X X No Chg
d = state of D input one setup time prior to active clock transition

IFDX
D Q
D Q
CE
CE
C CB
C
INV
X6422

Figure 6-16 IFDX_1 Implementation XC4000, Spartans

FDCE
D D_IN Q
D Q
CE IBUF
CE
C CB
C
CLR
INV
IOB=TRUE

GND
X8743

Figure 6-17 IFDX_1 Implementation Virtex

6-18 Xilinx Development System

Design Elements (IFDXI)

IFDXI
Input D Flip-Flop with Clock Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive Macro

The IFDXI D-type flip-flop is contained in an input/output block (IOB). The input (D)
D IFDXI Q
of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input
CE
for the flip-flop, which synchronizes data entering the chip. The data on input D is
C
loaded into the flip-flop during the Low-to-High clock (C) transition and appears at
X6016
the output (Q). The clock input can be driven by internal logic or through another
external pin. When the CE pin is Low, the output (Q) does not change.
The flip-flop is asynchronously preset with High output, when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, refer to
the “ILDXI” section.

Inputs Outputs

CE D C Q
1 D ↑ d
0 X X No Chg
d = state of D input one setup time prior to active clock transition

D D_IN PRE Q
D Q
CE IBUF
CE
C
C
FDPE

IOB=TRUE

GND
X8744

Figure 6-18 IFDXI Implementation Virtex

Libraries Guide, Release M1.5 6-19

Libraries Guide, Release M1.5

IFDXI_1
Input D Flip-Flop with Inverted Clock and Clock Enable
(Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

IFDXI_1
The IFDXI_1 D-type flip-flop is contained in an input/output block (IOB). The input
D Q
(D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data
CE
C
input for the flip-flop, which synchronizes data entering the chip. The data on input D
is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at
X6018 the output (Q). The clock input can be driven by internal logic or through another
external pin. When the CE pin is Low, the output (Q) does not change.
The flip-flop is asynchronously preset with High output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, refer to
the “ILDXI” section.

Inputs Outputs

CE D C Q
1 D ↓ d
0 X X No Chg
d = state of D input one setup time prior to active clock transition

IFDXI
D Q
D Q
CE
CE
C CB
C
INV

X6421

Figure 6-19 IFDXI_1 Implementation XC4000, Spartans

D D_IN PRE Q
D Q
CE IBUF
CE
C CB
C
INV
FDPE

IOB=TRUE

GND
X8745

Figure 6-20 IFDXI_1 Implementation Virtex

6-20 Xilinx Development System

Design Elements (ILD, 4, 8, 16)

ILD, 4, 8, 16
Transparent Input Data Latches

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

ILD Primitive Macro Macro Macro Macro Macro Macro Macro
ILD4, Macro Macro Macro Macro Macro Macro Macro Macro
ILD8,
ILD16

ILD, ILD4, ILD8, and ILD16 are single or multiple transparent data latches, which can
D ILD Q
be used to hold transient data entering a chip. The ILD latch is contained in an input/
G output block (IOB), except for XC5200 and XC9000. The latch input (D) is connected to
an IPAD or an IOPAD (without using an IBUF). When the gate input (G) is High, data
X3774 on the inputs (D) appears on the outputs (Q). Data on the D inputs during the High-
to-Low G transition is stored in the latch.
ILD4 Q0
D0 The latch is asynchronously cleared with Low output when power is applied. For
Q1
D1 CPLDs, the power-on condition can be simulated by applying a High-level pulse on
Q2
D2 the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
Q3
D3 reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
G
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
X3798
ILDs and IFDs for XC3000
D[7:0] ILD8 Q[7:0] The XC3000 ILD is actually the input flip-flop master latch. If both ILD and IFD
elements are controlled by the same clock signal, the relationship between the trans-
G parent sense of the latch and the active edge of the flip-flop is fixed as follows: a trans-
parent High latch (ILD) corresponds to a falling edge-triggered flip-flop (IFD_1), and
X3810
a transparent Low latch (ILD_1) corresponds to a rising edge-triggered flip-flop (IFD).
Because the place and route software does not support using both phases of a clock
D[15:0] ILD16 Q[15:0] for IOBs on a single edge of the device, certain combinations of ILD and IFD elements
are not allowed.
G
Refer to the following figure for legal IFD, IFD_1, ILD, and ILD_1 combinations for
X3832 the XC3000.

Libraries Guide, Release M1.5 6-21

Libraries Guide, Release M1.5

ILD ILD_1
IPAD IPAD
D Q D Q

G G

IFD_1 IFD
IPAD IPAD
D Q D Q

C C

X4690

Figure 6-21 Legal Combinations of IFD and ILD for a Single Device Edge of an
XC3000 IOB

ILDs and IFDs for XC4000 and Spartans

In XC4000 and Spartans, the ILD is actually the input flip-flop master latch. It is
possible to access two different outputs from the input flip-flop: one that responds to
the level of the clock signal and another that responds to an edge of the clock signal.
When using both outputs from the same input flip-flop, a transparent High latch
(ILD) corresponds to a falling edge-triggered flip-flop (IFD_1). Similarly, a transparent
Low latch (ILD_1) corresponds to a rising edge-triggered flip-flop (IFD).
Refer to the following figure for legal IFD, IFD_1, ILD, and ILD_1 combinations for
the XC4000 and Spartans.
ILD ILD_1
IPAD IPAD
D Q D Q

G G

IFD_1 IFD

D Q D Q

CLOCK C CLOCK C

X4688

Figure 6-22 Legal Combinations of IFD and ILD for a Single IOB in XC4000 or
Spartans

Inputs Outputs

G D Q
1 1 1
1 0 0
0 X d
d = state of referenced input one setup time prior to active G transition

6-22 Xilinx Development System

Design Elements (ILD, 4, 8, 16)

ILD_1
D Q
D Q

G GB
G
INV

X6492

Figure 6-23 ILD Implementation XC4000, Spartans

VCC

LDCE
D D_IN Q
D Q
IBUF
GE
G
G
CLR

INREG (XC5200)
IOB=TRUE (VIRTEX)

GND
X7937

Figure 6-24 ILD Implementation XC5200, Virtex

G
FDCP
D D_IN
IBUF
AND2 PRE Q
D Q

C
CLR
Q

AND2B1

GND X8123

Figure 6-25 ILD Implementation XC9000

Libraries Guide, Release M1.5 6-23

Libraries Guide, Release M1.5

Q[7:0]

ILD
D0 Q0
D Q

ILD
D1 Q1
D Q

ILD
D2 Q2
D Q

ILD
D3 Q3
D Q

ILD
D4 Q4
D Q

ILD
D5 Q5
D Q

ILD
D6 Q6
D Q

ILD
D7 Q7
D Q

D[7:0] Q7

X7853

Figure 6-26 ILD8 Implementation XC3000, XC4000, XC5200, XC9000, Spartans,

Virtex

6-24 Xilinx Development System

Design Elements (ILD_1)

ILD_1
Transparent Input Data Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Macro

ILD_1 is a transparent data latch, which can be used to hold transient data entering a
D ILD_1 Q
chip. When the gate input (G) is Low, data on the data input (D) appears on the data
G output (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously cleared with Low output when power is applied. FPGAs
X4387
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for
XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to
active-High but can be inverted by adding an inverter in front of the GR/GSR input of
the STARTUP or STARTUP_VIRTEX symbol.
For information on legal IFD, IFD_1, ILD, and ILD_1 combinations, refer to the “ILD,
4, 8, 16” section.

Inputs Outputs

G D Q
0 1 1
0 0 0
1 X d
d = state of referenced input one setup time prior to Low-to-High gate transition

ILD
D Q
D Q

G GB
G
INV X6493

Figure 6-27 ILD_1 Implementation XC3000

VCC
ILDX_1
D Q
D Q
GE
G
G

X6491

Figure 6-28 ILD_1 Implementation XC4000, Spartans

VCC
LDCE
D D_IN Q
D Q
IBUF
GE
G GB
G
CLR
INV

INREG (XC5200)
IOB=TRUE (VIRTEX)

GND X8121

Figure 6-29 ILD_1 Implementation XC5200, Virtex

Libraries Guide, Release M1.5 6-25

Libraries Guide, Release M1.5

ILDI
Transparent Input Data Latch (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

ILDI ILDI is a transparent data latch, which can hold transient data entering a chip. When
D Q
the gate input (G) is High, data on the input (D) appears on the output (Q). Data on
G the D input during the High-to-Low G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied. FPGAs
X4388
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

ILDIs and IFDIs

The ILDI is actually the input flip-flop master latch. It is possible to access two
different outputs from the input flip-flop: one that responds to the level of the clock
signal and another that responds to an edge of the clock signal. When using both
outputs from the same input flip-flop, a transparent High latch (ILDI) corresponds to
a falling edge-triggered flip-flop (IFDI_1). Similarly, a transparent Low latch (ILDI_1)
corresponds to a rising edge-triggered flip-flop (IFDI).
Refer to the following figure for legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations.

ILDI ILDI_1
IPAD IPAD
D Q D Q

G G

IFDI_1 IFDI

D Q D Q

CLOCK C CLOCK C

X4511

Figure 6-30 Legal Combinations of IFDI and ILDI for a Single IOB in XC4000
and Spartans

Inputs Outputs

G D Q
1 1 1
1 0 0
0 X d
d = state of referenced input one setup time prior to High-to-Low gate transition

6-26 Xilinx Development System

Design Elements (ILDI)

ILDI_1
D Q
D Q

C GB
G
INV
X7633

Figure 6-31 ILDI Implementation XC4000, Spartans

VCC

D D_IN PRE Q
D Q
IBUF GE
G
G

LDPE
IOB=TRUE

GND
X8746

Figure 6-32 ILDI Implementation Virtex

Libraries Guide, Release M1.5 6-27

Libraries Guide, Release M1.5

ILDI_1
Transparent Input Data Latch with Inverted Gate (Asynchronous
Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

ILDI_1 is a transparent data latch, which can hold transient data entering a chip.
D ILDI_1 Q
When the gate input (G) is Low, data on the data input (D) appears on the data output
G (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied. FPGAs
X4618
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.
For information on legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations, refer to the
“ILDI” section.

Inputs Outputs

G D Q
0 1 1
0 0 0
1 X d
d = state of input one setup time prior to High-to-Low gate transition

Vcc

ILDXI
D Q
D Q
CE
G CB
G
INV
X7411

Figure 6-33 ILDI_1 Implementation XC4000, Spartans

VCC

D D_IN PRE Q
D Q
IBUF GE
G GB
G
INV
LDPE
IOB=TRUE

GND
X8747

Figure 6-34 ILDI_1 Implementation Virtex

6-28 Xilinx Development System

Design Elements (ILDX, 4, 8, 16)

ILDX, 4, 8, 16
Transparent Input Data Latches

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

ILDX N/A Macro Macro N/A N/A Macro Macro Macro
ILDX4, N/A Macro Macro N/A N/A Macro Macro Macro
ILDX8,
ILDX16

D ILDX Q
ILDX, ILDX4, ILDX8, and ILDX16 are single or multiple transparent data latches,
GE which can be used to hold transient data entering a chip. The latch input (D) is
G connected to an IPAD or an IOPAD (without using an IBUF). When the gate input (G)
is High, data on the inputs (D) appears on the outputs (Q). Data on the D inputs
X6020 during the High-to-Low G transition is stored in the latch.
The latch is asynchronously cleared, output Low, when power is applied. FPGAs
D0 ILDX4 Q0 simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
D1 Q1 default to active-High but can be inverted by adding an inverter in front of the GSR
D2 Q2
input of the STARTUP symbol.
D3 Q3
GE
ILDXs and IFDXs
G

The ILDX is actually the input flip-flop master latch. Two different outputs can be
X6021
accessed from the input flip-flop: one that responds to the level of the clock signal and
another that responds to an edge of the clock signal. When using both outputs from
D[7:0] ILDX8 Q[7:0] the same input flip-flop, a transparent High latch (ILDX) corresponds to a falling
GE edge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corre-
G sponds to a rising edge-triggered flip-flop (IFDX).
X6022 Refer to the following figure for legal IFDX, IFDX_1, ILDX, and ILDX_1 combinations.

ILDX ILDX_1
D[15:0] ILDX16 Q[15:0] IPAD IPAD
D Q D Q
GE
IO_ENABLE GE IO_ENABLE GE
G
G G
X6023

IFDX_1 IFDX

D Q D Q
CE CE
CLOCK C CLOCK C

X6024

Figure 6-35 Legal Combinations of IFDX and ILDX for a Single IOB in XC4000
and Spartans

Libraries Guide, Release M1.5 6-29

Libraries Guide, Release M1.5

Inputs Outputs

GE G D Q
0 X X No Chg
1 0 X No Chg
1 1 1 1
1 1 0 0
1 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

ILDX_1
D Q
D Q
GE
GE
G GB
G
INV

X6419

Figure 6-36 ILDX Implementation XC4000, Spartans

LDCE
D D_IN Q
D Q
GE IBUF
GE
G G
CLR

IOB=TRUE

GND
X8748

Figure 6-37 ILDX Implementation Virtex

6-30 Xilinx Development System

Design Elements (ILDX, 4, 8, 16)

Q[7:0]

ILDX
D0 Q0
D Q
GE
G
Q0

ILDX
D1 Q1
D Q
GE
G
Q1

ILDX
D2 Q2
D Q
GE
G
Q2

ILDX
D3 Q3
D Q
GE
G
Q3

ILDX
D4 Q4
D Q
GE
G
Q4

ILDX
D5 Q5
D Q
GE
G
Q5

ILDX
D6 Q6
D Q
GE
G
Q6

ILDX
D7 Q7
D Q
GE
G
Q7
D[7:0]

G
X6405

Figure 6-38 ILDX8 Implementation XC4000, Spartans, Virtex

Libraries Guide, Release M1.5 6-31

Libraries Guide, Release M1.5

ILDX_1
Transparent Input Data Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive Macro

ILDX_1
ILDX_1 is a transparent data latch, which can be used to hold transient data entering a
D Q
chip. When the gate input (G) is Low, data on the data input (D) appears on the data
GE
G
output (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously cleared with Low output, when power is applied. FPGAs
X6025 simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.
For information on legal IFDX, IFDX_1, ILDX, and ILDX_1 combinations, refer to the
“ILDX, 4, 8, 16” section.

Inputs Outputs

GE G D Q
0 X X No Chg
1 1 X No Chg
1 0 1 1
1 0 0 0
1 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

LDCE
D D_IN Q
D Q
GE IBUF
GE
G GB
G
INV CLR

IOB=TRUE

GND
X8749

Figure 6-39 ILDX_1 Implementation Virtex

6-32 Xilinx Development System

Design Elements (ILDXI)

ILDXI
Transparent Input Data Latch (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

ILDXI
ILDXI is a transparent data latch, which can hold transient data entering a chip. When
D Q
GE
the gate input (G) is High, data on the input (D) appears on the output (Q). Data on
G
the D input during the High-to-Low G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied. FPGAs
X6026
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

ILDXIs and IFDXIs

The ILDXI is actually the input flip-flop master latch. Two different outputs can be
accessed from the input flip-flop: one that responds to the level of the clock signal and
another that responds to an edge of the clock signal. When using both outputs from
the same input flip-flop, a transparent High latch (ILDXI) corresponds to a falling
edge-triggered flip-flop (IFDXI_1). Similarly, a transparent Low latch (ILDXI_1) corre-
sponds to a rising edge-triggered flip-flop (IFDXI). Refer to the following figure for
legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations.

ILDXI ILDXI_1
IPAD IPAD
D Q D Q
IO_ENABLE GE IO_ENABLE GE
G G

IFDXI_1 IFDXI

D Q D Q
CE CE
CLOCK C CLOCK C

X6027

Figure 6-40 Legal Combinations of IFDXI and ILDXI for a Single IOB

Libraries Guide, Release M1.5 6-33

Libraries Guide, Release M1.5

Inputs Outputs

GE G D Q
0 X X No Chg
1 0 X No Chg
1 1 1 1
1 1 0 0
1 ↓ D d
d = state of referenced input one setup time prior to High-to-Low gate transition

ILDXI_1
D Q
D Q
GE
GE
G GB
G
INV

X6420

Figure 6-41 ILDXI Implementation XC4000, Spartans

D D_IN PRE Q
D Q
GE IBUF
GE
G G

LDPE
IOB=TRUE

GND
X8750

Figure 6-42 ILDXI Implementation Virtex

6-34 Xilinx Development System

Design Elements (ILDXI_1)

ILDXI_1
Transparent Input Data Latch with Inverted Gate (Asynchronous
Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive Macro

ILDXI_1 is a transparent data latch, which can hold transient data entering a chip.
ILDXI_1 Q
D When the gate input (G) is Low, data on the data input (D) appears on the data output
GE
(Q). Data on D during the Low-to-High G transition is stored in the latch.
G

The latch is asynchronously preset, output High, when power is applied. FPGAs
X6028 simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, refer to
the “ILDXI” section.

Inputs Outputs

GE G D Q
0 X X No Chg
1 1 X No Chg
1 0 1 1
1 0 0 0
1 ↑ D d
d = state of referenced input one setup time prior to Low-to-High gate transition

D D_IN PRE Q
D Q
GE IBUF
GE
G GB G
INV
LDPE
IOB=TRUE

GND
X8751

Figure 6-43 ILDXI_1 Implementation Virtex

Libraries Guide, Release M1.5 6-35

Libraries Guide, Release M1.5

ILFFX
Fast Capture Input Latch

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

ILFFX ILFFX, an optional latch that drives the input flip-flop, allows the very fast capture of
input data. Located on the input side of an IOB, the latch is latched by the output
INODE
D Q clock — the clock used for the output flip-flop — rather than the input clock. Thus,
GF
two different clocks can be used to clock the two input storage elements. The
CE
following figure shows an example IOB block diagram of the XC4000X IOB. After the
C data is captured, it is then synchronized to the internal clock (C) by the IOB flip-flop.
Passive
X6996 Slew Rate
Pull-Up/
Control Pull-Down

T
Output Mux

Flip-Flop
D Q
Out Output
CE Buffer
Pad
Output Input
Clock Buffer

Flip-Flop/
Latch
I2 Delay Delay
Q D

Q D
Clock Latch
Enable CE Fast G
Capture
Latch
Input
Clock

X6550n

Figure 6-44 Block Diagram of XC4000X IOB

The latch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
When the gate input (GF) is Low, the data at the input (D) appears at INODE and is
stored during the Low-to-High GF transition. The captured INODE data appears at
output (Q) during a Low-to-High clock (C) transition.
The fast latch is asynchronously cleared when power is applied. FPGAs simulate
power-on when global set/reset (GSR) is active. GSR (XC4000X, SpartanXL) default to
active-High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP symbol.

6-36 Xilinx Development System

Design Elements (ILFFX)

Inputs Outputs

CE D GF C Q
0 X X X No Chg
1 X 1 ↑ INODE
1 0 0 ↑ 0
1 1 0 ↑ 1

Libraries Guide, Release M1.5 6-37

Libraries Guide, Release M1.5

ILFFXI
Fast Capture Input Latch (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

ILFFXI ILFFXI, an optional latch that drives the input flip-flop, allows the very fast capture of
input data. Located on the input side of an IOB, the latch is latched by the output
D
INODE
Q clock — the clock used for the output flip-flop — rather than the input clock. Thus,
two different clocks can be used to clock the two input storage elements. See the
GF
“Block Diagram of XC4000X IOB” figure in the ILFFX section. After the data is
CE
C
captured, it is then synchronized to the internal clock by the IOB flip-flop.
X7711 The latch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
When the gate input (GF) is Low, the data at the input (D) appears at INODE and is
stored during the Low-to-High GF transition. The captured INODE data appears at
output (Q) during a Low-to-High clock (C) transition.
This component is identical to ILFFX except that on active GSR it is preset instead of
cleared. The latch is asynchronously preset, output High, when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000X,
SpartanXL) default to active-High but can be inverted by adding an inverter in front
of the GSR input of the STARTUP symbol.

6-38 Xilinx Development System

Design Elements (ILFLX)

ILFLX
Fast Capture Transparent Input Latch

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro N/A N/A N/A Macro N/A

ILFLX ILFLX, an optional latch that drives the input latch, allows the very fast capture of
input data. Located on the input side of an IOB, the latch is latched by the output
D INODE Q
clock — the clock used for the output flip-flop — rather than the input clock. Thus,
GF
two different clocks can be used to clock the two input storage elements. See the
GE “Block Diagram of XC4000X IOB” figure in the ILFFX section. After the data is
G
captured, it is then synchronized to the internal clock by the IOB latch.
X7695

Inputs Outputs

GE D GF G Q
0 X X X No Chg
1 X X 0 No Chg
1 X 1 1 INODE
1 0 0 1 0
1 1 0 1 1

ILFLX_1

D Q
D Q

GF
GF

GE GE

G GB G

INV X7418

Figure 6-45 ILFLX Implementation XC4000X, SpartanXL

Libraries Guide, Release M1.5 6-39

Libraries Guide, Release M1.5

ILFLX_1
Fast Capture Input Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

ILFLX_1 ILFLX_1, an optional latch that drives the input latch, allows the very fast capture of
D INODE Q
input data. Located on the input side of an IOB, the latch is latched by the output
clock — the clock used for the output flip-flop — rather than the input clock. Thus,
GF
two different clocks can be used to clock the two input storage elements. See the
GE “Block Diagram of XC4000X IOB” figure in the ILFFX section. After the data is
G
captured, it is then synchronized to the internal clock by the IOB latch.
X7712

The latch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
When the gate input (GF) is Low, the data at the input (D) appears at INODE and is
stored during the Low-to-High GF transition. The captured INODE data appears on
the output (Q) when the gate (G) is Low.
The fast latch is asynchronously cleared when power is applied. FPGAs simulate
power-on when global set/reset (GSR) is active. GSR (XC4000X, SpartanXL) default to
active-High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP symbol.

Inputs Outputs

GE D GF G Q
0 X X X No Chg
1 X X 1 No Chg
1 X 1 0 INODE
1 0 0 0 0
1 1 0 0 1

6-40 Xilinx Development System

Design Elements (ILFLXI_1)

ILFLXI_1
Fast Capture Input Latch with Inverted Gate (Asynchronous
Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

ILFLXI_1 ILFLXI_1, an optional latch that drives the input latch, allows the very fast capture of
D INODE Q
input data. Located on the input side of an IOB, the latch is latched by the output
clock — the clock used for the output flip-flop — rather than the input clock. Thus,
GF
two different clocks can be used to clock the two input storage elements. See the
GE “Block Diagram of XC4000X IOB” figure in the ILFFX section. After the data is
G
captured, it is then synchronized to the internal clock by the IOB latch.
X7713
The latch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
When the gate input (GF) is Low, the data at the input (D) appears at INODE and is
stored during the Low-to-High GF transition. The captured INODE data appears on
the output (Q) when the gate (G) is Low.
The fast latch is asynchronously preset when power is applied. FPGAs simulate
power-on when global set/reset (GSR) is active. GSR (XC4000X, SpartanXL) default to
active-High but can be inverted by adding an inverter in front of the GSR input of the
STARTUP symbol.

Inputs Outputs

GE D GF G Q
0 X X X No Chg
1 X X 1 No Chg
1 X 1 0 INODE
1 0 0 0 0
1 1 0 0 1

Libraries Guide, Release M1.5 6-41

Libraries Guide, Release M1.5

INV, 4, 8, 16
Single and Multiple Inverters

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

INV Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
INV4, Macro Macro Macro Macro Macro Macro Macro Macro
INV8,
INV16

INV, INV4, INV8, and INV16 are single and multiple inverters that identify signal
inversions in a schematic.
INV
X3788
O[7:0]

IO O0

INV
I1 O1

INV
I2 O2

INV
I3 O3
INV4
INV
X3795 I4 O4

INV
I5 O5

INV
I6 O6

INV
INV8 I7 O7
X3807 I[7:0] INV

X7653

Figure 6-46 INV8 Implementation XC3000, XC4000, XC5200, XC9000, Spartans,

INV16 Virtex
X3819

6-42 Xilinx Development System

Design Elements (IOB)

IOB
IOB Configuration Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive N/A N/A N/A N/A N/A N/A N/A

T IOB The IOB symbol is used to manually specify an IOB configuration. Use it in place of,
O I not in conjunction with, other I/O primitives. The configuration of the IOB is speci-
IK Q fied using the BASE and CONFIG commands. Enter these commands on the sche-
OK matic; the translator puts them into the CFG records in the LCA Xilinx netlist file. It is
not necessary for the translator program to parse the commands specifying the IOB
X4652
configuration. The mapping program from the LCA Xilinx netlist to the FPGA design
checks these commands for errors.
Refer to the appropriate CAE tool interface user guide for more information on speci-
fying the IOB configuration commands in a schematic.
The XC3000 blank IOB primitive symbol and its corresponding configured IOB primi-
tive and circuit are shown in the “XC3000 IOB Primitive Example and Equivalent
Circuit” figure.
The configuration commands must be consistent with the connections to the pins on
the symbol. For example, if the configuration commands specify the IOB as a 3-state
buffer, the T and O pins must be connected to signals.
You can specify the location of the IOB on the device. When specifying the LOC
attribute, a valid IOB location name must be used. Refer to the “LOC” section of the
“Attributes, Constraints, and Carry Logic” chapter for more information on the LOC
attribute.

T
IOB I
O
IK
Q
OK

J13
IO
IN:IQ:LATCH OUT:OQ TRI:T

U2 T

0 O
D

OK
U5 C
OUTFFT
PAD
J13
U4 n I

Q
D Q

L
INLAT

X4673

Figure 6-47 XC3000 IOB Primitive Example and Equivalent Circuit

Libraries Guide, Release M1.5 6-43

Libraries Guide, Release M1.5

IOBUF_selectIO
Bi-Directional Buffer with Selectable I/0 Interface

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

T IOBUF and its variants (listed below) are bi-directional buffers whose I/O interface
I IO corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3,
PCI33_5, etc.) specify the standard. The S, F, and 2, 4, 6, 8, 12, 16, 24 extensions specify
O
the slew rate (SLOW or FAST) and the drive power (2, 4, 6, 8, 12, 16, 24 mA) for the
X8406 LVTTL standard variants. For example, IOBUF_F_2 is a bi-directional buffer that uses
the LVTTL I/O-signaling standard with a FAST slew and 2mA of drive power.
IOBUF (LVTTL) has selectable drive and slew rates using the DRIVE and FAST or
SLOW constraints. The defaults are DRIVE=12 mA and SLOW slew.
IOBUFs are composites of IBUF and OBUFT elements. The O output is X (unknown)
when IO (input/output) is Z. IOBUFs can be implemented as interconnections of their
component elements.
The hardware implementation of the I/O standards requires that you follow a set of
usage rules for the SelectI/O buffer components. Refer to the “SelectI/O Usage
Rules” section under the IBUF_selectIO section for information on using these compo-
nents.

Component I/O Standard VCCO VREF

IOBUF LVTTL 3.3 N/A
IOBUF_S_2 LVTTL 3.3 N/A
IOBUF_S_4 LVTTL 3.3 N/A
IOBUF_S_6 LVTTL 3.3 N/A
IOBUF_S_8 LVTTL 3.3 N/A
IOBUF_S_12 LVTTL 3.3 N/A
IOBUF_S_16 LVTTL 3.3 N/A
IOBUF_S_24 LVTTL 3.3 N/A
IOBUF_F_2 LVTTL 3.3 N/A
IOBUF_F_4 LVTTL 3.3 N/A
IOBUF_F_6 LVTTL 3.3 N/A
IOBUF_F_8 LVTTL 3.3 N/A
IOBUF_F_12 LVTTL 3.3 N/A
IOBUF_F_16 LVTTL 3.3 N/A
IOBUF_F_24 LVTTL 3.3 N/A
IOBUF_LVCMOS2 LVCMOS2 2.5 N/A
IOBUF_PCI33_3 PCI33_3 3.3 N/A
IOBUF_PCI33_5 PCI33_5 3.3 N/A

6-44 Xilinx Development System

Design Elements (IOBUF_selectIO)

Component I/O Standard VCCO VREF

IOBUF_PCI66_3 PCI66_3 3.3 N/A
IOBUF_GTL GTL N/A 0.80
IOBUF_GTLP GTL+ N/A 1.00
IOBUF_HSTL_I HSTL_I 1.5 0.75
IOBUF_HSTL_III HSTL_III 1.5 0.90
IOBUF_HSTL_IV HSTL_IV 1.5 0.75
IOBUF_SSTL2_I SSTL2_I 2.5 1.10
IOBUF_SSTL2_II SSTL2_II 2.5 1.10
IOBUF_SSTL3_I SSTL3_I 3.3 0.90
IOBUF_SSTL3_II SSTL3_II 3.3 1.50
IOBUF_CTT CTT 3.3 1.50
IOBUF_AGP AGP 3.3 1.32

Libraries Guide, Release M1.5 6-45

Libraries Guide, Release M1.5

IOPAD, 4, 8, 16
Single- and Multiple-Input/Output Pads

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

IOPAD Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
IOPD4, Macro Macro Macro Macro Macro Macro Macro Macro
IOPAD8,
IOPAD16

IOPAD IOPAD, IOPAD4, IOPAD8, and IOPAD16 are single and multiple input/output pads.
The IOPAD is a connection point from a device pin, used as a bidirectional signal, to a
PLD device. The IOPAD is connected internally to an input/output block (IOB),
X3828
which is configured by the software as a bidirectional block. Bidirectional blocks can
consist of any combinations of a 3-state output buffer (such as OBUFT or OFDE) and
IOPAD4
any available input buffer (such as IBUF or IFD). Refer to the appropriate CAE tool
IO0
interface user guide for details on assigning pin location and identification.
IO1
IO2 Note: The LOC attribute cannot be used on IOPAD multiples.
IO3
IO[ 7: 0]
X3838

IO0
IOPAD8 IOPAD

IO[7:0] IO1
IOPAD

X3841
IO2
IOPAD

IOPAD16 IO3
IOPAD
IO[15:0]
IO4
IOPAD
X3845
IO5
IOPAD

IO6
IOPAD

IO7
IOPAD

X7854

Figure 6-48 IOPAD8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

6-46 Xilinx Development System

Design Elements (IPAD, 4, 8, 16)

IPAD, 4, 8, 16
Single- and Multiple-Input Pads

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

IPAD Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
IPAD4, Macro Macro Macro Macro Macro Macro Macro Macro
IPAD8,
IPAD16

IPAD IPAD, IPAD4, IPAD8, and IPAD16 are single and multiple input pads. The IPAD is a
connection point from a device pin used for an input signal to the PLD device. It is
connected internally to an input/output block (IOB), which is configured by the soft-
X3827 ware as an IBUF, IFD, or ILD. Refer to the appropriate CAE tool interface user guide
for details on assigning pin location and identification.
IPAD4 Note: The LOC attribute cannot be used on IPAD multiples.
I0
I[7:0]
I1
I2
I3 I0
IPAD
I1
X3837 IPAD
I2
IPAD

IPAD8 I3
IPAD
I[7:0] I4
IPAD
I5
X3840 IPAD
I6
IPAD
I7
IPAD16 IPAD

I[15:0] X7655

Figure 6-49 IPAD8 Implementation XC3000, XC4000, XC5200, XC9000,

X3844
Spartans, Virtex

Libraries Guide, Release M1.5 6-47

Libraries Guide, Release M1.5

KEEPER
KEEPER Symbol

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

KEEPER is a weak keeper element used to retain the value of the net connected to its
bidirectional O pin. For example, if a logic 1 is being driven onto the net, KEEPER
drives a weak/resistive 1 onto the net. If the net driver is then tri-stated, KEEPER
continues to drive a week/resistive 1 onto the net.
O
X8718
For additional information on using a KEEPER element with SelectI/O components,
refer to the “SelectI/O Usage Rules” in the "IBUF_selectIO" section.

6-48 Xilinx Development System

Chapter 7

Design Elements (LD to NOR16)

Libraries Guide, Release M1.5 — 7-1

Libraries Guide, Release M1.5

LD
Transparent Data Latch

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro Macro Macro N/A Macro Primitive

LD
LD is a transparent data latch. The data output (Q) of the latch reflects the data (D)
D Q
input while the gate enable (G) input is High. The data on the D input during the
G High-to-Low gate transition is stored in the latch. The data on the Q output remains
unchanged as long as G remains Low.
X3740
The latch is asynchronously cleared, output Low, when power is applied. For CPLDs,
the power-on condition can be simulated by applying a High-level pulse on the PRLD
global net. FPGAs simulate power-on when global reset (GR) or global set/reset
(GSR) is active. GR (XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-
High but can be inverted by adding an inverter in front of the GR/GSR input of the
STARTUP or STARTUP_VIRTEX symbol.
Refer to the “LD4, 8, 16” section for information on multiple transparent data latches
for the XC4000X, XC9000, and SpartanXL.

Inputs Outputs

G D Q
1 0 0
1 1 1
0 X No Chg
↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Vcc
LDCE_1
D Q
D Q
GE
G
G
CLR
INV

RLOC=R0C0

GND
X7419

Figure 7-1 LD Implementation XC4000X, SpartanXL

7-2 Xilinx Development System

Design Elements (LD)

VCC
LDCE
D Q
D Q
GE
G
G
CLR

RLOC=R0C0

GND X6368

Figure 7-2 LD Implementation XC5200

G
FDCP
D

AND2 PRE Q
D Q

C
CLR

AND2B1

GND
X7855

Figure 7-3 LD Implementation XC9000

Libraries Guide, Release M1.5 7-3

Libraries Guide, Release M1.5

LD_1
Transparent Data Latch with Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro Macro N/A N/A Macro Primitive

LD_1 is a transparent data latch with an inverted gate. The data output (Q) of the
D LD_1 Q
latch reflects the data (D) input while the gate enable (G) input is Low. The data on the
G D input during the Low-to-High gate transition is stored in the latch. The data on the
Q output remains unchanged as long as G remains High.
X3741
The latch is asynchronously cleared with Low output when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or
STARTUP_VIRTEX symbol.

Inputs Outputs

G D Q
0 0 0
0 1 1
1 X No Chg
↑ D d
d = state of input one setup time prior to Low-to-High gate transition

Vcc
LDCE_1
D Q
D Q
GE
G
G
CLR

RLOC=R0C0

GND
X7422

Figure 7-4 LD_1 Implementation XC4000X, SpartanXL

VCC
LDCE
D Q
D Q
GE
G GB
G
CLR
INV

RLOC=R0C0

GND

X6369

Figure 7-5 LD_1 Implementation XC5200

7-4 Xilinx Development System

Design Elements (LD4, 8, 16)

LD4, 8, 16
Multiple Transparent Data Latches

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

LD4, N/A N/A Macro N/A Macro N/A Macro Macro
LD8,
LD16

LD4
LD4, LD8, and LD16 have, respectively, 4, 8, and 16 transparent data latches with a
D0 Q0
common gate enable (G). The data output (Q) of the latch reflects the data (D) input
D1 Q1
D2 Q2
while the gate enable (G) input is High. The data on the D input during the High-to-
D3 Q3 Low gate transition is stored in the latch. The data on the Q output remains
unchanged as long as G remains Low.
G
The latch is asynchronously cleared, output Low, when power is applied. For CPLDs,
X4611 the power-on condition can be simulated by applying a High-level pulse on the PRLD
global net. FPGAs simulate power-on when global set/reset (GSR) is active. GSR
D[7:0] Q[7:0]
(XC4000X, SpartanXL, Virtex) default to active-High but can be inverted by adding an
LD8
inverter in front of the GSR input of the STARTUP or the STARTUP_VIRTEX symbol.
G
Refer to the “LD” section for information on single transparent data latches.
X4612

Inputs Outputs
D[15:0] LD16 Q[15:0]
G D Q
G
1 0 0
X4613 1 1 1
0 X No Chg
↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Libraries Guide, Release M1.5 7-5

Libraries Guide, Release M1.5

Q[7:0]

LD LD
D4 Q0 D0 Q4
D Q D Q

G G

Q0 Q4

LD LD
D5 Q1 D1 Q5
D Q D Q

G G

Q1 Q5

LD LD
D6 Q2 D2 Q6
D Q D Q

G G

Q2 Q6

LD LD
D7 Q3 D7 Q7
D Q D Q

G G

D[7:0] Q3 Q7

G X7856

Figure 7-6 LD8 Implementation XC4000X, XC9000, SpartanXL, Virtex

7-6 Xilinx Development System

Design Elements (LDC)

LDC
Transparent Data Latch with Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro Macro N/A N/A Macro Primitive

LDC is a transparent data latch with asynchronous clear. When the asynchronous
D LDC Q
clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output
G Low. Q reflects the data (D) input while the gate enable (G) input is High and CLR is
Low. The data on the D input during the High-to-Low gate transition is stored in the
CLR latch. The data on the Q output remains unchanged as long as G remains low.
X4070
The latch is asynchronously cleared with Low output when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR G D Q
1 X X 0
0 1 0 0
0 1 1 1
0 0 X No Chg
0 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Vcc
LDCE_1
D Q
D Q
GE
G GR
G
CLR
CLR INV

RLOC=R0C0

X7420

Figure 7-7 LDC Implementation XC4000X, SpartanXL

VCC

LDCE
D Q
D Q
GE
G
G
CLR
CLR
RLOC=R0C0

X6382

Figure 7-8 LDC Implementation XC5200

Libraries Guide, Release M1.5 7-7

Libraries Guide, Release M1.5

LDC_1
Transparent Data Latch with Asynchronous Clear and Inverted
Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro Macro N/A N/A Macro Primitive

LDC_1 is a transparent data latch with asynchronous clear and inverted gate. When
D LDC_1 Q
the asynchronous clear input (CLR) is High, it overrides the other inputs (D and G)
G
and resets the data (Q) output Low. Q reflects the data (D) input while the gate enable
(G) input and CLR are Low. The data on the D input during the Low-to-High gate
CLR transition is stored in the latch. The data on the Q output remains unchanged as long
as G remains High.
X3752

The latch is asynchronously cleared with Low output when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR G D Q
1 X X 0
0 0 0 0
0 0 1 1
0 1 X No Chg
0 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

Vcc
LDCE_1
D Q
D Q
GE
G
G
CLR
CLR
RLOC=R0C0

X7421

Figure 7-9 LDC_1 Implementation XC4000X, SpartanXL

VCC

LDCE
D Q
D Q
GE
G GB
G
CLR
CLR INV
RLOC=R0C0

X6384

Figure 7-10 LDC_1 Implementation XC5200

7-8 Xilinx Development System

Design Elements (LDCE)

LDCE
Transparent Data Latch with Asynchronous Clear and Gate Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro Primitive N/A N/A Macro Primitive

LDCE
LDCE is a transparent data latch with asynchronous clear and gate enable. When the
D Q
GE
asynchronous clear input (CLR) is High, it overrides the other inputs and resets the
G data (Q) output Low. Q reflects the data (D) input while the gate (G) input and gate
enable (GE) are High and CLR is Low. If GE is Low, data on D cannot be latched. The
CLR data on the D input during the High-to-Low gate transition is stored in the latch. The
X4979 data on the Q output remains unchanged as long as G or GE remains low.
The latch is asynchronously cleared with Low output when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR GE G D Q
1 X X X 0
0 0 X X No Chg
0 1 1 0 0
0 1 1 1 1
0 1 0 X No Chg
0 1 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

LDCE_1
D Q
D Q
GE
GE
G GB
G
CLR
INV
CLR
RLOC=R0C0 X7417

Figure 7-11 LDCE Implementation XC4000X, SpartanXL

Libraries Guide, Release M1.5 7-9

Libraries Guide, Release M1.5

LDCE_1
Transparent Data Latch with Asynchronous Clear, Gate Enable,
and Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive Macro N/A N/A Primitive Primitive

LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted
LDCE_1 Q
D gate. When the asynchronous clear input (CLR) is High, it overrides the other inputs
GE
G
and resets the data (Q) output Low. Q reflects the data (D) input while the gate (G)
input and CLR are Low and gate enable (GE) is High. If GE is Low, the data on D
CLR cannot be latched. The data on the D input during the Low-to-High gate transition is
X4930 stored in the latch. The data on the Q output remains unchanged as long as G remains
High or GE remains Low.
The latch is asynchronously cleared with Low output when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR GE G D Q
1 X X X 0
0 0 X X No Chg
0 1 0 0 0
0 1 0 1 1
0 1 1 X No Chg
0 1 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

LDCE
D Q
D
GE
GE
G GB
G
CLR
CLR INV
RLOC=R0C0

X6383

Figure 7-12 LDCE_1 Implementation XC5200

7-10 Xilinx Development System

Design Elements (LD4CE, LD8CE, LD16CE)

LD4CE, LD8CE, LD16CE

Transparent Data Latches with Asynchronous Clear and Gate
Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

LD4CE, N/A N/A Macro Macro N/A N/A Macro Macro
LD8CE,
LD16CE

LD4CE
LD4CE, LD8CE, and LD16CE have, respectively, 4, 8, and 16 transparent data latches
Q0
D0 with asynchronous clear and gate enable. When the asynchronous clear input (CLR) is
D1 Q1
High, it overrides the other inputs and resets the data (Q) outputs Low. Q reflects the
D2 Q2
D3 Q3
data (D) inputs while the gate (G) input is High, gate enable (GE) is High, and CLR is
GE Low. If GE for is Low, data on D cannot be latched. The data on the D input during the
G High-to-Low gate transition is stored in the latch. The data on the Q output remains
unchanged as long as GE remains Low.
CLR The latch is asynchronously cleared with Low output when power is applied. FPGAs
X6947
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR
(XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be
D[7:0] LD8CE Q[7:0]
inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the
STARTUP_VIRTEX symbol.
GE
G

CLR
Inputs Outputs
X6948
CLR GE G Dn Qn

D[15:0] LD16CE
1 X X X 0
Q[15:0]

GE
0 0 X X No Chg
G 0 1 1 1 1
0 1 1 0 0
CLR
X6949
0 1 0 X No Chg
0 1 ↓ Dn dn
Dn = referenced input, for example, D0, D1, D2
Qn = referenced output, for example, Q0, Q1, Q2
dn = referenced input state, one setup time prior to High-to-Low gate transition

Libraries Guide, Release M1.5 7-11

Libraries Guide, Release M1.5

LDCE
D0 Q0
D Q
GE
G
CLR
Q0
LDCE
D1 Q1
D Q
GE
G
CLR
Q1

LDCE
D2 D Q2
Q
GE
G
CLR
Q2
LDCE
D3 Q3
D Q
GE
GE
G
G
CLR
CLR
Q3

X6538

Figure 7-13 LD4CE Implementation XC4000X, XC5200, SpartanXL, Virtex

Q[7:0]

LDCE LDCE

D0 Q0 D4 Q4
D Q D Q
GE GE
G G
CLR CLR
Q0 Q4
LDCE LDCE
D1 Q1 D5 Q5
D Q D Q
GE GE
G G
CLR CLR
Q1 Q5
LDCE LDCE
D2 Q2 D6 Q6
D Q D Q
GE GE
G G
CLR CLR
Q2 Q6
LDCE LDCE
D3 Q3 D7 Q7
D Q D Q
GE GE
G G
CLR CLR
D[7:0] Q3 Q7

GE
G
CLR

X6385

Figure 7-14 LD8CE Implementation XC4000X, XC5200, SpartanXL, Virtex

7-12 Xilinx Development System

Design Elements (LDCP)

LDCP
Transparent Data Latch with Asynchronous Clear and Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE LDCP is a transparent data latch with data (D), asynchronous clear (CLR) and preset
(PRE) inputs. When CLR is High, it overrides the other inputs and resets the data (Q)
D LDCP output Low. When PRE is High and CLR is low, it presets the data (Q) output High. Q
Q reflects the data (D) input while the gate (G) input is High and CLR and PRE are Low.
G The data on the D input during the High-to-Low gate transition is stored in the latch.
The data on the Q output remains unchanged as long as G remains Low.
CLR
X8369
The latch is asynchronously cleared, output Low, when power is applied. Virtex simu-
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR PRE G D Q
1 X X X 0
0 1 X X 1
0 0 1 1 1
0 0 1 0 0
0 0 0 X No Chg
0 0 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Libraries Guide, Release M1.5 7-13

Libraries Guide, Release M1.5

LDCP_1
Transparent Data Latch with Asynchronous Clear and Preset and
Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR) and
preset (PRE) inputs. When CLR is High, it overrides the other inputs and resets the
D LDCP_1 data (Q) output Low. When PRE is High and CLR is low, it presets the data (Q) output
Q High. Q reflects the data (D) input while gate (G) input, CLR, and PRE are Low. The
G data on the D input during the Low-to-High gate transition is stored in the latch. The
data on the Q output remains unchanged as long as G remains High.
CLR
X8370
The latch is asynchronously cleared, output Low, when power is applied. Virtex simu-
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR PRE G D Q
1 X X X 0
0 1 X X 1
0 0 0 1 1
0 0 0 0 0
0 0 1 X No Chg
0 0 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

7-14 Xilinx Development System

Design Elements (LDCPE)

LDCPE
Transparent Data Latch with Asynchronous Clear and Preset and
Gate Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchro-
nous preset (PRE), and gate enable (GE). When CLR is High, it overrides the other
D LDCPE inputs and resets the data (Q) output Low. When PRE is High and CLR is low, it
GE Q presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input
G and gate enable (GE) are High and CLR and PRE are Low. The data on the D input
during the High-to-Low gate transition is stored in the latch. The data on the Q output
CLR remains unchanged as long as G or GE remain Low.
X8371
The latch is asynchronously cleared, output Low, when power is applied. Virtex simu-
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR PRE GE G D Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Chg
0 0 1 1 0 0
0 0 1 1 1 1
0 0 1 0 X No Chg
0 0 1 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Libraries Guide, Release M1.5 7-15

Libraries Guide, Release M1.5

LDCPE_1
Transparent Data Latch with Asynchronous Clear and Preset, Gate
Enable, and Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE LDCPE_1 is a transparent data latch with data (D), asynchronous clear (CLR), asyn-
chronous preset (PRE), and gate enable (GE). When CLR is High, it overrides the
D LDCPE_1 other inputs and resets the data (Q) output Low. When PRE is High and CLR is low, it
GE Q presets the data (Q) output High. Q reflects the data (D) input while gate enable (GE)
G is High and gate (G), CLR, and PRE are Low. The data on the D input during the Low-
to-High gate transition is stored in the latch. The data on the Q output remains
CLR unchanged as long as G is High or GE is Low.
X8372
The latch is asynchronously cleared, output Low, when power is applied. Virtex simu-
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

CLR PRE GE G D Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Chg
0 0 1 0 0 0
0 0 1 0 1 1
0 0 1 1 X No Chg
0 0 1 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

7-16 Xilinx Development System

Design Elements (LDE)

LDE
Transparent Data Latch with Gate Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LDE
LDE is a transparent data latch with data (D) and gate enable (GE) inputs. Output Q
D
reflects the data (D) while the gate (G) input and gate enable (GE) are High. The data
GE Q
on the D input during the High-to-Low gate transition is stored in the latch. The data
G
on the Q output remains unchanged as long as G or GE remain Low.
X8373 The latch is asynchronously cleared, output Low, when power is applied. Virtex simu-
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

GE G D Q
0 X X No Chg
1 1 0 0
1 1 1 1
1 0 X No Chg
1 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Libraries Guide, Release M1.5 7-17

Libraries Guide, Release M1.5

LDE_1
Transparent Data Latch with Gate Enable and Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LDE_1
LDE_1 is a transparent data latch with data (D) and gate enable (GE) inputs. Output Q
D
reflects the data (D) while the gate (G) input is Low and gate enable (GE) is High. The
GE Q
data on the D input during the Low-to-High gate transition is stored in the latch. The
G
data on the Q output remains unchanged as long as G is High or GE is Low.
X8374 The latch is asynchronously cleared, output Low, when power is applied. Virtex simu-
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

GE G D Q
0 X X No Chg
1 0 0 0
1 0 1 1
1 1 X No Chg
1 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

7-18 Xilinx Development System

Design Elements (LDP)

LDP
Transparent Data Latch with Asynchronous Preset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE LDP is a transparent data latch with asynchronous preset (PRE). When the PRE input
is High, it overrides the other inputs and resets the data (Q) output High. Q reflects
D LDP the data (D) input while gate (G) input is High and PRE is Low. The data on the D
Q input during the High-to-Low gate transition is stored in the latch. The data on the Q
G output remains unchanged as long as G remains Low.
The latch is asynchronously preset, output High, when power is applied. Virtex simu-
X8375
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

PRE G D Q
1 X X 1
0 1 0 0
0 1 1 1
0 0 X No Chg
0 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

Libraries Guide, Release M1.5 7-19

Libraries Guide, Release M1.5

LDP_1
Transparent Data Latch with Asynchronous Preset and Inverted
Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

PRE LDP_1 is a transparent data latch with asynchronous preset (PRE). When the PRE
input is High, it overrides the other inputs and resets the data (Q) output High. Q
D LDP_1 reflects the data (D) input while gate (G) input and PRE are Low. The data on the D
Q input during the Low-to-High gate transition is stored in the latch. The data on the Q
G output remains unchanged as long as G remains High.
The latch is asynchronously preset, output High, when power is applied. Virtex simu-
X8376
lates power-on when global set/reset (GSR) is active. GSR defaults to active-High but
can be inverted by adding an inverter in front of the GSR input of the
STARTUP_VIRTEX symbol.

Inputs Outputs

PRE G D Q
1 X X 1
0 0 0 0
0 0 1 1
0 1 X No Chg
0 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

7-20 Xilinx Development System

Design Elements (LDPE)

LDPE
Transparent Data Latch with Asynchronous Preset and Gate
Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Macro N/A N/A N/A Macro Primitive

PRE LDPE is a transparent data latch with asynchronous preset and gate enable. When the
asynchronous preset (PRE) is High, it overrides the other input and presets the data
D LDPE Q (Q) output High. Q reflects the data (D) input while the gate (G) input and gate enable
GE (GE) are High. If GE is low, data on D cannot be latched. The data on the D input
G during the High-to-Low gate transition is stored in the latch. The data on the Q output
remains unchanged as long as G or GE remains Low.
X6954
The latch is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000X, SpartanXL,
Virtex) default to active-High but can be inverted by adding an inverter in front of the
GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.

Inputs Outputs

PRE GE G D Q
1 X X X 1
0 0 X X No Chg
0 1 1 0 0
0 1 1 1 1
0 1 0 X No Chg
0 1 ↓ D d
d = state of input one setup time prior to High-to-Low gate transition

PRE LDPE_1

D PRE Q
D Q
GE
GE
G GB
G
INV
RLOC=R0C0 X7416

Figure 7-15 LDPE Implementation XC4000X, SpartanXL

Libraries Guide, Release M1.5 7-21

Libraries Guide, Release M1.5

LDPE_1
Transparent Data Latch with Asynchronous Preset, Gate Enable,
and Inverted Gate

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive Primitive

PRE LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and
inverted gated. When the asynchronous preset (PRE) is High, it overrides the other
D LDPE_1 Q input and presets the data (Q) output High. Q reflects the data (D) input while the
GE gate (G) input is low and gate enable (GE) is High.
G
If GE is low, data on D cannot be latched. The data on the D input during the Low-to-
X7573 High gate transition is stored in the latch. The data on the Q output remains
unchanged as long as G remains High or GE remains Low.
The latch is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000X, SpartanXL,
Virtex) default to active-High but can be inverted by adding an inverter in front of the
GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.

Inputs Outputs

PRE GE G D Q
1 X X X 1
0 0 X X No Chg
0 1 0 0 0
0 1 0 1 1
0 1 1 X No Chg
0 1 ↑ D d
d = state of input one setup time prior to Low-to-High gate transition

7-22 Xilinx Development System

Design Elements (LUT1, 2, 3, 4)

LUT1, 2, 3, 4
1-, 2-, 3-, 4-Bit Look-Up-Table with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LUT1 LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables
(LUTs) with general output (O).
O
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
IO
the number of inputs, must be attached to the LUT to specify its function.
X8358 LUT1 provides a look-up-table version of a buffer or inverter.
LUTs are the basic Virtex building blocks. Two LUTs are available in each CLB slice;
I1 LUT2 four LUTs are available in each CLB. The variants, “LUT1_D, LUT2_D, LUT3_D,
O LUT4_D” and “LUT1_L, LUT2_L, LUT3_L, LUT4_L”, provide additional types of
I0 outputs that can be used by different timing models for more accurate pre-layout
timing estimation.
X8379

I2 LUT3 Inputs Outputs

I1
I2 I1 I0 O
I0 O
0 0 0 INIT[0]
X8382
0 0 1 INIT[1]
0 1 0 INIT[2]
I3 LUT4
I2
0 1 1 INIT[3]
O
I1 1 0 0 INIT[4]
I0
1 0 1 INIT[5]
X8385 1 1 0 INIT[6]
1 1 1 INIT[7]
INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute

LUT3 Function Table

Libraries Guide, Release M1.5 7-23

Libraries Guide, Release M1.5

LUT1_D, LUT2_D, LUT3_D, LUT4_D

1-, 2-, 3-, 4-Bit Look-Up-Table with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LUT1_D LO
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit look-
up-tables (LUTs) with two functionally identical outputs, O and LO. The O output is a
I0 O general interconnect. The LO output is used to connect to another output within the
same CLB slice and to the fast connect buffer.
X8377
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
the number of inputs, must be attached to the LUT to specify its function.
I1 LUT2_D LO
LUT1_D provides a look-up-table version of a buffer or inverter.
I0 O See also “LUT1, 2, 3, 4” and “LUT1_L, LUT2_L, LUT3_L, LUT4_L”.

X8380

Inputs Outputs
I2 LUT3_D LO
I1 I2 I1 I0 O LO
I0 O
0 0 0 INIT[0] INIT[0]
X8383
0 0 1 INIT[1] INIT[1]
LUT4_D 0 1 0 INIT[2] INIT[2]
I3
I2 LO 0 1 1 INIT[3] INIT[3]
I1 O
1 0 0 INIT[4] INIT[4]
I0
1 0 1 INIT[5] INIT[5]
X8386 1 1 0 INIT[6] INIT[6]
1 1 1 INIT[7] INIT[7]
INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute

LUT3_D Function Table

7-24 Xilinx Development System

Design Elements (LUT1_L, LUT2_L, LUT3_L, LUT4_L)

LUT1_L, LUT2_L, LUT3_L, LUT4_L

1-, 2-, 3-, 4-Bit Look-Up-Table with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LUT1_L LO
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-up-
tables (LUTs) with a local output (LO) that is used to connect to another output within
I0 the same CLB slice and to the fast connect buffer.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
X8378
the number of inputs, must be attached to the LUT to specify its function.

LUT2_L LUT1_L provides a look-up-table version of a buffer or inverter.

I1 LO

LUT3_L Function Table

Libraries Guide, Release M1.5 7-25

Libraries Guide, Release M1.5

MD0
Mode 0, Input Pad Used for Readback Trigger Input

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A N/A N/A N/A

The MD0 input pad is connected to the Mode 0 (M0) input pin, which is used to deter-
MD0 mine the configuration mode on XC4000 and XC5200 devices. Following configura-
X3896 tion, MD0 can be used as an input pad, but it must be connected through an IBUF to
the user circuit. However, the user input signal must not interfere with the device
configuration. XC5200 devices allow an MD0 pad to be used as an output pad;
XC4000 devices do not. The IOB associated with the MD0 pad has no flip-flop or latch.
This pad is usually connected (automatically) to the RTRIG input of the READBACK
function.

7-26 Xilinx Development System

Design Elements (MD1)

MD1
Mode 1, Output Pad Used for Readback Data Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A N/A N/A N/A

The MD1 output pad is connected to the Mode 1 (M1) output pin, which is used to
MD1 determine the configuration mode on XC4000 and XC5200 devices. Following config-
X3898 uration, MD1 can be used as a 3-state or simple output pad, but it must be connected
through an OBUF or an OBUFT to the user circuit. However, the user output signal
must not interfere with the device configuration. XC5200 devices allow an MD1 pad
to be used as an input pad; XC4000 devices do not. The IOB associated with an MD1
pad has no flip-flop or latch. This pad is usually connected to the DATA output of the
READBACK function, and the output-enable input of the 3-state OBUFT is connected
to the RIP output of the READBACK function.

Libraries Guide, Release M1.5 7-27

Libraries Guide, Release M1.5

MD2
Mode 2, Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A N/A N/A N/A

The MD2 input pad is connected to the Mode 2 (M2) input pin, which is used to deter-
MD2
mine the configuration mode on XC4000 and XC5200 devices. Following configura-
X3900
tion, MD2 can be used as an input pad, but it must be connected through an IBUF to
the user circuit. However, the user input signal must not interfere with the device
configuration. XC5200 devices allow an MD2 pad to be used as an output pad;
XC4000 devices do not. The IOB associated with it has no flip-flop or latch.

7-28 Xilinx Development System

Design Elements (M2_1)

M2_1
2-to-1 Multiplexer

Macro Macro Macro Macro Macro Macro Macro Macro

D0 M2_1E is a 2-to-1 multiplexer with enable. When the enable input (E) is High, the
O
D1 M2_1E chooses one data bit from two sources (D1 or D0) under the control of select
S0 input (S0). When E is High, the output (O) reflects the state of the selected input.
E When Low, S0 selects D0 and when High, S0 selects D1. When E is Low, the output is
X4029 Low.

Inputs Outputs

E S0 D1 D0 O
0 X X X 0
1 0 X 1 1
1 0 X 0 0
1 1 1 X 1
1 1 0 X 0

D0
E M0
S0
AND3B1
O

OR2

M1
D1
AND3 X7858

Figure 7-19 M2_1E Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

7-32 Xilinx Development System

Design Elements (M4_1E)

M4_1E
4-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

D0 M4_1E is an 4-to-1 multiplexer with enable. When the enable input (E) is High, the
D1
O
M4_1E multiplexer chooses one data bit from four sources (D3, D2, D1, or D0) under
D2
the control of the select inputs (S1 – S0). The output (O) reflects the state of the
D3
S0 selected input as shown in the truth table. When E is Low, the output is Low.
S1
E
X4030
Inputs Outputs

E S1 S0 D0 D1 D2 D3 O
0 X X X X X X 0
1 0 0 D0 X X X D0
1 0 1 X D1 X X D1
1 1 0 X X D2 X D2
1 1 1 X X X D3 D3

M2_1E
D0 D0
O
D1 D1
S0 M2_1
M01 D0
E M01 O O
M23 D1
M2_1E S0 0
D2 D0
O
D3 D1
S0 S0
E E M23
S1
X7859

Figure 7-20 M4_1E Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

M2_1E
D0 D0
O
D1 D1
S0 MUXF5
M01 D0
E M01 O O
M23 D1
M2_1E S0 0
D2 D0
O
D3 D1
S0 S0
E E M23
S1
X8715

Figure 7-21 M4_1E Implementation Virtex

Libraries Guide, Release M1.5 7-33

Libraries Guide, Release M1.5

M8_1E
8-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

D0 M8_1E is an 8-to-1 multiplexer with enable. When the enable input (E) is High, the
D1 M8_1E multiplexer chooses one data bit from eight sources (D7 – D0) under the
D2
D3
control of the select inputs (S2 – S0). The output (O) reflects the state of the selected
D4
O input as shown in the truth table. When E is Low, the output is Low.
D5
D6
D7
S0 Inputs Outputs
S1
S2
E S2 S1 S0 D7 – D0 O
E
X4031
0 X X X X 0
1 0 0 0 D0 D0
1 0 0 1 D1 D1
1 0 1 0 D2 D2
1 0 1 1 D3 D3
1 1 0 0 D4 D4
1 1 0 1 D5 D5
1 1 1 0 D6 D6
1 1 1 1 D7 D7
Dn represents signal on the Dn input; all other data inputs are don’t-cares (X).

M2_1
D0 D0
O
D1 D1
M01
S0
M2_1
M01 D0
O
M23 D1
M03
S0
M2_1
D2 D0
O
D3 D1
M23
S0
M2_1E
M03 D0
O O
M47 D1
O
S0
M2_1 E
D4 D0
O
D5 D1

S0
M45
M2_1
M45 D0
O
M67 D1
M47
S0
M2_1
D6 D0
O
D7 D1
M67
S0 S0
S1
S2
E
X7640

Figure 7-22 M8_1E Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

7-34 Xilinx Development System

Design Elements (M8_1E)

M2_1E
D0 D0
O
D1 D1
S0 MUXF5_L
E M01 I0
M01 LO
M23 I1
M2_1E S M03
D2 D0
O
D3 D1
S0 MUXF6
M03 I0
E M23 O O
M47 I1 O
M2_1E S
D4 D0
O
D5 D1
S0 MUXF5_L
M45 I0
E M45 LO
M67 I1
M2_1E S M47
D6 D0
O
D7 D1
S0
S0 E M67

S1
S2
E
X8716

Figure 7-23 M8_1E Implementation Virtex

Libraries Guide, Release M1.5 7-35

Libraries Guide, Release M1.5

M16_1E
16-to-1 Multiplexer with Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

D0
M16_1E is a 16-to-1 multiplexer with enable. When the enable input (E) is High, the
D1 M16_1E multiplexer chooses one data bit from 16 sources (D15 – D0) under the
D2
control of the select inputs (S3 – S0). The output (O) reflects the state of the selected
D3
D4
input as shown in the truth table. When E is Low, the output is Low.
D5
D6
D7
O
D8 Inputs Outputs
D9
D10 E S3 S2 S1 S0 D15 – D0 O
D11
D12 0 X X X X X 0
D13
D14 1 0 0 0 0 D0 D0
D15
S0
1 0 0 0 1 D1 D1
S1
1 0 0 1 0 D2 D2
S2
S3 1 0 0 1 1 D3 D3
E
X4032
. . . . . . .
. . . . . . .
. . . . . . .
1 1 1 0 0 D12 D12
1 1 1 0 1 D13 D13
1 1 1 1 0 D14 D14
1 1 1 1 1 D15 D15
Dn represents signal on the Dn input; all other data inputs are don’t-cares (X).

7-36 Xilinx Development System

Design Elements (MULT_AND)

MULT_AND
Fast Multiplier AND

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

MULT_AND is an AND component used exclusively for building fast and smaller
I1
I0
LO multipliers. The I1 and I0 inputs must be connected to the I1 and I0 inputs of the asso-
X8405
ciated LUT. The LO output must be connected to the DI input of the associated
MUXCY, MUXCY_D, or MUXCY_L. See the “Example Multiplier Using
MULT_AND” figure.

Inputs Output

I1 I0 LO
0 0 0
0 1 0
1 0 0
1 1 1

LO MUXCY_L
S
0 1
DI CI
LUT4

B1 I3
A1 I2
LI SUM1
B0 I1 O O
CI
A0 IO
XORCY

I1
LO
I0
MULT_AND

CO
X8733

Figure 7-24 Example Multiplier Using MULT_AND

Libraries Guide, Release M1.5 7-37

Libraries Guide, Release M1.5

MUXCY
2-to-1 Multiplexer for Carry Logic with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

I0 MUXF5 provides a multiplexer function in one half of a Virtex CLB for creating a
O function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated
I1
lookup tables. The local outputs (LO) from the two lookup tables are connected to the
S
X8431 I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. When
Low, S selects I0. When High, S selects I1.
The variants, “MUXF5_D” and “MUXF5_L”, provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing estima-
tion.

Inputs Outputs

S I0 I1 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Libraries Guide, Release M1.5 7-41

Libraries Guide, Release M1.5

MUXF5_D
2-to-1 Lookup Table Multiplexer with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

I0
LO
MUXF5_D provides a multiplexer function in one half of a Virtex CLB for creating a
O function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated
I1
lookup tables. The local outputs (LO) from the two lookup tables are connected to the
S
X8432 I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. When
Low, S selects I0. When High, S selects I1.
Outputs O and LO are functionally identical. The O output is a general interconnect.
The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF5” and “MUXF5_L”.

Inputs Outputs

S I0 I1 O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0

7-42 Xilinx Development System

Design Elements (MUXF5_L)

MUXF5_L
2-to-1 Lookup Table Multiplexer with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

I0
LO
MUXF5_L provides a multiplexer function in one half of a Virtex CLB for creating a
function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated
I1
lookup tables. The local outputs (LO) from the two lookup tables are connected to the
S
X8433 I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. When
Low, S selects I0. When High, S selects I1.
The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF5” and “MUXF5_L”.

Inputs Output

S I0 I1 LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

Libraries Guide, Release M1.5 7-43

Libraries Guide, Release M1.5

MUXF6
2-to-1 Lookup Table Multiplexer with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

I0 MUXF6 provides a multiplexer function in a full Virtex CLB for creating a function-of-
O 6 lookup table or an 8-to-1 multiplexer in combination with the associated four
I1
lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the
S
X8434 CLB are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from
any internal net. When Low, S selects I0. When High, S selects I1.
The variants, “MUXF6_D” and “MUXF6_L”, provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing estima-
tion.

Inputs Outputs

S I0 I1 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

7-44 Xilinx Development System

Design Elements (MUXF6_D)

MUXF6_D
2-to-1 Lookup Table Multiplexer with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

I0
LO
MUXF6_D provides a multiplexer function in a full Virtex CLB for creating a function-
O of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four
I1
lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the
S
X8435 CLB are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from
any internal net. When Low, S selects I0. When High, S selects I1.
Outputs O and LO are functionally identical. The O output is a general interconnect.
The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF6” and “MUXF6_L”.

Inputs Outputs

S I0 I1 O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0

Libraries Guide, Release M1.5 7-45

Libraries Guide, Release M1.5

MUXF6_L
2-to-1 Lookup Table Multiplexer with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

I0
LO
MUXF6_L provides a multiplexer function in a full Virtex CLB for creating a function-
of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four
I1
lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the
S
X8436 CLB are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from
any internal net. When Low, S selects I0. When High, S selects I1.
The LO output is used to connect to other inputs within the same CLB slice.
See also “MUXF6” and “MUXF6_D”.

Inputs Output

S I0 I1 LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0

7-46 Xilinx Development System

Design Elements (NAND2-9)

NAND2-9
2- to 9-Input NAND Gates with Inverted and Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

NAND2, Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
NAND2B1,
NAND2B2,
NAND3,
NAND3B1,
NAND3B2,
NAND3B3,
NAND4,
NAND4B1,
NAND4B2,
NAND4B3,
NAND4B4
NAND5, Primitive Primitive Primitive Macro Primitive Primitive Primitive Primitive
NAND5B1,
NAND5B2,
NAND5B3,
NAND5B4,
NAND5B5
NAND6, Macro Macro Macro Macro Primitive Macro Macro Macro
NAND7,
NAND8,
NAND9

Libraries Guide, Release M1.5 7-47

Libraries Guide, Release M1.5

NAND2 NAND3 NAND4 NAND5 NAND6

NAND2B1 NAND3B1 NAND4B1 NAND5B1 NAND7

NAND2B2 NAND3B2 NAND4B2 NAND5B2 NAND8

NAND3B3 NAND4B3 NAND5B3 NAND9

NAND4B4 NAND5B4

X8031 NAND5B5

Figure 7-25 NAND Gate Representations

The NAND function is performed in the Configurable Logic Block (CLB) function
generators for XC3000, XC4000, XC5200, and Spartans. NAND gates of up to five
inputs are available in any combination of inverting and non-inverting inputs. NAND
gates of six to nine inputs are available with only non-inverting inputs. To invert
inputs, use external inverters. Since each input uses a CLB resource, replace gates
with unused inputs with gates having the necessary number of inputs.
Refer to the “NAND12, 16” section for information on additional NAND functions for
the XC5200 and Virtex.

7-48 Xilinx Development System

Design Elements (NAND2-9)

I4
I3 I35
I2
I1 AND3 O
I0
NAND3

X8152

Figure 7-26 NAND5 Implementation XC5200

I7
I6
I47
I5
I4
I3 AND4
I2 O
I1
I0
NAND5

X6524

Figure 7-27 NAND8 Implementation XC3000

I7
I6
I47
I5
I4
AND4
O
I3
I2 I13
NAND3
I1
AND3
I0

X6523

Figure 7-28 NAND8 Implementation XC4000, Spartans

FMAP
AND4 CO I7
I7 I4
CY_MUX
I6
I6 I3 S1
S1 S O
I5 0 1 I5
I2
VCC
I4 DI CI I4
I1

FMAP
I3
AND4 CO
CY_MUX I3
I4
I2 I2
S0 S I3
0 1 S0
I1 I1 O
DI CI I2
I0 I0
I1

CIN
CY_INIT
COUT
INIT

GND

X6447

Figure 7-29 NAND8 Implementation XC5200

Libraries Guide, Release M1.5 7-49

Libraries Guide, Release M1.5

FMAP
I4
I3 O
S1 O
I2
S0
I1
I7
I6 RLOC=R0C0.S0
S1
I5
I4
AND4 FMAP
I7
I4
I6
O I3 S1
I5 O
I2
I4
NAND2 I1
I3
RLOC=R0C0.S1
I2
S0
I1
I0 FMAP
AND4 I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8701 RLOC=R0C0.S1

Figure 7-30 NAND8 Implementation Virtex

7-50 Xilinx Development System

Design Elements (NAND12, 16)

NAND12, 16
12- and 16-Input NAND Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Macro N/A N/A N/A Macro

The NAND function is performed in the Configurable Logic Block (CLB) function
generators for XC5200 and Virtex. The 12- and 16-input NAND functions are available
only with non-inverting inputs. To invert some or all inputs, use external inverters.
Refer to the “NAND2-9” section for more information on NAND functions.

FMAP
AND4 CO I11
NAND12 I11 I4
CY_MUX
I10 I10
X8201 RLOC=R0C0.LC3 I3 S2
S2 S O
I9 0 1 I9
I2
I8 VCC DI CI I8
I1

RLOC=R0C0.LC3
C1

FMAP

I7 AND4 CO I7
CY_MUX I4
I6 I6
RLOC=R0C0.LC2 I3 S1
S1 S O
I5 0 1 I5
I2
I4 DI CI I4
I1

RLOC=R0C0.LC2
C0
NAND16
X8202 FMAP
I3 AND4
CY_MUX CO I3
I4
I2 RLOC=R0C0.LC1
S0 S I2
I3 S0
I1 0 1 O
I1
DI CI I2
I0
I0
I1

RLOC=R0C0.LC1
CY_INIT CIN

COUT
INIT

RLOC=R0C0.LC0

X6449
GND

Figure 7-31 NAND12 Implementation XC5200

Libraries Guide, Release M1.5 7-51

Libraries Guide, Release M1.5

FMAP
I4
S2
I3 O
S1 O
I2
S0
I1

RLOC=R0C0.S0

I11
I10 FMAP
S2 I11
I9 I4
I10
I8 I3 S2
I9 O
AND4 I2
I8
I1
I7
I6 RLOC=R0C0.S0
S1 O
I5
I4
NAND3 FMAP
AND4
I7
I4
I3 I6
I3 S1
I2 I5 O
S0 I2
I1 I4
I1
I0
AND4 RLOC=R0C0.S1

FMAP
I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8704 RLOC=R0C0.S1

Figure 7-32 NAND12 Implementation Virtex

7-52 Xilinx Development System

Design Elements (NAND12, 16)

AND4 CO
I15
CY_MUX
I14 RLOC=R0C0.LC3 FMAP
S3 S
I13 0 1 I15
I4
VCC DI CI
I12 I14
I3 S3
I13 O
I2
C1 I12
I1

RLOC=R0C0.LC3
AND4 CO
I11
CY_MUX
I10 RLOC=R0C0.LC2 FMAP
S2 S
I9 0 1 I11
I4
I8 DI CI
I10
I3 S2
I9 O
I2
C1 I8
I1

RLOC=R0C0.LC2
I7
AND4 CO
CY_MUX
I6 RLOC=R0C0.LC1 FMAP
S1 S
I5 0 1 I7
I4
I4 DI CI
I6
I3 S1
I5 O
I2
C0 I4
I1

RLOC=R0C0.LC1
AND4 CO
I3
CY_MUX
I2 RLOC=R0C0.LC0
S0 S FMAP
I1 0 1
DI CI I3
I0 I4
I2
I3 S0
I1 O
I2
CIN I0
I1
CY_INIT
COUT RLOC=R0C0.LC0

INIT
RLOC=R1C0.LC3

X6448
GND

Figure 7-33 NAND16 Implementation XC5200

Libraries Guide, Release M1.5 7-53

Libraries Guide, Release M1.5

FMAP

I15
I15 O I4
MUXCY I14
I14 RLOC=R0C0.S1 I3 S3
S3 S I13 O
I13 0 1 I2
VCC DI CI I12
I12 I1
AND4
RLOC=R0C0.S1
C2

FMAP

I11
I11 LO I4
MUXCY_L I10
I10 RLOC=R0C0.S1 I3 S2
S2 S I9 O
I9 0 1 I2
I8
I8 DI CI I1
AND4
RLOC=R0C0.S1
C1

FMAP

I7
I7 LO I4
MUXCY_L I6
I6 RLOC=R1C0.S1 I3 S1
S1 S I5 O
I5 0 1 I2
I4
I4 DI CI I1
AND4
RLOC=R1C0.S1
C0

FMAP

I3 LO I3
MUXCY_L I4
I2 RLOC=R1C0.S1 I2
S0 S I3 S0
I1 0 1 I1 O
I2
I0 DI CI I0
I1
AND4

RLOC=R1C0.S1

CIN

X8709

GND

Figure 7-34 NAND16 Implementation Virtex

7-54 Xilinx Development System

Design Elements (NOR2-9)

NOR2-9
2- to 9-Input NOR Gates with Inverted and Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

NOR2, Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
NOR2B1,
NOR2B2,
NOR3,
NOR3B1,
NOR3B2,
NOR3B3,
NOR4,
NOR4B1,
NOR4B2,
NOR4B3,
NOR4B4
NOR5, Primitive Primitive Primitive Macro Primitive Primitive Primitive Primitive
NOR5B1,
NOR5B2,
NOR5B3,
NOR5B4,
NOR5B5
NOR6, Macro Macro Macro Macro Primitive Macro Macro Macro
NOR7,
NOR8,
NOR9

Libraries Guide, Release M1.5 7-55

Libraries Guide, Release M1.5

NOR2 NOR3 NOR4 NOR5 NOR6

NOR2B1 NOR3B1 NOR4B1 NOR5B1

NOR7

NOR2B2 NOR3B2 NOR4B2 NOR5B2

NOR3B3 NOR4B3 NOR5B3 NOR8

NOR4B4 NOR5B4

NOR9

X8033 NOR5B5

Figure 7-35 NOR Gate Representations

The NOR function is performed in the Configurable Logic Block (CLB) function
generators for XC3000, XC4000, XC5200, and Spartans. NOR gates of up to five inputs
are available in any combination of inverting and non-inverting inputs. NOR gates of
six to nine inputs are available with only non-inverting inputs. To invert some or all
inputs, use external inverters. Since each input uses a CLB resource, replace gates
with unused inputs with gates having the necessary number of inputs.
Refer to the “NOR12, 16” section for information on additional NOR functions for the
XC5200 and Virtex.

7-56 Xilinx Development System

Design Elements (NOR2-9)

I4
I3 I35
I2
OR3
I1 O
I0
NOR3

X8153

Figure 7-36 NOR5 Implementation XC5200

I6
I47
I5

I4
OR4
I3

I2 O

I0 NOR5

X6521

Figure 7-37 NOR8 Implementation XC3000

I6
I47
I5

I4
OR4 O
I3

I2 I13
NOR3
I1
OR3
I0

X6520

Figure 7-38 NOR8 Implementation XC4000, Spartans

FMAP
I7 CY_MUX CO I7
I4
I6 I6
S1 S I3 S1
I5 0 1 O
I5
I2
I4 DI CI
I4
I1
NOR4

FMAP

I3 CY_MUX CO I3
I4
I2 I2
S0 S I3 S0
I1 0 1 I1 O
I2
I0 DI CI I0
I1
NOR4

GND CIN

VCC CY_INIT

COUT
INIT

X6446

Figure 7-39 NOR8 Implementation XC5200

Libraries Guide, Release M1.5 7-57

Libraries Guide, Release M1.5

FMAP
I4
I3 O
S1 O
I2
S0
I1
I7
I6 RLOC=R0C0.S0
S1
I5
I4
FMAP
OR4
I7
I4
I6
O I3 S1
I5 O
I2
I4
NOR2 I1
I3
RLOC=R0C0.S1
I2
S0
I1
I0 FMAP
OR4 I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8700 RLOC=R0C0.S1

Figure 7-40 NOR8 Implementation Virtex

7-58 Xilinx Development System

Design Elements (NOR12, 16)

NOR12, 16
12- and 16-Input NOR Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Macro N/A N/A N/A Macro

The 12- and 16-input NOR functions are available only with non-inverting inputs. To
invert some or all inputs, use external inverters.
Refer to the “NOR2-9” section for more information on NOR functions.
O

FMAP

NOR12 I15 CY_MUX CO I15

I4
I14 I14
X8196 S3 S RLOC=R0C0.LC3 I3 S3
I13 0 1 I13 O
I2
I12 DI CI I12
NOR4 I1

RLOC=R0C0.LC3
C2
FMAP

I11 CY_MUX CO I11

I4
I10 RLOC=R0C0.LC2 I10
S2 S I3 S2
I9 0 1 I9 O
I2
I8 DI CI I8
NOR4 I1

RLOC=R0C0.LC2
CI
FMAP

I7 CY_MUX CO I7
NOR16 I4
I6 I6
S1 S RLOC=R0C0.LC1 I3 S1
X8197 I5 0 1 I5 O
I2
I4 DI CI I4
NOR4 I1

RLOC=R0C0.LC1
C0
FMAP

I3 I3
CY_MUX CO I4
I2 I2
S0 S RLOC=R0C0.LC0 I3 S0
I1 0 1 I1 O
I2
I0 DI CI I0
NOR4 I1

RLOC=R0C0.LC0
CIN

GND
VCC

COUT RLOC=R1C0.LC3
INIT
CY_INIT X6536

Figure 7-41 NOR16 Implementation XC5200

Libraries Guide, Release M1.5 7-59

Libraries Guide, Release M1.5

FMAP

I15
I15 O I4
MUXCY I14
I14 RLOC=R0C0.S1 I3 S3
S3 S I13 O
I13 0 1 I2
DI CI I12
I12 I1
NOR4
RLOC=R0C0.S1
C2

FMAP

I11
I11 LO I4
MUXCY_L I10
I10 RLOC=R0C0.S1 I3 S2
S2 S I9 O
I9 0 1 I2
I8
I8 DI CI I1
NOR4
RLOC=R0C0.S1
C1

FMAP

I7
I7 LO I4
MUXCY_L I6
I6 RLOC=R1C0.S1 I3 S1
S1 S I5 O
I5 0 1 I2
I4
I4 DI CI I1
NOR4
RLOC=R1C0.S1
C0

FMAP

I3 LO I3
MUXCY_L I4
I2 RLOC=R1C0.S1 I2
S0 S I3 S0
I1 0 1 I1 O
I2
I0 DI CI I0
I1
NOR4

RLOC=R1C0.S1

CIN

GND
VCC

X8707

Figure 7-42 NOR16 Implementation Virtex

7-60 Xilinx Development System

Chapter 8

Design Elements (OAND2 to OXOR2)

Libraries Guide, Release M1.5 — 8-1

Libraries Guide, Release M1.5

OAND2
2-Input AND Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

F OAND2 is a 2-input AND gate that is implemented in the output multiplexer of the
O
I0 XC4000X IOB. The F pin is faster than I0. Input pins can be inverted even though there
is no library component showing inverted inputs. The mapper will automatically
X6955
bring any inverted input pins into the IOB.

8-2 Xilinx Development System

Design Elements (OBUF, 4, 8, 16)

OBUF, 4, 8, 16
Single- and Multiple-Output Buffers

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OBUF Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
OBUF4, Macro Macro Macro Macro Macro Macro Macro Macro
OBUF8,
OBUF16

OBUF
OBUF, OBUF4, OBUF8, and OBUF16 are single and multiple output buffers. An
OBUF isolates the internal circuit and provides drive current for signals leaving a
chip. OBUFs exist in input/output blocks (IOB). The output (O) of an OBUF is
X3785 connected to an OPAD or an IOPAD.
For XC9000 CPLDs, if a high impedance (Z) signal from an on-chip 3-state buffer (like
BUFE) is applied to the input of an OBUF, it is propagated to the CPLD device output
OBUF4
pin.
For Virtex, refer to the “OBUF_selectIO” section for information on OBUF variants
with selectable I/O interfaces. The I/O interface standard used by OBUF, 4, 8, and 16
is LVTTL. Also, Virtex OBUF, 4, 8, and 16 have selectable drive and slew rates using
the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and
X3792
SLOW slew.
O[7:0]
OBUF8
IO O0

OBUF
I1 O1
X3804 OBUF
I2 O2

OBUF
OBUF16 I3 O3

OBUF
I4 O4

OBUF
X3816 I5 O5

OBUF
I6 O6

OBUF
I7 O7
I[7:0] OBUF

X7654

Figure 8-1 OBUF8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 8-3

Libraries Guide, Release M1.5

OBUF_selectIO
Single Output Buffer with Selectable I/O Interface

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

OBUF and its variants (listed below) are single output buffers whose I/O interface
corresponds to a specific I/O standard. The name extensions (LVCMOS2, PCI33_3,
PCI33_5, etc.) specify the standard. The S, F, and 2, 4, 6, 8, 12, 16, 24 extensions specify
X3830
the slew rate (SLOW or FAST) and the drive power (2, 4, 6, 8, 12, 16, 24 mA) for the
LVTTL standard variants. For example, OBUF_F_12 is a single output buffer that uses
the LVTTL I/O-signaling standard with a FAST slew and 12mA of drive power.
OBUF has selectable drive and slew rates using the DRIVE and SLOW or FAST
constraints. The defaults are DRIVE=12 mA and SLOW slew.
An OBUF isolates the internal circuit and provides drive current for signals leaving a
chip. OBUFs exist in input/output blocks (IOB). The output (O) of an OBUF is
connected to an OPAD or an IOPAD.
The hardware implementation of the I/O standard requires that you follow a set of
usage rules for the SelectI/O buffer components. Refer to the “SelectI/O Usage
Rules” section under the IBUF_selectIO section for information on using these compo-
nents.

Component I/O Standard VCCO

OBUF LVTTL 3.3
OBUF_S_2 LVTTL 3.3
OBUF_S_4 LVTTL 3.3
OBUF_S_6 LVTTL 3.3
OBUF_S_8 LVTTL 3.3
OBUF_S_12 LVTTL 3.3
OBUF_S_16 LVTTL 3.3
OBUF_S_24 LVTTL 3.3
OBUF_F_2 LVTTL 3.3
OBUF_F_4 LVTTL 3.3
OBUF_F_6 LVTTL 3.3
OBUF_F_8 LVTTL 3.3
OBUF_F_12 LVTTL 3.3
OBUF_F_16 LVTTL 3.3
OBUF_F_24 LVTTL 3.3
OBUF_LVCMOS2 LVCMOS2 2.5
OBUF_PCI33_3 PCI33_3 3.3
OBUF_PCI33_5 PCI33_5 3.3

8-4 Xilinx Development System

Design Elements (OBUF_selectIO)

Component I/O Standard VCCO

OBUF_PCI66_3 PCI66_3 3.3
OBUF_GTL GTL N/A
OBUF_GTLP GTL+ N/A
OBUF_HSTL_I HSTL_I 1.5
OBUF_HSTL_III HSTL_III 1.5
OBUF_HSTL_IV HSTL_IV 1.5
OBUF_SSTL2_I SSTL2_I 2.5
OBUF_SSTL2_II SSTL2_II 2.5
OBUF_SSTL3_I SSTL3_I 3.3
OBUF_SSTL3_II SSTL3_II 3.3
OBUF_CTT CTT 3.3
OBUF_AGP AGP 3.3

Libraries Guide, Release M1.5 8-5

Libraries Guide, Release M1.5

OBUFE, 4, 8, 16
3-State Output Buffers with Active-High Output Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OBUFE Macro Macro Macro Macro Primitive Macro Macro Macro
OBUFE4, Macro Macro Macro Macro Macro Macro Macro Macro
OBUFE8,
OBUFE16

OBUFE OBUFE, OBUFE4, OBUFE8, and OBUFE16 are 3-state buffers with inputs I, I3 – I0, I7 –
E I0, and I15-I0, respectively; outputs O, O3 – O0, O7 – O0, and O15-O0, respectively;
and active-High output enable (E). When E is High, data on the inputs of the buffers is
X3787
transferred to the corresponding outputs. When E is Low, the output is High imped-
ance (off or Z state). An OBUFE isolates the internal circuit and provides drive current
for signals leaving a chip. An OBUFE output is connected to an OPAD or an IOPAD.
OBUFE4 An OBUFE input is connected to the internal circuit.
E

Inputs Outputs

E I O
0 X Z
X3794
1 1 1
1 0 0
OBUFE8
E E T T

INV
I O

OBUFT
X3806 X7860

Figure 8-2 OBUFE Implementation XC3000, XC4000, XC5200, Spartans, Virtex

OBUFE16 O[7:0]
E
E IO O0

E OBUFE
I1 O1

E OBUFE

X3818 I2 O2

E OBUFE
I3 O3

E OBUFE
I4 O4

E OBUFE
I5 O5

E OBUFE
I6 O6

E OBUFE
I7 O7

I[7:0] OBUFE

E X7649

Figure 8-3 OBUFE8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

8-6 Xilinx Development System

Design Elements (OBUFT, 4, 8, 16)

OBUFT, 4, 8, 16
Single and Multiple 3-State Output Buffers with Active-Low Output
Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OBUFT Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
OBUFT4, Macro Macro Macro Macro Macro Macro Macro Macro
OBUFT8,
OBUFT16

OBUFT OBUFT, OBUFT4, OBUFT8, and OBUFT16 are single and multiple 3-state output
T
buffers with inputs I, I3 – I0, I7 – I0, I15 – I0, outputs O, O3 – O0, O7 – O0, O15 – O0,
and active-Low output enables (T). When T is Low, data on the inputs of the buffers is
transferred to the corresponding outputs. When T is High, the output is high imped-
X3786 ance (off or Z state). OBUFTs isolate the internal circuit and provide extra drive
current for signals leaving a chip. An OBUFT output is connected to an OPAD or an
IOPAD.
OBUFT4
T For Virtex, refer to the “OBUFT_selectIO” section for information on OBUFT variants
with selectable I/O interfaces. OBUFT, 4, 8, and 16 use the LVTTL standard. Also,
Virtex OBUFT, 4, 8, and 16 have selectable drive and slew rates using the DRIVE and
SLOW or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

Inputs Outputs
X3793
T I O
1 X Z
OBUFT8
T
0 1 1

I O[7:0]
0 0 0
O[7:0]
X3805 T
IO O0

T OBUFT

OBUFT16 I1 O1

T OBUFT
T
I2 O2

I[15:0] O[15:0] T OBUFT

I3 O3

T OBUFT
X3817
I4 O4

T OBUFT
I5 O5

T OBUFT
I6 O6

T OBUFT
I7 O7

I[7:0] OBUFT

T
X7651

Figure 8-4 OBUFT8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 8-7

Libraries Guide, Release M1.5

OBUFT_selectIO
Single 3-State Output Buffer with Active-Low Output Enable and
Selectable I/O Interface

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

OBUFT and its variants (listed below) are single 3-state output buffers with active-
T
Low output Enable whose I/O interface corresponds to a specific I/O standard. The
name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. The S, F,
X8720 and 2, 4, 6, 8, 12, 16, 24 extensions specify the slew rate (SLOW or FAST) and the drive
power (2, 4, 6, 8, 12, 16, 24 mA) for the LVTTL standard. For example, OBUFT_S_4 is a
3-state output buffer with active-low output enable that uses the LVTTL I/O signaling
standard with a SLOW slew and 4mA of drive power.
OBUFT has selectable drive and slew rates using the DRIVE and FAST or SLOW
constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the input of the buffer is transferred to the output. When T is
High, the output is high impedance (off or Z state). OBUFTs isolate the internal circuit
and provide extra drive current for signals leaving a chip. An OBUFT output is
connected to an OPAD or an IOPAD.
The hardware implementation of the I/O standards requires that you follow a set of
usage rules for the SelectI/O buffer components. Refer to the “SelectI/O Usage
Rules” section under the IBUF_selectIO section for information on using these compo-
nents.

Inputs Outputs
T I O
1 X Z
0 1 1
0 0 0

Component I/O Standard VCCO

OBUFT LVTTL 3.3
OBUFT_S_2 LVTTL 3.3
OBUFT_S_4 LVTTL 3.3
OBUFT_S_6 LVTTL 3.3
OBUFT_S_8 LVTTL 3.3
OBUFT_S_12 LVTTL 3.3
OBUFT_S_16 LVTTL 3.3
OBUFT_S_24 LVTTL 3.3

8-8 Xilinx Development System

Design Elements (OBUFT_selectIO)

Component I/O Standard VCCO

OBUFT_F_2 LVTTL 3.3
OBUFT_F_4 LVTTL 3.3
OBUFT_F_6 LVTTL 3.3
OBUFT_F_8 LVTTL 3.3
OBUFT_F_12 LVTTL 3.3
OBUFT_F_16 LVTTL 3.3
OBUFT_F_24 LVTTL 3.3
OBUFT_LVCMOS2 LVCMOS2 2.5
OBUFT_PCI33_3 PCI33_3 3.3
OBUFT_PCI33_5 PCI33_5 3.3
OBUFT_PCI66_3 PCI66_3 3.3
OBUFT_GTL GTL N/A
OBUFT_GTLP GTL+ N/A
OBUFT_HSTL_I HSTL_I 1.5
OBUFT_HSTL_III HSTL_III 1.5
OBUF_HSTL_IV HSTL_IV 1.5
OBUFT_SSTL2_I SSTL2_I 2.5
OBUFT_SSTL2_II SSTL2_II 2.5
OBUFT_SSTL3_I SSTL3_I 3.3
OBUFT_SSTL3_II SSTL3_II 3.3
OBUFT_CTT CTT 3.3
OBUFT_AGP AGP 3.3

Libraries Guide, Release M1.5 8-9

Libraries Guide, Release M1.5

OFD, 4, 8, 16
Single- and Multiple-Output D Flip-Flops

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OFD Primitive Macro Macro Macro Macro Macro Macro Macro
OFD4, Macro Macro Macro Macro Macro Macro Macro Macro
OFD8,
OFD16

D OFD Q
OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops except for
XC5200 and XC9000. The flip-flops exist in an input/output block (IOB) for XC3000,
C XC4000, and Spartans. The outputs (for example, Q3 – Q0) are connected to OPADs or
IOPADs. The data on the D inputs is loaded into the flip-flops during the Low-to-
X3778 High clock (C) transition and appears on the Q outputs.
The flip-flops are asynchronously cleared with Low outputs when power is applied.
D0 OFD4 Q0 For CPLDs, the power-on condition can be simulated by applying a High-level pulse
D1 Q1 on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global
D2 Q2 set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR
D3 Q3 (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an
inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
C

X3800
Inputs Outputs

D[7:0] OFD8 Q[7:0]

D C Q
D ↑ dn
C
dn = state of referenced input one setup time prior to active clock transition
X3812
VCC

OFDX
D[15:0] OFD16 Q[15:0]
D Q
D Q
C CE
C
C

X3834
X6484

Figure 8-5 OFD Implementation XC4000, Spartans

VCC

FDCE
D O_OUT Q
D Q
OBUF
CE
C
C
CLR

OUTREG (XC5200)
IOB=TRUE (VIRTEX)

GND X7936

Figure 8-6 OFD Implementation XC5200, Virtex

8-10 Xilinx Development System

Design Elements (OFD, 4, 8, 16)

FD
D Q_OUT Q
D Q

OBUF
C
C

X6378

Figure 8-7 OFD Implementation XC9000

Q[7:0]

OFD
D0 Q0
D Q

OFD
D1 Q1
D Q

OFD
D2 Q2
D Q

OFD
D3 Q3
D Q

OFD
D4 Q4
D Q

OFD
D5 Q5
D Q

OFD
D6 Q6
D Q

OFD
D7 Q7
D Q

D[7:0] Q7

C X7644

Figure 8-8 OFD8 Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Libraries Guide, Release M1.5 8-11

Libraries Guide, Release M1.5

Q[7:0]

FD
D0 Q0
D Q
OBUF
C

FD
D1 Q1
D Q
OBUF
C

FD
D2 Q2
D Q
OBUF
C

FD
D3 Q3
D Q
OBUF
C

FD
D4 Q4
D Q
OBUF
C

FD
D5 Q5
D Q
OBUF
C

FD
D6 Q6
D Q
OBUF
C

FD
D7 Q7
D Q
OBUF
C

D[7:0] Q7

X7648

Figure 8-9 OFD8 Implementation XC9000

8-12 Xilinx Development System

Design Elements (OFD_1)

OFD_1
Output D Flip-Flop with Inverted Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Macro

OFD_1
OFD_1 is located in an input/output block (IOB) except for XC5200. The output (Q) of
D Q
the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is
C loaded into the flip-flop during the High-to-Low clock (C) transition and appears on
the Q output.
X3779
The flip-flop is asynchronously cleared, output Low, when power is applied. FPGAs
simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for
XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to
active-High but can be inverted by adding an inverter in front of the GR/GSR input of
the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

D C Q
D ↓ d
d = state of referenced input one setup time prior to active clock transition

OFD
D Q
D Q

C CB
C
INV
X7700

Figure 8-10 OFD_1 Implementation XC3000, XC4000, Spartans

VCC

FDCE
D Q_OUT O
D Q
CE OBUF
C CB
C
CLR
INV

OUTREG (XC5200)
IOB=TRUE (VIRTEX) X8151

GND

Figure 8-11 OFD_1 Implementation XC5200, Virtex

Libraries Guide, Release M1.5 8-13

Libraries Guide, Release M1.5

OFDE, 4, 8, 16
D Flip-Flops with Active-High Enable Output Buffers

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OFDE Macro Macro Macro Macro Macro Macro Macro Macro
OFDE4, Macro Macro Macro Macro Macro Macro Macro Macro
OFDE8,
OFDE16

E OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose
outputs are enabled by tristate buffers. The flip-flop data outputs (Q) are connected to
D OFDE Q
the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to
C OPADs or IOPADs. These flip-flops and buffers are contained in input/output blocks
X3782
(IOB) for XC3000 and XC4000. The data on the data inputs (D) is loaded into the flip-
flops during the Low-to-High clock (C) transition. When the active-High enable
inputs (E) are High, the data on the flip-flop outputs (Q) appears on the O outputs.
E
When E is Low, outputs are high impedance (Z state or Off).
D0 OFDE4 Q0 The flip-flops are asynchronously cleared with Low outputs when power is applied.
D1 Q1
For CPLDs, the power-on condition can be simulated by applying a High-level pulse
D2 Q2
D3 Q3
on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global
set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR
C
(XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an
X3802 inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

E
Inputs Outputs
D[7:0] OFDE8 Q[7:0]

E D C O
C

X3814
0 X X Z, not off
1 1 ↑ 1
E 1 0 ↑ 0
D[15:0] OFDE16 Q[15:0]
E T

C INV OFDT
D O
D Q
X3836

C
C

X6365

Figure 8-12 OFDE Implementation XC3000, XC4000, Spartans

8-14 Xilinx Development System

Design Elements (OFDE, 4, 8, 16)

VCC

E T
INV
FDCE T
D Q_OUT O
D Q
OBUFT
CE
C
C
CLR

OUTREG (XC5200) X8693

IOB=TRUE (VIRTEX)

GND

Figure 8-13 OFDE Implementation XC5200, Virtex

E T

INV O

OBUFT
FD
D
D Q

C
C

X8044

Figure 8-14 OFDE Implementation XC9000

O[7:0]
E OFDE
D0 O0
D Q

C O0

E OFDE
D1 O1
D Q

C O1

E OFDE
D2 O2
D Q

C O2

E OFDE
D3 O3
D Q

C O3

E OFDE
D4 O4
D Q

C O4

E OFDE
D5 O5
D Q

C O5

E OFDE
D6 O6
D Q

C O6

E OFDE
D[7:0]
D7 O7
D Q
E
C C O7
X6379

Figure 8-15 OFDE8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 8-15

Libraries Guide, Release M1.5

OFDE_1

D Flip-Flop with Active-High Enable Output Buffer and

Inverted Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Macro

E
OFDE_1 and its output buffer are located in an input/output block (IOB) except for
XC5200. The data output of the flip-flop (Q) is connected to the input of an output
D OFDE_1 Q
buffer or OBUFE. The output of the OBUFE is connected to an OPAD or an IOPAD.
The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock
C (C) transition. When the active-High enable input (E) is High, the data on the flip-flop
output (Q) appears on the O output. When E is Low, the output is high impedance (Z
X3783
state or Off).
The flip-flop is asynchronously cleared with Low output when power is applied.
FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active.
GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex)
default to active-High but can be inverted by adding an inverter in front of the GR/
GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

E D C O
0 X X Z
1 1 ↓ 1
1 0 ↓ 0
E T

INV OFDT
D O
D Q

C CB
C
INV

X6364

Figure 8-16 OFDE_1 Implementation XC3000, XC4000, Spartans

VCC

E T
INV
FDCE T
D Q_OUT O
D Q
OBUFT
CE
C CB
C
INV CLR

OUTREG (XC5200)
X8692
IOB=TRUE (VIRTEX)

GND

Figure 8-17 OFDE_1 Implementation XC5200, Virtex

8-16 Xilinx Development System

Design Elements (OFDEI)

OFDEI
D Flip-Flop with Active-High Enable Output Buffer (Asynchronous
Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

E OFDEI is a D flip-flop whose output is enabled by a 3-state buffer. The data output (Q)
of the flip-flop is connected to the input of an output 3-state buffer or OBUFE. The
D OFDEI
Q
output of the OBUFE (O) is connected to an OPAD or an IOPAD. These flip-flops and
buffers are contained in input/output blocks (IOB). The data on the data input (D) is
C
loaded into the flip-flop during the Low-to-High clock (C) transition. When the
active-High enable input (E) is High, the data on the flip-flop output (Q) appears on
X4382
the O output. When E is Low, the output is high impedance (Z state or off).
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

E D C O
0 X X Z
1 1 ↑ 1
1 0 ↑ 0

E T OFDTI

INV
D O
D Q

C
C

X7667

Figure 8-18 OFDEI Implementation XC4000, Spartans

Libraries Guide, Release M1.5 8-17

Libraries Guide, Release M1.5

OFDEI_1
D Flip-Flop with Active-High Enable Output Buffer and Inverted
Clock (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

E OFDEI_1 and its output buffer exist in an input/output block (IOB). The data output
of the flip-flop (Q) is connected to the input of an output buffer or OBUFE. The output
D OFDEI_1
Q of the OBUFE is connected to an OPAD or an IOPAD. The data on the data input (D) is
loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-
C
High enable input (E) is High, the data on the flip-flop output (Q) appears on the O
X4383
output. When E is Low, the output is high impedance (Z state or off).
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

E D C O
0 X X Z
1 1 ↓ 1
1 0 ↓ 0

OFDTI
E T T

INV
D O
D Q

C CB C
INV
X7861

Figure 8-19 OFDEI_1 Implementation XC4000, Spartans

8-18 Xilinx Development System

Design Elements (OFDEX, 4, 8, 16)

OFDEX, 4, 8, 16
D Flip-Flops with Active-High Enable Output Buffers and Clock
Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

E OFDEX, OFDEX4, OFDEX8, and OFDEX16 are single or multiple D flip-flops whose
outputs are enabled by tristate buffers. The flip-flop data outputs (Q) are connected to
D OFDEX Q the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to
CE OPADs or IOPADs. These flip-flops and buffers are contained in input/output blocks
C (IOB). The data on the data inputs (D) is loaded into the flip-flops during the Low-to-
High clock (C) transition. When the active-High enable inputs (E) are High, the data
X4993 on the flip-flop outputs (Q) appears on the O outputs. When E is Low, outputs are
high impedance (Z state or Off). When CE is Low and E is High, the outputs do not
E change.

OFDEX4
The flip-flops are asynchronously cleared with Low outputs when power is applied.
D0 Q0
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
D1 Q1
tans) default to active-High but can be inverted by adding an inverter in front of the
D2 Q2
GSR input of the STARTUP symbol.
D3 Q3
CE
C

Inputs Outputs
X4994
CE E D C O
E X 0 X X Z, not off
1 1 1 ↑ 1
D[7:0] OFDEX8 Q[7:0]

CE
1 1 0 ↑ 0
C 0 1 X X No Chg

X4995
E T

INV
OFDTX
D O
E D Q
CE CE
C
D[15:0] OFDEX16 Q[15:0] C
X6418
CE
C Figure 8-20 OFDEX Implementation XC4000, Spartans

X4996

Libraries Guide, Release M1.5 8-19

Libraries Guide, Release M1.5

O[7:0]
E OFDEX
D0 O0
D Q
CE
C O0

E OFDEX

D1 O1
D Q
CE
C
O1

E OFDEX

D2 O2
D Q
CE
C
O2

E OFDEX

D3 O3
D Q
CE
C
O3

E OFDEX

D4 D O4
Q
CE
C
O4

E OFDEX

D5 D O5
Q
CE
C
O5

E OFDEX

D6 O6
D Q
CE
C
O6

OFDEX
E E
D[7:0] D7 O7
D Q
CE CE
C C O7
X6413

Figure 8-21 OFDEX8 Implementation XC4000, Spartans

8-20 Xilinx Development System

Design Elements (OFDEX_1)

OFDEX_1
D Flip-Flop with Active-High Enable Output Buffer, Inverted Clock,
and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

E OFDEX_1 and its output buffer are located in an input/output block (IOB). The data
output of the flip-flop (Q) is connected to the input of an output buffer or OBUFE. The
D OFDEX_1 Q output of the OBUFE is connected to an OPAD or an IOPAD. The data on the data
CE input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When
C the active-High enable input (E) is High, the data on the flip-flop output (Q) appears
on the O output. When E is Low, the output is high impedance (Z state or Off). When
X4997
CE is Low and E is High, the output does not change.
The flip-flop is asynchronously cleared with Low output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE E D C O
X 0 X X Z
1 1 1 ↓ 1
1 1 0 ↓ 0
0 1 X X No Chg

E T
OFDTX
INV
D O
D Q
CE
CE
C CB
C
INV X6412

Figure 8-22 OFDEX_1 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 8-21

Libraries Guide, Release M1.5

OFDEXI
D Flip-Flop with Active-High Enable Output Buffer and Clock
Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

E OFDEXI is a D flip-flop whose output is enabled by a tristate buffer. The data output
(Q) of the flip-flop is connected to the input of an output buffer or OBUFE. The output
D OFDEXI Q of the OBUFE (O) is connected to an OPAD or an IOPAD. These flip-flops and buffers
CE are contained in input/output blocks (IOB). The data on the data input (D) is loaded
C into the flip-flop during the Low-to-High clock (C) transition. When the active-High
enable input (E) is High, the data on the flip-flop output (Q) appears on the O output.
X4998
When E is Low, the output is high impedance (Z state or Off). When CE is Low and E
is High, the output does not change.
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

CE E D C O
X 0 X X Z
1 1 1 ↑ 1
1 1 0 ↑ 0
0 1 X X No Chg

E T OFDTXI

D INV O
D Q
CE
CE
C
C
X6414

Figure 8-23 OFDEXI Implementation XC4000, Spartans

8-22 Xilinx Development System

Design Elements (OFDEXI_1)

OFDEXI_1
D Flip-Flop with Active-High Enable Output Buffer, Inverted Clock,
and Clock Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

E OFDEXI_1 and its output buffer are located in an input/output block (IOB). The data
output of the flip-flop (Q) is connected to the input of an output buffer or OBUFE. The
D OFDEXI_1 Q output of the OBUFE is connected to an OPAD or an IOPAD. The data on the data
CE input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When
C the active-High enable input (E) is High, the data on the flip-flop output (Q) appears
on the O output. When E is Low, the output is high impedance (Z state or Off). When
X4999 CE is Low and E is High, the output does not change.
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

CE E D C O
X 0 X X Z
1 1 1 ↓ 1
1 1 0 ↓ 0
0 1 X X No Chg

E T
OFDTXI
INV
D O
D Q
CE
CE
C CB
C
INV X6411

Figure 8-24 OFDEXI_1 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 8-23

Libraries Guide, Release M1.5

OFDI
Output D Flip-Flop (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

OFDI is contained in an input/output block (IOB). The output (Q) of the D flip-flop is
D OFDI Q
connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-
C flop during the Low-to-High clock (C) transition and appears at the output (Q).
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
X4582
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

D C Q
D ↑ d
d = state of referenced input one setup time prior to active clock transition

Vcc

OFDXI
D Q
D Q
CE
C
C

X7413

Figure 8-25 OFDI Implementation XC4000, Spartans

VCC

D PRE Q_OUT Q
D Q
CE OBUF
C
C

FDPE
IOB=TRUE

GND
X8752

Figure 8-26 OFDI Implementation Virtex

8-24 Xilinx Development System

Design Elements (OFDI_1)

OFDI_1
Output D Flip-Flop with Inverted Clock (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

OFDI_1 OFDI_1 exists in an input/output block (IOB). The D flip-flop output (Q) is connected
D Q
to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during
C the High-to-Low clock (C) transition and appears on the Q output.

X4384
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

D C Q
D ↓ d
d = state of referenced input one setup time prior to the active clock transition

OFDI
D Q
D Q

C CB C
INV
X7862

Figure 8-27 OFDI_1 Implementation XC4000, Spartans

VCC

D PRE Q_OUT Q
D Q
CE OBUF
C CB
C
INV
FDPE
IOB=TRUE

GND
X8753

Figure 8-28 OFDI_1 Implementation Virtex

Libraries Guide, Release M1.5 8-25

Libraries Guide, Release M1.5

OFDT, 4, 8, 16
Single and Multiple D Flip-Flops with Active-Low 3-State Output
Enable Buffers

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OFDT Primitive Macro Macro Macro Macro Macro Macro Macro
OFDT4, Macro Macro Macro Macro Macro Macro Macro Macro
OFDT8,
OFDT16

T OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs
are enabled by a tristate buffers. The data outputs (Q) of the flip-flops are connected to
D OFDT Q the inputs of output buffers (OBUFT). The outputs of the OBUFTs (O) are connected
to OPADs or IOPADs. These flip-flops and buffers are located in input/output blocks
C
(IOB) for XC3000 and XC4000. The data on the data inputs (D) is loaded into the flip-
X3780
flops during the Low-to-High clock (C) transition. When the active-Low enable inputs
(T) are Low, the data on the flip-flop outputs (Q) appears on the O outputs. When T is
T
High, outputs are high impedance (Off).
The flip-flops are asynchronously cleared with Low outputs, when power is applied.
OFDT4
D0 Q0 For CPLDs, the power-on condition can be simulated by applying a High-level pulse
D1 Q1 on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global
D2 Q2 set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR
D3 Q3 (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an
C
inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

X3801
Inputs Outputs
T
T D C O
D[7:0] OFDT8 Q[7:0] 1 X X Z
C
0 D ↑ d
d = state of referenced input one setup time prior to active clock transition
X3813
VCC
T T
T
OFDTX
D O
D[15:0] Q[15:0] D Q
OFDT16
CE
C
C
C X6479

X3835 Figure 8-29 OFDT Implementation XC4000, Spartans

8-26 Xilinx Development System

Design Elements (OFDT, 4, 8, 16)

VCC

FDCE T
D O_OUT O
D Q
OBUFT
CE
C
C
CLR

OUTREG (XC5200) X8691

IOB=TRUE (VIRTEX)

GND

Figure 8-30 OFDT Implementation XC5200, Virtex

T T

OBUFT
FD
D
D Q

C
C

O
X8043

Figure 8-31 OFDT Implementation XC9000

OFDT O[7:0]
T
D0 O0
D Q

C
O0

T OFDT
D1 O1
D Q

C
O1

T OFDT
D2 O2
D Q

C
O2

T OFDT
D3 O3
D Q

C
O3

T OFDT
D4 O4
D Q

C
O4

T OFDT
D5 O5
D Q

C
O5

T OFDT
D6 O6
D Q

C
O6

T OFDT
D[7:0] D7 O7
D Q
T
C
C X6377
O7

Figure 8-32 OFDT8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 8-27

Libraries Guide, Release M1.5

OFDT_1
D Flip-Flop with Active-Low 3-State Output Buffer and Inverted
Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro N/A Macro Macro Macro

T OFDT_1 and its output buffer are located in an input/output block (IOB). The flip-
flop data output (Q) is connected to the input of an output buffer (OBUFT). The
D OFDT_1 Q OBUFT output is connected to an OPAD or an IOPAD. The data on the data input (D)
is loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-
C
Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the O
output. When T is High, the output is high impedance (Off).
X3781
The flip-flop is asynchronously cleared with Low output when power is applied.
FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active.
GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex)
default to active-High but can be inverted by adding an inverter in front of the GR/
GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs Outputs

T D C O
1 X X Z
0 1 ↓ 1
0 0 ↓ 0

E T
OFDT
D O
D Q

C CB
C
INV

X6375

Figure 8-33 OFDT_1 Implementation XC3000, XC4000, Spartans

VCC

FDCE T
D Q_OUT O
D Q
OBUFT
CE
C CB
C
INV CLR

OUTREG (XC5200) X8690

IOB=TRUE (VIRTEX)

GND

Figure 8-34 OFDT_1 Implementation XC5200, Virtex

8-28 Xilinx Development System

Design Elements (OFDTI)

OFDTI
D Flip-Flop with Active-Low 3-State Output Buffer (Asynchronous
Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

T OFDTI and its output buffer are contained in an input/output block (IOB). The data
output of the flip-flop (Q) is connected to the input of an output buffer (OBUFT). The
D OFDTI Q output of the OBUFT is connected to an OPAD or an IOPAD. The data on the data
input (D) is loaded into the flip-flop on the Low-to-High clock (C) transition. When
C
the active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on
X4581
the output (O). When T is High, the output is high impedance (off).
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

T D C O
1 X X Z
0 1 ↑ 1
0 0 ↑ 0

Vcc
T T
OFDTXI
D O
D Q
CE
C
C
X7414

Figure 8-35 OFDTI Implementation XC4000, Spartans

Libraries Guide, Release M1.5 8-29

Libraries Guide, Release M1.5

OFDTI_1
D Flip-Flop with Active-Low 3-State Output Buffer and Inverted
Clock (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

T
OFDTI_1 and its output buffer are contained in an input/output block (IOB). The data
output of the flip-flop (Q) is connected to the input of an output buffer (OBUFT). The
D OFDTI_1
Q
OBUFT output is connected to an OPAD or an IOPAD. The data on the data input (D)
is loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-
C Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the O
X4385 output. When T is High, the output is high impedance (off).
The flip-flop is asynchronously preset, output High, when power is applied. FPGAs
simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans)
default to active-High but can be inverted by adding an inverter in front of the GSR
input of the STARTUP symbol.

Inputs Outputs

T D C O
1 X X Z
0 1 ↓ 1
0 0 ↓ 0

T OFDTI

D O
D Q

C CB
C
INV

X7665

Figure 8-36 OFDTI_1 Implementation XC4000, Spartans

8-30 Xilinx Development System

Design Elements (OFDTX, 4, 8, 16)

OFDTX, 4, 8, 16
Single and Multiple D Flip-Flops with Active-Low 3-State Output
Buffers and Clock Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OFDTX N/A Primitive Primitive N/A N/A Primitive Primitive N/A
OFDTX4, N/A Macro Macro N/A N/A Macro Macro N/A
OFDTX8,
OFDTX16

T OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D flip-flops whose
outputs are enabled by a tristate buffers. The data outputs (Q) of the flip-flops are
D OFDTX Q connected to the inputs of output buffers (OBUFT). The outputs of the OBUFTs (O)
CE are connected to OPADs or IOPADs. These flip-flops and buffers are located in input/
C output blocks (IOB) for XC4000E. The data on the data inputs (D) is loaded into the
flip-flops during the Low-to-High clock (C) transition. When the active-Low enable
X6002
inputs (T) are Low, the data on the flip-flop outputs (Q) appears on the O outputs.
When T is High, outputs are high impedance (Off). When CE is Low and T is Low, the
T
outputs do not change.
D0 OFDTX4 Q0 The flip-flops are asynchronously cleared with Low output when power is applied.
D1 Q1 FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
D2 Q2 tans) default to active-High but can be inverted by adding an inverter in front of the
D3 Q3 GSR input of the STARTUP symbol.
CE
C

X6003
Inputs Outputs

CE T D C Q
T
X 1 X X Z
D[7:0] OFDTX8 Q[7:0] 1 0 D ↑ d
CE 0 0 X X No Chg
C
d = state of referenced input one setup time prior to active clock transition

X6004

D[15:0] OFDTX16 Q[15:0]

CE
C

X6005

Libraries Guide, Release M1.5 8-31

Libraries Guide, Release M1.5

T OFDTX O[7:0]

D0 D Q O0
CE
C
O0

T OFDTX
D1 D O1
Q
CE
C
O1

T OFDTX
D2 D Q O2
CE
C
O2

T OFDTX
D3 D O3
Q
CE
C
O3

T OFDTX
D4 D O4
Q
CE
C
O4

T OFDTX

D5 O5
D Q
CE
C
O5

T OFDTX
D6 O6
D Q
CE
C
O6

T T OFDTX
D[7:0]
D7 O7
D Q
CE CE
C C
O7 X6410

Figure 8-37 OFDTX8 Implementation XC4000, Spartans

8-32 Xilinx Development System

Design Elements (OFDTX_1)

OFDTX_1
D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock,
and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

T OFDTX_1 and its output buffer are located in an input/output block (IOB). The flip-
flop data output (Q) is connected to the input of an output buffer (OBUFT). The
D OFDTX_1 Q OBUFT output is connected to an OPAD or an IOPAD. The data on the data input (D)
CE is loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-
C Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the O
output. When T is High, the output is high impedance (Off). When CE is High and T
X6006
is Low, the outputs do not change.
The flip-flop is asynchronously cleared with Low output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE T D C Q
X 1 X X Z
1 0 1 ↓ 0
1 0 0 ↓ 0
0 0 X X No Chg

T T
OFDTX
D O
D Q
CE
CE
C CB
C
INV X6409

Figure 8-38 OFDTX_1 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 8-33

Libraries Guide, Release M1.5

OFDTXI
D Flip-Flop with Active-Low 3-State Output Buffer and Clock
Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive N/A

T OFDTXI and its output buffer are contained in an input/output block (IOB). The data
output of the flip-flop (Q) is connected to the input of an output buffer (OBUFT). The
D OFDTXI Q output of the OBUFT is connected to an OPAD or an IOPAD. The data on the data
CE input (D) is loaded into the flip-flop on the Low-to-High clock (C) transition. When
C the active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on
the output (O). When T is High, the output is high impedance (Off). When CE is Low
X6007
and T is Low, the output does not change.
The flip-flop is asynchronously preset with High output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE T D C O
X 1 X X Z
1 0 1 ↑ 1
1 0 0 ↑ 0
0 0 X X No Chg

8-34 Xilinx Development System

Design Elements (OFDTXI_1)

OFDTXI_1
D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock,
and Clock Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro N/A

T OFDTXI_1 and its output buffer are contained in an input/output block (IOB). The
data output of the flip-flop (Q) is connected to the input of an output buffer (OBUFT).
D OFDTXI_1 Q The OBUFT output is connected to an OPAD or an IOPAD. The data on the data input
CE (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When the
C active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the
O output. When T is High, the output is high impedance (Off). When CE is Low and T
X6008 is Low, the output does not change.
The flip-flop is asynchronously preset with High output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE T D C Q
X 1 X X Z
1 0 1 ↓ 1
1 0 0 ↓ 0
0 0 X X No Chg

T T

OFDTXI
D O
D Q
CE
CE
C CB
C
INV X6423

Figure 8-39 OFDTXI_1 Implementation XC4000, Spartans

Libraries Guide, Release M1.5 8-35

Libraries Guide, Release M1.5

OFDX, 4, 8, 16
Single- and Multiple-Output D Flip-Flops with Clock Enable

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OFDX N/A Primitive Primitive N/A N/A Primitive Primitive Macro
OFDX4, N/A Macro Macro N/A N/A Macro Macro Macro
OFDX8,
OFDX16

OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops. The
D OFDX Q
flip-flops are located in an input/output block (IOB) for XC4000E. The Q outputs are
CE
connected to OPADs or IOPADs. The data on the D inputs is loaded into the flip-flops
C
during the Low-to-High clock (C) transition and appears on the Q outputs. When CE
X4988
is Low, flip-flop outputs do not change.
The flip-flops are asynchronously cleared with Low outputs, when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
OFDX4
D0 Q0 tans) default to active-High but can be inverted by adding an inverter in front of the
D1 Q1 GSR input of the STARTUP symbol.
D2 Q2
D3 Q3
CE
C
Inputs Outputs
CE D C Q
X4989
1 D ↑ dn
0 X X No Chg
D[7:0] OFDX8 Q[7:0]
dn = state of referenced input one setup time prior to active clock transition
CE
C
FDCE
D Q_OUT Q
X4990 D Q
CE OBUF
CE
C
C
D[15:0] OFDX16 Q[15:0] CLR

CE
IOB=TRUE
C

GND
X4991 X8754

Figure 8-40 OFDX Implementation Virtex

8-36 Xilinx Development System

Design Elements (OFDX, 4, 8, 16)

Q[7:0]

OFDX
D0 Q0
D Q
CE
C
Q0

OFDX
D1 Q1
D Q
CE
C
Q1

OFDX
D2 Q2
D Q
CE
C
Q2

OFDX
D3 Q3
D Q
CE
C
Q3

OFDX
D4 Q4
D Q
CE
C
Q4

OFDX
D5 Q5
D Q
CE
C
Q5

OFDX
D6 Q6
D Q
CE
C
Q6

OFDX
D7 Q7
D Q
CE
C
Q7
D[7:0]

CE X6408

Figure 8-41 OFDX8 Implementation XC4000, Spartans, Virtex

Libraries Guide, Release M1.5 8-37

Libraries Guide, Release M1.5

OFDX_1
Output D Flip-Flop with Inverted Clock and Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

OFDX_1 is located in an input/output block (IOB). The output (Q) of the D flip-flop is
D OFDX_1 Q
connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-
CE
flop during the High-to-Low clock (C) transition and appears on the Q output. When
C
the CE pin is Low, the output (Q) does not change.
X4992
The flip-flop is asynchronously cleared with Low output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE D C Q
1 D ↓ d
0 X X No Chg
d = state of referenced input one setup time prior to active clock transition

OFDX
D Q
D Q
CE
CE
C CB
C
INV
X6406

Figure 8-42 OFDX_1 Implementation XC4000, Spartans

FDCE
D Q_OUT Q
D Q
CE OBUF
CE
C CB
C
CLR
INV

IOB=TRUE

GND
X8755

Figure 8-43 OFDX_1 Implementation Virtex

8-38 Xilinx Development System

Design Elements (OFDXI)

OFDXI
Output D Flip-Flop with Clock Enable (Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive Macro

OFDXI is contained in an input/output block (IOB). The output (Q) of the D flip-flop
D OFDXI Q
is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-
CE
flop during the Low-to-High clock (C) transition and appears at the output (Q). When
C
CE is Low, the output does not change.
X6000 The flip-flop is asynchronously preset with High output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE D C Q
1 D ↑ d
0 X X No Chg
d = state of referenced input one setup time prior to active clock transition

D PRE Q_OUT Q
D Q
CE OBUF
CE
C
C

FDPE
IOB=TRUE

GND
X8756

Figure 8-44 OFDXI Implementation Virtex

Libraries Guide, Release M1.5 8-39

Libraries Guide, Release M1.5

OFDXI_1
Output D Flip-Flop with Inverted Clock and Clock Enable
(Asynchronous Preset)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

OFDXI_1 is located in an input/output block (IOB). The D flip-flop output (Q) is

D OFDXI_1 Q
connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-
CE
flop during the High-to-Low clock (C) transition and appears on the Q output. When
C
CE is Low, the output (Q) does not change.
X6001 The flip-flop is asynchronously preset with High output when power is applied.
FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spar-
tans) default to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP symbol.

Inputs Outputs

CE D C Q
1 D ↓ d
0 X X No Chg
d = state of referenced input one setup time prior to active clock transition

OFDXI
D Q
D Q
CE
CE
C CB
C
INV
X6407

Figure 8-45 OFDXI_1 Implementation XC4000, Spartans

D PRE Q_OUT Q
D Q
CE OBUF
CE
C CB
C
INV
FDPE
IOB=TRUE

GND
X8757

Figure 8-46 OFDXI_1 Implementation Virtex

8-40 Xilinx Development System

Design Elements (OMUX2)

OMUX2
2-to-1 Multiplexer

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

The OMUX2 multiplexer chooses one data bit from two sources (D1 or D0) under the
D0
D1
O control of the select input (S0). The output (O) reflects the state of the selected data
S0 input. When Low, S0 selects D0 and when High, S0 selects D1.
X4026

Inputs Outputs

S0 D1 D0 O
1 1 X 1
1 0 X 0
0 X 1 1
0 X 0 0

Libraries Guide, Release M1.5 8-41

Libraries Guide, Release M1.5

ONAND2
2-Input NAND Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

ONAND2 is a 2-input NAND gate that is implemented in the output multiplexer of

F
O the XC4000X IOB. The F pin is faster than I0. Input pins can be inverted even though
I0
there is no library component showing inverted inputs. The mapper will automati-
X6963 cally bring any inverted input pins into the IOB.

8-42 Xilinx Development System

Design Elements (ONOR2)

ONOR2
2-Input NOR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

F ONOR2 is a 2-input NOR gate that is implemented in the output multiplexer of the
O
I0 XC4000X IOB. The F pin is faster than I0. Input pins can be inverted even though there
is no library component showing inverted inputs. The mapper will automatically
X6956
bring any inverted input pins into the IOB.

Libraries Guide, Release M1.5 8-43

Libraries Guide, Release M1.5

OOR2
2-Input OR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

F
OOR2 is a 2-input OR gate that is implemented in the output multiplexer of the
XC4000X IOB. The F pin is faster than I0. Input pins can be inverted even though there
OOR2 is no library component showing inverted inputs. The mapper will automatically
X8191 bring any inverted input pins into the IOB.

8-44 Xilinx Development System

Design Elements (OPAD, 4, 8, 16)

OPAD, 4, 8, 16
Single- and Multiple-Output Pads

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OPAD Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
OPAD4, Macro Macro Macro Macro Macro Macro Macro Macro
OPAD8,
OPAD16

OPAD OPAD, OPAD4, OPAD8, and OPAD16 are single and multiple output pads. An OPAD
connects a device pin to an output signal of a PLD. It is internally connected to an
X3829
input/output block (IOB), which is configured by the software as an OBUF, an
OBUFT, an OBUFE, an OFD, or an OFDT.
OPAD4
Refer to the appropriate CAE tool interface user guide for details on assigning pin
O0 location and identification.
O1
O2 O[7:0]
O3

O0
X3839 OPAD
O1
OPAD
OPAD8 O2
OPAD
O[7:0] O3
OPAD
O4
X3842 OPAD
O5
OPAD
OPAD16 O6
OPAD
O[15:0] O7
OPAD

X3846
X7656

Figure 8-47 OPAD8 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 8-45

Libraries Guide, Release M1.5

OR2-9
2- to 9-Input OR Gates with Inverted and Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

OR2, Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
OR2B1,
OR2B2,
OR3,
OR3B1,
OR3B2,
OR3B3,
OR4,
OR4B1,
OR4B2,
OR4B3,
OR4B4
OR5, Primitive Primitive Primitive Macro Primitive Primitive Primitive Primitive
OR5B1,
OR5B2,
OR5B3,
OR5B4,
OR5B5
OR6, Macro Macro Macro Macro Primitive Macro Macro Macro
OR7,
OR8,
OR9

8-46 Xilinx Development System

Design Elements (OR2-9)

OR2 OR3 OR4 OR5 OR6

OR2B1 OR3B1 OR4B1 OR5B1

OR7

OR2B2 OR3B2 OR4B2 OR5B2

OR3B3 OR4B3 OR5B3

OR8

OR4B4 OR5B4

X7863 OR5B5 OR9

Figure 8-48 OR Gate Representations

The OR function is performed in the Configurable Logic Block (CLB) function genera-
tors for FPGAs. OR functions of up to five inputs are available in any combination of
inverting and non-inverting inputs. OR functions of six to nine inputs are available
with only non-inverting inputs. To invert some or all inputs, use external inverters.
Since each input uses a CLB resource, replace functions with unused inputs with func-
tions having the necessary number of inputs.
Refer to the “OR12, 16” section for information on additional OR functions for the
XC5200 and Virtex.

Libraries Guide, Release M1.5 8-47

Libraries Guide, Release M1.5

I4
I3 I35
I2
I1 OR3 O
I0
OR3
X8110

Figure 8-49 OR5 Implementation XC5200

I7
I6
I47
I5
I4
I3 OR4
I2 O
I1
I0
OR5

X7864

Figure 8-50 OR8 Implementation XC3000

I7
I6
I47
I5
I4 OR4
O
I3
I2 I13 OR3
I1
OR3
I0 X6535

Figure 8-51 OR8 Implementation XC4000, XC5200, Spartans

FMAP
I4
I3 O
S1 O
I2
S2
I1
I7
I6 RLOC=R0C0.S0
S1
I5
I4
FMAP
OR4
I7
I4
I6
O I3 S1
I5 O
I2
I4
OR2 I1
I3
RLOC=R0C0.S1
I2
S0
I1
I0 FMAP
OR4 I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8698 RLOC=R0C0.S1

Figure 8-52 OR8 Implementation Virtex

8-48 Xilinx Development System

Design Elements (OR12, 16)

OR12, 16
12- and 16-Input OR Gates with Non-Inverted Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Macro N/A N/A N/A Macro

Refer to the “OR2-9” section for information on OR functions.

FMAP

I15
CO I4
I15
CY_MUX I14
I14 RLOC=R0C0.LC3 I3 S3
S3 S I13 O
I13 0 1 I2
OR12
VCC I12
DI CI I1
I12
X8198
NOR4
RLOC=R0C0.LC3
C2

FMAP

I11
I11 CO I4
CY_MUX I10
I10 RLOC=R0C0.LC2 I3 S2
S2 S I9 O
I9 0 1 I2
I8
I8 DI CI I1

NOR4
RLOC=R0C0.LC2
C1

FMAP

I7
I7 CO I4
CY_MUX I6
I6 RLOC=R0C0.LC1 I3 S1
OR16 S1 S I5 O
I5 0 1 I2
X8199 I4
DI CI I1
I4
NOR4
RLOC=R0C0.LC1
C0

FMAP

I3 CO I3
CY_MUX I4
I2 RLOC=R0C0.LC0 I2
S0 S I3 S0
I1 0 1 I1 O
I2
DI CI I0
I0
I1
NOR4

RLOC=R0C0.LC0
CIN

COUT

INIT
CY_INIT X6518
RLOC=R1C0.LC3

GND

Figure 8-53 OR16 Implementation XC5200

Libraries Guide, Release M1.5 8-49

Libraries Guide, Release M1.5

FMAP

I15
I15 O I4
MUXCY I14
I14 RLOC=R0C0.S1 I3 S3
S3 S I13 O
I13 0 1 I2
VCC DI CI I12
I12 I1
NOR4
RLOC=R0C0.S1
C2

FMAP

I11
I11 LO I4
MUXCY_L I10
I10 RLOC=R0C0.S1 I3 S2
S2 S I9 O
I9 0 1 I2
I8
I8 DI CI I1
NOR4
RLOC=R0C0.S1
C1

FMAP

I7
I7 LO I4
MUXCY_L I6
I6 RLOC=R1C0.S1 I3 S1
S1 S I5 O
I5 0 1 I2
I4
I4 DI CI I1
NOR4
RLOC=R1C0.S1
C0

FMAP

I3 LO I3
MUXCY_L I4
I2 RLOC=R1C0.S1 I2
S0 S I3 S0
I1 0 1 I1 O
I2
I0 DI CI I0
I1
NOR4

RLOC=R1C0.S1

CIN

X8706

GND

Figure 8-54 OR16 Implementation Virtex

8-50 Xilinx Development System

Design Elements (OSC)

OSC
Crystal Oscillator Amplifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive N/A N/A N/A N/A N/A N/A N/A

OSC The OSC element’s clock signal frequency is derived from an external crystal-
controlled oscillator. The OSC output can be connected to an ACLK buffer, which is
connected to an internal clock net.
Two dedicated input pins (XTAL 1 and XTAL 2) on each FPGA device are internally
connected to pads and input/output blocks that are connected to the OSC amplifier.
X3885 The external components are connected as shown in the following example. Refer to
The Programmable Logic Data Book for details on component selection and tolerances.

OSC ACLK

IPAD OPAD

X8266

Libraries Guide, Release M1.5 8-51

Libraries Guide, Release M1.5

OSC4
Internal 5-Frequency Clock-Signal Generator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive N/A

OSC4 F8M OSC4 provides internal clock signals in applications where timing is not critical. The
F500K available frequencies are determined by FPGA device components, which are process
F16K dependent. Therefore, the available frequencies vary from device to device. Nominal
F490
F15
frequencies are 8 MHz, 500 kHz, 16 kHz, 490 Hz, and 15 Hz. Although there are five
outputs, only three can be used at a time, with 8 MHz on one output and one
X3912
frequency each on any two of the remaining four outputs. An error occurs if more
than three outputs are used simultaneously.

8-52 Xilinx Development System

Design Elements (OSC5)

OSC5
Internal Multiple-Frequency Clock-Signal Generator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

OSC5 provides internal clock signals in applications where timing is not critical. The
OSC5 OSC1
available frequencies are determined by FPGA device components that are process
OSC2 dependent. Therefore, the available frequencies vary from device to device. Use only
one OSC5 per design. The OSC5 is not available if the CK_DIV element is used.
@DIVIDE1_BY=
@DIVIDE2_BY= The clock frequencies of the OSC1 and OSC2 outputs are determined by specifying
X4971 the DIVIDE1_BY=n1 attribute for the OSC1 output and the DIVIDE2_BY=n2 attribute
for the OSC2 output. n1 and n2 are integer numbers by which the internal 16-MHz
clock is divided to produce the desired clock frequency. The available frequency
options are shown in the table.

n1 OSC1 Frequency n2 OSC2 Frequency

4 4 MHz 2 8 MHz
16 1 MHz 8 2 MHz
64 250 kHz 32 500 kHz
256 63 kHz 128 125 kHz
1,024 16 kHz
4,096 4 kHz
16,384 1 kHz
65,536 244 Hz

Libraries Guide, Release M1.5 8-53

Libraries Guide, Release M1.5

OSC52
Internal Multiple-Frequency Clock-Signal Generator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A Primitive N/A N/A N/A N/A

OSC52 OSC52 provides internal clock signals in applications where timing is not critical. The
available frequencies are determined by FPGA device components, which are process
OSC1
independent. Therefore, the available frequencies vary from device to device. Only
C OSC2 one OSC52 may be used per design.

X8051
The oscillator frequencies of the OSC1 and OSC2 outputs are determined by speci-
fying theDIVIDE1_BY=n1 attribute for the OSC1 output and DIVIDE2_BY=n2
attribute for the OSC2 output. n1 and n2 are integer numbers by which internal 16-
MHz clock is divided to produce the desired clock frequency. The available frequency
options appear in the table that follows.

n1 OSC1 Frequency n2 OSC2 Frequency

4 4 MHz 2 8 MHz
16 1 MHz 8 2 MHz
64 250 kHz 32 500 kHz
256 63 kHz 128 125 kHz
1,024 16 kHz
4,096 4 kHz
16,384 1 kHz
65,536 244 Hz

8-54 Xilinx Development System

Design Elements (OXNOR2)

OXNOR2
2-Input Exclusive-NOR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

F OXNOR2 is a 2-input exclusive NOR gate that is implemented in the output multi-
O
I0 plexer of the XC4000X and SpartanXL IOB. The F pin is faster than I0. Input pins can
X6965 be inverted even though there is no library component showing inverted inputs. The
mapper will automatically bring any inverted input pins into the IOB.

Libraries Guide, Release M1.5 8-55

Libraries Guide, Release M1.5

OXOR2
2-Input Exclusive-OR Gate with Invertible Inputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A Primitive N/A N/A N/A Primitive N/A

F OXOR2 is a 2-input exclusive OR gate that is implemented in the output multiplexer

O
I0 of the XC4000X IOB. The F pin is faster than I0. Input pins can be inverted even
though there is no library component showing inverted inputs. The mapper will auto-
matically bring any inverted input pins into the IOB.
X6964

8-56 Xilinx Development System

Chapter 9

Design Elements (PULLDOWN to ROM32X1)

Libraries Guide, Release M1.5 — 9-1

Libraries Guide, Release M1.5

PULLDOWN
Resistor to GND for Input Pads

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive Primitive

PULLDOWN resistor elements are available in each XC4000 or Spartan series Input/
Output Block (IOB). They are connected to input, output, or bidirectional pads to
guarantee a logic Low level for nodes that might float.

X3860

9-2 Xilinx Development System

Design Elements (PULLUP)

PULLUP
Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive N/A Primitive Primitive Primitive

PULLUP resistor elements are available in each XC3000, XC4000, and Spartan series
Input/Output Block (IOB). XC3000 IOBs only use PULLUP resistors on input pads.
XC4000 and Spartan series IOBs connect PULLUP resistors to input, output, or bidi-
rectional pads to guarantee a logic High level for nodes that might float.
X3861
The pull-up elements also establish a High logic level for open-drain elements and
macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF) when all the drivers
are off.
The buffer outputs are connected together as a wired-AND to form the output (O).
When all the inputs are High, the output is off. To establish an output High level, a
PULLUP resistor(s) is tied to output (O). One PULLUP resistor uses the least power,
two pull-up resistors achieve the fastest Low-to-High speed.
To indicate two PULLUP resistors, append a DOUBLE parameter to the pull-up
symbol attached to the output (O) node. Refer to the appropriate CAE tool interface
user guide for details.
The PULLUP element is ignored in XC9000 designs. Internal 3-state nodes (from
BUFE or BUFT) in CPLD designs are always pulled up when not driven.

Libraries Guide, Release M1.5 9-3

Libraries Guide, Release M1.5

RAM16X1
16-Deep by 1-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A N/A N/A N/A

RAM16X1
RAM16X1 is a 16-word by 1-bit static read-write random access memory. When the
D O
WE
write enable (WE) is High, the data on the data input (D) is loaded into the word
A0 selected by the 4-bit address (A3 – A0). The data output (O) reflects the selected
A1
(addressed) word, whether WE is High or Low. When WE is Low, the RAM content is
A2
A3 unaffected by address or input data transitions. Address inputs must be stable before
the High-to-Low WE transition for predictable performance.
X4124
You can initialize RAM16X1 during configuration. See “Specifying Initial Contents of
a RAM” in this section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) D O
0(read) X Data
1(write) D Data
Data = word addressed by bits A3 – A0

Specifying Initial Contents of a RAM

You can use the INIT attribute to specify an initial value directly on the symbol only if
the RAM is 1 bit wide and 16 or 32 bits deep. The value must be a hexadecimal
number, for example, INIT=ABAC.
If the INIT attribute is not specified, the RAM is initialized with zero.

9-4 Xilinx Development System

Design Elements (RAM16X1D)

RAM16X1D
16-Deep by 1-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive Primitive

RAM16X1D is a 16-word by 1-bit static dual port random access memory with
WE RAM16X1D SPO
D
synchronous write capability. The device has two separate address ports: the read
WCLK DPO address (DPRA3 – DPRA0) and the write address (A3 – A0). These two address ports
A0 are completely asynchronous. The read address controls the location of the data
A1 driven out of the output pin (DPO), and the write address controls the destination of a
A2
A3
valid write transaction.
DPRA0
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
DPRA1
DPRA2
ignored and data stored in the RAM is not affected. When WE is High, any positive
DPRA3 transition on WCLK loads the data on the data input (D) into the word selected by the
4-bit write address. For predictable performance, write address and data inputs must
X4950
be stable before a Low-to-High WCLK transition. This RAM block assumes an active-
High WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
You can initialize RAM16X1D during configuration. See “Specifying Initial Contents
of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D SPO DPO

0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D D data_d
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 – A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 – DPRA0.
Note: The write process is not affected by the address on the read address port.

Libraries Guide, Release M1.5 9-5

Libraries Guide, Release M1.5

RAM16X1D_1
16-Deep by 1-Wide Static Dual Port Synchronous RAM with
Negative-Edge Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with
WE RAM16X1D_1 SPO
D DPO
synchronous write capability and negative-edge clock. The device has two separate
WCLK address ports: the read address (DPRA3 – DPRA0) and the write address (A3 – A0).
A0 These two address ports are completely asynchronous. The read address controls the
A1
A2
location of the data driven out of the output pin (DPO), and the write address controls
A3 the destination of a valid write transaction.
DPRA0
DPRA1 When the write enable (WE) is Low, transitions on the write clock (WCLK) are
DPRA2
DPRA3
ignored and data stored in the RAM is not affected. When WE is High, any negative
transition on WCLK loads the data on the data input (D) into the word selected by the
X8419
4-bit write address. For predictable performance, write address and data inputs must
be stable before a High-to-Low WCLK transition. This RAM block assumes an active-
High WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
You can initialize RAM16X1D_1 during configuration. See “Specifying Initial
Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D SPO DPO

RAM16X1
D0 O0
D O
WE
A0
A1
A2
A3
O1

RAM16X1
D1 O1
D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
O2
X7745

Figure 9-1 RAM16X2 Implementation XC4000

Libraries Guide, Release M1.5 9-9

Libraries Guide, Release M1.5

RAM16X2D
16-Deep by 2-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM16X2D is a 16-word by 2-bit static dual port random access memory with
WE RAM16X2D SPO0
D0 SPO1
synchronous write capability. The device has two separate address ports: the read
D1 address (DPRA3 – DPRA0) and the write address (A3 – A0). These two address ports
WCLK DPO0 are completely asynchronous. The read address controls the location of data driven
A0 DPO1
A1
out of the output pin (DPO1 – DPO0), and the write address controls the destination
A2 of a valid write transaction.
A3
DPRA0
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
DPRA1 ignored and data stored in the RAM is not affected. When WE is High, any positive
DPRA2 transition on WCLK loads the data on the data input (D1 – D0) into the word selected
DPRA3
by the 4-bit write address. For predictable performance, write address and data inputs
X4951
must be stable before a Low-to-High WCLK transition. This RAM block assumes an
active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter
placed on the WCLK input net is absorbed into the block.
The initial contents of RAM16X2D cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D1-D0 SPO1-SPO0 DPO1-DPO0

0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D1-D0 D1-D0 data_d
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0

9-10 Xilinx Development System

Design Elements (RAM16X2S)

RAM16X2S
16-Deep by 2-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

WE RAM16X2S O0 RAM16X2S is a 16-word by 2-bit static random access memory with synchronous
D0 O1 write capability. When the write enable (WE) is Low, transitions on the write clock
D1 (WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
WCLK
any positive transition on WCLK loads the data on the data input (D1 – D0) into the
A0
A1
word selected by the 4-bit address (A3 – A0). For predictable performance, address
A2 and data inputs must be stable before a Low-to-High WCLK transition. This RAM
A3 block assumes an active-High WCLK. However, WCLK can be active-High or active-
Low. Any inverter placed on the WCLK input net is absorbed into the block.
X4944
The signal output on the data output pin (O1 – O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
The initial contents of RAM16X2S cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D1-D0 O1-O0

0 (read) X X Data
1(read) 0 X Data
1(read) 1 X Data
1(write) ↑ D1-D0 D1-D0
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0

Libraries Guide, Release M1.5 9-11

Libraries Guide, Release M1.5

RAM16X4
16-Deep by 4-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A N/A N/A N/A

RAM16X4 is a 16-word by 4-bit static read-write random access memory. When the
D0 RAM16X4 O0
write enable (WE) is High, the data on data inputs (D3 – D0) is loaded into the word
D1 O1
D2 O2 selected by the 4-bit address (A3 – A0). The data outputs (O3 – O0) reflect the selected
D3 O3 (addressed) word, whether WE is High or Low. When WE is Low, the RAM content is
WE unaffected by address or data input transitions. Address inputs must be stable before
A0
A1
the High-to-Low WE transition for predictable performance.
A2
A3
The initial contents of RAM16X4 cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
X4135
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) D3 – D0 O3 – O0
0(read) X data
1(write) D3 – D0 Data
Data = word addressed by bits A3 – A0

9-12 Xilinx Development System

Design Elements (RAM16X4)

RAM16X1
D0 O0
D O
WE
A0
A1
A2
A3

RAM16X1
D1 O1
D O
WE
A0
A1
A2
A3

RAM16X1
D2 O2
D O
WE
A0
A1
A2
A3

RAM16X1
D3 O3
D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
X7746

Figure 9-2 RAM16X4 Implementation XC4000

Libraries Guide, Release M1.5 9-13

Libraries Guide, Release M1.5

RAM16X4D
16-Deep by 4-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM16X4D is a 16-word by 4-bit static dual port random access memory with
WE RAM16X4D SPO0
D0
synchronous write capability. The device has two separate address ports: the read
SPO1
D1 SPO2 address (DPRA3 – DPRA0) and the write address (A3 – A0). These two address ports
D2 SPO3 are completely asynchronous. The read address controls the location of data driven
D3
out of the output pin (DPO3 – DPO0), and the write address controls the destination
WCLK DPO0
A0 DPO1 of a valid write transaction.
A1 DPO2
A2 DPO3
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
A3 ignored and data stored in the RAM is not affected. When WE is High, any positive
DPRA0 transition on WCLK loads the data on the data input (D3 – D0) into the word selected
DPRA1
by the 4-bit write address. For predictable performance, write address and data inputs
DPRA2
DPRA3
must be stable before a Low-to-High WCLK transition. This RAM block assumes an
active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter
X4952 placed on the WCLK input net is absorbed into the block.
The initial contents of RAM16X4D cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D3-D0 SPO3-SPO0 DPO3-DPO0

0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D3-D0 D3-D0 data_d
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0

9-14 Xilinx Development System

Design Elements (RAM16X4S)

RAM16X4S
16-Deep by 4-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM16X4S is a 16-word by 4-bit static random access memory with synchronous

WE RAM16X4S O0 write capability. When the write enable (WE) is Low, transitions on the write clock
D0 O1
D1
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
O2
D2 O3 any positive transition on WCLK loads the data on the data input (D3 – D0) into the
D3 word selected by the 4-bit address (A3 – A0). For predictable performance, address
WCLK and data inputs must be stable before a Low-to-High WCLK transition. This RAM
A0
A1
block assumes an active-High WCLK. However, WCLK can be active-High or active-
A2 Low. Any inverter placed on the WCLK input net is absorbed into the block.
A3
The signal output on the data output pin (O3 – O0) is the data that is stored in the
X4945 RAM at the location defined by the values on the address pins.
The initial contents of RAM16X4S cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D3 – D0 O3 – O0
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D3-D0 D3-D0
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0

Libraries Guide, Release M1.5 9-15

Libraries Guide, Release M1.5

RAM16X8
16-Deep by 8-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A N/A N/A N/A

D[7:0]
RAM16X8 is a 16-word by 8-bit static read-write random access memory. When the
RAM16X8 O[7:0]
WE
write enable (WE) is High, the data on data inputs (D7 – D0) is loaded into the word
A0 selected by the 4-bit address (A3 – A0). The data outputs (O7 – O0) reflect the selected
A1 (addressed) word, whether WE is High or Low. When WE is Low, the RAM content is
A2
A3 unaffected by address or data input transitions. Address inputs must be stable before
the High-to-Low WE transition for predictable performance.
X4142
The initial contents of RAM16X8 cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) D7 – D0 O7 – O0
0(read) X Data
1(write) D7 – D0 Data
Data = word addressed by bits A3 – A0

9-16 Xilinx Development System

Design Elements (RAM16X8)

O[7:0]

RAM16X1 RAM16X1
D0 O0 D4 O4
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
O0 O4

RAM16X1 RAM16X1
D1 O1 D5 O5
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 O1 A3
O5

RAM16X1 RAM16X1
D2 O2 D6 O6
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
O2 O6

RAM16X1 RAM16X1
D3 O3 D7 O7
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
O3 O7
D[7:0]

WE
A0
A1
A2
A3 X7600

Figure 9-3 RAM16X8 Implementation XC4000

Libraries Guide, Release M1.5 9-17

Libraries Guide, Release M1.5

RAM16X8D

16-Deep by 8-Wide Static Dual Port Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM16X8D is a 16-word by 8-bit static dual port random access memory with
WE RAM16X8D SPO[7:0]
synchronous write capability. The device has two separate address ports: the read
D[7:0]
WCLK DPO[7:0] address (DPRA3 – DPRA0) and the write address (A3 – A0). These two address ports
A0 are completely asynchronous. The read address controls the location of data driven
A1 out of the output pin (DPO7 – DPO0), and the write address controls the destination
A2 of a valid write transaction.
A3
DPRA0 When the write enable (WE) is Low, transitions on the write clock (WCLK) are
DPRA1
DPRA2
ignored and data stored in the RAM is not affected. When WE is High, any positive
DPRA3 transition on WCLK loads the data on the data input (D7 – D0) into the word selected
by the 4-bit write address (A3 – A0). For predictable performance, write address and
X4953 data inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The initial contents of RAM16X8D cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D7-D0 SP7-SPO0 DPO7-DPO0

0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D7-D0 D7-D0 data_d
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0

9-18 Xilinx Development System

Design Elements (RAM16X8D)

DPO[7:0]

SPO[7:0]

RAM16X1D RAM16X1D
WE SPO0 WE SPO4
SPO SPO
D0 D4
D D
WCLK DPO0 WCLK DPO4
DPO DPO
A0 A0
A1 A1
A2 A2
A3 A3
DPRA0 DPRA0
DPRA1 DPRA1
DPRA2 DPRA2
DPRA3 O0 DPRA3 O4
RAM16X1D RAM16X1D
WE SPO1 WE SPO5
SPO SPO
D1 D5
D D
WCLK DPO1 WCLK DPO5
DPO DPO
A0 A0
A1 A1
A2 A2
A3 A3
DPRA0 DPRA0
DPRA1 DPRA1
DPRA2 DPRA2
DPRA3 O1 DPRA3 O5
RAM16X1D RAM16X1D
WE SPO2 WE SPO6
SPO SPO
D2 D6
D D
WCLK DPO2 WCLK DPO6
DPO DPO
A0 A0
A1 A1
A2 A2
A3 A3
DPRA0 DPRA0
DPRA1 DPRA1
DPRA2 DPRA2
DPRA3 DPRA3
O2 O6
RAM16X1D RAM16X1D
SPO3 SPO7
WE SPO WE SPO
D3 D7
D D
WCLK DPO3 WCLK DPO7
DPO DPO
A0 A0
A1 A1
A2 A2
A3 A3
DPRA0 DPRA0
DPRA1 DPRA1
DPRA2 DPRA2
DPRA3 DPRA3
O3 O7

D[7:0]

WE
WCLK
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
X6416
DPRA3

Figure 9-4 RAM16X8D Implementation XC4000, Spartans

Libraries Guide, Release M1.5 9-19

Libraries Guide, Release M1.5

RAM16X8S
16-Deep by 8-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM16X8S is a 16-word by 8-bit static random access memory with synchronous

WE RAM16X8S O[7:0]
D[7:0]
write capability. When the write enable (WE) is Low, transitions on the write clock
WCLK
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
A0 any positive transition on WCLK loads the data on data inputs (D7 – D0) into the
A1 word selected by the 4-bit address (A3 – A0). For predictable performance, address
A2
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
A3
block assumes an active-High WCLK. However, WCLK can be active-High or active-
X4946 Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O7 – O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
The initial contents of RAM16X8S cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D7-D0 O7-O0

0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D7-D0 D7-D0
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0

9-20 Xilinx Development System

Design Elements (RAM16X8S)

O[7:0]

RAM16X1S RAM16X1S
O0 O4
WE O WE O
D0 D4
D D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 O0 A3 O4

RAM16X1S RAM16X1S
O1 O5
WE O WE O
D1 D5 D
D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 O1 A3 O5

RAM16X1S RAM16X1S
O2 O6
WE O WE O
D2 D6 D
D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 O2 A3 O6

RAM16X1S RAM16X1S
O3 O7
WE O WE O
D3 D7 D
D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 O3 A3 O7
D[7:0]

WE
WCLK
A0
A1
A2
A3 X6415

Figure 9-5 RAM16X8S Implementation XC4000, Spartans

Libraries Guide, Release M1.5 9-21

Libraries Guide, Release M1.5

RAM32X1
32-Deep by 1-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

RAM32X2 is a 32-word by 2-bit static read-write random access memory. When the
D0 RAM32X2 O0
D1 O1
write enable (WE) is High, the data on the data inputs (D1 – D0) is loaded into the
WE word selected by the address bits (A4 – A0). The data outputs (O1 – O0) reflect the
A0 selected (addressed) word, whether WE is High or Low. When WE is Low, the RAM
A1
content is unaffected by address or input data transitions. Address inputs must be
A2
A3
stable before the High-to- Low WE transition for predictable performance.
A4
The initial contents of RAM32X2 cannot be specified directly. Initial contents may be
X4129
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) D1 – D0 O1 – O0
0(read) X Data
1(write) D1 – D0 Data
Data = word addressed by bits A4 – A0

Libraries Guide, Release M1.5 9-25

Libraries Guide, Release M1.5

RAM32X2S
32-Deep by 2-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM32X2S is a 32-word by 2-bit static random access memory with synchronous

WE RAM32X2S O0 write capability. When the write enable (WE) is Low, transitions on the write clock
D0 O1
D1
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
WCLK any positive transition on WCLK loads the data on the data input (D1 – D0) into the
A0 word selected by the 5-bit address (A4 – A0). For predictable performance, address
A1
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
A2
A3
block assumes an active-High WCLK. However, WCLK can be active-High or active-
A4 Low. Any inverter placed on the WCLK input net is absorbed into the block.
X4947 The signal output on the data output pin (O1 – O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
The initial contents of RAM32X2S cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D0-D1 O0-O1

0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D1-D0 D1-D0
1 (read) ↓ X Data
Data = word addressed by bits A4 – A0

9-26 Xilinx Development System

Design Elements (RAM32X4)

RAM32X4
32-Deep by 4-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A N/A N/A N/A

RAM32X4 is a 32-word by 4-bit static read-write random access memory. When the
D0 RAM32X4 O0
D1 O1
write enable (WE) is High, the data on the data inputs (D3 – D0) is loaded into the
D2 O2 word selected by the address bits (A4 – A0). The data outputs (O3 – O0) reflect the
D3 O3 selected (addressed) word, whether WE is High or Low. When WE is Low, the RAM
WE
A0
content is unaffected by address or input data transitions. Address inputs must be
A1 stable before the High-to- Low WE transition for predictable performance.
A2
A3 The initial contents of RAM32X4 cannot be specified directly. Initial contents may be
A4 specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
X4136
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) D3 – D0 O3 – O0
0(read) X Data
1(write) D3 – D0 Data
Data = word addressed by bits A4 – A0

Libraries Guide, Release M1.5 9-27

Libraries Guide, Release M1.5

RAM32X4S
32-Deep by 4-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

WE RAM32X4S O0
RAM32X4S is a 32-word by 4-bit static random access memory with synchronous
D0 O1 write capability. When the write enable (WE) is Low, transitions on the write clock
D1 O2 (WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
D2 O3
any positive transition on WCLK loads the data on the data inputs (D3 – D0) into the
D3
WCLK
word selected by the 5-bit address (A4 – A0). For predictable performance, address
A0 and data inputs must be stable before a Low-to-High WCLK transition. This RAM
A1 block assumes an active-High WCLK. However, WCLK can be active-High or active-
A2
A3
Low. Any inverter placed on the WCLK input net is absorbed into the block.
A4
The signal output on the data output pin (O3 – O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
X4948
The initial contents of RAM32X4S cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE WCLK D3-D0 O3-O0

0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D3-D0 D3-D0
1 (read) ↓ X Data
Data = word addressed by bits A4 – A0

9-28 Xilinx Development System

Design Elements (RAM32X8)

RAM32X8
32-Deep by 8-Wide Static RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A N/A N/A N/A

D[7-0] RAM32X8 Q[7-0]

RAM32X8 is a 32-word by 8-bit static read-write random access memory. When the
WE
write enable (WE) is High, the data on the data inputs (D7 – D0) is loaded into the
A0 word selected by the address bits (A4 – A0). The data outputs (O7 – O0) reflect the
A1
A2
selected (addressed) word, whether WE is High or Low. When WE is Low, the RAM
A3 content is unaffected by address or input data transitions. The address inputs must be
A4 stable before the High-to- Low WE transition for predictable performance.

X4143
The initial contents of RAM32X8 cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE(mode) D7 – D0 O7 – O0
0(read) X Data
1(write) D7 – D0 Data
Data = word addressed by bits A4 – A0

Libraries Guide, Release M1.5 9-29

Libraries Guide, Release M1.5

O[7:0]

RAM32X1 RAM32X1
D0 O0 D4 O4
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
A4 A4
O0 O4

RAM32X1 RAM32X1
D1 O1 D5 O5
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
A4 A4
O1 O5

RAM32X1 RAM32X1
D2 O2 D6 O6
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
A4 A4
O2 O6

RAM32X1 RAM32X1
D3 O3 D7 O7
D O D O
WE WE
A0 A0
A1 A1
A2 A2
A3 A3
A4 A4
O3 O7

D[7:0]

WE
A0
A1
A2
A3
A4 X7865

Figure 9-6 RAM32X8 Implementation XC4000

9-30 Xilinx Development System

Design Elements (RAM32X8S)

RAM32X8S
32-Deep by 8-Wide Static Synchronous RAM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro N/A N/A Macro Macro Macro

RAM32X8S is a 32-word by 8-bit static random access memory with synchronous

WE RAM32X8S O[7:0]
D[7:0]
write capability. When the write enable (WE) is Low, transitions on the write clock
WCLK
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
A0 any positive transition on WCLK loads the data on the data inputs (D7 – D0) into the
A1 word selected by the 5-bit address (A4 – A0). For predictable performance, address
A2
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
A3
A4 block assumes an active-High WCLK. However, WCLK can be active-High or active-
Low. Any inverter placed on the WCLK input net is absorbed into the block.
X4949
The signal output on the data output pin (O7 – O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
The initial contents of RAM32X8S cannot be specified directly. Initial contents may be
specified only for RAMs that are 1-bit wide and 16 or 32 bits deep. See “Specifying
Initial Contents of a RAM” in the “RAM16X1” section.
Mode selection is shown in the following truth table.

Inputs Outputs

WE (mode) WCLK D7-D0 O7-O0

0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D7-D0 D7-D0
1 (read) ↓ X Data
Data = word addressed by bits A4 – A0

Libraries Guide, Release M1.5 9-31

Libraries Guide, Release M1.5

O[7:0]

RAM32X1S RAM32X1S
O0 O4
WE O WE O
D0 D4
D D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 A3
A4 O0 A4
O4
RAM32X1S RAM32X1S
O1 O5
WE O WE O
D1 D5
D D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 A3
A4 O1 A4 O5
RAM32X1S RAM32X1S
O2 O6
WE O WE O
D2 D6
D D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 A3
A4 O2 A4 O6
RAM32X1S RAM32X1S
O3 O7
WE O WE O
D3 D7
D D
WCLK WCLK
A0 A0
A1 A1
A2 A2
A3 A3
A4 A4 O7
O3
D[7:0]
WE
WCLK
A0
A1
A2
A3
A4
X6417

Figure 9-7 RAM32X8S Implementation XC4000, Spartans, Virtex

9-32 Xilinx Development System

Design Elements (RAMB4_Sn)

RAMB4_Sn
4096-Bit Single-Port Synchronous Block RAM with Port Width (n)
Configured to 1, 2, 4, 8, or 16 Bits

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

RAMB4_S1 DO[0]
RAMB4_S1, RAMB4_S2, RAMB4_S4, RAMB4_S8, and RAMB4_S16 are dedicated
WE
EN random access memory blocks with synchronous write capability. They provide the
RST capability for fast, discrete, large blocks of RAM in each Virtex device.The RAMB4_Sn
CLK
ADDR[11:0]
cell configurations are listed in the following table.
DI[0]

X8416 Component Depth Width Address Bus Data Bus

RAMB4_S1 4096 1 (11:0) (0:0)
WE RAMB4_S2 DO[1:0] RAMB4_S2 2048 2 (10:0) (1:0)
EN
RST RAMB4_S4 1024 4 (9:0) (3:0)
CLK
ADDR[10:0] RAMB4_S8 512 8 (8:0) (7:0)
DI[1:0]
RAMB4_S16 256 16 (7:0) (15:0)

X8415 The enable (EN) pin controls read, write, and reset. When EN is Low, no data is
written and the output (DO) retains the last state. When EN is High and reset (RST) is
WE RAMB4_S4 DO[3:0] High, DO is cleared during the Low-to-High clock (CLK) transition; if write enable
EN (WE) is High, the memory contents reflect the data at DI. When EN is High and WE is
RST Low, the data stored in the RAM address (ADDR) is read during the Low-to-High
CLK
ADDR[9:0] clock transition. When EN and WE are High, the data on the data input (DI) is loaded
DI[3:0] into the word selected by the write address (ADDR) during the Low-to-High clock
transition and the data output (DO) reflects the selected (addressed) word.
X8414
The above description assumes an active High EN, WE, RST, and CLK. However, the
active level can be changed by placing an inverter on the port. Any inverter placed on
WE RAMB4_S8 DO[7:0] a RAMB4 port is absorbed into the block and does not use a CLB resource.
EN
RST
RAMB4_Sn’s may be initialized during configuration. See the “Specifying Initial
CLK Contents of a Block RAM” section below.
ADDR[8:0]
DI[7:0] Block RAM output registers are asynchronously cleared, output Low, when power is
applied. The initial contents of the block RAM are not altered. Virtex simulates power-
X8413 on when global set/reset (GSR) is active. GSR defaults to active-High but can be
inverted by adding an inverter in front of the GSR input of the STARTUP_VIRTEX
symbol.
WE RAMB4_S16 DO[15:0]
EN Mode selection is shown in the following truth table.
RST
CLK
ADDR[7:0]
D1[15:0]

X8412

Libraries Guide, Release M1.5 9-33

Libraries Guide, Release M1.5

Inputs Outputs

EN RST WE CLK ADDR DI DO RAM Contents

0 X X X X X No Chg No Chg
1 1 0 ↑ X X 0 No Chg
1 1 1 ↑ addr data 0 RAM(addr) <=data
1 0 0 ↑ addr X RAM(addr) No Chg
1 0 1 ↑ addr data data RAM(addr) <=data
addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data

Specifying Initial Contents of a Block RAM

You can use the INIT_0x attributes to specify an initial value during device configura-
tion. The initialization of each RAMB4_Sn is set by 16 initialization attributes
(INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the “INIT_0x”
section of the “Attributes, Constraints, and Carry Logic” chapter for more information
on these attributes.
If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization
strings are padded with zeros to the left.

9-34 Xilinx Development System

Design Elements (RAMB4_Sn_Sn)

ENB ENB ENB ENB ENB
RSTB RSTB RSTB RSTB RSTB
DOB[7:0] DOB[15:0] DOB[7:0] DOB[15:0] DOB[15:0]
CLKB CLKB CLKB CLKB CLKB
ADDRB[8:0] ADDRB[7:0] ADDRB[8:0] ADDRB[7:0] ADDRB[7:0]

DIB[7:0] DIB[15:0] DIB[7:0] DIB[15:0] DIB[15:0]

X8399 X8400 X8401 X8402 X8403

X8727

Figure 9-8 RAMB4_Sn_Sn Representations

The RAMB4_Sn_Sn components listed below are 4096-bit dual-ported dedicated
random access memory blocks with synchronous write capability. Each port is inde-
pendent of the other while accessing the same set of 4096 memory cells. Each port is
independently configured to a specific data width.

Libraries Guide, Release M1.5 9-35

Libraries Guide, Release M1.5

Port A Port A Port A Port A Port B Port B Port B Port B

Component
Depth Width ADDR DI Depth Width ADDR DI
RAMB4_S1_S1 4096 1 (11:0) (0:0) 4096 1 (11:0) (0:0)
RAMB4_S1_S2 4096 1 (11:0) (0:0) 2048 2 (10:0) (1:0)
RAMB4_S1_S4 4096 1 (11:0) (0:0) 1024 4 (9:0) (3:0)
RAMB4_S1_S8 4096 1 (11:0) (0:0) 512 8 (8:0) (7:0)
RAMB4_S1_S16 4096 1 (11:0) (0:0) 256 16 (7:0) (15:0)
RAMB4_S2_S2 2048 2 (10:0) (1:0) 2048 2 (10:0) (1:0)
RAMB4_S2_S4 2048 2 (10:0) (1:0) 1024 4 (9:0) (3:0)
RAMB4_S2_S8 2048 2 (10:0) (1:0) 512 8 (8:0) (7:0)
RAMB4_S2_S16 2048 2 (10:0) (1:0) 256 16 (7:0) (15:0)
RAMB4_S4_S4 1024 4 (9:0) (3:0) 1024 4 (9:0) (3:0)
RAMB4_S4_S8 1024 4 (9:0) (3:0) 512 8 (8:0) (7:0)
RAMB4_S4_S16 1024 4 (9:0) (3:0) 256 16 (7:0) (15:0)
RAMB4_S8_S8 512 8 (8:0) (7:0) 512 8 (8:0) (7:0)
RAMB4_S8_S16 512 8 (8:0) (7:0) 256 16 (7:0) (15:0)
RAMB4_S16_S16 256 16 (7:0) (15:0) 256 16 (7:0) (15:0)
ADDR=address bus for the port
DI=data input bus for the port

Each port is fully synchronous with independent clock pins. All port A input pins
have setup time referenced to the CLKA pin and its data output bus DIA has a clock-
to-out time referenced to the CLKA. All port B input pins have setup time referenced
to the CLKB pin and its data output bus DIB has a clock-to-out time referenced to the
CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no
data is written and the output (DOA) retains the last state. When ENA is High and
reset (RSTA) is High, DOA is cleared during the Low-to-High clock (CLKA) transi-
tion; if write enable (WEA) is High, the memory contents reflect the data at DIA.
When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is
read during the Low-to-High clock transition. When ENA and WEA are High, the
data on the data input (DIA) is loaded into the word selected by the write address
(ADDRA) during the Low-to-High clock transition and the data output (DOA)
reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no
data is written and the output (DOB) retains the last state. When ENB is High and
reset (RSTB) is High, DOB is cleared during the Low-to-High clock (CLKB) transition;
if write enable (WEB) is High, the memory contents reflect the data at DIB. When ENB
is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during
the Low-to-High clock transition. When ENB and WEB are High, the data on the data
input (DIB) is loaded into the word selected by the write address (ADDRB) during the
Low-to-High clock transition and the data output (DOB) reflects the selected
(addressed) word.

9-36 Xilinx Development System

Design Elements (RAMB4_Sn_Sn)

The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA,
ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an
inverter on the port. Any inverter placed on a RAMB4 port is absorbed into the block
and does not use a CLB resource.
RAMB_Sn_Sn’s may be initialized during configuration. See “Specifying Initial
Contents of a Block RAM” section below.
Block RAM output registers are asynchronously cleared, output Low, when power is
applied. The initial contents of the block RAM are not altered.Virtex simulates power-
on when global set/reset (GSR) is active. GSR defaults to active-High but can be
inverted by adding an inverter in front of the GSR input of the STARTUP_VIRTEX
symbol.
Mode selection is shown in the following truth table.

Inputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Chg No Chg
1 1 0 ↑ X X 0 No Chg
1 1 1 ↑ addr data 0 RAM(addr) <=data
1 0 0 ↑ addr X RAM(addr) No Chg
1 0 1 ↑ addr data data RAM(addr) <=data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB

Address Mapping
Each port accesses the same set of 4096 memory cells using an addressing scheme that
is dependent on the width of the port. The physical RAM location that is addressed
for a particular width is determined from the following formula.
Start=((ADDR port+1)*(Widthport)) -1
End=(ADDRport)*(Widthport)
The following table shows address mapping for each port width.

Table 9-1 Port Address Mapping

Port Width Port Addresses

1 4096 <----- 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
2 2048 <----- 07 06 05 04 03 02 01 00
4 1024 <----- 03 02 01 00
8 512 <----- 01 00
16 256 <----- 00

Libraries Guide, Release M1.5 9-37

Libraries Guide, Release M1.5

Port A and Port B Conflict Resolution

A RAMB4_Sn_Sn component is a true dual-ported RAM in that it allows simulta-
neous reads of the same memory cell. When one port is performing a write to a given
memory cell, the other port should not address that memory cell (for a write or a read)
within the clock-to-clock setup window.
• If both ports write to the same memory cell simultaneously, violating the clock-to-
setup requirement, the data stored will be invalid.
• If one port attempts to read from the same memory cell that the other is simulta-
neously writing to, violating the clock setup requirement, the write will be
successful but the data read will be invalid.

Specifying Initial Contents of a Block RAM

You can use the INIT_0x attributes to specify an initial value during device configura-
tion. The initialization of each RAMB4_Sn_Sn is set by 16 initialization attributes
(INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the “INIT_0x”
section of the “Attributes, Constraints, and Carry Logic” chapter for more information
on these attributes.
If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization
strings are padded with zeros to the left.

9-38 Xilinx Development System

Design Elements (READBACK)

READBACK
FPGA Bitstream Readback Controller

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Macro Macro Macro N/A Macro Macro N/A

READBACK The READBACK macro accesses the bitstream readback function. A Low-to-High
transition on the TRIG input initiates the readback process. The readback data
CLK DATA
appears on the DATA output. The RIP (readback-in-progress) output remains High
TRIG RIP during the readback process. If you use the ReadAbort:Enable option in BitGen, a
High-to-Low transition on the TRIG input aborts the process. The signal on the CLK
X7756
input clocks out the readback data; if no signal is connected to the CLK input, the
internal CCLK is used. Set the ReadClk option in BitGen to indicate the readback
clock source.
Typically, READBACK inputs are sourced by device-external input pins and outputs
drive device-external output pins. If you want external input and output pins,
connect READBACK pins through IBUFs or OBUFs to pads, as with any I/O device.
However, you can connect READBACK pins to device-internal logic instead. For
details on the READBACK process for each architecture, refer to The Programmable
Logic Data Book.
Note: Virtex provides the readback function through dedicated configuration port
instructions, instead of with a READBACK component as in other FPGA architec-
tures. Refer to the “CAPTURE_VIRTEX” section for information on capturing register
(flip-flop and latch) information for the Virtex readback function.

RDCLK
CLK
I

RDBK
TRIG DATA
TRIG DATA
RIP
RIP

X7866

Figure 9-9 READBACK Implementation XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 9-39

Libraries Guide, Release M1.5

ROM16X1
16-Deep by 1-Wide ROM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive N/A

ROM16X1
ROM16X1 is a 16-word by 1-bit read-only memory. The data output (O) reflects the
A0 O
A1
word selected by the 4-bit address (A3 – A0). The ROM is initialized to a known value
A2 during configuration with the INIT=value parameter. The value consists of four hexa-
A3 decimal digits that are written into the ROM from the most-significant digit A=FH to
the least-significant digit A=0H. For example, the INIT=10A7 parameter produces the
X4137 data stream
0001 0000 1010 0111
An error occurs if the INIT=value is not specified. Refer to the appropriate CAE tool
interface user guide for details.

9-40 Xilinx Development System

Design Elements (ROM32X1)

ROM32X1
32-Deep by 1-Wide ROM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A Primitive Primitive N/A

ROM32X1
ROM32X1 is a 32-word by 1-bit read-only memory. The data output (O) reflects the
A0 O
word selected by the 5-bit address (A4 – A0). The ROM is initialized to a known value
A1
A2
during configuration with the INIT=value parameter. The value consists of eight hexa-
A3 decimal digits that are written into the ROM from the most-significant digit A=1FH to
A4 the least-significant digit A=00H. For example, the INIT=10A78F39 parameter
produces the data stream
X4130
0001 0000 1010 0111 1000 1111 0011 1001
An error occurs if the INIT=value is not specified. Refer to the appropriate CAE tool
interface user guide for details.

Libraries Guide, Release M1.5 9-41

Libraries Guide, Release M1.5

9-42 Xilinx Development System

Chapter 10

Design Elements (SOP3 to XORCY_L)

Libraries Guide, Release M1.5 — 10-1

Libraries Guide, Release M1.5

SOP3-4
Sum of Products

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

SOP3, Macro Macro Macro Macro Macro Macro Macro Macro
SOP3B1A,
SOP3B1B,
SOP3B2A,
SOP3B2B,
SOP3B3
SOP4,
SOP4B1,
SOP4B2A,
SOP4B2B,
SOP4B3,
SOP4B4

SOP3 SOP3B2A
SOP4 SOP4B2B

SOP3B1A SOP3B2B SOP4B1 SOP4B3

SOP3B1B SOP3B3 SOP4B2A SOP4B4

X7867

Figure 10-1 SOP Gate Representations

Sum Of Products macros and primitives provide common logic functions by OR
gating the outputs of two AND functions or the output of one AND function with one
direct input. Variations of inverting and non-inverting inputs are available.

I2
I1 O
I01
I0
OR2
AND2
X8111

Figure 10-2 SOP3 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

10-2 Xilinx Development System

Design Elements (SOP3-4)

I3
I2B3
I2

AND2
O

I1 OR2
I0B1B
I0

AND2
X8112

Figure 10-3 SOP4 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 10-3

Libraries Guide, Release M1.5

SR4CE, SR8CE, SR16CE

4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock
Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

SR4CE, SR8CE, and SR16CE are 4-, 8-, and 16-bit shift registers, respectively, with a
SLI SR4CE Q0
Q1 shift-left serial input (SLI), parallel outputs (Q), and clock enable (CE) and asynchro-
CE Q2 nous clear (CLR) inputs. The CLR input, when High, overrides all other inputs and
C Q3 resets the data outputs (Q) Low. When CE is High and CLR is Low, the data on the SLI
input is loaded into the first bit of the shift register during the Low-to-High clock (C)
CLR
transition and appears on the Q0 output. During subsequent Low-to-High clock tran-
X4145
sitions, when CE is High and CLR is Low, data is shifted to the next highest bit posi-
tion as new data is loaded into Q0 (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The
SLI SR8CE
register ignores clock transitions when CE is Low.
Q[7:0]

CE
Registers can be cascaded by connecting the last Q output (Q3 for SR4CE, Q7 for
C SR8CE, or Q15 for SR16CE) of one stage to the SLI input of the next stage and
connecting clock, CE, and CLR in parallel.
CLR
The register is asynchronously cleared, outputs Low, when power is applied. For
X4151
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
SLI SR16CE
Q[15:0] reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
CE Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
C front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

CLR
X4157
Inputs Outputs

CLR CE SLI C Q0 Qz – Q1
1 X X X 0 0
0 0 X X No Chg No Chg
0 1 1 ↑ 1 qn-1
0 1 0 ↑ 0 qn-1
z = 3 for SR4CE; z = 7for SR8CE; z = 15 for SR16CE
qn-1 = state of referenced output one setup time prior to active clock transition

10-4 Xilinx Development System

Design Elements (SR4CE, SR8CE, SR16CE)

Q[7:0]

FDCE
FDCE Q3 Q4
D Q
SLI Q0
D Q CE
CE
CE C
C CLR
CLR Q4
Q0

FDCE
FDCE Q5
D Q
Q1
D Q CE
CE C
CLR
C
CLR Q5
Q1

FDCE
FDCE Q6
D Q
Q2
D Q CE
CE C
CLR
C
CLR Q6
Q2

FDCE
FDCE Q7
D Q
Q3
D Q CE
CE C
CLR
C
CLR Q7
Q3

C
CLR
X7868

Figure 10-4 SR8CE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 10-5

Libraries Guide, Release M1.5

SR4CLE, SR8CLE, SR16CLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers
with Clock Enable and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

SR4CLE, SR8CLE, and SR16CLE are 4-, 8-, and 16-bit shift registers, respectively, with
SLI SR4CLE
D0 Q0 a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control
D1 Q1 inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR).The register
D2 Q2 ignores clock transitions when L and CE are Low. The asynchronous CLR, when
D3 Q3
High, overrides all other inputs and resets the data outputs (Q) Low. When L is High
L and CLR is Low, data on the Dn – D0 inputs is loaded into the corresponding Qn – Q0
bits of the register. When CE is High and L and CLR are Low, data on the SLI input is
CE
loaded into the first bit of the shift register during the Low-to-High clock (C) transi-
C
tion and appears on the Q0 output. During subsequent clock transitions, when CE is
High and L and CLR are Low, the data is shifted to the next highest bit position as
CLR
X4147
new data is loaded into Q0 (SLI→Q0, Q0→Q1, Q1→Q2, and so forth).
Registers can be cascaded by connecting the last Q output (Q3 for SR4CLE, Q7 for
SLI SR8CLE SR8CLE, or Q15 for SR16CLE) of one stage to the SLI input of the next stage and
D[7:0] connecting clock, CE, L, and CLR inputs in parallel.
Q[7:0] The register is asynchronously cleared, outputs Low, when power is applied. For
L CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
CE
C
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
CLR
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
X4153

SLI SR16CLE Inputs Outputs

D[15:0]
CLR L CE SLI Dn – D0 C Q0 Qz – Q1
Q[15:0]

L
1 X X X X X 0 0
0 1 X X Dn – D0 ↑ d0 dn
CE
C 0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Chg No Chg
CLR
X4159 z = 3 for SR4CLE; z = 7 for SR8CLE; z = 15 for SR16CLE
dn = state of referenced input one setup time prior to active clock transition
qn-1 = state of referenced output one setup time prior to active clock transition

10-6 Xilinx Development System

Design Elements (SR4CLE, SR8CLE, SR16CLE)

Q[7:0]

CE
L_OR_CE

L OR2

M2_1 FDCE
M2_1 FDCE D0
SLI D0 O MD4 Q4
O MD0 Q0 D4 D1 D Q
D0 D1 D Q
S0 MQ4 CE
S0 MQ0 CE
C
C CLR
CLR
Q4
Q0

M2_1 FDCE
M2_1 FDCE D0
D0 O MD5 Q5
O MD1 Q1 D5 D1 D Q
D1 D1 D Q
S0 MQ5 CE
S0 MQ1 CE
C
C CLR
CLR
Q5
Q1

M2_1 FDCE
M2_1 FDCE D0
D0 O MD6 Q6
O MD2 Q2 D6 D1 D Q
D2 D1 D Q
S0 MQ6 CE
S0 MQ2 CE
C
C CLR
CLR
Q6
Q2

M2_1 FDCE
M2_1 FDCE D0
D0 O MD7 Q7
O MD3 Q3 D7 D1 D Q
D3 D1 D Q
S0 MQ7 CE
S0 MQ3 CE
C
C CLR
CLR
Q7
Q3

CLR
C
D[7:0] X7869

Figure 10-5 SR8CLE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 10-7

Libraries Guide, Release M1.5

SR4CLED, SR8CLED, SR16CLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Asynchronous
Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

SLI SR4CLED SR4CLED, SR8CLED, and SR16CLED are 4-, 8-, and 16-bit shift registers, respectively,
D0 Q0 with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), and four
D1 Q1 control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), and asyn-
D2 Q2
Q3
chronous clear (CLR). The register ignores clock transitions when CE and L are Low.
D3
SRI The asynchronous clear, when High, overrides all other inputs and resets the data
L outputs (Qn) Low. When L is High and CLR is Low, the data on the D inputs is loaded
LEFT
into the corresponding Q bits of the register. When CE is High and L and CLR are
CE
C
Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is
High, data on the SLI is loaded into Q0 during the Low-to-High clock transition and
CLR
shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is
X4149 Low, data on the SRI is loaded into the last Q output (Q3 for SR4CLED, Q7 for
SR8CLED, or Q15 for SR16CLED) during the Low-to-High clock transition and
shifted right (to Q2, Q1,... for SR4CLED; to Q6, Q5,... for SR8CLED; and to Q14, Q13,...
SLI SR8CLED
D[7:0]
for SR16CLED) during subsequent clock transitions. The truth tables for SR4CLED,
SRI
SR8CLED, and SR16CLED indicate the state of the Q outputs under all input condi-
Q[7:0] tions for SR4CLED, SR8CLED, and SR16CLED.
L
LEFT The register is asynchronously cleared, outputs Low, when power is applied. For
CE CPLDs, the power-on condition can be simulated by applying a High-level pulse on
C the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
CLR Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
X4155
front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

SLI SR16CLED
D[15:0]
Inputs Outputs
SRI
Q[15:0]

L
CLR L CE LEFT SLI SRI D3 – D0 C Q0 Q3 Q2 – Q1
LEFT
1 X X X X X X X 0 0 0
CE
C 0 1 X X X X D3– D0 ↑ d0 d3 dn
0 0 0 X X X X X No Chg No Chg No Chg
CLR
X4161 0 0 1 1 SLI X X ↑ SLI q2 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
dn = state of referenced input one setup time prior to active clock transition
qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition

SR4CLED Truth Table

10-8 Xilinx Development System

Design Elements (SR4CLED, SR8CLED, SR16CLED)

Inputs Outputs

CLR L CE LEFT SLI SRI D7 – D0 C Q0 Q7 Q6 – Q1

1 X X X X X X X 0 0 0
0 1 X X X X D7 – D0 ↑ d0 d7 dn
0 0 0 X X X X X No Chg No Chg No Chg
0 0 1 1 SLI X X ↑ SLI q6 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
dn = state of referenced input one setup time prior to active clock transition
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR8CLED Truth Table

Inputs Outputs

CLR L CE LEFT SLI SRI D15 – D0 C Q0 Q15 Q14 – Q1

1 X X X X X X X 0 0 0
0 1 X X X X D15 – D0 ↑ d0 d15 dn
0 0 0 X X X X X No Chg No Chg No Chg
0 0 1 1 SLI X X ↑ SLI q14 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
dn = state of referenced input one setup time prior to active clock transition
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR16CLED Truth Table

Libraries Guide, Release M1.5 10-9

Libraries Guide, Release M1.5

CE L_OR_CE

OR2
M2_1 FDCE
M2_1 D0 Q[7:0]
SLI D0 O MDR0 Q0
O MDL0 D1 D Q
D0 D1
S0 MDR0 CE
S0 MDL0
C
CLR
Q0

M2_1 FDCE
M2_1 D0
D0 O MDR1 Q1
O MDL1 D1 D Q
D1 D1
S0 MDR1 CE
S0 MDL1
C
CLR
Q1

M2_1 FDCE
M2_1 D0
D0 O MDR2 Q2
O MDL2 D1 D Q
D2 D1
S0 MDR2 CE
S0 MDL2
C
CLR
Q2

M2_1 FDCE
M2_1 D0
D0 O MDR3 Q3
O MDL3 D1 D Q
D3 D1
S0 MDR3 CE
S0 MDL3
C
CLR
Q3

M2_1 FDCE
M2_1 D0
D0 O MDR4 Q4
O MDL4 D1 D Q
D4 D1
S0 MDR4 CE
S0 MDL4
C
CLR
Q4

M2_1 FDCE
M2_1 D0
D0 O MDR5 Q5
O MDL5 D1 D Q
D5 D1
S0 MDR5 CE
S0 MDL5
C
CLR
Q5

M2_1 FDCE
M2_1 D0
D0 O MDR6 Q6
O MDL6 D1 D Q
D6 D1
S0 MDR6 CE
S0 MDL6
C
CLR
Q6

M2_1 FDCE
M2_1 D0
D0 O MDR7 Q7
D[7:0] O MDL7 D1 D Q
D7 D1
S0 MDR7 CE
L S0 MDL7
C
SRI CLR
Q7
L_LEFT
LEFT

CLR OR2
C X7870

Figure 10-6 SR8CLED Implementation XC3000, XC4000, XC5200, Spartans,

Virtex

10-10 Xilinx Development System

Design Elements (SR4CLED, SR8CLED, SR16CLED)

VCC
±5

CE L_OR_CE

AND2
OR2
M2_1 FDCE
M2_1 D0 Q[7:0]
SLI D0 O MDR0 Q0
O MDL0 D1 D Q
D0 D1
S0 MDR0 CE
S0 MDL0
C
CLR
Q0

M2_1 FDCE
M2_1 D0
D0 O MDR1 Q1
O MDL1 D1 D Q
D1 D1
S0 MDR1 CE
S0 MDL1
C
CLR
Q1

M2_1 FDCE
M2_1 D0
D0 O MDR2 Q2
O MDL2 D1 D Q
D2 D1
S0 MDR2 CE
S0 MDL2
C
CLR
Q2

M2_1 FDCE
M2_1 D0
D0 O MDR3 Q3
O MDL3 D1 D Q
D3 D1
S0 MDR3 CE
S0 MDL3
C
CLR
Q3

M2_1 FDCE
M2_1 D0
D0 O MDR4 Q4
O MDL4 D1 D Q
D4 D1
S0 MDR4 CE
S0 MDL4
C
CLR
Q4

M2_1 FDCE
M2_1 D0
D0 O MDR5 Q5
O MDL5 D1 D Q
D5 D1
S0 MDR5 CE
S0 MDL5
C
CLR
Q5

M2_1 FDCE
M2_1 D0
D0 O MDR6 Q6
O MDL6 D1 D Q
D6 D1
S0 MDR6 CE
S0 MDL6
C
CLR
Q6

M2_1 FDCE
M2_1 D0
D0 O MDR7 Q7
D[7:0] O MDL7 D1 D Q
D7 D1
S0 MDR7 CE
S0 MDL7
C
CLR
L

LEFT OR2 L_LEFT Q7

OR2 OR2

GND
SRI
CLR X8108
C

Figure 10-7 SR8CLED Implementation XC9000

Libraries Guide, Release M1.5 10-11

Libraries Guide, Release M1.5

SR4RE, SR8RE, SR16RE

4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock
Enable and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

SR4RE
SR4RE, SR8RE, and SR16RE are 4-, 8-, and 16-bit shift registers, respectively, with
SLI Q0
Q1 shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE), and synchronous
CE Q2 reset (R) inputs. The R input, when High, overrides all other inputs during the Low-
C Q3 to-High clock (C) transition and resets the data outputs (Q) Low. When CE is High
and R is Low, the data on the SLI is loaded into the first bit of the shift register during
R the Low-to-High clock (C) transition and appears on the Q0 output. During subse-
X4144
quent Low-to-High clock transitions, when CE is High and R is Low, data is shifted to
the next highest bit position as new data is loaded into Q0 (SLI→Q0, Q0→Q1,
SLI SR8RE Q1→Q2, and so forth). The register ignores clock transitions when CE is Low.
Q[7:0]

CE Registers can be cascaded by connecting the last Q output (Q3 for SR4RE, Q7 for
C SR8RE, or Q15 for SR16RE) of one stage to the SLI input of the next stage and
connecting clock, CE, and R in parallel.
R
X4150 The register is asynchronously cleared, outputs Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
SLI SR16RE
Q[15:0]
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
CE
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
C front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

X4156 Inputs Outputs

R CE SLI C Q0 Qz – Q1
1 X X ↑ 0 0
0 0 X X No Chg No Chg
0 1 1 ↑ 1 qn-1
0 1 0 ↑ 0 qn-1
z = 3 for SR4RE; z = 7 for SR8RE; z = 15 for SR16RE
qn-1 = state of referenced output one setup time prior to active clock transition

10-12 Xilinx Development System

Design Elements (SR4RE, SR8RE, SR16RE)

Q[7:0]

FDRE
FDRE Q3 Q4
D Q
SLI Q0
D Q CE
CE
CE C
C R
R Q4
Q0

FDRE
FDRE Q5
D Q
Q1
D Q CE
CE C
R
C
R Q5
Q1

FDRE
FDRE Q6
D Q
Q2
D Q CE
CE C
R
C
R Q6
Q2

FDRE
FDRE Q7
D Q
Q3
D Q CE
CE C
R
C
R Q7
Q3

C
R
X7871

Figure 10-8 SR8RE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 10-13

Libraries Guide, Release M1.5

SR4RLE, SR8RLE, SR16RLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers
with Clock Enable and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

SLI
SR4RLE, SR8RLE, and SR16RLE are 4-, 8-, and 16-bit shift registers, respectively, with
SR4RLE
D0 Q0 shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control
D1 Q1 inputs — clock enable (CE), load enable (L), and synchronous reset (R). The register
D2 Q2 ignores clock transitions when L and CE are Low. The synchronous R, when High,
D3 Q3
overrides all other inputs during the Low-to-High clock (C) transition and resets the
L data outputs (Q) Low. When L is High and R is Low, data on the D inputs is loaded
into the corresponding Q bits of the register. When CE is High and L and R are Low,
CE
data on the SLI input is loaded into the first bit of the shift register during the Low-to-
C
High clock (C) transition and appears on the Q0 output. During subsequent clock
transitions, when CE is High and L and R are Low, the data is shifted to the next
R
X4146
highest bit position as new data is loaded into Q0 (SLI→Q0, Q0→Q1, Q1→Q2, and so
forth).

SLI SR8RLE
Registers can be cascaded by connecting the last Q output (Q3 for SR4RLE, Q7 for
D[7:0] SR8RLE, or 15 for SR16RLE) of one stage to the SLI input of the next stage and
connecting clock, CE, L, and R inputs in parallel.
Q[7:0]

L The register is asynchronously cleared, outputs Low, when power is applied. For
CPLDs, the power-on condition can be simulated by applying a High-level pulse on
CE
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
C
reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
R
X4152 front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

SLI SR16RLE
D[15:0] Inputs Outputs

Q[15:0] R L CE SLI Dz – D0 C Q0 Qz – Q1
L
1 X X X X ↑ 0 0
CE 0 1 X X Dz – D0 ↑ d0 dn
C
0 0 1 SLI X ↑ SLI qn-1
R 0 0 0 X X X No Chg No Chg
X4158
z = 3 for SR4RLE; z = 7 for SR8RLE; z = 15 for SR16RLE
dn = state of referenced input one setup time prior to active clock transition
qn-1 = state of referenced output one setup time prior to active clock transition

10-14 Xilinx Development System

Design Elements (SR4RLE, SR8RLE, SR16RLE)

Q[7:0]

CE
L_OR_CE

L OR2

M2_1 FDRE
M2_1 FDRE Q3 D0
SLI D0 O MD4 Q4
O MD0 Q0 D4 D1 D Q
D0 D1 D Q
S0 MQ4 CE
S0 MQ0 CE
C
C R
R
Q4
Q0

M2_1 FDRE
M2_1 FDRE D0
D0 O MD5 Q5
O MD1 Q1 D5 D1 D Q
D1 D1 D Q
S0 MQ5 CE
S0 MQ1 CE
C
C R
R
Q5
Q1

M2_1 FDRE
M2_1 FDRE D0
D0 O MD6 Q6
O MD2 Q2 D6 D1 D Q
D2 D1 D Q
S0 MQ6 CE
S0 MQ2 CE
C
C R
R
Q6
Q2

M2_1 FDRE
M2_1 FDRE D0
D0 O MD7 Q7
O MD3 Q3 D7 D1 D Q
D3 D1 D Q
S0 MQ7 CE
S0 MQ3 CE
C
C R
R
Q7
Q3

R
C
D[7:0]
X7872

Figure 10-9 SR8RLE Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

Libraries Guide, Release M1.5 10-15

Libraries Guide, Release M1.5

SR4RLED, SR8RLED, SR16RLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Synchronous
Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro Macro

SLI SR4RLED
SR4RLED, SR8RLED, and SR16RLED are 4-, 8-, and 16-bit shift registers, respectively,
D0 Q0 with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), and four
D1 Q1 control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), and
D2 Q2
synchronous reset (R). The register ignores clock transitions when CE and L are Low.
D3 Q3
SRI
The synchronous R, when High, overrides all other inputs during the Low-to-High
L clock (C) transition and resets the data outputs (Q) Low. When L is High and R is Low,
LEFT the data on the D inputs is loaded into the corresponding Q bits of the register. When
CE
CE is High and L and R are Low, data is shifted right or left, depending on the state of
C
the LEFT input. If LEFT is High, data on SLI is loaded into Q0 during the Low-to-
High clock transition and shifted left (to Q1, Q2, and so forth) during subsequent
R
X4148
clock transitions. If LEFT is Low, data on the SRI is loaded into the last Q output (Q3
for SR4RLED, Q7 for SR8RLED, or Q15 for SR16RLED) during the Low-to-High clock
transition and shifted right (to Q2, Q1,... for SR4RLED; to Q6, Q5,... for SR8RLED; or
SLI SR8RLED to Q14, Q13,... for SR16RLED) during subsequent clock transitions. The truth table
D[7:0]
indicates the state of the Q outputs under all input conditions.
SRI
Q[7:0] The register is asynchronously cleared, outputs Low, when power is applied. For
L CPLDs, the power-on condition can be simulated by applying a High-level pulse on
LEFT
CE
the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/
C reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000,
Spartans, Virtex) default to active-High but can be inverted by adding an inverter in
R front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
X4154

SLI SR16RLED Inputs Outputs

D[15:0]

SRI R L CE LEFT SLI SRI D3 – D0 C Q0 Q3 Q2 – Q1

Q[15:0]

L
1 X X X X X X ↑ 0 0 0
LEFT
0 1 X X X X D3 – D0 ↑ d0 d3 dn
CE
C 0 0 0 X X X X X No Chg No Chg No Chg
0 0 1 1 SLI X X ↑ SLI q2 qn-1
R
X4160 0 0 1 0 X SRI X ↑ q1 SRI qn+1
dn = state of referenced input one setup time prior to active clock transition
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR4RLED Truth Table

10-16 Xilinx Development System

Design Elements (SR4RLED, SR8RLED, SR16RLED)

Inputs Outputs

R L CE LEFT SLI SRI D7– D0 C Q0 Q7 Q6 – Q1

1 X X X X X X ↑ 0 0 0
0 1 X X X X D7 – D0 ↑ d0 d7 dn
0 0 0 X X X X X No Chg No Chg No Chg
0 0 1 1 SLI X X ↑ SLI q6 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
dn = state of referenced input one setup time prior to active clock transition
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR8RLED Truth Table

Inputs Outputs

R L CE LEFT SLI SRI D15 – D0 C Q0 Q15 Q14 – Q1

1 X X X X X X ↑ 0 0 0
0 1 X X X X D15 – D0 ↑ d0 d15 dn
0 0 0 X X X X X No Chg No Chg No Chg
0 0 1 1 SLI X X ↑ SLI q14 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
dn = state of referenced input one setup time prior to active clock transition
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR16RLED Truth Table

Libraries Guide, Release M1.5 10-17

Libraries Guide, Release M1.5

CE
L_OR_CE

OR2
M2_1 FDRE
M2_1 D0 Q[7:0]
SLI D0 O MDR0 Q0
O MDL0 D1 D Q
D0 D1 CE
S0 MDR0
S0 MDLO C
R
Q0

M2_1 FDRE
M2_1 D0
D0 O MDR1
D Q
Q1
O MDL1 D1
D1 D1 CE
S0 MDR1
S0 MDL1 C
R
Q1

M2_1 FDRE
M2_1 D0
D0 O MDR2
D Q
Q2
O MDL2 D1
D2 D1 CE
S0 MDR2
S0 MDL2 C
R
Q2

M2_1 FDRE
M2_1 D0
D0 O MDR3
D Q
Q3
O MDL3 D1
D3 D1 CE
S0 MDR3
S0 MDL3 C
R
Q3

M2_1 FDRE
M2_1 D0
D0 O MDR4
D Q
Q4
O MDL4 D1
D4 D1 CE
S0 MDR4
S0 MDL4 C
R
Q4

M2_1 FDRE
M2_1 D0
D0 O MDR5
D Q
Q5
O MDL5 D1
D5 D1 CE
S0 MDR5
S0 MDL5 C
R
Q5

M2_1 FDRE
M2_1 D0
D0 O MDR6
D Q
Q6
O MDL6 D1
D6 D1 CE
S0 MDR6
S0 MDL6 C
R
Q6

M2_1 FDRE
M2_1 D0
D0 O MDR7
D Q
Q7
D[7:0] O MDL7 D1
D7 D1 CE
S0 MDR7
MDL7 C
L S0
R
SRI
Q7
L_LEFT
LEFT

R OR2
C X8688

Figure 10-10 SR8RLED Implementation XC3000, XC4000, XC5200, XC9000,

Spartans, Virtex

10-18 Xilinx Development System

Design Elements (SRL16)

SRL16
16-Bit Shift Register Look-Up-Table (LUT)

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

SRL16 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the
D SRL16 Q
CLK
output length of the shift register. The shift register may be of a fixed, static length or
A0 dynamically adjusted.
A1
A2 The shift register LUT contents are initialized by assigning a four-digit hexadecimal
A3 number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
X8420
(0000) so that the shift register LUT is cleared during configuration.
The data (D) is loaded into the first bit of the shift register during the Low-to-High
clock (CLK) transition and appears on the Q output. During subsequent Low-to-High
clock transitions data is shifted to the next highest bit position as new data is loaded
into Q.

Static Length Mode

To get a fixed length shift register, drive the A3 through A0 inputs with static values.
The length of the shift register can vary from 1 bit to 16 bits as determined from the
following formula:
Length = (8*A3) +(4*A2) + (2*A1) + A0 +1
If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are
all ones (1111), it is 16 bits long.

N/A Primitive Primitive Primitive N/A Primitive Primitive N/A

XC4000, Spartans The STARTUP primitive is used for Global Set/Reset, global 3-state control, and the
GSR STARTUP Q2 user configuration clock. The Global Set/Reset (GSR) input, when High, sets or resets
GTS Q3
Q1Q4
every flip-flop in the device, depending on the initialization state (S or R) of the flip-
CLK DONEIN flop. Following configuration, the global 3-state control (GTS), when High, forces all
the IOB outputs into high impedance mode, which isolates the device outputs from
X8060
the circuit but leaves the inputs active.
XC5200
Including the STARTUP symbol in a design is optional. You must include the symbol
GR STARTUP Q2
GTS
under the following conditions.
Q3
Q1Q4
• If you intend to exert external control over global set/reset, you must connect the
CLK DONEIN
GSR pin to an IPAD and an IBUF, as shown here. (For the XC5200, connect the GR
X8732
pin to an IPAD and an IBUF.)

GSR STARTUP Q2
GTS Q3
Q1Q4
CLK DONEIN

X6970

• If you intend to exert external control over global tristate, you must connect the
GTS pin to an IPAD and IBUF, as shown here.

GSR STARTUP Q2
GTS Q3
Q1Q4
CLK DONEIN

X3911

• If you wish to synchronize startup to a user clock, you must connect the user
clock signal to the CLK input, as shown here. Furthermore, “user clock” must be
selected in the BitGen program.

GSR STARTUP Q2
GTS Q3
Q1Q4
CLK DONEIN

X6972

You can use location constraints to specify the pin from which GSR or GTS (or both) is
accessed.
The STARTUP outputs (Q2, Q3, Q1Q4, and DONEIN) display the progress/status of
the start-up process following the configuration. Refer to The Programmable Logic Data
Book for additional details.

Libraries Guide, Release M1.5 10-23

Libraries Guide, Release M1.5

STARTUP_VIRTEX
Virtex User Interface to Global Clock, Reset, and 3-State Controls

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

STARTUP_VIRTEX The STARTUP_VIRTEX primitive is used for Global Set/Reset, global 3-state control,
GSR and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets
GTS or resets all flip-flops, all latches, and every block RAM (RAMB4) output register in
the device, depending on the initialization state (S or R) of the component.
CLK
Note: Block RAMB4 content, LUT RAMs, delay locked loop elements (CLKDLL,
X8682
CLKDLLHF, BUFGDLL), and shift register LUTs (SRL16, SRL16_1, SRL16E,
SRL16E_1) are not set/reset.
Following configuration, the global 3-state control (GTS), when High—and BSCAN is
not enabled and executing an EXTEST instruction—forces all the IOB outputs into
high impedance mode, which isolates the device outputs from the circuit but leaves
the inputs active.
Including the STARTUP symbol in a design is optional. You must include the symbol
under the following conditions.
• If you intend to exert external control over global set/reset, you must connect the
GSR pin to a top level port and an IBUF, as shown here.
STARTUP_VIRTEX
GSR
GTS

CLK

X8683

• If you intend to exert external control over global tristate, you must connect the
GTS pin to a top level port and IBUF, as shown here.
STARTUP_VIRTEX
GSR
GTS

CLK

X8684

• If you wish to synchronize startup to a user clock, you must connect the user
clock signal to the CLK input, as shown here. Furthermore, “user clock” must be
selected in the BitGen program.
STARTUP_VIRTEX
GSR
GTS

CLK

X8685

You can use location constraints to specify the pin from which GSR or GTS (or both) is
accessed.

10-24 Xilinx Development System

Design Elements (TCK)

TCK
Boundary Scan Test Clock Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive N/A

TCK
The TCK input pad is connected to the boundary scan test clock, which shifts the
serial data and instructions into and out of the boundary scan data registers. The func-
X3895 tion of the TCK pad is device configuration dependent and can be used as follows.
• During configuration TCK is connected to the boundary scan logic.
• After configuration, if boundary scan is not used, the TCK pad is unrestricted and
can be used by the routing tool as an input/output pad.
• After configuration, if boundary scan is used, the TCK pad can be used for user-
logic input by connecting it directly to the user logic.

Libraries Guide, Release M1.5 10-25

Libraries Guide, Release M1.5

TDI
Boundary Scan Test Data Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive N/A

The TDI input pad is connected to the boundary scan TDI input. It loads instructions
TDI
and data on the Low-to-High TCK transition. The function of the TDI pad is device
X3897 configuration dependent and can be used as follows.
• During configuration, TDI is connected to the boundary scan logic.
• After configuration, if boundary scan is not used, the TDI pad is unrestricted and
can be used by the routing tools as an input/output pad.
• After configuration, if boundary scan is used, the TDI pad can be used for user-
logic input by connecting the TDI pad directly to the user logic.

10-26 Xilinx Development System

Design Elements (TDO)

TDO
Boundary Scan Data Output Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive N/A

The TDO data output pad is connected to the boundary scan TDO output. It is
TDO connected to the external circuit to provide the boundary scan data for each Low-to-
X3899 High TCK transition. The function of the TDO pad is device configuration dependent
and can be used as follows.
• During configuration, TDO is connected to the boundary scan logic.
• After configuration, if boundary scan is not used, the TDO pad can be used as a
bidirectional 3-state I/O pad by the routing tool.
• After configuration, if boundary scan is used, the TDO pad is still used as an
output from the boundary scan logic.

Libraries Guide, Release M1.5 10-27

Libraries Guide, Release M1.5

TIMEGRP
Schematic-Level Table of Basic Timing Specification Groups

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

The TIMEGRP primitive table defines timing groups used in “from-to” TIMESPEC
statements in terms of other groups. The TIMEGRP table is shown in the following
figure.

T I MEG R P

X4699
These groups can include predefined groups, such as “ffs,” groups created by using
TNM attributes, such as TNM-reg on schematics, and other groups defined by a state-
ment in the TIMEGRP symbol.
The following sample statement defines groups in a TIMEGRP symbol.
TIMEGRP=all_but_regs=ffs:except:regs
The table can contain up to 8 statements of any character length, but only 30 charac-
ters are displayed in the symbol.
Note: When entering timegroup properties into a TIMEGRP symbol, some property
names should not be used because they cause a conflict with the predefined (reserved)
property names of the TIMEGRP primitive.
The standard procedure for adding a property to a symbol is to use the following
command.
PROPERTY = property_name VALUE=value
For property_name you must not use any of the system reserved names LIBVER, INST,
COMP, MODEL, or any other names reserved by your schematic capture program.
Please consult your schematic capture documentation to familiarize yourself with
reserved property names.
For more on time group attributes, see the “Time Group Attributes” section of the
“Attributes, Constraints, and Carry Logic” chapter.

10-28 Xilinx Development System

Design Elements (TIMESPEC)

TIMESPEC
Schematic-Level Timing Requirement Table

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

The TIMESPEC primitive is a table that you can use to specify up to eight timing
attributes (TS). TS attributes can be any length, but only 30 characters are displayed in
the TIMESPEC window. The TIMESPEC table is displayed in the following figure.

TIMESPEC

X3866

For more information on "TS" timing attributes refer to the “TSidentifier” section of
the “Attributes, Constraints, and Carry Logic” chapter.

Libraries Guide, Release M1.5 10-29

Libraries Guide, Release M1.5

TMS
Boundary Scan Test Mode Select Input Pad

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive Primitive N/A Primitive Primitive N/A

The TMS input pad is connected to the boundary scan TMS input. It determines
TMS
which boundary scan operation is performed. The function of the TMS pad is device
X3901 configuration dependent and can be used as follows.
• During configuration, TMS is connected to the boundary scan logic.
• After configuration, if boundary scan is not used, the TMS pad is unrestricted and
can be used by the routing tools as an input/output pad.
• After configuration, if boundary scan is used, the TMS pad can be used for user-
logic input by connecting the TMS pad directly to the user logic.

10-30 Xilinx Development System

Design Elements (UPAD)

UPAD
Connects the I/O Node of an IOB to the Internal PLD Circuit

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive N/A Primitive Primitive Primitive

UPAD
A UPAD allows the use of any unbonded IOBs in a device. It is used the same way as
a IOPAD except that the signal output is not visible on any external device pins.

X3843

Libraries Guide, Release M1.5 10-31

Libraries Guide, Release M1.5

VCC
VCC-Connection Signal Tag

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

VCC The VCC signal tag or parameter forces a net or input function to a logic High level. A
net tied to VCC cannot have any other source.

X8721 When the placement and routing software encounters a net or input function tied to
VCC, it removes any logic that is disabled by the VCC signal. The VCC signal is only
implemented when the disabled logic cannot be removed.

10-32 Xilinx Development System

Design Elements (WAND1, 4, 8, 16)

WAND1, 4, 8, 16
Open-Drain Buffers

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

WAND1 N/A Primitive Primitive N/A N/A N/A N/A N/A
WAND4, N/A Macro Macro N/A N/A N/A N/A N/A
WAND8.
WAND16

WAND1 WAND1, WAND4, WAND8, and WAND16 are single and multiple open-drain
buffers. Each buffer has an input (I) and an open-drain output (O). When any of the
inputs is Low, the output is Low. When all the inputs are High, the output is off. To
X3905 obtain a High output, add pull-up resistors to the output (O). One pull-up resistor
uses the least power, and two pull-up resistors achieve the fastest Low-to-High transi-
tion.
I1 WAND4
I2 To indicate two pull-up resistors, add a DOUBLE parameter to the pull-up symbol
I3
attached to the output (O) node. Refer to the appropriate CAE tool interface user
I4 O
guide for details.
X3915
I0 O

WAND1
I[7:0] I1
WAND8
O WAND1
I2

WAND1
X3916 I3

WAND1
I4
I[15:0] WAND16
WAND1
O
I5

WAND1
X3917 I6

WAND1
I7

I[ 7: 0] WAND1

X7873

Figure 10-11 WAND8 Implementation XC4000

Libraries Guide, Release M1.5 10-33

Libraries Guide, Release M1.5

WOR2AND
2-Input OR Gate with Wired-AND Open-Drain Buffer Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A Primitive Primitive N/A N/A N/A N/A N/A

WOR2AND is a 2-input (I1 and I2) OR gate/buffer with an open-drain output (O). It
is used in bus applications by tying multiple open-drain outputs together. When both
inputs (I1 and I2) are Low, the output (O) is Low. When either input is High, the
X3906 output is off; wor2and cannot source or sink current. To establish an output High
level, tie a pull-up resistor(s) to the output (O). One pull-up resistor uses the least
power, two pull-up resistors achieve the fastest Low-to-High speed.
To indicate two pull-up resistors, append a DOUBLE parameter to the pull-up symbol
attached to the output (O) node. Refer to the appropriate CAE tool interface user
guide for details.

10-34 Xilinx Development System

Design Elements (XNOR2-9)

XNOR2-9
2- to 9-Input XNOR Gates with Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

XNOR2, Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
XNOR3,
XNOR4
XNOR5 Primitive Primitive Primitive Macro Macro Primitive Primitive Primitive
XNOR6, Macro Macro Macro Macro Macro Macro Macro Macro
XNOR7,
XNOR8,
XNOR9

XNOR2

XNOR7
XNOR3

XNOR4

XNOR8

XNOR5

XNOR6 XNOR9
X6966

Figure 10-12 XNOR Gate Representations

The XNOR function is performed in the Configurable Logic Block (CLB) function
generators in XC3000, XC4000, and Spartans. XNOR functions of up to nine inputs are
available. All inputs are non-inverting. Because each input uses a CLB resource,
replace functions with unused inputs with functions having the necessary number of
inputs.

Libraries Guide, Release M1.5 10-35

Libraries Guide, Release M1.5

I4
I3 I35
I2
I1 XOR3 O
I0
XNOR3

X8106

Figure 10-13 XNOR5 Implementation XC5200

I0
I1
I2
XOR3 O

I3
XNOR2
I4

XOR2
X7836

Figure 10-14 XNOR5 Implementation XC9000

I0
I1
I2
XOR3 O
I3
I4 XNOR2
I5
XOR3

X7876

Figure 10-15 XNOR6 Implementation XC9000

I6
I5 I46
I4
I3
XOR3
I2 O
I1
XNOR5
I0

X7575

Figure 10-16 XNOR7 Implementation XC3000

I6
I5 I46
I4 XOR3
I3 O
I2 I13
I1 XOR3 XNOR3
I0

X7576

Figure 10-17 XNOR7 Implementation XC4000, XC5200, Spartans

I0
I1
I2
I3
O
XOR4
I4
I5 XNOR2
I6
XOR3
X8205

Figure 10-18 XNOR7 Implementation XC9000

10-36 Xilinx Development System

Design Elements (XNOR2-9)

I6 FMAP
I6
I5 I4
I36 I5
I4 I3 I36
I4 O
I3 I2
I3
XOR4 I1

I2 RLOC=R0C0.S1
O

FMAP
XNOR4 I36
I4
I2
I1 I3 O
I1 O
I0 I2
I0
I1

X8699 RLOC=R0C0.S1

Figure 10-19 XNOR7 Implementation Virtex

I7
I6
I47
I5
I4
I3 XOR4
I2 O
I1
I0
XNOR5
X7874

Figure 10-20 XNOR8 Implementation XC3000

I7
I6
I47
I5
I4
XOR4 O
I3
I2 I13
XNOR3
I1
XOR3
I0

X7875

Figure 10-21 XNOR8 Implementation XC4000, XC5200, Spartans

I0
I1
I2
I3
O
I4 XOR4

I5 XNOR2
I6
I7
XOR4
X7877

Figure 10-22 XNOR8 Implementation XC9000

Libraries Guide, Release M1.5 10-37

Libraries Guide, Release M1.5

FMAP
I4
I3 O
S1 O
I2
S2
I1
I7
I6 RLOC=R0C0.S0
S1
I5
I4
FMAP
XOR4
I7
I4
I6
O I3 S1
I5 O
I2
I4
XNOR2 I1
I3
RLOC=R0C0.S1
I2
S0
I1
I0 FMAP
XOR4 I3
I4
I2
I3 S0
I1 O
I2
I0
I1

X8697 RLOC=R0C0.S1

Figure 10-23 XNOR8 Implementation Virtex

I8
I7
I6 I48
I5
XOR5
I4
I3
I2 O
I1
XNOR5
I0

X7577

Figure 10-24 XNOR9 Implementation XC3000

I8
I7
I58
I6
I5 XOR4 O
I4
I3
I14 XNOR3
I2
I1
XOR4
I0
X7578

Figure 10-25 XNOR9 Implementation XC4000, XC5200, Spartans

I0
I1
I2
XOR3

I3
I4 XOR2
I5 O
XOR3
XNOR2
I6
I7
I8
XOR3 X7878

Figure 10-26 XNOR9 Implementation XC9000

10-38 Xilinx Development System

Design Elements (XNOR2-9)

FMAP
I4
S1
I8 I3 O
S0 O
I2
I8
I1

FMAP
I7 I7
I4
I6 I6
S1 O I3 S1
I5 I5 O
I2
I4 I4
XNOR3 I1
XOR4

FMAP
I3 I3
I4
I2 I2
S0 I3 S0
I1 I1 O
I2
I0 I0
I1
XOR4

X8696

Figure 10-27 XNOR9 Implementation Virtex

Libraries Guide, Release M1.5 10-39

Libraries Guide, Release M1.5

XOR2-9
2- to 9-Input XOR Gates with Non-Inverted Inputs

Element XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

XOR2, Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
XOR3,
XOR4
XOR5 Primitive Primitive Primitive Macro Macro Primitive Primitive Primitive
XOR6, Macro Macro Macro Macro Macro Macro Macro Macro
XOR7,
XOR8,
XOR9

XOR2 XOR5 XOR8

XOR3

XOR6

XOR4
XOR9

XOR7

x6811

Figure 10-28 XOR Gate Representations

The XOR function is performed in the Configurable Logic Block (CLB) function gener-
ators in XC3000, XC4000, and Spartans. XOR functions of up to nine inputs are avail-
able. All inputs are non-inverting. Because each input uses a CLB resource, replace
functions with unused inputs with functions having the necessary number of inputs.
I4
I3 I35
I2
I1 XOR3 O
I0
XOR3
X7881

Figure 10-29 XOR5 Implementation XC5200

10-40 Xilinx Development System

Design Elements (XOR2-9)

I0
I1
I2
XOR3 O

I3 XOR2
I4

XOR2

X7882

Figure 10-30 XOR5 Implementation XC9000

I0
I1
I2
XOR3 O
I3
I4 XOR2
I5
XOR3

X7883

Figure 10-31 XOR6 Implementation XC9000

I0
I1
I2
I3
O
XOR4
I4
I5 XOR2
I6
XOR3
X7884

Figure 10-32 XOR7 Implementation XC9000

I7
I6
I47
I5
I4
I3 XOR4
I2 O
I1
I0
XOR5
X7879

Figure 10-33 XOR8 Implementation XC3000

I7
I6
I47
I5
I4
XOR4 O
I3
I2 I13
XOR3
I1
XOR3
I0

X7880

Figure 10-34 XOR8 Implementation XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 10-41

Libraries Guide, Release M1.5

I0
I1
I2
I3
O
I4 XOR4

I5 XOR2
I6
I7
XOR4

X7885

Figure 10-35 XOR8 Implementation XC9000

FMAP
I4
I3 O
S1 O
I2
S2
I1
I7
I6 RLOC=R0C0.S0
S1
I5
I4
FMAP
XOR4
I7
I4
I6
O I3 S1
I5 O
I2
I4
XOR2 I1
I3
RLOC=R0C0.S1
I2
S0
I1
I0 FMAP
XOR4 I3
I4
I2
I3 S2
I1 O
I2
I0
I1

X8695 RLOC=R0C0.S1

Figure 10-36 XOR8 Implementation Virtex

I0
I1
I2
XOR3

I3
I4 XOR2
I5 O
XOR3
XOR2
I6
I7
I8
XOR3 X7886

Figure 10-37 XOR9 Implementation XC9000

10-42 Xilinx Development System

Design Elements (XORCY)

XORCY
XOR for Carry Logic with General Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LI
O
XORCY is a special XOR with general O output used for generating faster and smaller
CI
arithmetic functions.
X8410

Its O output is a general interconnect. See also“XORCY_D” and “XORCY_L”.

Libraries Guide, Release M1.5 10-43

Libraries Guide, Release M1.5

XORCY_D
XOR for Carry Logic with Dual Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LI
LO
XORCY_D is a special XOR used for generating faster and smaller arithmetic func-
O
CI tions.
X8409
XORCY_D has two functionally identical outputs, O and LO. The O output is a
general interconnect. The LO output is used to connect to another output within the
same CLB slice.
See also “XORCY” and “XORCY_L”.

10-44 Xilinx Development System

Design Elements (XORCY_L)

XORCY_L
XOR for Carry Logic with Local Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

N/A N/A N/A N/A N/A N/A N/A Primitive

LI
LO
XORCY_L is a special XOR with local LO output used for generating faster and
CI smaller arithmetic functions. The LO output is used to connect to another output
X8404 within the same CLB slice.
See also “XORCY” an d “XORCY_D”.

Libraries Guide, Release M1.5 10-45

Libraries Guide, Release M1.5

10-46 Xilinx Development System

Chapter 11

Design Elements (X74_42 to X74_521)

Libraries Guide, Release M1.5 — 11-1

Libraries Guide, Release M1.5

X74_42
4- to 10-Line BCD-to-Decimal Decoder with Active-Low Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A Y0
X74_42 decodes the 4-bit BCD number on the data inputs (A – D). Only one of the ten
X74_42
B Y1 outputs (Y9 – Y0) is active (Low) at a time, which reflects the decimal equivalent of the
C Y2 BCD number on inputs A – D. All outputs are inactive (High) during any one of six
D Y3 illegal states, as shown in the truth table.
Y4
Y5
Y6
Y7
Y8
Inputs Outputs
Y9
D C B A Selected (Low) Output
X4162 0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 All Outputs High
1 0 1 1 All Outputs High
1 1 0 0 All Outputs High
1 1 0 1 All Outputs High
1 1 1 0 All Outputs High
1 1 1 1 All Outputs High
Selected output is Low (0) and all others are High

11-2 Xilinx Development System

Design Elements (X74_42)

OR4

NAND4B3

NAND4B2

NAND4B3

NAND4B2

NAND4B1

NAND4B3

A
Y9
B
C
D NAND4B2
X7887

Figure 11-1 X74_42 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-3

Libraries Guide, Release M1.5

X74_L85
4-Bit Expandable Magnitude Comparator

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

AGBI X74_L85 AGBO X74_L85 is a 4-bit magnitude comparator that compares two 4-bit binary-weighted
AEBI AEBO words A3 – A0 and B3 – B0, where A3 and B3 are the most significant bits. The
ALBI ALBO greater-than output, AGBO, is High when A>B. The less-than output, ALBO, is High
A0
when A<B, and the equal output, AEBO, is High when A=B. The expansion inputs,
A1
A2 AGBI, ALBI, and AEBI, are the least significant bits. Words of greater length can be
A3 compared by cascading the comparators. The AGBO, ALBO, and AEBO outputs of
B0 the stage handling less-significant bits are connected to the corresponding AGBI,
B1
B2
ALBI, and AEBI inputs of the next stage handling more-significant bits. For proper
B3 operation, the stage handling the least significant bits must have AGBI and ALBI tied
Low and AEBI tied High.
X4163

Inputs Outputs

A3, B3 A2, B2 A1, B1 A0, B0 AGBI ALBI AEBI AGBO ALBO AEBO
A3>B3 X X X X X X 1 0 0
A3<B3 X X X X X X 0 1 0
A3=B3 A2>B2 X X X X X 1 0 0
A3=B3 A2<B2 X X X X X 0 1 0
A3=B3 A2=B2 A1>B1 X X X X 1 0 0
A3=B3 A2=B2 A1<B1 X X X X 0 1 0
A3=B3 A2=B2 A1=B1 A0>B0 X X X 1 0 0
A3=B3 A2=B2 A1=B1 A0<B0 X X X 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 1 0 0 1 0 0
A3=B3 A2=B2 A1=B1 A0=B0 0 1 0 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 0 0 1 0 0 1
A3=B3 A2=B2 A1=B1 A0=B0 0 1 1 0 1 1
A3=B3 A2=B2 A1=B1 A0=B0 1 0 1 1 0 1
A3=B3 A2=B2 A1=B1 A0=B0 1 1 1 1 1 1
A3=B3 A2=B2 A1=B1 A0=B0 1 1 0 1 1 0
A3=B3 A2=B2 A1=B1 A0=B0 0 0 0 0 0 0

11-4 Xilinx Development System

Design Elements (X74_L85)

AEBI

AEBO

AND5
AGBI

AL_7

AGBO
AND5
ALBI
OR5
AG_7

ALBO
AND5

OR5
AB0

AND5B1
A_B0
A0
NA_B1
AND2B1
A_B1
B0 NOR2

AND2B1

AB1

AND5B1

AB2

AND4B1
A_B2
A1
NA_B3
AND2B1
A_B3
B1 NOR2

AND2B1

AB3

AND4B1

AB4

AND3B1

A_B4
A2
NA_B5
AND2B1
A_B5
B2 NOR2

AND2B1

AB5

AND3B1
AB6

AND2B1
A_B6
A3
NA_B7
AND2B1
A_B7
B3 NOR2

AND2B1
AB7

AND2B1
X7888

Figure 11-2 X74_L85 Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 11-5

Libraries Guide, Release M1.5

ALBI

AND2
B0
A0 OR2
OR2B1

AND2
AND2B1
B1
A1 OR2
OR2B1

AND2
AND2B1
B2
A2 OR2
OR2B1

AND2
AND2B1
B3 ALBO
A3 OR2
OR2B1

AND2B1

AEBI

B0
A0
XOR2
B1
A1
AEBO
XOR2
B2
A2
AND5B4
XOR2
B3
A3
XOR2

AGBI

AND2
B0
A0 OR2
OR2B1

AND2
AND2B1
B1
A1 OR2
OR2B1

AND2
AND2B1
B2
A2 OR2
OR2B1

AND2
AND2B1
B3 AGBO
A3 OR2
OR2B1

AND2B1
X7716

Figure 11-3 X74_L85 Implementation XC9000

11-6 Xilinx Development System

Design Elements (X74_138)

X74_138
3- to 8-Line Decoder/Demultiplexer with Active-Low Outputs and
Three Enables

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A X74_138 Y0
X74_138 is an expandable decoder/demultiplexer with one active-High enable input
B Y1 (G1), two active-Low enable inputs (G2A and G2B), and eight active-Low outputs (Y7
C Y2 – Y0). When G1 is High and G2A and G2B are Low, one of the eight active-Low
Y3
outputs is selected with a 3-bit binary address on address inputs A, B, and C. The non-
Y4
G2A Y5 selected outputs are High. When G1 is Low or when G2A or G2B is High, all outputs
G2B Y6 are High.
G1 Y7
X74_138 can be used as an 8-output active-Low demultiplexer by tying the data input
X4164 to one of the enable inputs.

Inputs Outputs

C B A G1 G2A G2B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 1 0 0 1 1 1 1 1 1 1 0
0 0 1 1 0 0 1 1 1 1 1 1 0 1
0 1 0 1 0 0 1 1 1 1 1 0 1 1
0 1 1 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 0 0 1 1 0 1 1 1 1 1
1 1 0 1 0 0 1 0 1 1 1 1 1 1
1 1 1 1 0 0 0 1 1 1 1 1 1 1
X X X 0 X X 1 1 1 1 1 1 1 1
X X X X 1 X 1 1 1 1 1 1 1 1
X X X X X 1 1 1 1 1 1 1 1 1

Libraries Guide, Release M1.5 11-7

Libraries Guide, Release M1.5

G1
G2A E Y[7:0]
G2B
Y0
AND3B2

NAND4B3

NAND4B2

NAND4B1

NAND4B2

NAND4B1

A
Y7
B
C
NAND4
X7889

Figure 11-4 X74_138 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-8 Xilinx Development System

Design Elements (X74_139)

X74_139
2- to 4-Line Decoder/Demultiplexer with Active-Low Outputs and
Active-Low Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A X74_139 Y0
X74_139 implements one half of a standard 74139 dual 2- to 4-line decoder/demulti-
B Y1 plexer. When the active-Low enable input (G) is Low, one of the four active-Low
Y2 outputs (Y3 – Y0) is selected with the 2-bit binary address on the A and B address
G Y3
input lines. B is the High-order address bit. The non-selected outputs are High. Also,
X4165
when G is High all outputs are High.
X74_139 can be used as a 4-output active-Low demultiplexer by tying the data input
to G.

Inputs Outputs

G B A Y3 Y2 Y1 Y0
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
1 X X 1 1 1 1

Y0
NAND3B3

Y1
NAND3B2

Y2
NAND3B2
A
B Y3
G
Y3
NAND3B1
X7890

Figure 11-5 X74_139 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-9

Libraries Guide, Release M1.5

X74_147
10- to 4-Line Priority Encoder with Active-Low Inputs and Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A
X74_147 is a 10-line-to-BCD-priority encoder that accepts data from nine active-Low
I1 X74_147
I2 B inputs (I9 – I1) and produces a binary-coded decimal (BCD) representation on the four
I3 C active-Low outputs A, B, C, and D. The data inputs are weighted, so when more than
I4 D one input is active, only the one with the highest priority is encoded, with I9 having
I5
I6
the highest priority. Only nine inputs are provided, because the implied “zero” condi-
I7 tion requires no data input. “Zero” is encoded when all data inputs are High.
I8
I9

X4166 Inputs Outputs

I9 I8 I7 I6 I5 I4 I3 I2 I1 D C B A
1 1 1 1 1 1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 0 X 1 1 0 1
1 1 1 1 1 1 0 X X 1 1 0 0
1 1 1 1 1 0 X X X 1 0 1 1
1 1 1 1 0 X X X X 1 0 1 0
1 1 1 0 X X X X X 1 0 0 1
1 1 0 X X X X X X 1 0 0 0
1 0 X X X X X X X 0 1 1 1
0 X X X X X X X X 0 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1

11-10 Xilinx Development System

Design Elements (X74_147)

I1
AND5B1

I2
D1

I3
AND4B1 A

NOR5B1
AND3B1
D3

AND2B1

AND4B1

B
AND4B1
D6
NOR4
AND2B1
D7

AND2B1
D8
I4
AND2B1
D9
I5
AND2B1 C

D10
I6
NOR4
AND2B1
D11
I7
I8 AND2B1 D
I9

AND2 X7891

Figure 11-6 X74_147 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-11

Libraries Guide, Release M1.5

X74_148
8- to 3-Line Cascadable Priority Encoder with Active-Low Inputs
and Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

I0 A0
X74_148 8-input priority encoder accepts data from eight active-Low inputs (I7 – I0)
X74_148
I1 A1 and produces a binary representation on the three active-Low outputs (A2 – A0). The
I2 A2 data inputs are weighted, so when more than one of the inputs is active, only the
I3
input with the highest priority is encoded, I7 having the highest priority. The active-
I4 EO
I5 GS
Low group signal (GS) is Low whenever one of the data inputs is Low and the active-
I6 Low enable input (EI) is Low.
I7
EI The active-Low enable input (EI) and active-Low enable output (EO) are used to
cascade devices and retain priority control. The EO of the highest priority stage is
X4167 connected to the EI of the next-highest priority stage. When EI is High, the data
outputs and EO are High. When EI is Low, the encoder output represents the highest-
priority Low data input, and the EO is High. When EI is Low and all the data inputs
are High, the EO output is Low to enable the next-lower priority stage.

Inputs Outputs

EI I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 GS EO
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 0 1 1 1 0 1
0 1 1 1 1 1 1 0 X 1 1 0 0 1
0 1 1 1 1 1 0 X X 1 0 1 0 1
0 1 1 1 1 0 X X X 1 0 0 0 1
0 1 1 1 0 X X X X 0 1 1 0 1
0 1 1 0 X X X X X 0 1 0 0 1
0 1 0 X X X X X X 0 0 1 0 1
0 0 X X X X X X X 0 0 0 0 1

11-12 Xilinx Development System

Design Elements (X74_148)

AND5B1 EO

NAND2

AND5B1 GS

NAND2B1

D0
I1

AND5B2

A0
AND4B2

D2
NOR4

AND3B2
D3

NOR2

D4
I2

AND4B2

D5
I3

A1
AND4B2
D6
NOR4
NOR2
D7

NOR2
I4
D8

NOR2
I5
D9

NOR2 A2
I6
D10
NOR4
NOR2
I7
D11
EI
NOR2 X7892

Figure 11-7 X74_148 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-13

Libraries Guide, Release M1.5

X74_150
16-to-1 Multiplexer with Active-Low Enable and Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

When the active-Low enable input (G) is Low, the X74_150 multiplexer chooses one
E0 X74_150
E1
data bit from 16 sources (E15 – E0) under the control of select inputs A, B, C, and D.
E2 The active-Low output (W) reflects the inverse of the selected input, as shown in the
E3 truth table. When the enable input (G) is High, the output (W) is High.
E4
E5
E6
E7
Inputs Outputs
E8 W
E9
Selected Input Appears
E10 G D C B A
E11 (Inverted) on W
E12
E13
1 X X X X 1
E14
0 0 0 0 0 E0
E15
A 0 0 0 0 1 E1
B
C 0 0 0 1 0 E2
D
0 0 0 1 1 E3
G
0 0 1 0 0 E4
X4168
0 0 1 0 1 E5
0 0 1 1 0 E6
0 0 1 1 1 E7
0 1 0 0 0 E8
0 1 0 0 1 E9
0 1 0 1 0 E10
0 1 0 1 1 E11
0 1 1 0 0 E12
0 1 1 0 1 E13
0 1 1 1 0 E14
0 1 1 1 1 E15

11-14 Xilinx Development System

Design Elements (X74_150)

M2_1
E0 D0
O
E1 D1
S0 M01 M2_1
M01 D0
O
M23 D1
M2_1 S0 M03
E2 D0
O
E3 D1
S0 M23 M2_1
M03 D0
O
M47 D1
M2_1 S0 M07
E4 D0
O
E5 D1
S0 M45 M2_1
M45 D0
O M07
M67 D1
M2_1 S0 M47
E6 D0
O
E7 D1 AND3B2
S0 M67

W
M2_1
E8 D0 XNOR2
O
E9 D1
S0 M89 M2_1
M89 D0
O M8F
MAB D1
M2_1 S0 M8B
E10 D0 AND3B1
O
E11 D1
S0 MAB M2_1
M8B D0
O O
MCF D1
M2_1 S0 M8F
E12 D0
O
E13 D1
S0 MCD M2_1
MCD D0
O
MEF D1
M2_1 S0 MCF
E14 D0
O
E15 D1
A S0 MEF
B
C
D X7893
G

Figure 11-8 X74_150 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-15

Libraries Guide, Release M1.5

X74_151
8-to-1 Multiplexer with Active-Low Enable and Complementary
Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

D0
When the active-Low enable (G) is Low, the X74_151 multiplexer chooses one data bit
X74_151
D1 from eight sources (D7 – D0) under control of the select inputs A, B, and C. The output
D2 (Y) reflects the state of the selected input, and the active-Low output (W) reflects the
D3 Y
inverse of the selected input as shown in the truth table. When G is High, the Y output
D4 W
D5 is Low, and the W output is High.
D6
D7
A
B Inputs Outputs
C
G G C B A Y W
X4169 1 X X X 0 1
0 0 0 0 D0 D0
0 0 0 1 D1 D1
0 0 1 0 D2 D2
0 0 1 1 D3 D3
0 1 0 0 D4 D4
0 1 0 1 D5 D5
0 1 1 0 D6 D6
0 1 1 1 D7 D7

M2_1
D0 D0
O
D1 D1
S0 M01 M2_1
M01 D0
O
M23 D1
M2_1 S0 M03
D2 D0
O
D3 D1
S0 M23 M2_1E
M03 D0
O Y
M47 D1
W
M2_1 S0 Y
D4 D0 E INV
O
D5 D1
S0 M45 M2_1
M45 D0
O
M67 D1
M2_1 S0 M47
D6 D0
O
D7 D1
A S0 M67
B
C
G E X7894
INV

Figure 11-9 X74_151 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-16 Xilinx Development System

Design Elements (X74_152)

X74_152
8-to-1 Multiplexer with Active-Low Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

D0
X74_152 multiplexer chooses one data bit from eight sources (D7 – D0) under control
X74_152
D1 of the select inputs A, B, and C. The active-Low output (W) reflects the inverse of the
D2 selected data input, as shown in the truth table.
D3
D4 W
D5
D6 Inputs Outputs
D7
A
C B A W
B
C
0 0 0 D0
X4170 0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

M2_1
D0 D0
O
D1 D1
S0 M01 M2_1
M01 D0
O
M23 D1
M2_1 S0 M03
D2 D0
O
D3 D1
S0 M23 M2_1
M03 D0
O O W
M47 D1
M2_1 S0 O INV
D4 D0
O
D5 D1
S0 M45 M2_1
M45 D0
O
M67 D1
M2_1 S0 M47
D6 D0
O
D7 D1
A S0 M67
B
C
X7895

Figure 11-10 X74_152 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-17

Libraries Guide, Release M1.5

X74_153
Dual 4-to-1 Multiplexer with Active-Low Enables and Common
Select Input

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

I1C0 X74_153 Y1
When the active-Low enable inputs G1 and G2 are Low, the data output Y1, reflects
I1C1 the data input chosen by select inputs A and B from data inputs I1C3 – I1C0. The data
I1C2 output Y2 reflects the data input chosen by select inputs A and B from data inputs
I1C3
Y2
I2C3 – I2C0. When G1 or G2 is High, the corresponding output, Y1 or Y2 respectively,
I2C0
I2C1 is Low.
I2C2
I2C3
A
B Inputs Outputs
G1
G2 G1 G2 B A Y1 Y2
X4171 1 1 X X 0 0
1 0 0 0 0 I2C0
1 0 0 1 0 I2C1
1 0 1 0 0 I2C2
1 0 1 1 0 I2C3
0 1 0 0 I1C0 0
0 1 0 1 I1C1 0
0 1 1 0 I1C2 0
0 1 1 1 I1C3 0
0 0 0 0 I1C0 I2C0
0 0 0 1 I1C1 I2C1
0 0 1 0 I1C2 I2C2
0 0 1 1 I1C3 I2C3

11-18 Xilinx Development System

Design Elements (X74_153)

M2_1
I1C0 D0
O
I1C1 D1
S0 M1_01 M2_1E
M1_01 D0
O Y1
M1_23 D1
M2_1 S0 Y1
I1C2 D0
O E
I1C3 D1
S0 M1_23

G1 E1
INV
M2_1
I2C0 D0
O
I2C1 D1
S0 M2_01 M2_1E
M2_01 D0
O Y2
M2_23 D1
M2_1 S0 Y2
I2C2 D0
O E
I2C3 D1
A S0 M2_23
B
G2 E2

INV

X7896

Figure 11-11 X74_153 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-19

Libraries Guide, Release M1.5

X74_154
4- to 16-Line Decoder/Demultiplexer with Two Enables and Active-
Low Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

When the active-Low enable inputs G1 and G2 of the X74_154 decoder/demultiplexer

A X74_154 Y0
B Y1 are Low, one of 16 active-Low outputs, Y15 – Y0, is selected under the control of four
C Y2 binary address inputs A, B, C, and D. The non-selected inputs are High. Also, when
D Y3 either input G1 or G2 is High, all outputs are High.
Y4
Y5 The X74_154 can be used as a 16-to-1 demultiplexer by tying the data input to one of
Y6
the G inputs and tying the other G input Low.
Y7
Y8
Y9
Y10
Y11 Inputs Outputs
Y12
Y13 G1 G2 D C B A Y15 Y14 Y13 Y12 Y11 Y10 Y9 ... Y0
G1 Y14
G2 Y15 1 X X X X X 1 1 1 1 1 1 1 ... 1
X 1 X X X X 1 1 1 1 1 1 1 ... 1
X4172
0 0 1 1 1 1 0 1 1 1 1 1 1 ... 1
0 0 1 1 1 0 1 0 1 1 1 1 1 ... 1
0 0 1 1 0 1 1 1 0 1 1 1 1 ... 1
- - - - - - - - - - - - - ... -
- - - - - - - - - - - - - ... -
- - - - - - - - - - - - - ... -
0 0 0 0 0 0 1 1 1 1 1 1 1 ... 0

11-20 Xilinx Development System

Design Elements (X74_154)

NAND5B4

NAND5B3

NAND5B2

NAND5B3

NAND5B2

NAND5B1

NAND5B3

NAND5B2

Y10

Libraries Guide, Release M1.5

X74_160
4-Bit BCD Counter with Parallel and Trickle Enables, Active-Low
Load Enable, and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A X74_160 QA
X74_160 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable, binary-
B QB coded decimal (BCD) counter. The active-Low asynchronous clear (CLR), when Low,
C QC overrides all other inputs and resets the data (QD, QC, QB, QA) and ripple carry-out
D QD
LOAD
(RCO) outputs Low. When the active-Low load enable input (LOAD) is Low and CLR
ENP RCO is High, parallel clock enable (ENP), and trickle clock enable (ENT) are overridden
ENT and data on inputs A, B, C, and D are loaded into the counter during the Low-to-High
CK clock transition. The data outputs (QD, QC, QB, QA) increment when ENP, ENT
LOAD, and CLR are High during the Low-to-High clock transition. The counter
CLR
X4175
ignores clock transitions when ENP or ENT are Low and LOAD is High. RCO is High
when QD, QA, and ENT are High and QC and QB are Low.

Inputs Outputs

CLR LOAD ENP ENT D–A CK QD – QA RCO

0 X X X X X 0 0
1 0 X X D–A ↑ d–a RCO
1 1 0 X X X No Chg RCO
1 1 X 0 X X No Chg 0
1 1 1 1 X ↑ Inc RCO
RCO = (QD•QC•QB•QA•ENT)
d – a = state of referenced input one set-up time prior to active clock transition

Carry-Lookahead Design
The carry-lookahead design allows cascading of large counters without extra gating.
Both ENT and ENP must be High to count. ENT is fed forward to enable RCO, which
produces a High output pulse with the approximate duration of the QA output. The
following figure illustrates a carry-lookahead design.

11-24 Xilinx Development System

Design Elements (X74_160)

RCO
ENP
ENT

Vcc RCO
ENP
ENT

Vcc
RCO
ENP
CE ENT

X4719

Figure 11-15 Carry-Lookahead Design

Libraries Guide, Release M1.5 11-25

Libraries Guide, Release M1.5

FTCLE
A
D
LOAD LB
L
INV T Q
CE
CK
C
CLR
CLR CLRB
QA
INV QA

FTCLE
B
D
L
T1 Q
T
AND2B1 CE
C
CLR
QB
QB
FTCLE
C D
L
ENP T Q
CE
ENT CE
AND2 C
CLR
QC
QC
FTCLE
D
D
TQB L
T2 T3 Q
T
AND2 CE
AND2 OR2
C
CLR
TQAD
QD

AND3 QD

RCO

AND5B2
X7900

Figure 11-16 X74_160 Implementation XC3000

VCC
FTCLE
A D
LOAD LB
L
INV T Q
CE
CK C
CLR
CLR CLRB
QA
QA
INV

FTCLE
B D
L
T1 Q
T
CE
AND3B1 C
CLR
QB QB

FTCLE
C D
L
T Q
CE
C
CLR
QC QC

FTCLE
D D
TQB L
ENP CE T2 T3 Q
T
ENT
AND2 CE
AND2 AND3 OR2
C
CLR
TQAD
QD

AND3 QD

RCO

AND5B2
X7602

Figure 11-17 X74_160 Implementation XC4000, XC5200, Spartans

11-26 Xilinx Development System

Design Elements (X74_160)

VCC
+5
FTCLE

A
S
D

AND2 L
QA
T Q
CE
C
CLR
QA

FTCLE

B
S
D

AND2 L
QB
T Q
CE
C
CLR T2
QB
AND2

FTCLE

C
S
D

AND2 L
QC
T Q
CE
C
CLR T3
QC
AND3

FTCLE

D
S
D
L
AND2 QD
T Q
CE
CK
C
CLR
CLR QD

INV AND4B2
LOAD
GND
INV
OR2 RCO
ENT

AND2

ENP

AND2 OR3

AND3
X7901

Figure 11-18 X74_160 Implementation XC9000

Libraries Guide, Release M1.5 11-27

Libraries Guide, Release M1.5

X74_161
4-Bit Binary Counter with Parallel and Trickle Enables, Active-Low
Load Enable, and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A X74_161 QA
X74_161 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable binary
B QB counter. The active-Low asynchronous clear (CLR), when Low, overrides all other
C QC inputs and resets the data outputs (QD, QC, QB, QA) and the ripple carry-out output
D QD
(RCO) Low. When the active-Low load enable (LOAD) is Low and CLR is High,
LOAD
ENP RCO
parallel clock enable (ENP) and trickle clock enable (ENT) are overridden and the
ENT data on inputs A, B, C, and D is loaded into the counter during the Low-to-High clock
CK (CK) transition. The data outputs (QD, QC, QB, QA) increment when LOAD, ENP,
ENT, and CLR are High during the Low-to-High clock transition. The counter ignores
CLR
clock transitions when LOAD is High and ENP or ENT are Low. RCO is High when
X4176
QD – QA and ENT are High.
The carry-lookahead design accommodates large counters without extra gating. Refer
to “Carry-Lookahead Design” in the “X74_160” section for more information.

Inputs Outputs

CLR LOAD ENP ENT D–A CK QD – QA RCO

0 X X X X X 0 0
1 0 X X D–A ↑ d–a RCO
1 1 0 X X X No Chg RCO
1 1 X 0 X X No Chg 0
1 1 1 1 X ↑ Inc RCO
RCO = (QD•QC•QB•QA•ENT)
d – a = state of referenced input one setup time prior to active clock transition

11-28 Xilinx Development System

Design Elements (X74_161)

FTCLE
A
D
VCC L
QA
T Q
CE
C
CLR
Q0

FTCLE
B
D
L
QB
T Q
CE
C
CLR T2
Q1
AND2

FTCLE
C
D
L
QC
T Q
CE
C
CLR T3
Q2
AND3

FTCLE
D
D
LOAD LOADB
L
QD
INV T Q
CE
CK
C
CLR
CLR CLRB Q3

ENP INV RCO

CE
ENT
AND2

AND5

X7902

Figure 11-19 X74_161 Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 11-29

Libraries Guide, Release M1.5

VCC
+5

LOAD

AND2

ENT
AND2

ENP

AND2

FDC
AND3
QA
D Q

XOR2
C
AND2
CLR
A QA
OR2

AND2B1

FDC
AND4
QB
D Q

XOR2
AND2 C
CLR
B OR2 QB

AND2B1

FDC
AND5
QC
D Q

XOR2
C
AND2
CLR
C QC
OR2

AND2B1

FDC
AND6 QD
D Q

XOR2
C
AND2 CLR
QD
D
OR2 RCO

AND2B1
CK AND5
CLR

INV X7903

Figure 11-20 X74_161 Implementation XC9000

11-30 Xilinx Development System

Design Elements (X74_162)

X74_162
4-Bit BCD Counter with Parallel and Trickle Enables, Active-Low
Load Enable, and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A X74_162 QA
X74_162 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable binary-coded
B QB decimal (BCD) counter. The active-Low synchronous reset (R), when Low, overrides
C QC all other inputs and resets the data (QD, QC, QB, QA) and ripple carry-out (RCO)
D QD outputs Low during the Low-to-High clock (CK) transition. When the active-Low
LOAD
ENP RCO
load enable input (LOAD) is Low and R is High, parallel clock enable (ENP) and
ENT trickle clock enable (ENT) are overridden and data on inputs A, B, C, and D is loaded
CK into the counter during the Low-to-High clock transition. The data outputs (QD, QC,
QB, QA) increment when ENP, ENT, LOAD, and R are High during the Low-to-High
R
clock transition. The counter ignores clock transitions when ENP or ENT are Low and
X4177
LOAD is High. RCO is High when QD, QA, and ENT are High and QC and QB are
Low.
The carry-lookahead design accommodates cascading large counters without extra
gating. Refer to “Carry-Lookahead Design” in the “X74_160” section for more infor-
mation.

Inputs Outputs

R LOAD ENP ENT D–A CK QD – QA RCO

0 X X X X ↑ 0 0
1 0 X X D–A ↑ d–a RCO
1 1 0 X X X No Chg RCO
1 1 X 0 X X No Chg 0
1 1 1 1 X ↑ Inc RCO
RCO = (QD•QC•QB•QA•ENT)
d – a = state of referenced input one setup time prior to active clock transition

Libraries Guide, Release M1.5 11-31

Libraries Guide, Release M1.5

FTRSLE

A S
D
LOAD LB
L
INV T Q
CE
CK
C
R
R RB
QA
INV QA
FTRSLE

B S
D
L
T1
T Q
AND2 CE
C
R
QB
QB
FTRSLE

C S
D
L
ENP T Q
CE
ENT CE
AND2 C
R
QC
QC
FTRSLE

D S
D
TQB L
T2 T3
T Q
AND2 CE
AND2 OR2
C
R
TQAD
QD

AND3 QD

RCO

AND5B2
X7904
GND

Figure 11-21 X74_162 Implementation XC3000, XC4000, XC5200, Spartans

11-32 Xilinx Development System

Design Elements (X74_162)

VCC
+5

ENT
AND2
CE
ENP
AND2
AND2

LOAD
AND2
CK

R RCO
RCO
INV
INV AND5B2
INV
AND6

FD
D Q
QA
AND5B2
OR4
C

QA
AND4B1

AND3B1

INV
INV AND6

INV FD
D Q
QB
INV AND6
OR4
C

QB
AND4B1

AND3B1

INV
INV AND7

INV

INV AND6

FD
D Q
QC
INV
OR5
C
INV AND6
QC

AND4B1

AND3B1

INV AND7

INV FD
INV
D Q QD
INV AND7
OR4
C

AND4B1

AND3B1
X8046

Figure 11-22 X74_162 Implementation XC9000

Libraries Guide, Release M1.5 11-33

Libraries Guide, Release M1.5

X74_163
4-Bit Binary Counter with Parallel and Trickle Enables, Active-Low
Load Enable, and Synchronous Reset

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

X74_163 is a 4-stage, 4-bit, synchronous, loadable, resettable, cascadable binary

A X74_163 QA
B QB
counter. The active-Low synchronous reset (R), when Low, overrides all other inputs
C QC and resets the data outputs (QD, QC, QB, QA) and the ripple carry-out output (RCO)
D QD Low during the Low-to-High clock (CK) transition. When the active-Low load enable
LOAD
RCO
(LOAD) is Low and R is High, parallel clock enable (ENP) and trickle clock enable
ENP
ENT
(ENT) are overridden and the data on inputs (A, B, C, D) is loaded into the counter
CK during the Low-to-High clock (CK) transition. The outputs (QD, QC, QB, QA) incre-
ment when LOAD, ENP, ENT, and R are High during the Low-to-High clock transi-
R tion. The counter ignores clock transitions when LOAD is High and ENP or ENT are
X4178
Low; RCO is High when QD – QA and ENT are High.
The carry-lookahead design accommodates large counters without extra gating. Refer
to “Carry-Lookahead Design” in the “X74_160” section for more information.

Inputs Outputs

R LOAD ENP ENT D–A CK QD – QA RCO

11-34 Xilinx Development System

Design Elements (X74_163)

FTRSLE

A S
D
VCC L
QA
T Q
CE
C
R
Q0

FTRSLE

B S
D
L
QB
T Q
CE
C
R T2
Q1
AND2

FTRSLE

C S
D
L
QC
T Q
CE
C
R T3
Q2
AND3

FTRSLE

D S
D
LOAD LOADB
L
QD
INV T Q
CE
CK
C
R
R RB Q3

ENP INV RCO

CE
ENT
AND2

AND5

GND X7905

Figure 11-23 X74_163 Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 11-35

Libraries Guide, Release M1.5

VCC
+5

LOAD
AND2

ENT
AND2

ENP
AND2
R

AND4
FD
QA
D Q

XOR2
C
AND3
QA
A OR2

AND3B1

FD
AND5
QB
D Q

XOR2
C
AND3
B QB
OR2

AND3B1

FD
AND6
QC
D Q

XOR2
C
AND3
C QC
OR2

AND3B1

FD
AND7
QD
D Q

XOR2
C
AND3
D QD
OR2 RCO

AND3B1
CK AND5

X7639

Figure 11-24 X74_163 Implementation XC9000

11-36 Xilinx Development System

Design Elements (X74_164)

X74_164
8-Bit Serial-In Parallel-Out Shift Register with Active-Low
Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

X74_164 is an 8-bit, serial input (A and B), parallel output (QH – QA) shift register
A X74_164 QA
B QB with an active-Low asynchronous clear (CLR) input. The asynchronous CLR, when
QC Low, overrides the clock input and sets the data outputs (QH – QA) Low. When CLR
QD is High, the AND function of the two data inputs (A and B) is loaded into the first bit
QE
QF
of the shift register during the Low-to-High clock (CK) transition and appears on the
QG QA output. During subsequent Low-to-High clock transitions, with CLR High, the
CK QH data is shifted to the next-highest bit position as new data is loaded into QA (A and
B→QA, QA→QB, QB→QC, and so forth).
CLR
X4179 Registers can be cascaded by connecting the QH output of one stage to the A input of
the next stage, by tying B High, and by connecting the clock and CLR inputs in
parallel.

Inputs Outputs

CLR A B CK QA QB – QH
0 X X X 0 0
1 1 1 ↑ 1 qA – qG
1 0 X ↑ 0 qA – qG
1 X 0 ↑ 0 qA – qG
qA – qG = state of referenced output one setup time prior to active clock transition

Libraries Guide, Release M1.5 11-37

Libraries Guide, Release M1.5

VCC
+5
FDCE
A QA
SLI
B D Q
AND2 CE
C
CLR
QA

FDCE
QB
D Q
CE
C
CLR
QB

FDCE
QC
D Q
CE
C
CLR
QC

FDCE
QD
D Q
CE
C
CLR
QD

FDCE
QE
D Q
CE
C
CLR
QE

FDCE
QF
D Q
CE
C
CLR
QF

FDCE
QG
D Q
CE
C
CLR
QG

FDCE
QH
D Q
CE
CK
C
CLR
CLR CLRB QH
INV

X7646

Figure 11-25 X74_164 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-38 Xilinx Development System

Design Elements (X74_165S)

X74_165S
8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with
Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

X74_165S is an 8-bit shift register with serial-input (SI), parallel- inputs (H – A),
SI X74_165S
A QA parallel-outputs (QH – QA), and two control inputs – clock enable (CE) and active-
B QB Low shift/load enable (S_L). When S_L is Low, data on the H – A inputs is loaded into
C QC the corresponding QH – QA bits of the register on the Low-to-High clock (CK) transi-
D QD
QE
tion. When CE and S_L are High, data on the SI input is loaded into the first bit of the
E
F QF register during the Low-to-High clock transition. During subsequent Low-to-High
G QG clock transitions, with CE and S_L High, the data is shifted to the next-highest bit
QH
H position (shift right) as new data is loaded into QA (SI→ QA, QA→QB, QB→QC, and
S_L
CE
so forth). The register ignores clock transitions when CE is Low and S_L is High.
CK
Registers can be cascaded by connecting the QH output of one stage to the SI input of
X4180
the next stage and connecting clock, CE, and S_L inputs in parallel.

Inputs Outputs

S_L CE SI A–H CK QA QB – QH
0 X X A–H ↑ qa qb – qh
1 0 X X X No Chg No Chg
1 1 SI X ↑ si qA – qG
si = state of referenced input one setup time prior to active clock transition
qn = state of referenced output one setup time prior to active clock transition

Libraries Guide, Release M1.5 11-39

Libraries Guide, Release M1.5

CE L_OR_CE
S_L
OR2B1

M2_1 FDCE
A D0
O MDA QA
SI D1 D Q
S0 MDA CE
C
CLR
Q0

M2_1 FDCE
B D0
O MDB QB
D1 D Q
S0 MDB CE
C
CLR
Q1

M2_1 FDCE
C D0
O MD2 QC
D1 D Q
S0 MDC CE
C
CLR
Q2

M2_1 FDCE
D D0
O MDD QD
D1 D Q
S0 MDD CE
C
CLR
Q3

M2_1 FDCE
E D0
O MDE QE
D1 D Q
S0 MDE CE
C
CLR
Q4

M2_1 FDCE
F D0
O MDF QF
D1 D Q
S0 MDF CE
C
CLR
Q5

M2_1 FDCE
G D0
O MDG QG
D1 D Q
S0 MDG CE
C
CLR
Q6

M2_1 FDCE
H D0
O MDH QH
D1 D Q
S0 MDH CE
C
CK CLR
Q7

GND X7906

Figure 11-26 X74_165S Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-40 Xilinx Development System

Design Elements (X74_168)

X74_168
4-Bit BCD Bidirectional Counter with Parallel and Trickle Clock
Enables and Active-Low Load Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

X74_168 is a 4-stage, 4-bit, synchronous, loadable, cascadable, bidirectional binary-

A X74_168 QA
B QB
coded-decimal (BCD) counter. The data on the D – A inputs is loaded into the counter
C QC when the active-Low load enable (LOAD) is Low during the Low-to-High clock (CK)
D QD transition. The LOAD input, when Low, has priority over parallel clock enable (ENP),
LOAD
ENP
trickle clock enable (ENT), and the bidirectional (U_D) control. The outputs (QD –
RCO
ENT QA) increment when U_D and LOAD are High and ENP and ENT are Low during the
U_D Low-to-High clock transition. The outputs decrement when LOAD is High and ENP,
CK ENT, and U_D are Low during the Low-to-High clock transition. The counter ignores
clock transitions when LOAD and either ENP or ENT are High.
X4278

Inputs Outputs

LOAD ENP ENT U_D A–D CK QA – QD RCO

0 X X X A–D ↑ qa – qd RCO
1 0 0 1 X ↑ Inc RCO
1 0 0 0 X ↑ Dec RCO
1 1 0 X X X No Chg RCO
1 X 1 X X X No Chg 1
RCO = (Q3•Q2•Q1•Q0•U_D•ENT) + (Q3•Q2•Q1•Q0•U_D•ENT)
qa – qd = state of referenced input one setup time prior to active clock transition

The active-Low ripple carry-out output (RCO) is Low when QD, QA, and U_D are
High and QC, QB, and ENT are Low. RCO is also Low when all outputs, ENT and
U_D are Low. The following figure illustrates a carry-lookahead design.

Libraries Guide, Release M1.5 11-41

Libraries Guide, Release M1.5

RCO
ENP
ENT

Vcc RCO
ENP
ENT

Vcc
RCO
ENP
CE ENT

X4719

Figure 11-27 Carry-Lookahead Design

The RCO output of the first stage of the ripple carry is connected to the ENP input of
the second stage and all subsequent stages. The RCO output of second stage and all
subsequent stages is connected to the ENT input of the next stage. The ENT of the
second stage is always enabled/tied to VCC. CE is always connected to the ENT input
of the first stage. This cascading method allows the first stage of the ripple carry to be
built as a prescaler. In other words, the first stage is built to count very fast.

11-42 Xilinx Development System

Design Elements (X74_168)

M2_1 FDCE
A D0
O DA QA
UDA D1 D Q
S0 CE
INV
C
CLR
Q0

B
M2_1 FDCE
DB1 D0
O DB QB
D1 D Q
AND2 S0 CE
DB2 M2_1 C
DNB D0 CLR
O UDB
AND2 D1 Q1
S0
OR4
DB3

AND3B2

DB4

AND4B3

UB1

AND2B1
UB2 UPB

AND2
OR3

UB4

AND3B2
C

DC1 M2_1 FDCE

D0
O DC QC
D1 D Q
AND3
S0 CE
DC2 CC M2_1 C
DNC D0 CLR
O UDC
D1 Q2
OR3 S0
AND4B3 XOR

DC3

AND4B3

UC1

AND2 UPC

XOR2
D

M2_1 FDCE
DD1 D0
O DD QD
D1 D Q
AND3B1 S0 CE
DD2 M2_1 C
DND D0 CLR
O UDD
D1 Q3
AND3B1 S0
OR4
DD3
GND

AND4B2

DD4

AND4B4
UD1

AND2B1

UPD
UD2
OR2

AND4B1

DRC

OR4 M2_1
D0
O RC
URC D1 RCO
S0
OR2
NAND4B2
U_D
LOAD

ENP CE
ENT
ENT_P OR2B2
OR2
X7907
CK

Figure 11-28 X74_168 Implementation XC3000, XC4000, XC5200, Spartans

Libraries Guide, Release M1.5 11-43

Libraries Guide, Release M1.5

ENT

ENP OR2

OR2

GND
AND2B2

CK
UD
RCO

VCC
+5 AND5B3
AND5B3

LOAD
AND2 FD
QA
AND4B2 D Q

OR4
C

AND3B1 QA
A

AND2B1

INV
INV
INV
INV
AND7

INV
INV
INV

INV AND7

INV
INV AND6

FD
QB
D Q
INV

C
INV AND6
OR7
QB

INV

INV AND6

AND3B1
B

AND2B1

INV
INV AND7

INV
INV
INV
INV
AND7

INV

INV AND6

INV
FD
INV AND6 QC
D Q

C
INV
OR8 QC

INV AND6

INV

INV AND6

AND3B1
C

AND2B1

INV AND7

INV
INV
INV
AND7

INV
INV
INV
INV FD
INV AND7 QD
D Q

C
OR6
INV
QD
INV
INV
AND7

AND3B1
D
X7636

AND2B1

Figure 11-29 X74_168 Implementation XC9000

11-44 Xilinx Development System

Design Elements (X74_174)

X74_174
6-Bit Data Register with Active-Low Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

D1 X74_174 Q1
The active-Low asynchronous clear input (CLR), when Low, overrides the clock and
D2 Q2 resets the six data outputs (Q6 – Q1) Low. When CLR is High, the data on the six data
D3 Q3 inputs (D6 – D1) is transferred to the corresponding data outputs on the Low-to-High
D4 Q4
clock (CK) transition.
D5 Q5
D6 Q6
CK

Inputs Outputs
CLR

X4193 CLR D6 – D1 CK Q6 – Q1
0 X X 0
1 D6 – D1 ↑ d6 – d1
dn = state of referenced input one setup time prior to active clock transition

FDC
D1 Q1
D Q

C
CLR
Q1

FDC
D2 Q2
D Q

C
CLR
Q2

FDC
D3 Q3
D Q

C
CLR
Q3

FDC
D4 Q4
D Q

C
CLR
Q4

FDC
D5 Q5
D Q

C
CLR
Q5

FDC
D6 Q6
D Q

CK
C
CLR
CLR CLRB Q6

INV X7908

Figure 11-30 X74_174 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-45

Libraries Guide, Release M1.5

X74_194
4-Bit Loadable Bidirectional Serial/Parallel-In Parallel-Out Shift
Register

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

SLI X74_194
X74_194 is a 4-bit shift register with shift-right serial input (SRI), shift-left serial input
A QA (SLI), parallel inputs (D – A), parallel outputs (QD – QA), two control inputs (S1, S0),
B QB and active-Low asynchronous clear (CLR). The shift register performs the following
C QC
functions.
D QD
SRI
S0
S1
Clear When CLR is Low, all other inputs are ignore and outputs QD –
CK
QA go to logic state zero.
CLR Load When S1 and S0 are High, the data on inputs D –A is loaded
X4181 into the corresponding output bits QD –QA during the Low-to-
High clock (CK) transition.
Shift Right When S1 is Low and S0 is High, the data is to the next-highest
bit position (right) as new data is loaded into
QA(SRI→QA,QA→QB, QB→QC, and so forth).
Shift Left When S1 is High and S0 is Low, the data is shifted to the next-
lowest bit position (left) as new data is loaded into QD
(SLI→QD,QD→QC,QC→QB, and so forth).

Registers can be cascaded by connecting the QD output of one stage to the SRI input
of the next stage, the QA output of one stage to the SLI input of the next stage, and
connecting clock, S1, S0, and CLR inputs in parallel.

Inputs Outputs

CLR S1 S0 SRI SLI A–D CK QA QB QC QD

0 X X X X X X 0 0 0 0
1 0 0 X X X X No Chg No Chg No Chg No Chg
1 1 1 X X A–D ↑ a b c d
1 0 1 SRI X X ↑ sri qa qb qc
1 1 0 X SLI X ↑ qb qc qd sli
Lowercase letters represent state of referenced input or output one setup time prior to
active clock transition

11-46 Xilinx Development System

Design Elements (X74_194)

M2_1
D0
O MLA
D1
S0 MLA M2_1 FDC
D0
O MA QA
D1 D Q
M2_1 S0 MA
SRI D0
O MRA C
A D1 CLR
S0 MRA QA

M2_1
D0
O MLB
D1
S0 MLB M2_1 FDC
D0
O MB QB
D1 D Q
M2_1 S0 MB
D0
O MRB C
B D1 CLR
S0 MRB QB

M2_1
D0
O MLC
D1
S0 MLC M2_1 FDC
D0
O MC QC
D1 D Q
M2_1 S0 MC
D0
O MRC C
C D1 CLR
S0 MRC QC

M2_1
D0
O MLD
SLI D1
S0 MLD M2_1 FDC
D0
O MD QD
D1 D Q
M2_1 S0 MD
D0
O MRD C
D D1 CLR
S1 S0 MRD QD
S0
CLR
CK INV
X7909

Figure 11-31 X74_194 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-47

Libraries Guide, Release M1.5

X74_195
4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A QA
X74_195 is a 4-bit shift register with shift-right serial inputs (J, active High, and K,
X74_195
B QB active Low), parallel inputs (D – A), parallel outputs (QD – QA) and QDB, shift/load
C QC control input (S_L), and active-Low asynchronous clear (CLR). Asynchronous CLR,
D QD when Low, overrides all other inputs and resets data outputs QD – QA Low and QDB
J QDB
K
High. When S_L is Low and CLR is High, data on the D – A inputs is loaded into the
S_L corresponding QD – QA bits of the register during the Low-to-High clock (CK) transi-
CK tion. When S_L and CLR are High, the first bit of the register (QA) responds to the J
and K inputs during the Low-to-High clock transition, as shown in the truth table.
CLR
During subsequent Low-to-High clock transitions, with S_L and CLR High, the data
X4182
is shifted to the next-highest bit position (shift right) as new data is loaded into QA (J,
K→QA, QA→QB, QB→QC, and so forth).
Registers can be cascaded by connecting the QD and QDB outputs of one stage to the
J and K inputs, respectively, of the next stage and connecting clock, S_L and CLR
inputs in parallel.

Inputs Outputs

CLR S_L J K A–D CK QA QB QC QD QDB

0 X X X X X 0 0 0 0 1
1 0 X X A–D ↑ a b c d d
1 1 0 0 X ↑ 0 qa qb qc qc
1 1 1 1 X ↑ 1 qa qb qc qc
1 1 0 1 X ↑ qa qa qb qc qc
1 1 1 0 X ↑ qa qa qb qc qc
Lowercase letters represent state of referenced input or output one setup time prior to active
clock transition

11-48 Xilinx Development System

Design Elements (X74_195)

J
NAND3B1

OR3B1 NAND3

NAND2
M2_1 FDC
A D0
O MA QA
D1 D Q
S0 MA
C
CLR
QA

M2_1 FDC
B D0
O MB QB
D1 D Q
S0 MB
C
CLR
QB

M2_1 FDC
C D0
O MC QC
D1 D Q
S0 MC
C
CLR
QC

M2_1 FDC
D D0
O MD QD
D1 D Q
QDB
S_L S0 MD
C INV
CLR
CLR CLRB QD

INV
CK
X7910

Figure 11-32 X74_195 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-49

Libraries Guide, Release M1.5

X74_273
8-Bit Data Register with Active-Low Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

X74_273 is an 8-bit data register with active-low asynchronous clear. The active-Low
D1 X74_273 Q1
D2 Q2 asynchronous clear (CLR), when Low, overrides all other inputs and resets the data
D3 Q3 outputs (Q8 – Q1) Low. When CLR is High, the data on the data inputs (D8 – D1) is
D4 Q4 transferred to the corresponding data outputs (Q8 – Q1) during the Low-to-High
D5 Q5
D6 Q6
clock transition (CK).
D7 Q7
D8 Q8
CK
Inputs Outputs
CLR
CLR D8 – D1 CK Q8 – Q1
X4183
0 X X 0
1 D8 – D1 ↑ d8 – d1
dn = state of referenced input one setup time prior to active clock transition

FDC
D1 Q1
D Q

C
CLR
Q1

FDC
D2 Q2
D Q

C
CLR
Q2

FDC
D3 Q3
D Q

C
CLR
Q3

FDC
D4 Q4
D Q

C
CLR
Q4

FDC
D5 Q5
D Q

C
CLR
Q5

FDC
D6 Q6
D Q

C
CLR
Q6

FDC
D7 Q7
D Q

C
CLR
Q7

FDC
D8 Q8
D Q

CK
C
CLR
CLR CLRB Q8
INV X7911

Figure 11-33 X74_273 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-50 Xilinx Development System

Design Elements (X74_280)

X74_280
9-Bit Odd/Even Parity Generator/Checker

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A X74_280
X74_280 parity generator/checker compares up to nine data inputs (I – A) and
B provides both even (EVEN) and odd parity (ODD) outputs. The EVEN output is High
C when an even number of inputs is High. The ODD output is High when an odd
D
EVEN number of inputs is High.
E
ODD
F
Expansion to larger word sizes is accomplished by tying the ODD outputs of up to
G
H
nine parallel components to the data inputs of one more X74_280; all other inputs are
I tied to ground.

X4184

Inputs Outputs

Number of Ones on A – I EVEN ODD

0, 2, 4, 6, or 8 1 0
1, 3, 5, 7, or 9 0 1

A
B
C X5
ODD
D
E
XOR5 XOR2
F
G
X4
H EVEN
I
XOR4 XNOR2
X7912

Figure 11-34 X74_280 Implementation XC3000, XC4000, XC5200, Spartans

A
B
C
D
E EVEN
F
G
H
I
XNOR9

ODD

XOR9 X7913

Figure 11-35 X74_280 Implementation XC9000

Libraries Guide, Release M1.5 11-51

Libraries Guide, Release M1.5

X74_283
4-Bit Full Adder with Carry-In and Carry-Out

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

CO X74_283 S1
X74_283, a 4-bit full adder with carry-in and carry-out, adds two 4-bit words (A4 – A1
A1 S2 and B4 – B1) and a carry-in (C0) and produces a binary sum output (S4 – S1) and a
A2 S3 carry-out (C4).
A3 S4
A4 C4 16(C4)+8(S4)+4(S3)+2(S2)+S1=8(A4+B4)+4(A3+B3)+2(A2+B2)+(A1+B1)+CO
B1 (where “+” = addition)
B2
B3 A1
B4 B1

AND2

X4185 C1
C0

AND2 OR3

AND2

XOR3

A2
B2

AND2
C2

AND2 OR3

AND2

XOR3

A3
B3

AND2
C3

AND2 OR3

AND2

XOR3

A4
B4

AND2
C4

AND2 OR3

AND2

X7914 XOR3

Figure 11-36 X74_283 Implementation XC3000, XC4000, XC5200, Spartans

11-52 Xilinx Development System

Design Elements (X74_283)

S3_0

CO ADD4X2

CI
A1
A0
A2
A1
A3
A2 S1
A4 S0
A3 S2
S1
S3
B1 S2
B0 S4
B2 S3
B1
B3
B2
B4
B3
CO

C4
X7915

Figure 11-37 X74_283 Implementation XC9000

Libraries Guide, Release M1.5 11-53

Libraries Guide, Release M1.5

X74_298
Quadruple 2-Input Multiplexer with Storage and Negative-Edge
Clock

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

A1 QA
X74_298 selects 4-bits of data from two sources (D1 – A1 or D2 – A2) under the control
X74_298
A2 of a common word select input (WS). When WS is Low, D1 – A1 is chosen, and when
B1 QB WS is High, D2 – A2 is chosen. The selected data is transferred into the output register
B2 (QD – QA) during the High-to-Low transition of the negative-edge triggered clock
C1 QC
C2
(CK).
D1 QD
D2
WS
CK Inputs Outputs

X4186
WS A1 – D1 A2 – D2 CK QA – QD
0 A1 – D1 X ↓ a1 – d1
1 X A2 – D2 ↓ a2 – d2
an – dn = state of referenced input one setup time prior to active clock transition

M2_1 FD_1
A1 D0
O MA QA
A2 D1 D Q
S0 MA
C

M2_1 FD_1
B1 D0
O MB QB
B2 D1 D Q
S0 MB
C

M2_1 FD_1
C1 D0
O MC QC
C2 D1 D Q
S0 MC
C

M2_1 FD_1
D1 D0
O MD QD
D2 D1 D Q
WS S0 MD
C
CK
QD X7916

Figure 11-38 X74_298 Implementation XC3000, XC4000, XC5200, Spartans

11-54 Xilinx Development System

Design Elements (X74_298)

CK
WS
INV

A1
FD
AND2B1 QA
D Q
A2
OR2
C
AND2
QA
B1
FD
QB
AND2B1 D Q
B2
OR2
C
AND2
QB
C1
FD
QC
AND2B1 D Q
C2
OR2
C
AND2
QC
D1
FD
QD
AND2B1 D Q
D2
OR2
C
AND2
QD

X7917

Figure 11-39 X74_298 Implementation XC9000

Libraries Guide, Release M1.5 11-55

Libraries Guide, Release M1.5

X74_352
Dual 4-to-1 Multiplexer with Active-Low Enables and Outputs

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

I1C0
X74_352 comprises two 4-to-1 multiplexers with separate enables (G1 and G2) but
X74_352 Y1
I1C1 with common select inputs (A and B). When an active-Low enable (G1 or G2) is Low,
I1C2 the multiplexer chooses one data bit from the four sources associated with the partic-
I1C3
ular enable (I1C3 – I1C0 for G1 and I2C3 – I2C0 for G2) under the control of the
I2C0 Y2
I2C1
common select inputs (A and B). The active-Low outputs (Y1 and Y2) reflect the
I2C2 inverse of the selected data as shown in truth table. Y1 is associated with G1 and Y2 is
I2C3 associated with G2. When an active-Low enable is High, the associated output is
A
High.
B
G1
G2

Inputs Outputs
X4187

G B A IC0 IC1 IC2 IC3 Y

1 X X X X X X 1
0 0 0 IC0 X X X IC0
0 0 1 X IC1 X X IC1
0 1 0 X X IC2 X IC2
0 1 1 X X X IC3 IC3

M2_1
I1C0 D0
O
I1C1 D1
S0 M1C01 M2_1E
M1C01 D0
O Y1B Y1
M1C23 D1
M2_1 S0 Y1 INV
I1C2 D0
O E
I1C3 D1
S0 M1C23

G1 G1B
INV
M2_1
I2C0 D0
O
I2C1 D1
S0 M2C01 M2_1E
M2C01 D0
O Y2B Y2
M2C23 D1
M2_1 S0 Y2 INV
I2C2 D0
O E
I2C3 D1
A S0 M2C23
B
G2 G2B

INV
X7918

Figure 11-40 X74_352 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-56 Xilinx Development System

Design Elements (X74_377)

X74_377
8-Bit Data Register with Active-Low Clock Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan Spartan Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

D1 Q1
When the active-Low clock enable (G) is Low, the data on the eight data inputs (D8 –
X74_377
D2 Q2 D1) is transferred to the corresponding data outputs (Q8 – Q1) during the Low-to-
D3 Q3 High clock (CK) transition. The register ignores clock transitions when G is High.
D4 Q4
D5 Q5
D6 Q6
D7 Q7 Inputs Outputs
D8 Q8
G
G D8 – D1 CK Q8 – Q1
CK
1 X X No Chg
X4188
0 D8 – D1 ↑ d8 – d1
dn = state of referenced input one setup time prior to active clock transition

FDCE
D1 Q1
D Q
CE
C
CLR
Q1

FDCE
D2 Q2
D Q
CE
C
CLR
Q2

FDCE
D3 Q3
D Q
CE
C
CLR
Q3

FDCE
D4 Q4
D Q
CE
C
CLR
Q4

FDCE
D5 Q5
D Q
CE
C
CLR
Q5

FDCE
D6 Q6
D Q
CE
C
CLR
Q6

FDCE
D7 Q7
D Q
CE
C
CLR
Q7

FDCE
D8 Q8
D Q
G GB
CE
CK INV
C
CLR
Q8

GND X7647

Figure 11-41 X74_377 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

Libraries Guide, Release M1.5 11-57

Libraries Guide, Release M1.5

X74_390
4-Bit BCD/Bi-Quinary Ripple Counter with Negative-Edge Clocks
and Asynchronous Clear

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

X74_390 is a cascadable, resettable binary-coded decimal (BCD) or bi-quinary counter

CKA X74_390 QA
CKB QB
that can be used to implement cycle lengths equal to whole and/or cumulative multi-
QC ples of 2 and/or 5. In BCD mode, the output QA is connected to negative-edge clock
QD input (CKB), and data outputs (QD – QA) increment during the High-to-Low clock
transition as shown in the truth table, provided asynchronous clear (CLR) is Low. In
CLR
bi-quinary mode, output QD is connected to the negative-edge clock input (CKA). As
X4189
shown in the truth table, in bi-quinary mode, QA supplies a divide-by-five output
and QB supplies a divide-by-two output, provided asynchronous CLR is Low. When
asynchronous CLR is High, the other inputs are overridden, and data outputs (QD –
QA) are reset Low.
Larger ripple counters are created by connecting the QD output (BCD mode) or QA
output (bi-quinary mode) of the first stage to the appropriate clock input of the next
stage and connecting the CLR inputs in parallel.

BCD Bi-Quinary
Count
QD QC QB QA QD QC QB QA
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 1 0
2 0 0 1 0 0 1 0 0
3 0 0 1 1 0 1 1 0
4 0 1 0 0 1 0 0 0
5 0 1 0 1 0 0 0 1
6 0 1 1 0 0 0 1 1
7 0 1 1 1 0 1 0 1
8 1 0 0 0 0 1 1 1
9 1 0 0 1 1 0 0 1

11-58 Xilinx Development System

Design Elements (X74_390)

VCC

FDCE_1
D0 QA
D Q
INV CE
CKA
C
CLR
QA

FDCE_1
D1 QB
D Q
NOR2 CE
C
CLR
QB

FDCE_1
AX2
D2 QC
D Q
AND2B1 CE
XOR2
C
CLR
QC

FDCE_1
OX3
A21 D3 QD
D Q
OR2 CE
CKB AND2 XOR2
C
CLR
CLR QD

X7919

Figure 11-42 X74_390 Implementation XC3000, XC4000, XC5200, Spartans

CKA
CKB INV
CLR INV

FDC
QA
D Q
INV
C
CLR
QA

FDC
QB
D Q
NOR2
C
CLR
QB

FDC
QC
D Q
XOR2
C
CLR
AND2B1 QC

FDC
QD
D Q
XOR2
C
CLR
OR2 QD

AND2 X7920

Figure 11-43 X74_390 Implementation XC9000

Libraries Guide, Release M1.5 11-59

Libraries Guide, Release M1.5

X74_518
8-Bit Identity Comparator with Active-Low Enable

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

P0
X74_518 is an 8-bit identity comparator with 16 data inputs for two 8-bit words (P7 –
X74_518
Q0 P0 and Q7 – Q0), data output (PEQ), and active-Low enable (G). When G is High, the
P1 PEQ output is Low. When G is Low and the two input words are equal, PEQ is High.
Q1
Equality is determined by a bit comparison of the two words. When any of the two
P2
Q2
equivalent bits from the two words are not equal, PEQ is Low.
P3
Q3 P0
PQ0
P4 PEQ Q0
Q4 XNOR2
P5
Q5 P1
PQ1
Q1
P6
Q6 XNOR2 PQ03
P7
P2
Q7 PQ2
Q2 AND4
G
XNOR2

X4190 P3
PQ3
Q3
XNOR2 PEQ

P4
PQ4 AND3B1
Q4
XNOR2

P5
PQ5
Q5
XNOR2 PQ47

P6
PQ6
Q6 AND4

XNOR2

P7
PQ7
Q7

XNOR2

G
X7921

Figure 11-44 X74_518 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-60 Xilinx Development System

Design Elements (X74_521)

X74_521
8-Bit Identity Comparator with Active-Low Enable and Output

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

Macro Macro Macro Macro Macro Macro Macro N/A

P0
X74_521 is an 8-bit identity comparator with 16 data inputs for two 8-bit words (P7 –
X74_521
Q0 P0 and Q7 – Q0), active-Low data output (PEQ), and active-Low enable (G). When G
P1 is High, the PEQ output is High. When G is Low and the two input words are equal,
Q1 PEQ is Low. X74_521 does a bit comparison of the two words to determine equality.
P2
Q2
When any of the two equivalent bits from the two words are not equal, PEQ is High.
P3
Q3
P4 PEQ
Q4 Inputs Outputs
P5
Q5 G P7, Q7 P6, Q6 P5, Q5 P4, Q4 P3, Q3 P2, Q2 P1, Q1 P0, Q0 PEQ
P6
Q6 1 X X X X X X X X 1
P7
Q7
0 P7≠Q7 X X X X X X X 1
G 0 X P6≠Q6 X X X X X X 1
X4191 0 X X P5≠Q5 X X X X X 1
0 X X X P4≠Q4 X X X X 1
0 X X X X P3≠Q3 X X X 1
0 X X X X X P2≠Q2 X X 1
0 X X X X X X P1≠Q1 X 1
0 X X X X X X X P0≠Q0 1
0 P7=Q7 P6=Q6 P5=Q5 P4=Q4 P3=Q3 P2=Q2 P1=Q1 P0=Q0 0

Libraries Guide, Release M1.5 11-61

Libraries Guide, Release M1.5

P0
PQ0
Q0

XNOR2

P1
PQ1
Q1

XNOR2 PQ03

P2
PQ2
Q2 AND4

XNOR2

P3
PQ3
Q3
XNOR2 PEQ

P4
PQ4 NAND3B1
Q4
XNOR2

P5
PQ5
Q5
XNOR2 PQ47

P6
PQ6
Q6 AND4

XNOR2

P7
PQ7
Q7

XNOR2

G
X7922

Figure 11-45 X74_521 Implementation XC3000, XC4000, XC5200, XC9000,

Spartans

11-62 Xilinx Development System

Chapter 12

Attributes, Constraints, and Carry Logic

This chapter lists and describes all the attributes that you can use with your design
entry software and the constraints that are contained in machine- and user-generated
files.
This chapter contains the following major sections.
• “Overview”
• “Information for Mentor Customers”
• “Schematic Syntax”
• “UCF/NCF File Syntax”
• “Attributes/Logical Constraints”
This section contains alphabetical listings of the attributes and constraints as well
as descriptions, syntax, and examples of each constraint.
• “Placement Constraints”
• “Relative Location (RLOC) Constraints”
• “Timing Constraints”
• “Physical Constraints”
• “Relationally Placed Macros (RPMs)”
• “Carry Logic in XC4000 and Spartans”
• “Carry Logic in XC5200”
• “Carry Logic in Virtex”

Overview
This section gives an overview of attributes, constraints, and carry logic.

Attributes
Attributes are instructions placed on symbols or nets in an FPGA or CPLD schematic
to indicate their placement, implementation, naming, directionality, and so forth. This
information is used by the design implementation software during placement and
routing of a design. All the attributes listed in this chapter are available in the sche-
matic entry tools directly supported by Xilinx unless otherwise noted, but some may
not be available in textual entry methods such as VHDL.
Attributes applicable only to a certain schematic entry tool are described in the docu-
mentation for that tool. For third-party interfaces, consult the interface user guides for
information on which attributes are available and how they are used.

Libraries Guide, Release M1.5 — 12-1

Libraries Guide, Release M1.5

Refer to the “Schematic Syntax” section in this chapter for guidelines on placing
attributes on symbols on a schematic.

Constraints
Constraints, which are a type, or subset, of attributes, indicate where an element
should be placed.

Logical Constraints
Constraints that are attached to elements in the design prior to mapping are referred
to as logical constraints. Applying logical constraints helps you to adapt your design’s
performance to expected worst-case conditions. Later, when you choose a specific
Xilinx architecture and place and route your design, the logical constraints are
converted into physical constraints.
You can attach logical constraints using attributes in the input design, which are
written into the Netlist Constraints File (NCF), or with a User Constraints File (UCF).
Refer to the “UCF/NCF File Syntax” section for the rules for entering constraints in a
UCF or NCF file.
Three categories of logical constraints are described in detail in the “Attributes/
Logical Constraints” section: placement constraints, relative location constraints, and
timing constraints.
The “Placement Constraints” section gives examples showing how to place
constraints on the various types of logic elements in FPGA designs.
For FPGAs, relative location constraints (RLOCs) group logic elements into discrete
sets and allow you to define the location of any element within the set relative to other
elements in the set, regardless of eventual placement in the overall design. Refer to the
“Relative Location (RLOC) Constraints” section for detailed information on RLOCs.
Timing constraints allow you to specify the maximum allowable delay or skew on any
given set of paths or nets in your design. Refer to the “Timing Constraints” section for
detailed information on using timing constraints in a UCF file.

Physical Constraints
Constraints can also be attached to the elements in the physical design, that is, the
design after mapping has been performed. These constraints are referred to as phys-
ical constraints and are defined in the Physical Constraints File (PCF), which is
created during mapping. See the “Physical Constraints” section.
Note: It is preferable to place any user-generated constraint in the UCF file — not in
an NCF or PCF file.

Carry Logic
Dedicated fast carry logic increases the efficiency and performance of adders,
subtracters, accumulators, comparators, and counters. See the “Carry Logic in
XC4000 and Spartans” section, “Carry Logic in XC5200” section, and “Carry Logic in
Virtex” section at the end of this chapter.

12-2 Xilinx Development System

Attributes, Constraints, and Carry Logic

Information for Mentor Customers

In some software programs, particularly Mentor Graphics, attributes are called prop-
erties, but their functionality is the same as that of attributes. In this document, they
are referred to as attributes.
There are two types of Mentor Graphics properties. In one, a property is equal to a
value, for example, LOC=AA. In the other, the property name and the value are the
same, for example, DECODE. In the first type, “attribute” refers to the property. In the
second, “attribute” refers to the property and the value.
The Mentor netlist writer program (ENWRITE) converts all property names to lower-
case letters, and the Xilinx netlist reader EDIF2NGD then converts the property
names to uppercase letters. Because property names are processed in this way, you
must enter the variable text of certain constraints in uppercase letters only. The most
salient examples are the following.
• A TSidentifier name should contain only uppercase letters on a Mentor Schematic
(TSMAIN, for example, but not TSmain or TSMain). Also, if a TSidentifier name is
referenced in a property value, it must be entered in uppercase letters. For
example, the TSID1 in the second constraint below must be entered in uppercase
letters to match the TSID1 name in the first constraint.
TSID1 = FROM: gr1: TO: gr2: 50;
TSMAIN = FROM: here: TO: there: TSID1: /2;
• Group names should contain only uppercase letters on a Mentor schematic
(MY_FLOPS, for example, but not my_flops or My_flops).
• If a group name appears in a property value, it must also be expressed in upper-
case letters. For example, the GROUP3 in the first constraint below must be
entered in uppercase letters to match the GROUP3 in the second constraint.
TIMEGRP GROUP1 = gr2: GROUP3;
TIMEGRP GROUP3 = FFS: except: grp5;

Schematic Syntax
This section describes how to place attributes on symbols on a schematic. The
following guidelines are for specifying locations.
• To specify a single location, use the following syntax.
attribute=location
• To specify multiple locations, use the following syntax.
attribute=location,location,location
A comma separates locations in a list of locations. (Spaces are ignored if entered.)
When you specify a list of locations, PAR (Place and Route) chooses any one of the
listed locations.
• To define a range by specifying the two corners of a bounding box, use the
following syntax.
attribute=location:location [SOFT]
A colon is only used to separate the corners of a bounding box. The logic repre-
sented by the symbol is placed somewhere inside the bounding box. If SOFT is
specified, PAR may place the attribute elsewhere to obtain better results.

Libraries Guide, Release M1.5 12-3

Libraries Guide, Release M1.5

Following are some examples of location attributes.

LOC=CLB_R1C2 Locates the element in the CLB in the first row,
second column.
LOC=CLB_R1C2.LC3 Locates the element in the top-most slice of the
four slices of the XC5200 CLB located in the first
row, second column.
LOC=CLB_R1C2.S1 Locates the element in the right-most slice of the
two slices of the Virtex CLB located in the first
row, second column.
LOC=P12 Assigns the signal to the pin P12 (for CPLDs).
RLOC=R4C4 Assigns the location relative to other elements in
the set to row 4, column 4.
RLOC=R0Cl.FFX Assigns the location relative to other elements in
the set to the X flip-flop in row 0, column 1.
RLOC=R2C3.LC0 Assigns the location of the element to be one slice
below another element in the set that has an
RLOC=R2C3.LC1 attribute. (XC5200)
RLOC=R2C3.S0 Assigns the location of the element to be the left-
most slice of another element in the set that has
an RLOC=R2C3.S1 attribute. (Virtex)
RLOC_ORIGIN=R4C4 Fixes the reference CLB of a designated set at row
4, column 4.
RLOC_RANGE=R4C4 : R10C10 Limits the members of a designated set to a range
between row 4, column 4 and row 10, column 10.
A name can be composed of any ASCII character except for control characters and
characters that have special meanings.
Control characters are : (colon) ; (semi-colon) , (comma) and “(double quotes).
Characters with special meaning are / (forward slash) used as the hierarchy separator
and . (period) used as the pin separator and for extensions.
For additional propagation rules for each constraint and attribute, refer to the “Macro
and Net Propagation Rules” table in the "Attributes/Logical Constraints" section.

UCF/NCF File Syntax

Logical constraints are found in a Netlist Constraint File (NCF), an ASCII file gener-
ated by synthesis programs, and in a User Constraint File (UCF), an ASCII file gener-
ated by the user. This section describes the rules for entering constraints in a UCF or
NCF file.
Note: It is preferable to place any user-generated constraint in the UCF file — not in
an NCF or PCF file.
The UCF and NCF files are case sensitive. Identifier names (names of objects in the
design, such as net names) must exactly match the case of the name as it exists in the
source design netlist. However, any Xilinx constraint keyword (for example, LOC,
PERIOD, HIGH, LOW) may be entered in either all upper-case or all lower-case
letters; mixed case is not allowed.
Each statement is terminated by a semicolon (;).

12-4 Xilinx Development System

Attributes, Constraints, and Carry Logic

No continuation characters are necessary if a statement exceeds one line, since a semi-
colon marks the end of the statement.
You can add comments to the UCF/NCF file by beginning each comment line with a
pound (#) sign. Following is an example of part of a UCF/NCF file containing
comments.
# file TEST.UCF
# net constraints for TEST design
NET $SIG_0 MAXDELAY 10 ;
NET $SIG_1 MAXDELAY 12 ns ;
Statements do not have to be placed in any particular order in the UCF/NCF file.
The constraints in the UCF/NCF files and the constraints in the schematic or
synthesis file are applied equally; it does not matter whether a constraint is entered in
the schematic or synthesis file or in the UCF/NCF files. If the constraints overlap,
however, UCF/NCF constraints override the schematic constraint. Refer to the
“Constraints Priority” section of the “Using Timing Constraints” chapter of the Devel-
opment System Reference Guide for additional details on constraint priorities.
If by mistake two or more elements are locked onto a single location, the mapper
detects the conflict, issues a detailed error message, and stops processing so that you
can correct the mistake.
The syntax for constraints in the UCF/NCF files is as follows.
{NET | INST | PIN} full_name constraint ;
or
SET set_name set_constraint ;
where
full_name is a full hierarchically qualified name of the object being referred to. When
the name refers to a pin, the instance name of the element is also required.
constraint is a constraint in the same form as it would be used if it were attached as an
attribute on a schematic object. For example, LOC=P38 or FAST, and so forth.
set_name is the name of an RLOC set. Refer to the “RLOC Sets” section for more infor-
mation.
set_constraint is an RLOC_ORIGIN or RLOC_RANGE constraint.
Note: To specify attributes for the CONFIG or TIMEGRP primitives (tables), the
keywords CONFIG or TIMEGRP precede the attribute definitions in the constraints
files.
CONFIG PROHIBIT=CLB_R6C8 ;
TIMEGRP input_pads=pads EXCEPT output_pads ;
For the TIMESPEC primitive (table), the use of the keyword TIMESPEC in the
constraints files is optional.
Note: In all of the constraints files (NCF, UCF, and PCF), instance or variable names
that match internal reserved words will be rejected unless the names are enclosed in
double quotes. It is good practice to enclose all names in double quotes.
For example, the following entry would not be accepted because the word net is a
reserved word.
NET net OFFSET=IN 20 BEFORE CLOCK;

Libraries Guide, Release M1.5 12-5

Libraries Guide, Release M1.5

Following is the recommended way to enter the constraint.

NET “net” OFFSET=IN 20 BEFORE CLOCK;
or
NET “$SIG_0” OFFSET=IN 20 BEFORE CLOCK;
Inverted signal names, for example ~OUTSIG1, must always be enclosed in double
quotes as shown in the following example.
NET “~OUTSIG1” OFFSET=IN 20 BEFORE CLOCK;

Wildcards
You can use the wildcard characters, * and ?, in constraint statements as follows. The
asterisk (*) represents any string of zero or more characters. The question mark (?)
indicates a single character.
In net names, the wildcard characters enable you to select a group of symbols whose
output net names match a specific string or pattern. For example, the following
constraint increases the output speed of the pads to which nets with names that begin
with any series of characters followed by "AT" and end with one single characters are
connected.
NET *AT? FAST ;
In an instance name, a wildcard character by itself represents every symbol of the
appropriate type. For example, the following constraint initializes an entire set of
ROMs to a particular hexadecimal value, 5555.
INST $1I3*/ROM2 INIT=5555 ;
If the wildcard character is used as part of a longer instance name, the wildcard repre-
sents one or more characters at that position.
In a location, you can use a wildcard character for either the row number or the
column number. For example, the following constraint specifies placement of any
instance under the hierarchy of loads_of_logic in any CLB in column 8.
INST /loads_of_logic/* LOC=CLB_r*c8 ;
Wildcard characters can be used in dot extensions.
CLB_R1C3.*
Wildcard characters cannot be used for both the row number and the column number
in a single constraint, since such a constraint is meaningless.

Traversing Hierarchies
Note: Top-level block names (design names) are ignored when searching for instance
name matches.
You can use the asterisk wildcard character (*) to traverse the hierarchy of a design
within a UCF or NCF file. The following syntax applies (where level1 is an example
hierarchy level name).

* Traverses all levels of the hierarchy

level1/* Traverses all blocks in level1 and below
level1/*/ Traverses all blocks in the level1 hierarchy level but no further

12-6 Xilinx Development System

Attributes, Constraints, and Carry Logic

Consider the following design hierarchy.

$A1 $B1 $C1

$A21 $A22 $B21 $B22 $C21 $C22

$A3 $B3 $C3

$A4

X8571

With the example design hierarchy, the following specifications illustrate the scope of
the wildcard.
INST * => <everything>
INST /* => <everything>
INST /*/ => <$A1,$B1,$C1>
INST $A1/* => <$A21,$A22,$A3,$A4>
INST $A1/*/ => <$A21,$A22>
INST $A1/*/* => <$A3,$A4>
INST $A1/*/*/ => <$A3>
INST $A1/*/*/* => <$A4>
INST $A1/*/*/*/ => <$A4>
INST /*/*22/ => <$A22,$B22,$C22>
INST /*/*22 => <$A22,$A3,$A4,$B22,$B3,$C22,$C3>

File Name
By default, NGDBuild reads the constraints file that carries the same name as the
input design with a .ucf extension; however, you can specify a different constraints
file name with the -uc option when running NGDBuild. NGDBuild automatically
reads in the NCF file if it has the same base name as the input XNF or EDIF file and is
in the same directory as the XNF or EDIF file.
Note: The implementation tools (NGDBuild, MAP, PAR, etc.) require file name exten-
sions in all lowercase (.ucf, for example) in command lines.

Instances and Blocks

Because the statements in the constraints file concern instances and blocks, these enti-
ties are defined here.
An instance is a symbol on the schematic. An instance name is the symbol name as it
appears in the EDIF or XNF netlist. A block is a CLB, an IOB, or a TBUF. You can
specify the block name by using the BLKNM, HBLKNM, or the XBLKNM attribute; by
default, the software assigns a block name on the basis of a signal name associated
with the block.

Libraries Guide, Release M1.5 12-7

Libraries Guide, Release M1.5

Attributes/Logical Constraints
Syntax Summary
This section summarizes attribute and logical constraints syntax. This syntax
conforms to the conventions given in the “Conventions” section. A checkmark (√)
appearing in a column means that the attribute/constraint is supported for architec-
tures that use the indicated library. (Refer to the “Applicable Architectures” section of
the “Xilinx Unified Libraries” chapter for information on the specific device architec-
tures supported in each library.) A blank column means that the attribute/constraint
is not supported for architectures using that library.

BASE BASE = {F | FG | FGM | IO}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

BLKNM BLKNM = block_name

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

BUFG BUFG = {CLK | OE | SR}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CLKDV_DIVIDE CLKDV_DIVIDE={ 1.5 | 2 | 2.5 | 3 | 4 | 5 | 8 | 16}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

COLLAPSE COLLAPSE
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

CONFIG* CONFIG = tag value [tag value]

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√
*The CONFIG attribute configures internal options of an XC3000 CLB or IOB. Do not confuse this attribute with the CONFIG
primitive, which is a table containing PROHIBIT and PART attributes.

DECODE DECODE
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √

12-8 Xilinx Development System

Attributes, Constraints, and Carry Logic

DIVIDE1_BY and DIVIDE1_BY = {4 | 16 | 64 | 256}

DIVIDE2_BY DIVIDE2_BY = {2 | 8 | 32 | 128 | 1024 | 4096 | 16384 | 65536}
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

DOUBLE DOUBLE
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

DRIVE XC4000X, SpartanXL:

DRIVE = {12 |24}
Virtex:
DRIVE = {2 | 4 | 6 | 8 | 12 | 16 | 24}
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√∗ √ √
* supported for XC4000XV and XC4000XLA designs only

DROP_SPEC TSidentifier=DROP_SPEC
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

DUTY_CYCLE_ DUTY_CYCLE_CORRECTION={TRUE | FALSE}

CORRECTION
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

EQUATE_F and EQUATE_F = equation

EQUATE_G EQUATE_G = equation
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

FAST FAST
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

Libraries Guide, Release M1.5 12-9

Libraries Guide, Release M1.5

FILE FILE = file_name [.extension]

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

HBLKNM HBLKNM = block_name

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

HU_SET HU_SET = set_name

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

INIT INIT ={S | R | value}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

INIT_0x INIT_0x = value

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

INREG INREG
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

IOB IOB={TRUE | FALSE}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

KEEP KEEP
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √∗
*Only at BEL level

12-10 Xilinx Development System

Attributes, Constraints, and Carry Logic

LOC FPGAs:
LOC=location1[,location2,... , locationn]
or:
LOC=location : location [SOFT ]
CPLDs:
LOC = {pin_name | FBnn | FBnn_mm}
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

MAP MAP = [PUC | PUO | PLC | PLO ]*

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √
*Only PUC and PUO are observed. PLC and PLO are translated to PUC and PUO, respectively. The default is PUO.

MAXDELAY MAXDELAY = allowable_delay [units]

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

MAXSKEW MAXSKEW = allowable_skew [units]

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

MEDDELAY MEDDELAY
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

NODELAY NODELAY
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √

NOREDUCE NOREDUCE
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √

Libraries Guide, Release M1.5 12-11

Libraries Guide, Release M1.5

OFFSET OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} "clk_net" [TIMEGRP

"reggroup"]
or:
NET "name" OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} "clk_net"
[TIMEGRP "reggroup"]
or:
TIMEGRP "group" OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER}
"clk_net" [TIMEGRP "reggroup"]
or:
TSidentifier= [TIMEGRP name] OFFSET = {IN|OUT} offset_time [units]
{BEFORE|AFTER} "clk_net" [TIMEGRP "reggroup"]
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

OPT_EFFORT OPT_EFFORT= {NORMAL | HIGH}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

OPTIMIZE OPTIMIZE ={AREA | SPEED | BALANCE | OFF}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

OUTREG OUTREG
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

PART PART = part_type

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

PERIOD PERIOD = period[units] [{HIGH | LOW} [high_or_low_time [hi_lo_units]]]

or:
TSidentifier=PERIOD TNM_reference period[units] [{HIGH | LOW} [high_or_low_time
[hi_lo_units]]]
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

12-12 Xilinx Development System

Attributes, Constraints, and Carry Logic

PROHIBIT PROHIBIT = location1[, location2, ... , locationn]

or:
PROHIBIT = location : location
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

PWR_MODE PWR_MODE ={LOW | STD}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

RLOC XC4000:
RLOC = RmCn[.extension]
XC5200, Virtex:
RLOC = RmCn.extension
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

RLOC_ORIGIN RLOC_ORIGIN = RmCn

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

RLOC_RANGE RLOC_RANGE = Rm1Cn1:Rm2Cn2

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

S(ave) - Net Flag Attribute S

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

SLOW SLOW
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

STARTUP_WAIT STARUP_WAIT={TRUE | FALSE}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√

Libraries Guide, Release M1.5 12-13

Libraries Guide, Release M1.5

TEMPERATURE TEMPERATURE=value[C | F | K ]
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√∗ √∗ √∗ √∗ √∗ √∗ √∗
*Availability depends on the release of characterization data

TIG TIG
or:
TIG= TSidentifier1 [, TSidentifier2, ... ,TSidentifiern]
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

Time Group Attributes new_group_name=[RISING | FALLING] group_name1 [EXCEPT group_name2...

group_namen]
or:
new_group_name=[TRANSHI | TRANSLO] group_name1 [EXCEPT group_name2...
group_namen]
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

TNM TNM = [predefined_group:] identifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

TNM_NET TNM_NET = [predefined_group:] identifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

TPSYNC TPSYNC = identifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

TPTHRU TPTHRU = identifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √

12-14 Xilinx Development System

Attributes, Constraints, and Carry Logic

TSidentifier TSidentifier=[MAXDELAY] FROM source_group TO dest_group allowable_delay [units]

or:
TSidentifier=FROM source_group TO dest_group allowable_delay [units]
or:
TSidentifier=FROM source_group THRU thru_point [THRU thru_point1... thru_pointn]
TO dest_group allowable_delay [units]
or:
TSidentifier=FROM source_group TO dest_group another_TSid[/ | *] number
or:
TSidentifier=PERIOD TNM_reference period[units] [{HIGH | LOW} [high_or_low_time
[hi_lo_units]]]
or:
TSidentifier=PERIOD TNM_reference another_PERIOD_identifier [/ | *] number
[{HIGH | LOW} [high_or_low_time [hi_lo_units]]]
or:
TSidentifier=FROM source_group TO dest_group TIG
or:
TSidentifier=FROM source_group THRU thru_point [THRU thru_point1... thru_pointn]
TO dest_group TIG
NOTE:
The use of a colon (:) instead of a space as a separator is optional.
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √ √ √

U_SET U_SET = name

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

USE_RLOC USE_RLOC = {TRUE | FALSE}

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

VOLTAGE VOLTAGE=value[V]
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√∗ √∗ √∗ √∗ √∗ √∗ √∗
*Availability depends on the release of characterization data

WIREAND WIREAND
XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√∗
* not supported for XC9500XL designs only

Libraries Guide, Release M1.5 12-15

Libraries Guide, Release M1.5

XBLKNM XBLKNM = block_name

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex
√ √ √ √ √ √

12-16 Xilinx Development System

Attributes, Constraints, and Carry Logic

Attributes/Constraints Applicability
Certain constraints can only be defined at the design level, whereas other constraints
can be defined in the various configuration files. The following table lists the
constraints and their applicability to the design, and the NCF, UCF, and PCF files. A
check mark (√) indicates that the constraint applies to the item for that column.
Table 12-1 Constraint Applicability Table

Attribute/Constraint Design NCF UCF PCF

BASE √
BLKNM √ √ √
BUFG √ √ √
CLKDV_DIVIDE √ √ √
COLLAPSE √ √ √
COMPGRP √
CONFIG** √
DECODE √ √ √
DIVIDE1_BY √ √
DIVIDE2_BY √ √
DOUBLE √
DRIVE √ √ √
DROP_SPEC √ √ √∗
DUTY_CYCLE_CORRECTION √ √ √
EQUATE_F √
EQUATE_G √
FAST √ √ √
FILE √
FREQUENCY √
HBLKNM √ √ √
HU_SET √ √ √
INIT √ √
INIT_0x √ √ √
INREG √ √ √ √
IOB √ √ √
KEEP √ √ √
LOC √ √ √ √*
LOCATE √
LOCK √
MAP √ √ √
MAXDELAY √ √ √ √*
MAXSKEW √ √ √ √*
MEDDELAY √ √ √

Libraries Guide, Release M1.5 12-17

Libraries Guide, Release M1.5

Table 12-1 Constraint Applicability Table

Attribute/Constraint Design NCF UCF PCF

NODELAY √ √ √
NOREDUCE √ √ √
OFFSET √ √ √*
OPT_EFFORT √ √ √
OPTIMIZE √ √ √
OUTREG √ √ √ √
PATH √
PART √ √ √
PENALIZE TILDE √
PERIOD √ √ √ √*
PIN √
PRIORITIZE √
PROHIBIT √ √ √ √*
PWR_MODE √ √ √
RLOC √ √ √
RLOC_ORIGIN √ √ √ √
RLOC_RANGE √ √ √ √
S(ave) - Net Flag attribute √ √ √
SITEGRP √
SLOW √ √ √
STARTUP_WAIT √ √ √
TEMPERATURE √ √ √ √
TIG √ √ √ √*
Time group attributes √ √ √ √
TNM √ √ √
TNM_NET √ √ √
TPSYNC √ √ √
TPTHRU √ √ √
TSidentifier √ √ √ √*
U_SET √ √ √
USE_RLOC √ √ √
VOLTAGE √ √ √ √
WIREAND √ √ √
XBLKNM √ √ √
*Use cautiously — while constraint is available, there are differences between the UCF/
NCF and PCF syntax.
**The CONFIG attribute configures internal options of an XC3000 CLB or IOB. Do not
confuse this attribute with the CONFIG primitive, which is a table containing PROHIBIT
and PART attributes.

12-18 Xilinx Development System

Attributes, Constraints, and Carry Logic

Macro and Net Propagation Rules

Not all constraints can be attached to nets and macros. The following table lists the
constraints and stipulates whether they can be attached to a net, a macro, or neither.

Table 12-2 Macro and Net Propagation Rules

Action when Action when attached

Constraint/Attribute
attached to a net to a macro
BASE illegal illegal
BLKNM illegal Note 4
BUFG Note 3 illegal
CLKDV_DIVIDE illegal illegal
COLLAPSE Note 3 illegal
CONFIG* illegal illegal
DECODE Note 1 Note 4
DIVIDE1_BY and DIVIDE2_BY Note 1 Note 4
DOUBLE Note 1 Note 4
DRIVE Note 6 Note4
DROP_SPEC illegal illegal
DUTY_CYCLE_CORRECTION illegal Note 4
EQUATE_F and EQUATE_G illegal illegal
FAST Note 6 Note 4
FILE illegal Note 5
HBLKNM illegal Note 4
HU_SET illegal Note 4
INIT FPGA: illegal Note 4
CPLD: Note 1
INIT_0x illegal illegal
INREG illegal illegal
IOB illegal Note 4
KEEP Note 3 illegal
LOC FPGA: Note 6 Note 4
CPLD: Note 1
MAP illegal illegal
MAXDELAY Note 3 illegal
MAXSKEW Note 3 illegal
MEDDELAY Note 6 Note 4
NODELAY Note 6 Note 4
NOREDUCE Note 3 illegal
OFFSET Note 3 illegal
OPTIMIZE illegal Note 5

Libraries Guide, Release M1.5 12-19

Libraries Guide, Release M1.5

Table 12-2 Macro and Net Propagation Rules

Action when Action when attached

Constraint/Attribute
attached to a net to a macro
OPT_EFFORT illegal Note 5
OUTREG illegal illegal
PART illegal illegal
PERIOD Note 3 illegal
PROHIBIT illegal illegal
PWR_MODE Note 2 Note 4
RLOC illegal Note 4
RLOC_ORIGIN illegal Note 4
RLOC_RANGE illegal Note 4
S(ave) - Net Flag Attribute Note 3 illegal
SLOW Note 6 Note 4
STARTUP_WAIT illegal Note 4
TEMPERATURE illegal illegal
TIG Note 2 Note 4
Time Group Attributes illegal illegal
TNM Note 2 Note 4
TNM_NET Note 2 illegal
TPSYNC Note 3 illegal
TPTHRU Note 3 illegal
TSidentifier illegal illegal
U_SET illegal Note 4
USE_RLOC illegal Note 4
VOLTAGE illegal illegal
WIREAND Note 3 illegal
XBLKNM illegal Note 4
Note 1: Attaches to all applicable elements that drive the net.
Note 2: The attribute has a net form and so no special propagation is required.
Note 3: Attribute is a net attribute and any attachment to a macro is illegal.
Note 4: Propagated to all applicable elements in the hierarchy below the module.
Note 5: Attribute is a macro attribute and any attachment to a net is illegal.
Note 6: Attribute is illegal when attached to a net except when the net is connected to a pad.
In this case, the attribute is treated as attached to the pad instance.
*The CONFIG attribute configures internal options of an XC3000 CLB or IOB. Do not
confuse this attribute with the CONFIG primitive, which is a table containing PROHIBIT
and PART attributes.

12-20 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax Descriptions
The information that follows describes in alphabetical order the attributes and
constraints. A checkmark (√) appearing in a column means that the attribute/
constraint is supported for architectures that use the indicated library. (Refer to the
“Applicable Architectures” section of the “Xilinx Unified Libraries” chapter for infor-
mation on the specific device architectures supported in each library.) A blank column
means that the attribute/constraint is not supported for architectures that use that
library.
The description for each attribute contains a subsection entitled “Applicable
Elements.” This section describes the base primitives and circuit elements to which
the constraint or attribute can be attached. In many cases, constraints or attributes can
be attached to macro elements, in which case some resolution of the user’s intent is
required. Refer to the “Macro and Net Propagation Rules” section for a table
describing the additional propagation rules for each constraint and attribute.

BASE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
CLB or IOB primitives

Description
The BASE attribute defines the base configuration of a CLB or an IOB. For an IOB
primitive, it should always be set to IO. For a CLB primitive, it can be one of three
modes in which the CLB function generator operates.
• F mode allows the CLB to implement any one function of up to five variables.
• FG mode gives the CLB any two functions of up to four variables. Of the two sets
of four variables, one input (A) must be common, two (B and C) can be either
independent inputs or feedback from the Qx and Qy outputs of the flip-flops
within the CLB, and the fourth can be either of the two other inputs to the CLB (D
and E).
• FGM mode is similar to FG, but the fourth input must be the D input. The E input
is then used to control a multiplexer between the two four-input functions,
allowing some six- and seven-input functions to be implemented.
CLB and IOB base configurations of the XC3000 family are illustrated in the “IOB and
CLB Primitives for Base Configurations XC3000” figure. In this drawing, BASE F, FG,
and FGM are for CLBs; BASE IO is for IOBs.

Libraries Guide, Release M1.5 12-21

Libraries Guide, Release M1.5

CLB: BASE F CLB: BASE FG

QX F QX

F
QY G QY

CLB: BASE FGM IOB: BASE IO

F M QX

PAD
G QY

X4708

Figure 12-1 IOB and CLB Primitives for Base Configurations XC3000
In a schematic, BASE can be attached to any valid instance. Not supported for UCF,
NCF, or PCF files.

Syntax
BASE=mode
where mode can be F, FG, or FGM for a CLB and IO for an IOB.

Example
Schematic
Attached to a valid instance.
UCF/NCF file
N/A

BLKNM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1, 2, 3, 7, 8 2, 3, 4, 5, 7, 8, 2, 3, 4, 5, 7, 8, 2, 3, 4, 6, 7, 2, 3, 4, 5, 7, 8, 2, 3, 4, 5, 7, 8,
9, 10, 11 9, 10, 11 11 9, 10, 11 9, 10, 11

Applicable Elements
1. IOB, CLB and CLBMAP (See the Note at the end of this list)
2. Flip-flop and latch primitives
3. Any I/O element or pad
4. FMAP
5. HMAP
6. F5MAP

12-22 Xilinx Development System

Attributes, Constraints, and Carry Logic

7. BUFT
8. ROM primitive
9. RAM primitives
10. RAMS and RAMD primitives
11. Carry logic primitives
Note: You can also attach the BLKNM constraint to the net connected to the pad
component in a UCF file. NGDBuild transfers the constraint from the net to the pad
instance in the NGD file so that it can be processed by the mapper. Use the following
syntax.
NET net_name BLKNM=property_value

Description
Assigns block names to qualifying primitives and logic elements. If the same BLKNM
attribute is assigned to more than one instance, the software attempts to map them
into the same block. Conversely, two symbols with different BLKNM names are not
mapped into the same block. Placing similar BLKNMs on instances that do not fit
within one block creates an error.
Specifying identical BLKNM attributes on FMAP and/or HMAP symbols tells the
software to group the associated function generators into a single CLB. Using
BLKNM, you can partition a complete CLB without constraining the CLB to a phys-
ical location on the device.
BLKNM attributes, like LOC constraints, are specified from the schematic. Hierar-
chical paths are not prefixed to BLKNM attributes, so BLKNM attributes for different
CLBs must be unique throughout the entire design. See the section on the
“HBLKNM” attribute for information on attaching hierarchy to block names.
The BLKNM attribute allows any elements except those with a different BLKNM to be
mapped into the same physical component. Elements without a BLKNM can be
packed with those that have a BLKNM. See the section on the “XBLKNM” attribute
for information on allowing only elements with the same XBLKNM to be mapped
into the same physical component.
For XC5200, a given BLKNM string can only be used to group a logic cell (LC), which
contains one register, one LUT (FMAP), and one F5_MUX element. An error will
occur if two or more registers, two or more FMAPs, or two or more F5_MUX elements
have the same BLKNM attribute.

Syntax
BLKNM=block_name
where block_name is a valid LCA block name for that type of symbol. For a list of
prohibited block names, see the “Naming Conventions” section of each user interface
manual.
For information on assigning hierarchical block names, see the “HBLKNM” section
elsewhere in this chapter.

Libraries Guide, Release M1.5 12-23

Libraries Guide, Release M1.5

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement assigns an instantiation of an element named block1 to a block named
U1358.
INST $1I87/block1 BLKNM=U1358;

BUFG

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Any input buffer (IBUF) that drives a CLK, OE, or SR pin or the pad net connected to
the IBUF input

Description
Maps the tagged signal to a global net.

Syntax
BUFG={CLK | OE | SR}
where CLK, OE, and SR indicate clock, output enable, or set/reset, respectively.

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement maps the signal named “fastclk” to a global net.
INST clkgen/fastclk BUFG;

CLKDV_DIVIDE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Any CLKDLL or CLKDLLHF instance

12-24 Xilinx Development System

Attributes, Constraints, and Carry Logic

Description
Specifies the extent to which the CLKDLL or CLKDLLHF clock divider (CLKDV
output) is to be frequency divided.

Syntax
CLKDV_DIVIDE={1.5 | 2 | 2.5 | 3 | 4 | 5 | 8 | 16}
The default is 2 if no CLKDV_DIVIDE attribute is specified.

Example
Schematic
Attached to a CLKDLL or CLKDLLHF instance.
UCF/NCF file
This statement specifies a frequency division factor of 8 for the clock divider foo/bar.
INST foo/bar CLKDV_DIVIDE=8;

COLLAPSE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Any internal net

Description
Forces a combinatorial node to be collapsed into all of its fanouts.

Syntax
COLLAPSE

Example
Schematic
Attached to a net.
UCF/NCF file
This statement forces net $1N6745 to collapse into all its fanouts.
NET $1I87/$1N6745 COLLAPSE;

Libraries Guide, Release M1.5 12-25

Libraries Guide, Release M1.5

CONFIG

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
IOB and CLB primitives

Description
Defines the configuration of the internal options of a CLB or IOB.
Note: Do not confuse this attribute with the CONFIG primitive, which is a table
containing PROHIBIT and PART attributes. Refer to the “PROHIBIT” section for
information on disallowing the use of a site and to the “PART” section for information
on defining the part type for the design.

Syntax
CONFIG=tag value [tag value]
where tag and value are derived from the following tables.

Table 12-3 XC3000 CLB Configuration Options

Tag BASE F BASE FG BASE FGM*

X F, QX F, QX M, QX
Y F, QY G, QY M, QY
DX DI, F DI, F, G DI, M
DY DI, F DI, F, G DI, M
CLK K, NOT K, NOT K, NOT
RSTDIR RD RD RD
ENCLK EC EC EC
F A,B,C,D,E,QX, QY A,B,C,D,E,QX, QY A,B,C,D,QX, QY
G None A,B,C,D,E,QX, QY A,B,C,D,QX, QY
*For BASE FGM, M=F if E=0, and M=G if E=1

Table 12-4 XC3000 IOB Configuration Options

Tag BASE IO
IN I, IQ, IKNOT, FF, LATCH, PULLUP
OUT O, OQ, NOT, OKNOT, FAST
TRI T, NOT

12-26 Xilinx Development System

Attributes, Constraints, and Carry Logic

Example
Schematic
Attached to a valid instance.
Following is an example of a valid XC3000 CLB CONFIG attribute value.
X:QX Y:QY DX:F DY:G CLK:K ENCLK:EC
UCF/NCF file
N/A

DECODE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √

Applicable Elements
WAND1

Description
Defines how a wired-AND (WAND) instance is created, either using a BUFT or an
edge decoder. If the DECODE attribute is placed on a single-input WAND1 gate, the
gate is implemented as an input to a wide-edge decoder in XC4000 designs.

Syntax
DECODE
DECODE attributes can only be attached to a WAND1 symbol.

Example
Schematic
Attached to a WAND1 symbol.
UCF/NCF file
This statement implements an instantiation of a wired AND using the edge decoder
$COMP_1
INST address_decode/$COMP_1 DECODE;

DIVIDE1_BY and DIVIDE2_BY

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
OSC5, CK_DIV

Libraries Guide, Release M1.5 12-27

Libraries Guide, Release M1.5

Description
Defines the division factor for the on-chip clock dividers.

Syntax
DIVIDE1_BY={4 | 16 | 64 | 256}
DIVIDE2_BY={2 | 8 | 32 | 128 | 1024 | 4096 | 16384 | 65536}

Examples
Schematic
Attached to a valid instance.
NCF file
This statement defines the division factor of 8 for the clock divider $1I45678.
INST clk_gen/$1I45678 divide2_by=8;
Note: DIVDE1_BY and DIVIDE2_BY are not supported in the UCF file.

DOUBLE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √

Applicable Elements
PULLUPs

Description
Specifies double pull-up resistors on the horizontal longline. On XC3000 parts, there
are internal nets that can be set as 3-state with two programmable pull-up resistors
available per line. If the DOUBLE attribute is placed on a PULLUP symbol, both pull-
ups are used, enabling a fast, high-power line. If the DOUBLE attribute is not placed
on a pull-up, only one pull-up is used, resulting in a slower, lower-power line.
When the DOUBLE attribute is present, the speed of the distributed logic is increased,
as is the power consumption of the part. When only half of the longline is used, there
is only one pull-up at each end of the longline.
While the DOUBLE attribute can be used for the XC4000 and Spartans, it is not recom-
mended. The mapper activates both pull-up resistors if the entire longline (not a half-
longline) is used. When DOUBLE is used, PAR will not add an additional pull-up to
achieve your timing constraints while routing XC4000 or Spartan series designs (refer
to the “PAR—Place and Route” chapter of the Development System Reference Guide for
information on PAR and timing optimization).

Syntax
DOUBLE

12-28 Xilinx Development System

Attributes, Constraints, and Carry Logic

Example
Schematic
Attached to a PULLUP only.
UCF/NCF file
N/A

DRIVE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√∗ √ √
1 1 2
* supported for XC4000XV and XC4000XLA designs only

Applicable Elements
1. IOB output components (OBUF, OFD, etc.)
2. OBUF, OBUFT, IOBUF instances (with implied LVTTL standards)

Description
For the XC4000XV, XC4000XLA, and SpartanXL, programs the output drive current
from High (24 mA) to Low (12 mA).
For Virtex, selects output drive strength (mA) for the components that use the LVTTL
interface standard.

Syntax
XC4000XV, XC4000XLA, and SpartanXL
DRIVE={12 | 24}
Virtex
DRIVE={2 | 4 | 6 | 8 | 12 | 16 | 24}
where 12 mA is the default.

Example
Schematic
Attached to a valid IOB output component.
UCF/NCF file
This statement specifies a High drive.
INST /top/my_design/obuf DRIVE=24 ;

Libraries Guide, Release M1.5 12-29

Libraries Guide, Release M1.5

DROP_SPEC

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
All timing specifications. Should be used only in UCF or PCF files.

Description
Allows you to specify that a timing constraint defined in the input design should be
dropped from the analysis. This constraint can be used when new specifications
defined in a constraints file do not directly override all specifications defined in the
input design, and some of these input design specifications need to be dropped.
While this timing command is not expected to be used much in an input netlist (or
NCF file), it is not illegal. If defined in an input design this attribute must be attached
to a TIMESPEC primitive.

Syntax
TSidentifier=DROP_SPEC
where TSidentifier is the identifier name used for the timing specification that is to be
removed.

Example
Schematic
N/A
UCF/NCF file
This statement cancels the input design specification TS67.
TIMESPEC TSidentifier TS67=DROP_SPEC;

DUTY_CYCLE_CORRECTION

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Any CLKDLL, CLKDLLHF, or BUFGDLL instance

Description
Corrects the duty cycle of the CLK0 output.

12-30 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
DUTY_CYCLE_CORRECTION={TRUE | FALSE}
where TRUE corrects the duty cycle to be a 50_50 duty cycle and FALSE does not
change the duty cycle. The default is FALSE.

Example
Schematic
Attached to a CLKDLL, CLKDLLHF, or BUFGDLL instance.
UCF/NCF file
This statement specifies a 50_50 duty cycle for foo/bar.
INST foo/bar DUTY_CYCLE_CORRECTION=TRUE;

EQUATE_F and EQUATE_G

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
CLB primitive

Description
These attributes set the logic equations describing the F and G function generators of a
CLB, respectively.

Syntax
EQUATE_F=equation
EQUATE_G=equation
where equation is a logical equation of the function generator inputs (A, B, C, D, E, QX,
QY) using the boolean operators listed in the following table.

Table 12-5 Valid XC3000 Boolean Operators

Symbol Boolean Equivalent

~ NOT
* AND
@ XOR
+ OR
() Group expression

Libraries Guide, Release M1.5 12-31

Libraries Guide, Release M1.5

Example
Schematic
Attached to a valid instance.
Here are two examples illustrating the use of the EQUATE_F attribute.
EQUATE_F=F=((~A*B)+D))@Q
F=A@B+(C*~D)
UCF/NCF file
N/A

FAST

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Output primitives, output pads, bidirectional pads
Note: You can also attach the FAST attribute to the net connected to the pad compo-
nent in a UCF file. NGDBuild transfers the attribute from the net to the pad instance
in the NGD file so that it can be processed by the mapper. Use the following syntax.
NET net_name FAST

Description
Increases the speed of an IOB output.
Note: The FAST attribute produces a faster output but may increase noise and power
consumption.

Syntax
FAST

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement increases the output speed of the element y2.
INST $1I87/y2 FAST;
This statement increases the output speed of the pad to which net1 is connected.
NET net1 FAST;

12-32 Xilinx Development System

Attributes, Constraints, and Carry Logic

FILE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Macros that refer to underlying non-schematic designs

Description
FILE is attached to a macro that does not have an underlying schematic. It identifies
the file to be looked at for a logic definition. The type of file to be searched for is
defined by the search order of the program compiling the design.

Syntax
FILE=file_name[.extension]
where file_name is the name of a file that represents the underlying logic for the
element carrying the attribute. Example file types include EDIF, XTF, NMC.
Schematic
Attached to a valid instance.
UCF/NCF file
N/A

HBLKNM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1, 2, 3, 7, 8, 9, 2, 3, 4, 5, 7, 8, 2, 3, 4, 5, 7, 8, 2, 3, 4, 6, 7, 2, 3, 4, 5, 7, 8, 2, 3, 4, 5, 7, 8,
10,12 10, 11, 12, 13, 10, 12, 13, 14, 10, 15 10, 11, 12, 13, 10, 12, 13, 14,
14, 15 15 14, 15 15

Applicable Elements
1. IOB, CLB and CLBMAP (See Note below)
2. Registers
3. I/O elements and pads
4. FMAP
5. HMAP
6. F5MAP
7. BUFT
8. PULLUP
9. ACLK, GCLK

Libraries Guide, Release M1.5 12-33

Libraries Guide, Release M1.5

10. BUFG
11. BUFGS, BUFGP
12. ROM
13. RAM
14. RAMS and RAMD
15. Carry logic primitives
Note: You can also attach the HBLKNM constraint to the net connected to the pad
component in a UCF file. NGDBuild transfers the constraint from the net to the pad
instance in the NGD file so that it can be processed by the mapper. Use the following
syntax.
NET net_name HBLKNM=property_value

Description
Assigns hierarchical block names to logic elements and controls grouping in a flat-
tened hierarchical design. When elements on different levels of a hierarchical design
carry the same block name and the design is flattened, NGDBuild prefixes a hierar-
chical path name to the HBLKNM value.
Like BLKNM, the HBLKNM attribute forces function generators and flip-flops into
the same CLB. Symbols with the same HBLKNM attribute map into the same CLB, if
possible. However, using HBLKNM instead of BLKNM has the advantage of adding
hierarchy path names during translation, and therefore the same HBLKNM attribute
and value can be used on elements within different instances of the same macro.
For XC5200, a given HBLKNM string can only be used to group a logic cell (LC),
which contains one register, one LUT (FMAP), and one F5_MUX element. An error
will occur if two or more registers, two or more FMAPs, or two or more F5_MUX
elements have the same HBLKNM attribute.

Syntax
HBLKNM=block_name
where block_name is a valid LCA block name for that type of symbol.

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement specifies that the element this_hmap will be put into the block named
group1.
INST $I13245/this_hmap HBLKNM=group1;
This statement attaches the HBLKNM constraint to the pad connected to net1.
NET net1 HBLKNM=$COMP_0;
Note: Elements with the same HBLKNM are placed in the same logic block if
possible. Otherwise an error occurs. Conversely, elements with different block names
will not be put into the same block.

12-34 Xilinx Development System

Attributes, Constraints, and Carry Logic

HU_SET

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1, 2, 3, 5, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 4, 6, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 3, 5, 7, 8, 1,2, 7, 11, 12
9, 10, 12 9, 10, 12 12 9, 10, 12 9, 10, 12

Applicable Elements
1. Registers
2. FMAP
3. HMAP
4. F5MAP
5. CY4
6. CY_MUX
7. Macro Instance
8. EQN
9. ROM
10. RAM
11. RAMS, RAMD
12. BUFT

Description
The HU_SET constraint is defined by the design hierarchy. However, it also allows
you to specify a set name. It is possible to have only one H_SET constraint within a
given hierarchical element (macro) but by specifying set names, you can specify
several HU_SET sets.
NGDBuild hierarchically qualifies the name of the HU_SET as it flattens the design
and attaches the hierarchical names as prefixes. The difference between an HU_SET
constraint and an H_SET constraint is that an HU_SET has an explicit user-defined
and hierarchically qualified name for the set, but an H_SET constraint has only an
implicit hierarchically qualified name generated by the design-flattening program. An
HU_SET set “starts” with the symbols that are assigned the HU_SET constraint, but
an H_SET set “starts” with the instantiating macro one level above the symbols with
the RLOC constraints.
For background information about using the various set attributes, refer to the “RLOC
Sets” section.

Syntax
HU_SET=set_name
where set_name is the identifier for the set; it must be unique among all the sets in the
design.

Libraries Guide, Release M1.5 12-35

Libraries Guide, Release M1.5

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement assigns an instance of the register FF_1 to a set named heavy_set.
INST $1I3245/FF_1 HU_SET=heavy_set;

INIT

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1, 2, 3 1, 2, 3 3 1, 2, 3 1, 2, 3 2, 3, 4

Applicable Elements
1. ROM
2. RAM
3. Registers
4. LUTs, SRLs

Description
Initializes ROMs, RAMs, registers, and look-up tables. The least significant bit of the
value corresponds to the value loaded into the lowest address of the memory element.
For register initialization, S indicates Set and R indicates Reset. The INIT attribute can
be used to specify the initial value directly on the symbol with the following limita-
tion. INIT may only be used on a RAM or ROM that is 1 bit wide and not more than 32
bits deep.

Syntax
INIT={value | S | R}
where value is a 4-digit or 8-digit hexadecimal number that defines the initialization
string for the memory element, depending on whether the element is 16-bit or 32-bit.
For example, INIT=ABAC1234.
S indicates Set and R indicates Reset for registers.
Note: For XC4000 and Spartans, INIT cannot specify a register as Set if the reset pin is
being used or as Reset if the set pin is being used.

Example
Schematic
Attached to a net, pin, or instance.
UCF/NCF file
INIT={S | R} is supported in both the NCF and UCF files. It is allowed in the UCF to
control the startup state of registers (primarily for CPLDs).

12-36 Xilinx Development System

Attributes, Constraints, and Carry Logic

INIT=value is supported in the NCF file only. This statement defines the initialization
string for an instantiation of the memory element ROM2 to be the 16-bit hexadecimal
string 5555.
INST $1I3245/ROM2 INIT = 5555;
Note: INIT=value is not supported in the UCF file.

INIT_0x

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Block RAMs

Description
Specifies initialization strings for block RAM components.

Syntax
INIT_0x=value
where
x is any hexadecimal value 0 through F that specifies which 256 bits (see the following
table) of the 4096-bit block RAM to initialize to the specified value.
value is a string of hexadecimal characters up to 64 digits wide. If the INIT_0x
attribute has a value less than the required 64 hex digits, the value will be padded
with zeros from the most significant bit (MSB) side. This fills the 256 bits in the initial-
ization string (4 bits per hexadecimal character * 64 characters).

INIT_0x Addresses

4096 x 1 2048 x 2 1024 x 4 512 x 8 256 x 16

INIT_00 255 — 0 127 — 0 63 — 0 31 — 0 15 — 0
INIT_01 511 — 256 255 — 128 127— 64 63 — 32 31 — 16
INIT_02 767 — 512 383 — 256 191 — 128 95 — 64 47 — 32
INIT_03 1023 — 768 511 — 384 255 — 192 127 — 96 63 — 48
INIT_04 1279 — 1024 639 — 512 319 — 256 159 — 128 79 — 64
INIT_05 1535 — 1280 767 — 640 383 — 320 191 — 160 95 — 80
INIT_06 1791 — 1536 895 — 768 447 — 384 223 — 192 111 — 96
INIT_07 2047 — 1792 1023 — 896 511 — 448 255 — 224 127 — 112
INIT_08 2303 — 2048 1151 — 1024 575 — 512 287 — 256 143 — 128
INIT_09 2559 — 2304 1279 — 1152 639 — 576 319 — 288 159 — 144
INIT_0A 2815 — 2560 1407 — 1280 703 — 640 351 — 320 175 — 160
INIT_0B 3071 — 2816 1535 — 1408 767 — 704 383 — 352 191 — 176

Libraries Guide, Release M1.5 12-37

Libraries Guide, Release M1.5

INIT_0x Addresses

4096 x 1 2048 x 2 1024 x 4 512 x 8 256 x 16

INIT_0C 3327 — 3072 1663 — 1536 831 — 768 415 — 384 207 — 192
INIT_0D 3583 — 3328 1791 — 1664 895 — 832 447 — 416 223 — 208
INIT_0E 3839 — 3584 1919 — 1792 959 — 896 479 — 448 239 — 224
INIT_0F 4095 — 3840 2047 — 1920 1023 — 960 511 — 480 255 — 240

INIT_0x usage rules

A summary of the rules for the INIT_0x attribute follows.
• If no INIT_0x attribute is attached to a block RAM, the contents of the RAM
defaults to zero.
• Each initialization string defines 256 bits of the 4096-bit block RAM. For example,
for a 4096-bit deep x 1-bit wide block RAM, INIT_00 assigns the 256 bits to
addresses 0 through 255 and INIT_01 assigns the 256 bits to addresses 256
through 511. For a 2048-bit deep x 2-bit wide block RAMs, INIT_00 assigns the 256
bits to addresses 0 through 127 (a 2-bit value at each address) and INIT_01 assigns
the 256 bits to addresses 128 through 255.
• If a subset of the INIT_00 through INIT_0F properties are specified for a block
RAM, the remaining properties default to zero.
• In an initialization string, the least significant bit (LSB) is the right-most value.
• The least significant word of the block RAM is composed of the least significant
bits of the block RAM.
INIT_0x on block RAMs of various widths
The initialization string "fills" the block RAM beginning from the LSB of the 256 bits
for the specified INIT_0x addresses. The size of the word filling each address depends
on the width of the block RAM being initialized— 1, 2, 4, 8, or 16 bits.
For example, if INIT_0C=bcde7, the corresponding binary sequence is as follows:

1011 1100 1101 1110 0111 ←LSB

b c d e 7

The appropriate addresses in the RAM are initialized with the binary string content
depending on the width of the RAM as shown in the following table.

Block RAM Address

Contents
(depth x width) (INIT_0C)
4096 x 1 3072 1
3073 1
3074 1
3075 0
. .
3327 0

12-38 Xilinx Development System

Attributes, Constraints, and Carry Logic

Block RAM Address

Contents
(depth x width) (INIT_0C)
2048 x 2 1536 11
1537 01
1538 10
1539 11
. .
1663 00
1024 x 4 768 0111
769 1110
770 1101
771 1100
. .
831 0000
512 x 8 384 11100111
385 11001101
386 00001011
387 00000000
. .
415 00000000
256 x 16 192 1100110111101111
193 0000000000001011
194 0000000000000000
195 0000000000000000
. .
207 0000000000000000

Example
Schematic
Attached to a block RAM instance.
UCF/NCF file
The following statement specifies that the INIT_03 addresses in instance foo/bar be
initialized, starting from the LSB, to the hex value aaaaaaaaaaaaaaaaaaaa (padded
with 44 zeros from the MSB side).
INST foo/bar INIT_03=aaaaaaaaaaaaaaaaaaaa;

INREG

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Flip-flops, latches

Libraries Guide, Release M1.5 12-39

Libraries Guide, Release M1.5

Description
Because XC5200 IOBs do not have flip-flops or latches, you can apply this attribute to
meet fast setup timing requirements. If a flip-flop or latch is driven by an IOB, you can
specify INREG to enable PAR (Place and Route) to place the flip-flop/latch close to
the IOB so that the two elements can be connected using fast routes. See also the
“OUTREG” section.

Syntax
INREG

Example
Schematic
Attached to a latch or flip-flop instance.
UCF/NCF file
This statement directs PAR to place the flip-flop $I1 near the IOB driving it.
INST $I1 INREG;

IOB

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Non-INFF/OUTFF flip-flop and latch primitives, registers

Description
Indicates which flip-flops and latches can be moved into the IOB. The mapper
supports a command line option (-pr i | o | b) that allows flip-flop/latch primitives to
be pushed into the input IOB (i), output IOB (o), or input/output IOB (b) on a global
scale. The IOB constraint, when associated with a flip-flop or latch, tells the mapper to
pack that instance into an IOB type component if possible. The IOB constraint has
precedence over the mapper "-pr" command line option.

Syntax
IOB={TRUE | FALSE}
where TRUE allows the flip-flop/latch to be pulled into an IOB and FALSE indicates
not to pull it into an IOB.

Example
Schematic
Attached to a flip-flop or latch instance or to a register.

12-40 Xilinx Development System

Attributes, Constraints, and Carry Logic

UCF/NCF file
This statement prevents the mapper from placing the foo/bar instance into an IOB
component.
INST foo/bar IOB=TRUEE;

KEEP

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Nets

Description
When a design is mapped, some nets may be absorbed into logic blocks. When a net is
absorbed into a block, it can no longer be seen in the physical design database. This
may happen, for example, if the components connected to each side of a net are
mapped into the same logic block. The net may then be absorbed into the block
containing the components. The KEEP constraint prevents this from happening.
In Virtex, KEEP makes the signal visible at the BEL level, not the CLB level as in other
architectures.
Note: The KEEP property is translated into an internal constraint known as
NOMERGE when targeting an FPGA. Messaging from the implementation tools will
therefore refer to the system property NOMERGE—not KEEP.

Syntax
KEEP

Example
Schematic
Attached to a net.
UCF/NCF file
This statement ensures that the net $SIG_0 will remain visible.
NET $1I3245/$SIG_0 KEEP;

Libraries Guide, Release M1.5 12-41

Libraries Guide, Release M1.5

LOC

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √
1, 5, 6, 12 1, 2, 3, 5, 7, 9, 1, 2, 3, 5, 7, 9, 1, 2, 4, 5, 8, 1, 5, 16 1, 2, 3, 5, 7, 9, 1, 2, 3, 5, 7, 9, 1, 2, 5, 6, 10,
10, 11, 12, 13, 10, 11, 12, 13, 12, 14 10, 11, 12, 13, 10, 11, 12, 13, 11, 12, 13, 14,
14, 15 14, 15 14, 15 14, 15 15, 16, 17

Applicable Elements
1. Registers
2. FMAP
3. HMAP
4. F5MAP
5. IO elements
6. CLB and IOB primitives, CLBMAP
7. CY4
8. CY_MUX
9. ROM
10. RAM
11. RAMS, RAMD
12. BUFT
13. WAND
14. Clock buffers
15. Edge decoders
16. Any instance
17. RAMB4s

Description for FPGAs

Defines where a symbol can be placed within an FPGA. It specifies the absolute place-
ment of a design element on the FPGA die. It can be a single location, a range of loca-
tions, or a list of locations. The LOC constraint can be specified from the schematic
and statements in a constraints file can also be used to direct placement.
You can specify multiple locations for the same symbol by using a comma (,) to sepa-
rate each location within the field. It specifies that the symbols be placed in any of the
locations specified. Also, you can specify an area in which to place a symbol or group
of symbols.
The legal names are a function of the target part type. However, to find the correct
syntax for specifying a target location, you can load an empty part into EPIC (the
design editor). Place the cursor on any block and click to display its location in the
EPIC history area. Do not include the pin name such as .I, .O, or .T as part of the loca-
tion.

12-42 Xilinx Development System

Attributes, Constraints, and Carry Logic

You can use the LOC constraint for logic that uses multiple CLBs, IOBs, soft macros,
or other symbols. To do this, use the LOC attribute on a soft macro symbol, which
passes the location information down to the logic on the lower level. The location
restrictions are applied to all blocks on the lower level for which LOCs are legal.
XC5200
The XC5200 CLB is divided into four physical site locations that each contain one flip-
flop, one function generator, and one carry logic element. Therefore, for the XC5200,
each LOC attribute can be used for only one register, one FMAP, one F5_MUX
element, or one CY_MUX element. An error will occur if two or more registers, two or
more FMAPs, two or more F5_MUX elements, or two or more CY_MUX elements
have the same LOC attribute.
Virtex
The physical site specified in the location value is defined by the row and column
numbers for the array, with an optional extension to define the slice for a given row/
column location. The Virtex slice is composed of two LUTs (that can be configured as
RAM or shift registers), two flip-flops (that can also be configured as latches), two
XORCYs, two MULT_ANDs, one F5MUX, one F6MUX, and one MUXCY. Only one
F6MUX can be used between the two adjacent slices in a specific row/column loca-
tion. The two slices at a specific row/column location are adjacent to one another.
The block RAMs (RAMB4s) have a different row/column grid specification than the
CLB and TBUFs. A block RAM located at RAMB4_R3C1 is not located at the same site
as a flip-flop located at CLB_R3C1. Therefore, the location value must start with
"CLB," "TBUF," or "RAMB4." The location cannot be shortened to reference only the
row, column, and extension.The optional extension specifies the left-most or right-
most slice for the row/column. While the XC4000 and Spartans allow extensions such
as .FFX, .FFY, .F and .G to identify specific flip-flops and LUTs within the CLB, these
extensions are not required or allowed for Virtex.
The location value for global buffers and DLL elements is the specific physical site
names for available locations.

Description for CPLDs

For CPLDs, use the LOC=pin_name attribute on a PAD symbol or pad net to assign
the signal to a specific pin. The PAD symbols are IPAD, OPAD, and IOPAD. You can
use the LOC=FBnn attribute on any instance or its output net to assign the logic or
register to a specific function block or macrocell, provided the instance is not
collapsed.
Pin assignments and function block assignments are unconditional; that is, the soft-
ware does not attempt to relocate a pin if it cannot achieve the specified assignment.
You can apply the LOC constraint to as many symbols in your design as you like.
However, each assignment further constrains the software as it automatically allo-
cates logic and I/O resources to internal nodes and I/O pins with no LOC constraints.
The LOC=FBnn_mm attribute on any internal instance or output pad assigns the
corresponding logic to a specific function block or macrocell within the CPLD. If a
LOC is placed on a symbol that does not get mapped to a macrocell or is otherwise
removed through optimization, the LOC will be ignored.
Note: Pin assignment using the LOC attribute is not supported for bus pad symbols
such as OPAD8.

Libraries Guide, Release M1.5 12-43

Libraries Guide, Release M1.5

Location Types
Use the following location types to define the physical location of an element.

P12 IOB location (chip carrier)

A12 IOB location (pin grid)
B, L, T, R Indicates edge locations (bottom, left, top, right) —
applies to edge decoders only
LB, RB, LT, RT, BR, TR, BL, TL Indicates half edges (left bottom, right bottom, and
so forth) — applies to edge decoders only
TL, TR, BL, BR Indicates a corner for global buffer placement
AA CLB location for XC3000
CLB_R4C3 CLB location for XC4000, XC5200, or Spartans
CLB_R4C3 (or .S0 or .S1) CLB location for Virtex
CLB_R6C8.F (or .G) Function generator, RAM, ROM, or RAMS location
for XC4000 or Spartans
CLB_R6C8.LC0 (or .LC1, .LC2, Function generator or register location for XC5200
.LC3)
CLB_R6C8.S0 (or .S1) Function generator or register slice for Virtex
CLB_R6C8.LC0 (or .LC2) F5_MUX location for XC5200
CLB_R6C8.FFX (or.FFY) Flip-flop location for XC4000 or Spartans
TBUF_R6C7.1 (or.2) TBUF location for XC4000 or Spartans
TBUF_R6C7.0 (or .1, .2, or .3) TBUF location for XC5200
TBUF_R6C7 (or .0 or .1) TBUF location for Virtex
RAMB4_R3C1 Block RAM location for Virtex
GCLKBUG0 (or 1, 2, or 3) Global clock buffer location for Virtex
GCLKPAD0 (or 1, 2, or 3) Global clock pad location for Virtex
DLL0 (or 1, 2, or 3) Delay Locked Loop element location for Virtex
The wildcard character (*) can be used to replace a single location with a range as
shown in the following examples.

C* Any CLB in row C of an XC3000 device

*D Any CLB in column D of an XC3000 device
CLB_R*C5 Any CLB in column 5 of an XC4000, XC5200, or
Spartan series device
CLB_R*C5 Any CLB in either slice in column 5 of a Virtex
device
Note: The wildcard character is not supported for Virtex global buffer or DLL loca-
tions.
The following are not supported.
• Dot extensions on ranges. For example, LOC=CLB_R0C0:CLB_R5C5.G. However,
for the XC5200, range locations will be expanded to include extensions,
CLB_R0C0.*:CLB_R5C5.*, for example, when the mapper passes a range
constraint to the PCF file.
• B, L, R, T used to indicate IO edge locations (bottom, left, top, right)

12-44 Xilinx Development System

Attributes, Constraints, and Carry Logic

• LB, RB, LT, RT, BR, TR, BL, TL used to indicate IO half edges (left bottom, right
bottom, etc.)
• Wildcard character for Virtex global buffer, global pad, or DLL locations.

Syntax for FPGAs

Single location
LOC=location
where location is a legal LCA location for the LCA part type. Examples of the syntax
for single LOC constraints are given in the “Single LOC Constraint Examples” table.

Table 12-6 Single LOC Constraint Examples

Attribute Description
LOC=P12 Place I/O at location P12.
LOC=B Place decode logic on the bottom edge.
LOC=TL Place decode logic on the top left edge, or global
buffer in the top left corner.
LOC=AA Place logic in CLB AA.
(XC3000)
LOC=TBUF.AC.2 Place BUFT in TBUF above and one column to the
(XC3000) right of CLB AC.
LOC=CLB_R3C5 Place logic in the CLB in row 3, column 5.
(XC4000 or Spartans)
LOC=CLB_R3C5 Place logic in either slice of the CLB in row3,
(Virtex) column 5.
LOC=CLB_R4C4.LC0 Place logic in the lowest slice of the CLB in row 4,
(XC5200) column 4.
LOC=CLB_R3C5.S0 Place logic in the left slice of the CLB in row 1,
(Virtex) column 1.
LOC=CLB_R4C5.ffx Place CLB flip-flop in the X flip-flop of the CLB in
(XC4000 or Spartans) row 4, column 5.
LOC=CLB_R4C5.F Place CLB function generator in the F generator of
(XC4000 or Spartans) row 4, column 5.
LOC=TBUF_R2C1.1 Place BUFT in row 2, column 1, along the top.
(XC4000 or Spartans)
LOC=TBUF_R4C4.3 Place BUFT in the top buffer in row 4, column 4.
(XC5200)
LOC=TBUF_R*C0 Place BUFT in any row in column 0.
(XC4000, XC5200, Spartans)
LOC=TBUF_R1C2.* Place both TBUFs in row 1, column 2.
(Virtex)
RAMB4_R*C1 Specifies any block RAM in column 1 of the block
(Virtex) RAM array

Libraries Guide, Release M1.5 12-45

Libraries Guide, Release M1.5

Multiple locations
LOC=location1,location2,...,locationn
Repeating the LOC constraint and separating each such constraint by a comma speci-
fies multiple locations for an element. When you specify multiple locations, PAR can
use any of the specified locations. Examples of multiple LOC constraints are provided
in the “Multiple LOC Constraint Examples” table.

Table 12-7 Multiple LOC Constraint Examples

Attribute Description
LOC=T,B Place decoder (XC4000) on the top or bottom edge.
(XC4000 or Spartans)
LOC=clb_r2c4, clb_r7c9 Place the flip-flop in either CLB R2C4 or CLB R7C9.
(XC4000 or Spartans)
LOC=clb_r4c5.s1, Place the flip-flop in the right-most slice of CLB
clb_r4c6.* R4C5 or in either slice of CLB R4C6
(Virtex)

Range of locations
LOC=location:location [SOFT]
You can define a range by specifying the two corners of a bounding box. Specify the
upper left and lower right corners of an area in which logic is to be placed. Use a colon
(:) to separate the two boundaries. The logic represented by the symbol is placed
somewhere inside the bounding box. The default is to interpret the constraint as a
“hard” requirement and to place it within the box. If SOFT is specified, PAR may place
the constraint elsewhere if better results can be obtained at a location outside the
bounding box. Examples of LOC constraints used to specify an area (range) are given
in the “Area LOC Constraint Examples” table.

Table 12-8 Area LOC Constraint Examples

Attribute Description
LOC=AA:FF Place CLB logic anywhere in the top left
(XC3000) corner of the LCA bounded by row F and
column F.
LOC=CLB_R1C1:CLB_R5C5 Place logic in the top left corner of the LCA
(XC4000, Spartans) in a 5 x 5 area bounded by row 5 and
column 5.
LOC=CLB_R1C1:CLB_R5C5 Place CLB logic in the top left corner of the
PROHIBIT=CLB_R5C5 LCA in a 5 x 5 area, but not in the CLB in
(must be specified in one continuous row 5, column 5.
line)
(XC4000, Spartans)

12-46 Xilinx Development System

Attributes, Constraints, and Carry Logic

Table 12-8 Area LOC Constraint Examples

Attribute Description
LOC=CLB_R1C1.LC3:CLB_R4C4.LC0 Place logic in any slice in the top left corner
(XC5200) of the LCA bounded by row 4, column 4.
LOC=CLB_R1C1:CLB_R4C4 Place logic in either slice in the top left
(Virtex) corner of the LCA bounded by row 4,
column 4.
LOC=TBUF_R1C1:TBUF_R2C8 Place BUFT anywhere in the area bounded
(XC4000, XC5200, Spartans) by row 1, column 1 and row 2, column 8.
Note: For area constraints, LOC ranges can be supplemented by the user with the
keyword SOFT.

Syntax for CPLDs

LOC=pin_name
or
LOC=FBnn
or
LOC=FBnn_mm
where
pin_name is Pnn for PC packages; nn is a pin number. The pin name is nn (row number
and column number) for PG packages. See the appropriate data book for the pin
package names, for example, p12. Examples are LOC=P24 and LOC=G2. This form is
valid only on pad instances.
nn is a function block number and mm is a macrocell within a function block number.
This form is valid on any instances.

Examples
Refer to the “Placement Constraints” section for multiple examples of legal place-
ment constraints for each type of logic element (flip-flops, ROMs and RAMs, block
RAMS, FMAPs and HMAPs, CLBMAPs, BUFTs, CLBs, IOBs, I/Os, edge decoders,
global buffers) in FPGA designs.
Schematic
Attached to an instance.
UCF/NCF file
This specifies that an instance of the element BUF1 be placed above the CLB in row 6,
column 9. For XC4000 or Spartan series devices, you can place the TBUF above or
below the CLB. For XC5200 devices, you can place the TBUF in one of four locations
(.0-.3).
INST /DESIGN1/GROUPS/BUF1 LOC=TBUF_R6C9.1 ;
This specifies that each instance found under “FLIP_FLOPS” is to be placed in any
CLB in column 8.
INST /FLIP_FLOPS/* LOC=CLB_R*C8;

Libraries Guide, Release M1.5 12-47

Libraries Guide, Release M1.5

This specifies that an instantiation of MUXBUF_D0_OUT be placed in IOB location

P110.
INST MUXBUF_D0_OUT LOC=P110 ;
This specifies that the net DATA<1> be connected to the pad from IOB location P111.
NET DATA<1> LOC=P111 ;

MAP

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √
4 1, 2 1, 2 1, 3 1, 2 1, 2 1

Applicable Elements
1. FMAP
2. HMAP
3. F5MAP
4. CLBMAP

Description
Placed on an FMAP, F5MAP, HMAP, or CLBMAP to specify whether pin swapping
and the merging of other functions with the logic in the map are allowed. If merging
with other functions is allowed, other logic can also be placed within the CLB, if space
allows.

Syntax
MAP=[PUC | PUO | PLC | PLO]
where
PUC means that the CLB pins are unlocked, ad the CLB is closed.
PUO means that the CLB pins are unlocked, and the CLB is open.
PLC means that the CLB pins are locked, and the CLB is closed.
PLO means that the CLB pins are locked, and the CLB is open.
“Unlocked” in these definitions means that the software can swap signals among the
pins on the CLB; “locked” means that it cannot. “Open” means that the software can
add or remove logic from the CLB; conversely, “closed” indicates that the software
cannot add or remove logic from the function specified by the MAP symbol.
The default is PUO.
Note: Currently, only PUC and PUO are observed. PLC and PLO are translated into
PUC and PUO, respectively.

12-48 Xilinx Development System

Attributes, Constraints, and Carry Logic

Example
Schematic
Attached to a map symbol instance.
UCF/NCF file
This statement allows pin swapping and ensures that no logic other than that defined
by the original map will be mapped into the function generators.
INST $1I3245/map_of_the_world map=puc;

MAXDELAY

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets

Description
The MAXDELAY attribute defines the maximum allowable delay on a net.

Syntax
MAXDELAY=allowable_delay[units]
where units may be ps, ns, us, ms, GHz, MHz, or kHz. The default is ns.

Example
Schematic
Attached to a net.
UCF/NCF file
This statement assigns a maximum delay of 1 us to the net $SIG_4.
NET $1I3245/$SIG_4 MAXDELAY=1us;

MAXSKEW

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets

Description
Defines the allowable skew on a net.

Libraries Guide, Release M1.5 12-49

Libraries Guide, Release M1.5

Syntax
MAXSKEW=allowable_skew [units]
where units may be ps, ns, us, ms, GHz, MHz, or kHz. The default is ns.

Example
Schematic
Attached to a net.
UCF/NCF file
This statement specifies a maximum skew of 3 ns on net $SIG_6.
NET $1I3245/$SIG_6 MAXSKEW=3;

MEDDELAY

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √

Applicable Elements
Input register
Note: You can also attach the MEDDELAY constraint to a net that is connected to a
pad component in a UCF file. NGDBuild transfers the constraint from the net to the
pad instance in the NGD file so that it can be processed by the mapper. Use the
following syntax.
NET net_name MEDDELAY

Description
Specifies a medium sized delay for the IOB register.

Syntax
MEDDELAY

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement specifies that the register in the IOB $COMP_6 will have a medium
sized delay.
INST $1I87/$COMP_6 MEDDELAY;
This statement assigns a medium sized delay to the pad to which net1 is connected.
NET Net1 MEDDELAY ;

12-50 Xilinx Development System

Attributes, Constraints, and Carry Logic

NODELAY

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √

Applicable Elements
Input register
Note: You can also attach the NODELAY constraint to a net connected to a pad
component in a UCF file. NGDBuild transfers the constraint from the net to the pad
instance in the NGD file so that it can be processed by the mapper. Use the following
syntax.
NET net_name NODELAY

Description
The default configuration of IOB flip-flops in XC4000 and Spartan series designs
includes an input delay that results in no external hold time on the input data path.
However, this delay can be removed by placing the NODELAY attribute on input flip-
flops or latches, resulting in a smaller setup time but a positive hold time.
The NODELAY attribute can be attached to the I/O symbols and the special function
access symbols TDI, TMS, and TCK.

Syntax
NODELAY

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement specifies that IOB register inreg67 not have an input delay.
INST $1I87/inreg67 NODELAY;
This statement specifies that there be no input delay to the pad that is attached to net1.
NET net1 NODELAY ;

NOREDUCE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Any net

Libraries Guide, Release M1.5 12-51

Libraries Guide, Release M1.5

Description
NOREDUCE prevents minimization of redundant logic terms that are typically
included in a design to avoid logic hazards or race conditions. NOREDUCE also iden-
tifies the output node of a combinatorial feedback loop to ensure correct mapping.
When constructing combinatorial feedback latches in a design, always apply NORE-
DUCE to the latch’s output net and include redundant logic terms when necessary to
avoid race conditions.

Syntax
NOREDUCE

Example
Schematic
Attached to a net.
UCF/NCF file
This statement specifies that there be no Boolean logic reduction or logic collapse from
the net named $SIG_12 forward.
NET $SIG_12 NOREDUCE;

OFFSET

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Global, nets, time groups

Description
Specifies the timing relationship between an external clock and its associated data-in
or data-out pin. Used only for pad-related signals and cannot be used to extend the
arrival time specification method to the internal signals in a design.
OFFSET constraints allow you to do the following.
• Calculate whether a setup time is being violated at a flip-flop whose data and
clock inputs are derived from external nets.
• Specify the delay of an external output net derived from the Q output of an
internal flip-flop being clocked from an external device pin.
For CPLD designs, clock inputs referenced by OFFSET constraints must be explicitly
assigned to a global clock pin (using either the BUFG symbol or applying the
BUFG=CLK attribute to an ordinary input). Otherwise, the OFFSET constraint will
not be used during timing-driven optimization of the design.

12-52 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
Global method
The OFFSET constraint can be a "global" constraint that applies to all data pad nets in
the design for the specified clock.
OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} "clk_net" [TIMEGRP
"reggroup"]
Net-Specific method
When the NET "name" specifier is used, the constraint is associated with a specific net.
NET "name" OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER} "clk_net"
[TIMEGRP "reggroup"]
Group method
When the TIMEGRP "group" specifier is used, the constraint is associated with a
group of data pad nets.
TIMEGRP "group" OFFSET={IN | OUT} offset_time [units] {BEFORE | AFTER}
"clk_net" [TIMEGRP "reggroup"]
Alternate method
Because the global and group OFFSET constraints are not associated with a single
data net or component, these two types can also be entered on a TIMESPEC symbol in
the design netlist with TSidentifier.
TSidentifier=[TIMEGRP name] OFFSET = {IN|OUT} offset_time [units]
{BEFORE|AFTER} "clk_net" [TIMEGRP "reggroup"]
where
group is the name of a time group containing IOB components or pad BELs.
offset_time is the external offset.
units is an optional field to indicate the units for the offset time. The default is nano-
seconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or kHz
to indicate the intended units.
clk_net is the fully hierarchical netname of the clock net between the pad and its input
buffer.
reggroup is a previously defined time group of register bels. Only registers in the time
group clocked by the specified IOB component is checked against the specified offset
time. The optional time group qualifier, TIMEGRP "reggroup," can be added to any
OFFSET constraint to indicate that the offset applies only to registers specified in the
qualifying group. When used with the "Group method," the "register time" group lists
the synchronous elements that qualify which register elements clocked by "clk_net"
get analyzed.
Note: CPLD designs do not support the "Group Method" or the TIMEGRP options in
the other methods described above.

Example
Schematic
N/A

Libraries Guide, Release M1.5 12-53

Libraries Guide, Release M1.5

UCF/NCF file
This statement specifies that the data will be present on input43 at least 20 ns before
the triggering edge of the clock signal CLOCK.
NET input43 OFFSET=IN 20 BEFORE CLOCK;
For a detailed description of OFFSET, please see the “OFFSET Timing Specifications”
section of the “Using Timing Constraints” chapter in the Development System Reference
Guide.

OPT_EFFORT

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √

Applicable Elements
Any macro or hierarchy level

Description
Defines an effort level to be used by the optimizer.

Syntax
OPT_EFFORT={NORMAL | HIGH}

Example
Schematic
Attached to a macro.
UCF/NCF file
This statement attaches a High effort of optimization to all of the logic contained
within the module defined by instance $1I678/adder.
INST $1I678/adder OPT_EFFORT=HIGH;

OPTIMIZE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √

Applicable Elements
Any macro or hierarchy level

Description
Defines whether optimization is performed on the flagged hierarchical tree. The
OPTIMIZE attribute has no effect on any symbol that contains no combinational logic,
such as an input/output buffer.

12-54 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
OPTIMIZE={AREA | SPEED | BALANCE | OFF}

Example
Schematic
Attached to a macro.
UCF/NCF file
This statement specifies that no optimization be performed on an instantiation of the
macro CTR_MACRO.
INST /$1I678/CTR_MACRO OPTIMIZE=OFF;

OUTREG

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Flip-flops, latches

Description
Because XC5200 IOBs do not have flip-flops or latches, you can apply this attribute to
meet fast setup requirements. If a flip-flop or latch is driving an IOB, you can specify
OUTREG to enable PAR (Place and Route) to place the flip-flop/latch close to the IOB
so that the two elements can be connected using fast routes. See also the “INREG”
section.

Syntax
OUTREG

Example
Schematic
Attached to a latch or flip-flop instance.
UCF/NCF file
This statement directs PAR to place the flip-flop $I1 near the IOB that it is driving.
INST $I1 OUTREG;

Libraries Guide, Release M1.5 12-55

Libraries Guide, Release M1.5

PART

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
1. Global
2. Attached to CONFIG symbol in schematics

Description
Defines the part type used for the design.

Syntax
PART=part_type
where part_type can be device-speed-package or device-package-speed. For example,
4028EX-PG299-3 or 4028EX-3-PG299
The package string must always begin with an alphabetic character — never with a
number.
The speed string must always begin with an numeric character —never with an alpha-
betic character.
The text XC is an optional prefix to the whole part_type string.
In a constraints file, the PART specification must be preceded by the keyword
CONFIG.

Example
Schematic
Global or attached to the CONFIG symbol.
UCF/NCF file
This statement specifies a 4005E device, a PQ160C package, with a speed of 5.
CONFIG PART=4005E-PQ160C-5;

PERIOD

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Nets that feed forward to drive flip-flop clock pins

12-56 Xilinx Development System

Attributes, Constraints, and Carry Logic

Description
Provides a convenient way of defining a clock period for registers attached to a partic-
ular clock net.
PERIOD controls pad-to-setup and clock-to-setup paths but not clock-to-pad paths.
Refer to the “Using Timing Constraints” chapter in the Development System Reference
Guide for more information on clock period specifications.

Syntax
Simple method
PERIOD=period[units] [{HIGH | LOW} [high_or_low_time[hi_lo_units]]]
where
period is the required clock period.
units is an optional field to indicate the units for a clock period. The default is nano-
seconds (ns), but the timing number can be followed by ps, ns, or us to indicate the
intended units.
HIGH or LOW can be optionally specified to indicate whether the first pulse is to be
High or Low.
high_or_low_time is the optional High or Low time, depending on the preceding
keyword. If an actual time is specified, it must be less than the period. If no High or
Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.
Alternate method
TSidentifier=PERIOD TNM_reference period [units] [{HIGH | LOW} [high_or_low_time
[hi_lo_units]]]
where
identifier is a reference identifier that has a unique name.
TNM_reference is the identifier name that is attached to a clock net (or a net in the clock
path) using the TNM attribute.
period is the required clock period.
units is an optional field to indicate the units for a clock period. The default is nano-
seconds (ns), but the timing number can be followed by ps, ms, us, or % to indicate
the intended units.
HIGH or LOW indicates whether the first pulse is to be High or Low.
high_or_low_time is the optional High or Low time, depending on the preceding
keyword. If an actual time is specified, it must be less than the period. If no High or
Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.

Libraries Guide, Release M1.5 12-57

Libraries Guide, Release M1.5

Example
The following examples are for the “simple method.”
Schematic
Attached to a net.
PERIOD=40 HIGH 25;
UCF/NCF file
This statement assigns a clock period of 40 ns to the net named $SIG_24, with the first
pulse being High and having a duration of 25 nanoseconds.
NET $SIG_24 PERIOD=40 HIGH 25;

PROHIBIT

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Attached to CONFIG symbol

Description
Disallows the use of a site within PAR, EPIC, and the CPLD fitter.

Location Types
Use the following location types to define the physical location of an element.

P12 IOB location (chip carrier)

A12 IOB location (pin grid)
B, L, R, T Indicates edge locations (bottom, left, top, right) —
applies to edge decoders only
LB, RB, LT, RT, BR, TR, BL, TL Indicates half edges (left bottom, right bottom, and
so forth) — applies to edge decoders only
TL, TR, BL, BR Indicates a corner for global buffer placement
AA CLB location for XC3000
CLB_R4C3 CLB location for XC4000 or XC5200
CLB_R4C3 (or .S0 or .S1) CLB location for Virtex
CLB_R6C8.LC0 (or 1, 2, 3) Function generator or register location for XC5200
CLB_R6C8.S0 (or .S1) Function generator or register location for Virtex
CLB_R6C8.LC0 (or 2) F5_MUX location for XC5200
TBUF_R6C7.1 (or.2) TBUF location for XC4000
TBUF_R6C7.0 (or.1,.2, or.3) TBUF location for XC5200
TBUF_R6C7 (or .0 or .1) TBUF location for Virtex
RAMB4_R3C1 Block RAM location for Virtex

12-58 Xilinx Development System

Attributes, Constraints, and Carry Logic

GCLKBUG0 (or 1, 2, or 3) Global clock buffer location for Virtex

GCLKPAD0 (or 1, 2, or 3) Global clock pad location for Virtex
DLL0 (or 1, 2, or 3) Delay Locked Loop element location for Virtex
The wildcard character (*) can be used to replace a single location with a range as
shown in the following examples.
C* Any CLB in row C of an XC3000 device
*D Any CLB in column D of an XC3000 device
CLB_R*C5 Any CLB in column 5 of an XC4000 or XC5200
device
CLB_R*C5 Any CLB in either slice in column 5 of a Virtex
device

Note: The wildcard character is not supported for Virtex global buffer or DLL loca-
tions.
The following are not supported.
• Dot extensions on ranges. For example, LOC=CLB_R0C0:CLB_R5C5.G. However,
for the XC5200, range locations will be expanded to include extensions,
CLB_R0C0.*:CLB_R5C5.*, for example, when the mapper passes a range
constraint to the PCF file.
• B, L, R, T used to indicate IO edge locations (bottom, left, top, right)
• LB, RB, LT, RT, BR, TR, BL, TL used to indicate IO half edges (left bottom, right
bottom, etc.)
• .F or .G extension for function generator, RAM, ROM, or RAMS location for
XC4000
• .FFX or .FFY extension for flip-flop location for XC4000
• Wildcard character for Virtex global buffer, global pad, or DLL locations.

Syntax
Single location
PROHIBIT=location
Multiple single locations
PROHIBIT=location1, location2, ... , locationn ;
Range of locations
PROHIBIT=location:location
In a constraints file, the PROHIBIT specification must be preceded by the keyword
CONFIG.
Note: CPLDs do not support the "Range of locations" form of PROHIBIT.

Example
Schematic
Unattached attribute or attached to a CONFIG symbol.

Libraries Guide, Release M1.5 12-59

Libraries Guide, Release M1.5

UCF/NCF file
This statement prohibits use of the site P45.
CONFIG PROHIBIT=P45;
This statement prohibits use of the CLB located in Row 6, Column 8.
CONFIG PROHIBIT=CLB_R6C8 ;
This statement prohibits use of the site TBUF_R5C2.2.
CONFIG PROHIBIT=TBUF_R5C2.2 ;

PWR_MODE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
1. Nets
2. Any instance

Description
Defines the mode, Low power or High performance (standard power) of the macro-
cell that implements the tagged element.
Note: If the tagged function is collapsed forward into its fanouts, the attribute is not
applied.

Syntax
PWR_MODE={LOW | STD}

Example
Schematic
Attached to a net or an instance.
UCF/NCF file
This statement specifies that the macrocell that implements the net $SIG_0 will be in
Low power mode.
NET $1187/$SIG_0 PWR_MODE=LOW;

12-60 Xilinx Development System

Attributes, Constraints, and Carry Logic

RLOC

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1, 2, 3, 5, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 4, 6, 10 1, 2, 3, 5, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 8, 9, 10,
9, 10, 11 9, 10, 11 9, 10 9, 10 12

Applicable Elements
1. Registers
2. FMAP
3. HMAP
4. F5MAP
5. CY4
6. CY_MUX
7. ROM
8. RAM
9. RAMS, RAMD
10. BUFT. (Can only be used if the associated RPM has an RLOC_ORIGIN that causes
the RLOC values in the RPM to be changed to LOC values.)
11. WAND primitives that do not have a DECODE attribute attached
12. LUTs, F5MUX, F6MUX, MUXCY, XORCY, MULT_AND, SRL16, SRL16E

Description
Relative location (RLOC) constraints group logic elements into discrete sets and allow
you to define the location of any element within the set relative to other elements in
the set, regardless of eventual placement in the overall design. See the “Physical
Constraints” section for detailed information about this type of constraint.
For XC5200, the RLOC attribute must include the extension that defines in which of
the four slices of a CLB the element will be placed (.LC0, .LC1, .LC2, .LC3). This
defines the relationship of the elements in the set and also specifies in which of the
four slices the element will eventually be placed.
For Virtex, the RLOC attribute must include the extension that defines in which of the
two slices of a CLB the element will be placed (.S0, .S1).

Syntax
XC4000 or Spartans
RLOC=RmCn[.extension]
XC5200 or Virtex
RLOC=RmCn.extension

Libraries Guide, Release M1.5 12-61

Libraries Guide, Release M1.5

where
m and n are integers (positive, negative, or zero) representing relative row numbers
and column numbers, respectively.
extension uses the LOC extension syntax as appropriate; it can take all the values that
are available with the current absolute LOC syntax.
For the XC4000 and Spartans, the available extensions are FFX, FFY, F, G, H, 1, and 2.
The 1 and 2 values are available for BUFT primitives, and the rest are available for
primitives associated with CLBs. See the “LOC” section for more details.
For the XC5200, extension is required to define in which of the four slices of a CLB the
element will be placed (.LC0, .LC1, .LC2, .LC3).
For Virtex, extension is required to define the spatial relationships (.S0 is the left-most
slice; .S1 is the right-most slice) of the objects in the RPM.
The RLOC value cannot specify a range or a list of several locations; it must specify a
single location. See the “Guidelines for Specifying Relative Locations” section for
more information.

Example
Schematic
Attached to an instance.
UCF/NCF file
This statement specifies that an instantiation of FF1 be placed in the CLB at row 4,
column 4.
INST /4K/design/FF1 RLOC=R4C4;
This statement specifies that an instantiation of elemA be placed in the X flip-flop in
the CLB at row 0, column 1.
INST /$1I87/elemA RLOC=r0cl.FFX;

RLOC_ORIGIN

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √

Applicable Elements
Instances or macros that are members of sets

Description
An RLOC_ORIGIN constraint fixes the members of a set at exact die locations. This
constraint must specify a single location, not a range or a list of several locations. For
more information about this constraint, refer to the “Fixing Members of a Set at Exact
Die Locations” section.
The RLOC_ORIGIN constraint is required for a set that includes BUFT symbols. The
RLOC_ORIGIN constraint cannot be attached to a BUFT instance.

12-62 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
RLOC_ORIGIN=RmCn
where m and n are positive integers (including zero) representing relative row and
column numbers, respectively.

Example
Schematic
Attached to an instance that is a member of a set.
UCF/NCF file
This statement specifies that an instantiation of FF1, which is a member of a set, be
placed in the CLB at R4C4 relative to FF1. For example, if RLOC=R0C2 for FF1, then
the instantiation of FF1 is placed in the CLB that occupies row 4 (R0 + R4) , column 6
(C2 + C4).
INST /archive/designs/FF1 RLOC_ORIGIN=R4C4;

RLOC_RANGE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √

Applicable Elements
Instances or macros that are members of sets

Description
The RLOC_RANGE constraint is similar to the RLOC_ORIGIN constraint except that
it limits the members of a set to a certain range on the die. The range or list of loca-
tions is meant to apply to all applicable elements with RLOCs, not just to the origin of
the set.

Syntax
RLOC_RANGE=Rm1Cn1:Rm2Cn2
where the relative row numbers (m1 and m2) and column numbers (n1 and n2) can be
positive integers (including zero) or the wildcard (*) character. This syntax allows
three kinds of range specifications, which are defined in the “Fixing Members of a Set
at Exact Die Locations” section.

Example
Schematic
Attached to an instance that is a member of a set.
UCF/NCF file
This statement specifies that an instantiation of the macro MACRO4 be placed within
a region that is enclosed by the rows R4-R10 and the columns C4-C10.
INST /archive/designs/MACRO4 RLOC_RANGE=R4C4:R10C10;

Libraries Guide, Release M1.5 12-63

Libraries Guide, Release M1.5

S(ave) - Net Flag Attribute

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets

Description
Attaching the net flag attribute to nets affects the mapping, placement, and routing of
the design.

Syntax
S
The S (save) net flag attribute prevents the removal of unconnected signals. If you do
not have the S attribute on a net, any signal not connected to logic and/or an I/O
primitive is removed.

Example
Schematic
Attached to a net.
UCF/NCF file
This statement specifies that the net named $SIG_9 will not be removed.
NET $SIG_9 S;

SLOW

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Output primitives, output pads, bidirectional pads
Note: You can also attach the SLOW constraint to the net connected to the pad
component in a UCF file. NGDBuild transfers the constraint from the net to the pad
instance in the NGD file so that it can be processed by the mapper. Use the following
syntax.
NET net_name SLOW

Description
Stipulates that the slew rate limited control should be enabled. This is the default.

12-64 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
SLOW

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement establishes a slow slew rate for an instantiation of the element y2.
INST $1I87/y2 SLOW;
This statement establishes a slow slew rate for the pad to which net1 is connected.
NET net1 SLOW;

STARTUP_WAIT

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√

Applicable Elements
Any CLKDLL, CLKDLLHF, or BUGDGLL instance

Description
Controls whether the DONE signal (device configuration) can go HIGH (indicating
that the device is fully configured).

Syntax
START_WAIT={TRUE | FALSE}
where
TRUE specifies that the DONE signal cannot go High until the instance assigned this
property locks.
FALSE, the default, specifies that the locking of the instance has no impact on the
DONE signal.

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement specifies that the DONE signal cannot go High until the foo/bar
instance locks.
INST foo/bar STARTUP_WAIT=TRUE;

Libraries Guide, Release M1.5 12-65

Libraries Guide, Release M1.5

TEMPERATURE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√∗ √∗ √∗ √∗ √∗ √∗ √∗
*Availability depends on the release of characterization data

Applicable Elements
Global

Description
Allows the specification of the operating junction temperature. This provides a means
of prorating device delay characteristics based on the specified temperature. Prorating
is a scaling operation on existing speed file delays and is applied globally to all delays.
Note: Each architecture has its own specific range of valid operating temperatures. If
the entered temperature does not fall within the supported range, the constraint is
ignored and an architecture-specific default value is used instead. Also note that the
error message for this condition does not appear until PCF processing.

Syntax
TEMPERATURE=value[C |F| K]
where
value is real number specifying the temperature.
C, K, and F are the temperature units. F is degrees Fahrenheit, K is degrees Kelvin,
and C is degrees Celsius, the default.

Example
Schematic
Unattached attribute.
UCF/NCF file
This statement specifies that the analysis for everything relating to speed file delays
assumes a junction temperature of 25 degrees Celsius.
TEMPERATURE=25C;

TIG

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets, pins

12-66 Xilinx Development System

Attributes, Constraints, and Carry Logic

Description
Paths that fan forward from the point of application are treated as if they do not exist
(for the purposes of the timing model) during implementation.
A TIG may be applied relative to a specific timing specification.

Syntax
TIG
or
TIG=TSidentifier1,..., TSidentifiern
where identifier refers to a timing specification that should be ignored.

Example
Schematic
Attached to a net or pin.
UCF/NCF file
This statement specifies that the timing specifications TS_fast and TS_even_faster will
be ignored on all paths fanning forward from the net $Sig_5.
NET $1I567/$Sig_5 TIG=TS_fast, TS_even_faster;
For more on TIG, see the “Ignoring Selected Paths” section of the “Using Timing
Constraints” chapter in the Development System Reference Guide.

Time Group Attributes

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
1. Global in constraints file (preceded by the keyword TIMEGRP)
2. Time group primitive

Description
Time group properties (attributes) are a set of grouping mechanisms that use existing
TNMs (Timing Names) to create new groups or to define new groups based on the
output net that the group sources. The timing group primitive (TIMEGRP) exists for
the purpose of hosting these properties. In a constraints file, the specification of these
properties must be preceded with the keyword TIMEGRP.
Note: When entering time group properties into a TIMEGRP symbol, some property
names may conflict with the predefined property names of the TIMEGRP primitive.
The standard procedure for adding a property to a symbol is to use the following
format.
PROPERTY=property_name VALUE=value

Libraries Guide, Release M1.5 12-67

Libraries Guide, Release M1.5

However, some property names are reserved, and should not be used because they
cause a conflict. Hence, for property_name you must not use any of the system reserved
names LIBVER, INST, COMP, MODEL, or any other names reserved by your sche-
matic capture program. Please consult your schematic capture documentation to
become familiar with reserved property names.
Note: For more on the TIMEGRP symbol, see the “TIMEGRP” section in the Design
Elements chapter.

Syntax
new_group_name=[RISING | FALLING] group_name1 [EXCEPT group_name2...
group_namen]
or
new_group_name=[TRANSHI | TRANSLO] group_name1 [EXCEPT group_name2...
group_namen]
where
group_names can be
• the name assigned to a previously defined group.
• all of the members of a predefined group using the keywords FFS, RAMS, PADS
or LATCHES. FFS refers to all flip-flops. RAMS refers to all RAMs. PADS refers to
all I/O pads. LATCHES refers to all latches.
• a subset of elements in a group predefined by name matching using the following
syntax.
predefined_group name qualifier1... name_qualifiern
RISING or FALLING applies to the rising or falling edge sensitive elements of a group
of flip-flops to be referred to as a subset.
TRANSHI or TRANSLO is the form of the constraint applied to latches.
EXCEPT excludes the object group.

Example 1
Schematic
The following attribute would be attached to a TIMEGRP primitive to combine the
elements in two groups to form a new group.
big_group=little_group other_group
UCF/NCF file
The same constraint could appear in a User Constraints File (UCF) as follows.
TIMEGRP big_group=little_group other_group;

Example 2
Schematic
The following constraints would be attached to a TIMEGRP primitive to define new
groups by exclusion.
input_pads=pads except output_pads

12-68 Xilinx Development System

Attributes, Constraints, and Carry Logic

UCF/NCF file
The same constraint could appear in a UCF as follows.
TIMEGRP input_pads=pads EXCEPT output_pads;
For more on Time Group Attributes, see the “Timing Specifications” section of the
“Using Timing Constraints” chapter in the Development System Reference Guide. See
also the “Syntax Summary” section in the same chapter.

TNM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
Nets, instances, macros
Note: You can attach the TNM constraint to the net connected to the pad component
in a UCF file. NGDBuild transfers the constraint from the net to the pad instance in
the NGD file so that it can be processed by the mapper. Use the following syntax.
NET net_name TNM=property_value

Description
Tags specific flip-flops, RAMs, pads, and latches as members of a group to simplify
the application of timing specifications to the group.
TNMs (Timing Names) applied to pad nets do not propagate forward through the
IBUF/ OBUF. The TNM is applied to the external pad. This case includes the net
attached to the D input of an IFD. See the “TNM_NET” section if you want the TNM
to trace forward from an input pad net.
TNMs applied to the input pin of an IBUF/ OBUF will propagate the TNM to the next
appropriate element.
TNMs applied to the output pin of an IBUF/OBUF will propagate the TNM to the
next appropriate element.
TNMs applied to an IBUF or OBUF element stay attached to that element.
TNMs applied to a clock-pad-net will not propagate forward through the clock buffer.
When TNM is applied to a macro, all the elements in the macro will have that timing
name.
See the “Entering Timing Specifications” section of the “Using Timing Constraints”
chapter in the Development System Reference Guide for detailed information about this
attribute.

Syntax
TNM=[predefined_group:] identifier;

Libraries Guide, Release M1.5 12-69

Libraries Guide, Release M1.5

where
predefined_group can be
• the name assigned to a previously defined group.
• all of the members of a predefined group using the keywords FFS, RAMS, PADS
or LATCHES. FFS refers to all flip-flops. RAMS refers to all RAMs. PADS refers to
all I/O pads. LATCHES refers to all latches.
• a subset of elements in a group predefined by name matching using the following
syntax.
predefined_group name_qualifier1... name_qualifiern
identifier can be any combination of letters, numbers, or underscores. Do not use
reserved words, such as FFS, LATCHES, RAMS, or PADS for TNM identifiers.

Example
Schematic
Attached to a net or a macro.
UCF/NCF file
This statement identifies the element register_ce as a member of the timing group
the_register.
NET $1I87/register_ce TNM=the_register;

TNM_NET

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets

Description
Tags specific flip-flops, RAMs, pads, and latches as members of a group to simplify
the application of timing specifications to the group. NGDBuild never transfers a
TNM_NET constraint from the attached net to a pad, as it does with the TNM
constraint.
TNM_NETs applied to pad nets propagate forward through the IBUF/ OBUF.
TNM_NETs applied to a clock-pad-net propagate forward through the clock buffer.
When TNM_NET is applied to a macro, all the elements in the macro will have that
timing name.
See the “Timing Specifications” section of the “Using Timing Constraints” chapter in
the Development System Reference Guide for detailed information about this attribute.

Syntax
TNM_NET=[predefined_group:]identifier

12-70 Xilinx Development System

Attributes, Constraints, and Carry Logic

Example
Schematic
Attached to a net.
UCF/NCF file
This statement identifies all flip-flops fanning out from the PADCLK net as a member
of the timing group FFGRP.
NET PADCLK TNM_NET=FFS(*):FFGRP;

TPSYNC

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets, instances, pins

Description
Flags a particular point or a set of points with an identifier for reference in subsequent
timing specifications. You can use the same identifier on several points, in which case
timing analysis treats the points as a group. See the “Time Group Attributes” section.

Defining synchronous points

When the timing of a design must be designed from or to a point that is not a flip-flop,
latch, RAM, or I/O pad, the following rules apply if a TPSYNC timing point is
attached to a net, macro pin, output or input pin of a primitive, or an instance.
• A net — the source of the net is identified as a potential source or destination for
timing specifications.
• A macro pin — all of the sources inside the macro that drive the pin to which the
attribute is attached are identified as potential sources or destinations for timing
specifications. If the macro pin is an input pin (that is, if there are no sources for

Libraries Guide, Release M1.5 12-71

Libraries Guide, Release M1.5

the pin in the macro), then all of the load pins in the macro are flagged as synchro-
nous points.
• The output pin of a primitive — the primitive’s output is flagged as a potential
source or destination for timing specifications.
• The input pin of a primitive — the primitive’s input is flagged as a potential
source or destination for timing specifications.
• An instance — the output of that element is identified as a potential source or
destination for timing specifications.

Syntax
TPSYNC=identifier
where identifier is a name that is used in timing specifications in the same way that
groups are used.
All flagged points are used as a source or destination or both for the specification
where the TPSYNC identifier is used.
Note: The name for the identifier must be different from any identifier used for a
TNM attribute.

Example
Schematic
Attached to a net, instance, or pin.
UCF/NCF file
This statement identifies latch as a potential source or destination for timing specifica-
tions for the net logic_latch.
NET $1I87/logic_latch TPSYNC=latch;

TPTHRU

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √

Applicable Elements
Nets, pins, instances

Defining through points

The TPTHRU attribute is used when it is necessary to define intermediate points on a
path to which a specification applies. See the “TSidentifier” section.

12-72 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
TPTHRU=identifier
where identifier is a name used in timing specifications for further qualifying timing
paths within a design.
Note: The name for the identifier must be different from any identifier used for a
TNM attribute.

Example
Schematic
Attached to a net, instance, or pin.
UCF/NCF file
This statement identifies the net on_the_way as an intermediate point on a path to
which the timing specification named “here” applies.
NET $1I87/on_the_way TPTHRU=here;

TSidentifier

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √ √ √

Applicable Elements
1. Global in constraints file
2. TIMESPEC primitive

Description
TSidentifier properties beginning with the letters “TS” are placed on the TIMESPEC
symbol. In a constraints file, the specification of these properties can be preceded with
the optional keyword TIMESPEC. The value of the TSidentifier attribute corresponds
to a specific timing specification that can then be applied to paths in the design.

Syntax
Note: All the following syntax definitions use a space as a separator. The use of a
colon (:) as a separator is optional.

Defining a maximum allowable delay

TSidentifier=[MAXDELAY] FROM source_group TO dest_group allowable_delay [units]
or
TSidentifier=FROM source_group TO dest_group allowable_delay [units]

Defining intermediate points

Note: This form is not supported for CPLDs.
TSidentifier=FROM source_group THRU thru_point [THRU thru_point1... thru_pointn] TO
dest_group allowable_delay [units]

Libraries Guide, Release M1.5 12-73

Libraries Guide, Release M1.5

where
identifier is an ASCII string made up of the characters A-Z, a-z, 0-9, and _.
source_group and dest_group are user-defined or predefined groups.
thru_point is an intermediate point used to qualify the path, defined using a TPTHRU
attribute.
allowable_delay is the timing requirement.
units is an optional field to indicate the units for the allowable delay. The default units
are nanoseconds (ns), but the timing number can be followed by ps, ns, us, ms, GHz,
MHz, or kHz to indicate the intended units.

Defining a linked specification

This allows you to link the timing number used in one specification to another specifi-
cation.
TSidentifier=FROM source_group TO dest_group another_TSid[/ | *] number
where
identifier is an ASCII string made up of the characters A-Z, a-z, 0-9, and _.
source_group and dest_group are user-defined or predefined groups.
another_Tsid is the name of another timespec.
number is a floating point number.

Defining a clock period

This allows more complex derivative relationships to be defined as well as a simple
clock period.
TSidentifier=PERIOD TNM_reference period[units] [{HIGH | LOW} [high_or_low_time
[hi_lo_units]]]
where
identifier is a reference identifier with a unique name.
TNM_reference is the identifier name attached to a clock net (or a net in the clock path)
using a TNM attribute.
period is the required clock period.
units is an optional field to indicate the units for the allowable delay. The default units
are nanoseconds (ns), but the timing number can be followed by ps, ns, us, ms, GHz,
MHz, or kHz to indicate the intended units.
HIGH or LOW can be optionally specified to indicate whether the first pulse is to be
High or Low.
high_or_low_time is the optional High or Low time, depending on the preceding
keyword. If an actual time is specified, it must be less than the period. If no High or
Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.

12-74 Xilinx Development System

Attributes, Constraints, and Carry Logic

Specifying derived clocks

TSidentifier=PERIOD TNM_reference another_PERIOD_identifier [/ | *] number
[{HIGH | LOW} [high_or_low_time [hi_lo_units]]]
where
TNM_reference is the identifier name attached to a clock net (or a net in the clock path)
using a TNM attribute.
another_PERIOD_identifier is the name of the identifier used on another period specifi-
cation.
number is a floating point number.
HIGH or LOW can be optionally specified to indicate whether the first pulse is to be
High or Low.
high_or_low_time is the optional High or Low time, depending on the preceding
keyword. If an actual time is specified, it must be less than the period. If no High or
Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.

Ignoring paths
Note: This form is not supported for CPLDs.
There are situations in which a path that exercises a certain net should be ignored
because all paths through the net, instance, or instance pin are not important from a
timing specification point of view.
TSidentifier=FROM source_group TO dest_group TIG
or
TSidentifier=FROM source_group THRU thru_point [THRU thru_point1... thru_pointn]TO
dest_group TIG
where
identifier is an ASCII string made up of the characters A-Z, a-z 0-9, and _.
source_group and dest_group are user-defined or predefined groups.
thru_point is an intermediate point used to qualify the path, defined using a TPTHRU
attribute.

Example
Schematic
Attached to a TIMESPEC primitive.
UCF/NCF file
This statement says that the timing specification TS_35 calls for a maximum allowable
delay of 50 ns between the groups “here” and “there”.
TIMESPEC TS_35=FROM here TO there 50;

Libraries Guide, Release M1.5 12-75

Libraries Guide, Release M1.5

This statement says that the timing specification TS_70 calls for a 25 ns clock period
for clock_a, with the first pulse being High for a duration of 15 ns.
TIMESPEC TS_70=PERIOD “clock_a” 25 high 15;
For more information, see the “Timing Constraints” section.
Note: In either example above, a colon can be used instead of a space as the separator.
(Additional spaces entered before or after the colon are ignored.) The statements then
become as follows.
TIMESPEC TS_35=FROM:here:TO:there:50;
TIMESPEC TS_70=PERIOD:”clock_a”:25:high:15;

U_SET

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1, 2, 3, 5, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 4, 6, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 3, 5, 7, 8, 1, 2, 7, 8, 10,
9, 10, 11, 12 9, 10, 11, 12 12 9, 10, 11, 12 9, 10, 11, 12 11, 12, 13

Applicable Elements
1. Registers
2. FMAP
3. HMAP
4. F5MAP
5. CY4
6. CY_MUX
7. Macro instance
8. EQN
9. ROM
10. RAM
11. RAMS, RAMD
12. BUFT (Can only be used for Virtex if the associated RPM has an RLOC_ORIGIN
that causes the RLOC values in the RPM to be changed to LOC values.)
13. LUTs, F5MUX, F6MUX, MUXCY, XORCY, MULT_AND, SRL16, SRL16E

Description
The U_SET constraint groups design elements with attached RLOC constraints that
are distributed throughout the design hierarchy into a single set. The elements that
are members of a U_SET can cross the design hierarchy; that is, you can arbitrarily
select objects without regard to the design hierarchy and tag them as members of a
U_SET. For detailed information about this attribute, refer to the “RLOC Sets”
section.

12-76 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
U_SET=name
where name is the identifier of the set. This name is absolute. It is not prefixed by a
hierarchical qualifier.

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement specifies that the design element ELEM_1 be in a set called JET_SET.
INST $1I3245/ELEM_1 U_SET=JET_SET;

USE_RLOC

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √

Applicable Elements
Instances or macros that are members of sets

Description
Turns on or off the RLOC constraint for a specific element or section of a set. For
detailed information about this constraint, refer to the “Toggling the Status of RLOC
Constraints” section.

Syntax
USE_RLOC={TRUE | FALSE}
where TRUE turns on the RLOC attribute for a specific element, and FALSE turns it
off. Default is TRUE.

Example
Schematic
Attached to a member of a set.
UCF/NCF file
INST $1I87/big_macro USE_RLOC=FALSE;

Libraries Guide, Release M1.5 12-77

Libraries Guide, Release M1.5

VOLTAGE

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√∗ √∗ √∗ √∗ √∗ √∗ √∗
*Availability depends on the release of characterization data

Applicable Elements
Global

Description
Allows the specification of the operating voltage. This provides a means of prorating
delay characteristics based on the specified voltage. Prorating is a scaling operation
on existing speed file delays and is applied globally to all delays.
Note: Each architecture has its own specific range of supported voltages. If the
entered voltage does not fall within the supported range, the constraint is ignored and
an architecture-specific default value is used instead. Also note that the error message
for this condition appears during PCF processing.

Syntax
VOLTAGE=value[V]
where
value is a real number specifying the voltage.
V indicates volts, the default voltage unit.

Example
Schematic
Unattached attribute.
UCF/NCF file
This statement specifies that the analysis for everything relating to speed file delays
assumes an operating power of 5 volts.
VOLTAGE=5;

WIREAND

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√∗
* not supported for XC9500XL designs

Applicable Elements
Any net

12-78 Xilinx Development System

Attributes, Constraints, and Carry Logic

Description
Forces a tagged node to be implemented as a wired AND function in the interconnect
(UIM and Fastconnect).

Syntax
WIREAND

Example
Schematic
Attached to a net.
UCF/NCF file
This statement specifies that the net named SIG_11 be implemented as a wired AND
when optimized.
NET $I16789/SIG_11 WIREAND;

XBLKNM

XC3000 XC4000E XC4000X XC5200 XC9000 Spartan SpartanXL Virtex

√ √ √ √ √ √
1,2, 3, 7, 8 2, 3, 4, 5, 7, 8, 2, 3, 4, 5, 7, 8, 2, 3, 4, 6, 7, 2, 3, 4, 5, 7, 8, 2, 3, 4, 5, 7, 8,
9, 10, 11 9, 10, 11 11 9, 10, 11 9, 10, 11

Applicable Elements
1. IOB, CLB, and CLBMAP
2. Flip-flop and latch primitives
3. Any I/O element or pad
4. FMAP
5. HMAP
6. F5MAP
7. BUFT
8. ROM primitive
9. RAM primitives
10. RAMS and RAMD primitives
11. Carry logic primitives

Description
Assigns LCA block names to qualifying primitives and logic elements. If the same
XBLKNM attribute is assigned to more than one instance, the software attempts to
map them into the same LCA block. Conversely, two symbols with different
XBLKNM names are not mapped into the same block. Placing similar XBLKNMs on
instances that do not fit within one LCA block creates an error.

Libraries Guide, Release M1.5 12-79

Libraries Guide, Release M1.5

Specifying identical XBLKNM attributes on FMAP and/or HMAP symbols tells the
software to group the associated function generators into a single CLB. Using
XBLKNM, you can partition a complete CLB without constraining the CLB to a phys-
ical location on the device.
XBLKNM attributes, like LOC constraints, are specified from the schematic. Hierar-
chical paths are not prefixed to XBLKNM attributes, so XBLKNM attributes for
different CLBs must be unique throughout the entire design.
The BLKNM attribute allows any elements except those with a different BLKNM to be
mapped into the same physical component. XBLKNM, however, allows only elements
with the same XBLKNM to be mapped into the same physical component. Elements
without an XBLKNM cannot be not mapped into the same physical component as
those with an XBLKNM.
For XC5200, a given XBLKNM string can only be used to group a logic cell (LC),
which contains one register, one LUT (FMAP), and one F5_MUX element. An error
will occur if two or more registers, two or more FMAPs, or two or more F5_MUX
elements have the same XBLKNM attribute.

Syntax
XBLKNM=block_name
where block_name is a valid LCA block name for that type of symbol. For a list of
prohibited block names, see the “Naming Conventions” section of each user interface
manual.

Example
Schematic
Attached to a valid instance.
UCF/NCF file
This statement assigns an instantiation of an element named flip_flop2 to a block
named U1358.
INST $1I87/flip_flop2 XBLKNM=U1358;

12-80 Xilinx Development System

Attributes, Constraints, and Carry Logic

Placement Constraints
This section describes the legal placement constraints for each type of logic element,
such as flip-flops, ROMs and RAMs, FMAPs, F5MAPs, and HMAPs, CLBMAPs,
BUFTs, CLBs, IOBs, I/Os, edge decoders, and global buffers in FPGA designs. Indi-
vidual logic gates, such as AND or OR gates, are mapped into CLB function genera-
tors before the constraints are read and therefore cannot be constrained. However, if
gates are represented by an FMAP, F5MAP, HMAP, or CLBMAP symbol, you can put
a placement constraint on that symbol.
You can use the following constraints (described earlier in the “Attributes/Logical
Constraints” section) to control mapping and placement of symbols in a netlist.
• BLKNM
• HBLKNM
• XBLKNM
• LOC
• PROHIBIT
• RLOC
• RLOC_ORIGIN
• RLOC_RANGE
Most constraints can be specified either in the schematic or in the UCF file.
In a constraints file, each placement constraint acts upon one or more symbols. Every
symbol in a design carries a unique name, which is defined in the input file. Use this
name in a constraint statement to identify the symbol.
Note: The UCF and NCF files are case sensitive. Identifier names (names of objects in
the design, such as net names) must exactly match the case of the name as it exists in
the source design netlist. However, any Xilinx constraint keyword (for example, LOC,
PROHIBIT, RLOC, BLKNM) can be entered in either all upper-case or all lower-case
letters; mixed case is not allowed.
The following sections describe various types of placement constraints, explains the
method of determining the symbol name for each, and provides examples.

BUFT Constraint Examples

You can constrain internal 3-state buffers (BUFTs) to an individual BUFT location, a
list of BUFT locations, or a rectangular block of BUFT locations. BUFT constraints all
refer to locations with a prefix of TBUF, which is the name of the physical element on
the device.
BUFT constraints can be assigned from the schematic or through the UCF file. From
the schematic, LOC constraints are attached to the target BUFT. The constraints are
then passed into the EDIF netlist file and after mapping are read by PAR. Alterna-
tively, in a constraints file a BUFT is identified by a unique instance name.
In the XC3000, BUFT locations are not straightforward. View the device in EPIC to
determine the exact BUFT names.

Libraries Guide, Release M1.5 12-81

Libraries Guide, Release M1.5

In XC4000 or Spartans, BUFT locations are identified by the adjacent CLB. Thus,
TBUF_R1C1.1 is just above CLB_R1C1, and TBUF_R1C1.2 is just below it. For XC4000
or Spartans, use the following syntax to denote fixed locations.
TBUF_RrowCcol [.1 | .2]
where row is the row location and col is the column location; they can be any number
between 0 and 99, inclusive. They must be less than or equal to the number of CLB
rows or columns in the target device. The suffixes have the following meanings.
• 1 indicates that the instance should be placed above the CLB.
• 2 indicates that the instance should be placed below the CLB.
In the XC5200, BUFT locations are identified by the adjacent slice. From bottom to top,
they are number 0, 1, 2, and 3. Thus, TBUF_R1C1.0 is located toward the bottom of the
row. TBUF_R1C1.3 is located toward the top of the row. For an XC5200, Use the
following syntax to denote fixed locations.
TBUF_RrowCcol [.0 | .1 | .2 | .3]
where row is the row location and col is the column location; they can be any number
between 0 and 99, inclusive. They must be less than or equal to the number of CLB
rows or columns in the target device. The suffixes have the following meanings.
• 0 indicates that the instance should be placed in the bottom buffer.
• 1 indicates that the instance should be placed in the buffer that is second from
bottom.
• 2 indicates that the instance should be placed in the buffer that is second from top.
• 3 indicates that the instance should be placed in the top buffer.
For Virtex, use the following syntax to denote fixed locations.
TBUF_RrowCcol [.0 | .1]
where row is the row location and col is the column location; they can be any number
between 0 and 99, inclusive. They must be less than or equal to the number of CLB
rows or columns in the target device. The suffixes have the following meanings.
• 0 indicates one TBUF at the specific row/column.
• 1 indicates the second TBUF at the specific row/column.
For the XC4000, Spartans, XC5200, or Virtex, use the following syntax to denote a
range of locations from the lowest to the highest.
TBUF_RrowCcol TBUF_RrowCcol
The following examples illustrate the format of BUFT LOC constraints. Specify LOC=
and the BUFT location.
The following statements place the BUFT in the designated location.

LOC=TBUF.AA.1 (XC3000)
LOC=TBUF_R1C1.1 (or .2) (XC4000, Spartans)
LOC=TBUF_R1C1.3 (or .0, .1, .2) (XC5200)
LOC=TBUF_R1C1.0 (or .1) (Virtex)

12-82 Xilinx Development System

Attributes, Constraints, and Carry Logic

The next statements place BUFTs at any location in the first column of BUFTs. The
asterisk (*) is a wildcard character.

LOC=TBUF.*A (XC3000)
LOC=TBUF_R*C0 (XC4000, XC5200, Spartans,
Virtex)
The following statements place BUFTs within the rectangular block defined by the
first specified BUFT in the upper left corner and the second specified BUFT in the
lower right corner.

LOC=TBUF.AA:TBUF.BH (XC3000)
LOC=TBUF_R1C1:TBUF_R2C8 (XC4000, XC5200, Spartans,
Virtex)
In the following examples, the instance names of two BUFTs are /top-72/rd0 and/
top-79/ed7.
Example 1
This example specifies a BUFT adjacent to a specific CLB.

Schematic LOC=TBUF_r1c5
UCF INST /top-72/rd0 LOC=TBUF_r1c5 ;
Place the BUFT adjacent to CLB R1C5. In XC4000 or Spartans, PAR uses either the
longline above the row of CLBs or the longline below. In an XC5200, PAR places the
BUFT in one of the four slices of the CLB at row 1, column 5. In Virtex, PAR places the
BUFT in one of two slices of the CLB at row 1, column 5.
Example 2
The following example places a BUFT in a specific location.

Schematic LOC=TBUF_r1c5.1
UCF INST /top-72/rd0 LOC=TBUF_r1c5.1 ;
Place the BUFT adjacent to CLB R1C5. In an XC4000 or Spartan series device, .1 tag
specifies the longline above the row of CLBs; the .2 tag specifies the longline below it.
In an XC5200 device, the .1 tag specifies the longline associated with the slice above
the bottom-most slice in the CLB at the location; the .1, .2, .3 tags specify slices above
the .0 slice for the specified row and column. In Virtex, the .1 tag specifies the second
TBUF in CLB R1C5.
BUFTs that drive the same signal must carry consistent constraints. If you specify .1 or
.2 for one of the BUFTs that drives a given signal, you must also specify .1 or .2 on the
other BUFTs on that signal; otherwise, do not specify any constraints at all.
Example 3
The next example specifies a column of BUFTs.

Schematic LOC=TBUF_r*c3
UCF INST /top-72/rd0 /top-79/ed7 LOC=TBUF_r*c3 ;
Place BUFTs in column 3 on any row. This constraint might be used to align BUFTs
with a common enable signal. You can use the wildcard (*) character in place of either
the row or column number to specify an entire row or column of BUFTs.

Libraries Guide, Release M1.5 12-83

Libraries Guide, Release M1.5

Example 4
This example specifies a row of BUFTs .

Schematic LOC=TBUF_r7c*
UCF INST /top-79/ed7 LOC=TBUF_r7c* ;

Place the BUFT on one of the longlines in row 7 for any column. You can use the wild-
card (*) character in place of either the row or column number to specify an entire row
or column of BUFTs.

CLB Constraint Examples

You can assign soft macros and flip-flops to a single CLB location, a list of CLB loca-
tions, or a rectangular block of CLB locations. You can also specify the exact function
generator or flip-flop within a CLB. CLB locations are identified as CLB_RrowCcol for
XC4000, XC5200, Spartans, and Virtex or aa for XC3000, where aa is a two-letter desig-
nator. The upper left CLB is CLB_R1C1 (for XC4000, XC5200, Spartans, and Virtex) or
AA (for XC3000).
CLB locations can be a fixed location or a range of locations. Use the following syntax
to denote fixed locations.
For XC4000 or Spartans:
CLB_R rowCcol {.F | .G | .FFX | .FFY }
For XC5200:
CLB_R rowCcol {.LC0 | .LC1 | .LC2 | .LC3 }
For Virtex:
CLB_R rowCcol {.S0 | .S1}
where
row is the row location and col is the column location; they can be any number
between 0 and 99, inclusive, or *. They must be less than or equal to the number of
CLB rows or columns in the target device. The suffixes have the following meanings.
.F means the CLB is mapped into the F function generator.
.G means the CLB is mapped into the G function generator.
.FFX indicates the X flip-flop in the CLB.
.FFY indicates the Y flip-flop in the CLB.
.LC0 means the bottom-most slice in the XC5200 CLB.
.LC1 means the slice above the .LC0 slice in the XC5200 CLB.
.LC2 means the slice above the .LC1 slice in the XC5200 CLB.
.LC3 means top-most slice in the XC5200 CLB.
.S0 means the left-most slice in the Virtex CLB.
.S1 means the right-most slice in the Virtex CLB.
Use the following syntax to denote a range of locations from the highest to the lowest.
CLB_Rrow1Ccol:CLB_Rrow2Ccol2

12-84 Xilinx Development System

Attributes, Constraints, and Carry Logic

The following examples illustrate the format of CLB constraints. Enter LOC= and the
pin or CLB location. If the target symbol represents a soft macro, the LOC constraint is
applied to all appropriate symbols (flip-flops, maps) contained in that macro. If the
indicated logic does not fit into the specified blocks, an error is generated.
The following statements place logic in the designated CLB.

LOC=AA (XC3000)
LOC=CLB_R1C1 (XC4000, Spartans)
LOC=CLB_R1C1.LC0 (XC5200)
LOC=CLB_R1C1.S0 (Virtex)
The following statements place logic within the first column of CLBs. The asterisk (*)
is a wildcard character.

LOC=*A (XC3000)
LOC=CLB_R*C1 (XC4000, Spartans)
LOC=CLB_R*C1.LC0 (XC5200)
LOC=CLB_R*C1.S0 (Virtex)
The next two statements place logic in any of the three designated CLBs. There is no
significance to the order of the LOC statements.

LOC=AA,AB,AC (XC3000)
LOC=CLB_R1C1,CLB_R1C2,CLB_R1C3 (XC4000, Spartans, XC5200,
Virtex)
The following statements place logic within the rectangular block defined by the first
specified CLB in the upper left corner and the second specified CLB towards the
lower right corner.

LOC=AA:HE (XC3000)
LOC=CLB_R1C1:CLB_R8C5 (XC4000, XC5200, Spartans,
Virtex)
The next statement places logic in the X flip-flop of CLB_R2C2. For the Y flip-flop, use
the FFY tag.

LOC=CLB_R2C2.FFX (XC4000, Spartans)

You can prohibit PAR from using a specific CLB, a range of CLBs, or a row or column
of CLBs. Such prohibit constraints can be assigned only through the User Constraints
File (UCF). CLBs are prohibited by specifying a PROHIBIT constraint at the design
level, as shown in the following examples.
Example 1

Schematic None
UCF CONFIG PROHIBIT=clb_r1c5 ;
Do not place any logic in the CLB in row 1, column 5. CLB R1C1 is in the upper left
corner of the device.

Libraries Guide, Release M1.5 12-85

Libraries Guide, Release M1.5

Example 2

Schematic None
UCF CONFIG PROHIBIT=clb_r1c1:clb_r5c7 ;

Do not place any logic in the rectangular area bounded by the CLB R1C1 in the upper
left corner and CLB R5C7 in the lower right.
Example 3

Schematic None
UCF CONFIG PROHIBIT=clb_r*c3 ;

Do not place any logic in any row of column 3. You can use the wildcard (*) character
in place of either the row or column number to specify an entire row or column of
CLBs.
Example 4
Schematic None
UCF CONFIG PROHIBIT=clb_r2c4, clb_r7c9 ;

Do not place any logic in either CLB R2C4 or CLB R7C9.

Delay Locked Loop (DLL) Constraint Examples (Virtex Only)

You can constrain Virtex DLL elements—CLKDLL and CLKDLLHF—to a specific
physical site name. Specify LOC=DLL and a numeric value (0 through 3) to identify
the location.
Following is an example.

Schematic LOC=DLL1
UCF INST buf1 LOC=DLL1;

Edge Decoder Constraint Examples (XC4000 Only)

In an XC4000 design, you can assign the decode logic to a specified die edge or half-
edge. All elements of a single decode function must lie along the same edge; they
cannot be split across two edges of the die. If you use decoder constraints, you must
assign all decode inputs for a given function to the same edge. From the schematic,
attach LOC constraints to the decode logic — either a DECODE macro or a WAND
gate with the DECODE attribute. The constraints are then passed into the EDIF netlist
and after mapping is read by PAR.
The format of decode constraints is LOC= and the decode logic symbol location. If the
target symbol represents a soft macro containing only decode logic, for example,
DECODE8, the LOC constraint is applied to all decode logic contained in that macro.
If the indicated decode logic does not fit into the specified decoders, an error is gener-
ated.
To constrain decoders to precise positions within a side, constrain the associated pads.
However, because PAR determines decoder edges before processing pad constraints,
it is not enough to constrain the pads alone. To constrain decoders to a specific die

12-86 Xilinx Development System

Attributes, Constraints, and Carry Logic

side, use the following rule. For every output net that you want to constrain, specify
the side for at least one of its input decoders (WAND gates), using one of the
following.

LOC=L LOC=T
LOC=R LOC=B

The “Legal Edge Designations for Edge Decoders” table shows the legal edge desig-
nations.
Example 1

Schematic LOC=T
UCF INST dec1/$1I1 LOC=T ;

Place the decoder along the top edge of the die.

Example 2

Schematic LOC=L
UCF INST dec1/$1I1 LOC=L ;
Place the decoder logic along the left edge of the die.
Example 3

Schematic LOC=LT
UCF INST dec1/$1I1 LOC=LT ;
Place decoders along the top half of the left edge of the die. The first letter in this code
represents the die edge, and the second letter represents the desired half of that edge.

Table 12-9 Legal Edge Designations for Edge Decoders

Edge Code Edge Location

T Top edge
B Bottom edge
L Left edge
R Right edge
TL Left half of top edge
TR Right half of top edge
BL Left half of bottom edge
BR Right half of bottom edge
LT Top half of left edge
LB Bottom half of left edge
RT Top half of right edge
RB Bottom half of right edge
Note: The edges referred to in these constraints are die edges, which do not neces-
sarily correspond to package edges. View the device in EPIC to determine which pins
are on which die edge.

Libraries Guide, Release M1.5 12-87

Libraries Guide, Release M1.5

Flip-Flop Constraint Examples

Flip-flops can be constrained to a specific CLB, a range of CLBs, a row or column of
CLBs, a specific half-CLB, or one of four specific slices of the XC5200 CLB. Flip-flop
constraints can be assigned from the schematic or through the UCF file.
From the schematic, attach LOC constraints to the target flip-flop. The constraints are
then passed into the EDIF netlist and are read by PAR after the design is mapped.
The following examples show how the LOC constraint is applied to a schematic and
to a UCF (User Constraints File). The instance names of two flip-flops, /top-12/fdrd
and /top-54/fdsd, are used to show how you would enter the constraints in the UCF.
Example 1

Schematic LOC=clb_rlc5
UCF INST /top-12/fdrd LOC=clb_r1c5 ;
Place the flip-flop in the CLB in row 1, column 5. CLB R1C1 is in the upper left corner
of the device.
Example 2

Schematic LOC=clb_r1c1:clb_r5c7
UCF INST /top-12/fdrd LOC=clb_r1c1:clb_r5c7 ;
Place the flip-flop in the rectangular area bounded by the CLB R1C1 in the upper left
corner and CLB R5C7 in the lower right corner.
Example 3

Schematic LOC=clb_r*c3
UCF INST /top-12/fdrd/top-54/fdsd LOC=clb_r*c3 ;
Place the flip-flops in any row of column 3. You can use the wildcard (*) character in
place of either the row or column number to specify an entire row or column of CLBs.
In the following example, repeating the LOC constraint and separating each such
constraint by a comma specifies multiple locations for an element. When you specify
multiple locations, PAR can use any of the specified locations.
Example 4

Schematic LOC=clb_r2c4,clb_r7c9
UCF INST /top-54/fdsd LOC=clb_r2c4,clb_r7c9 ;
Place the flip-flop in either CLB R2C4 or CLB R7C9.
Example 5

Schematic LOC=clb_r3c5.ffx
UCF INST /top-12/fdrd LOC=clb_r3c5.ffx ;
Place the flip-flop in CLB R3C5 and assign the flip-flop output to the XQ pin. (Note:
Use the FFY tag to indicate the YQ pin of the CLB.) If either the FFX or FFY tags are
specified, the wildcard (*) character cannot be used for the row or column numbers.

12-88 Xilinx Development System

Attributes, Constraints, and Carry Logic

Example 6

Schematic PROHIBIT=clb_r5c*
UCF CONFIG PROHIBIT=clb_r5c* ;

Do not place the flip-flop in any column of row 5. You can use the wildcard (*) char-
acter in place of either the row or column number to specify an entire row or column
of CLBs.
The XC5200 CLB is divided into four specific slices for every row and column location
on the array. In order to place a flip-flop in a specific slice, use the .LC0, .LC1, .LC2, or
.LC3 extension on the location constraint as shown in the following example.
Example 7

Schematic LOC=clb_r1c5.LC3
UCF INST /top-12/fdrd LOC=clb_r1c5.LC3 ;

Place the flip-flop in the top slice of the XC5200 CLB in row 1, column 5.

Global Buffer Constraint Examples

XC3000
You cannot assign placement to the GCLK or ACLK buffers in the XC3000 family,
since there is only one each, and their placements are fixed on the die.

XC4000, XC5200, Spartans

For the XC4000, XC5200, and Spartans, you can constrain a global buffer — BUFG,
BUFGP, BUFGS, BUFGLS, BUFGE, or BUFFCLK— to a corner of the die. From the
schematic, attach LOC constraints to the global buffer symbols; specify LOC= and the
global clock buffer location. The constraints are then passed into the EDIF netlist and
after mapping are read by PAR.
Following is an example.

Schematic LOC=TL
UCF INST buf1 LOC=TL ;

Place the global buffer in the top left corner of the die. The following table shows the
legal corner designations.
Table 12-10 Legal Corner Designations for Global Buffers

Corner Code Corner Location

TL Top left corner
TR Top right corner
BL Bottom left corner
BR Bottom right corner

If a global buffer is sourced by an external signal, the dedicated IOB for that buffer
must not be used by any other signal. For example, if a BUFGP is constrained to TL,
the PGCK1 pin must be used to source it, and no other I/O can be assigned to that
pin.

Libraries Guide, Release M1.5 12-89

Libraries Guide, Release M1.5

Virtex
You can constrain a Virtex global buffer—BUFGP, and IBUFG_selectIO variants—to a
specific buffer site name or dedicated global clock pad in the device model. From the
schematic, attach LOC constraints to the global buffer symbols. Specify LOC= and
GCLKBUF plus a number (0 through 3) to create a specific buffer site name in the
device model. Or, specify LOC= and GCLKPAD plus a number (0 through 3) to create
a specific dedicated global clock pad in the device model.The constraints are then
passed into the EDIF netlist and after mapping are read by PAR.
Following is an example.
Schematic LOC=GCLKBUF1
UCF INST buf1 LOC=GCLKBUF1;
Schematic LOC=GCLKPAD1
UCF INST buf1 LOC=GCLKPAD1;

I/O Constraint Examples

You can constrain I/Os to a specific IOB. You can assign I/O constraints from the
schematic or through the UCF file.
From the schematic, attach LOC constraints to the target PAD symbol. The constraints
are then passed into the netlist file and read by PAR after mapping.
Alternatively, in the UCF file a pad is identified by a unique instance name. The
following example shows how the LOC constraint is applied to a schematic and to a
UCF (User Constraints File). In the examples, the instance names of the I/Os are /top-
102/data0_pad and /top-117/q13_pad. The example uses a pin number to lock to one
pin.

Schematic LOC=p17
UCF INST /top-102/data0_pad LOC=p17 ;
Place the I/O in the IOB at pin 17. For pin grid arrays, a pin name such as B3 or T1 is
used.

IOB Constraint Examples

You can assign I/O pads, buffers, and registers to an individual IOB location. IOB
locations are identified by the corresponding package pin designation.
The following examples illustrate the format of IOB constraints. Specify LOC= and
the pin location. If the target symbol represents a soft macro containing only I/O
elements, for example, INFF8, the LOC constraint is applied to all I/O elements
contained in that macro. If the indicated I/O elements do not fit into the specified
locations, an error is generated.
The following statement places the I/O element in location P13. For PGA packages,
the letter-number designation is used, for example, B3.
LOC=P13
You can prohibit the mapper from using a specific IOB. You might take this step to
keep user I/O signals away from semi-dedicated configuration pins. Such prohibit
constraints can be assigned only through the UCF file.

12-90 Xilinx Development System

Attributes, Constraints, and Carry Logic

IOBs are prohibited by specifying a PROHIBIT constraint preceded by the CONFIG

keyword, as shown in the following example.
Schematic None
UCF CONFIG PROHIBIT=p36, p37, p41 ;

Do not place user I/Os in the IOBs at pins 36, 37, or 41. For pin grid arrays, pin names
such as D14, C16, or H15 are used.

Mapping Constraint Examples

Mapping constraints control the mapping of logic into CLBs. They have two parts.
The first part is a FMAP, HMAP, or CLBMAP component placed on the schematic.
The second is a LOC constraint that can be placed on the schematic or in the
constraints file.

CLBMAP (XC3000 Only)

With the CLBMAP symbol, you can specify logic mapping at the schematic level for
all XC3000 designs. It is used in conjunction with standard logic elements, such as
gates and flip-flops. It implicitly specifies the configuration of a CLB by defining the
signals on its pins. Use the CLBMAP symbol to control mapping when the default
mapping is not acceptable.
Enter the CLBMAP symbol on the schematic and assign signals to its pins. MAP
processes this symbol and maps the appropriate logic, as defined by the input and
output signals, into one CLB. The easiest way to define a CLBMAP is to connect a
labeled wire segment to each pin, which connects that pin to the net carrying the same
label.
If a CLBMAP specifies an illegal CLB configuration, MAP issues an error explaining
why the CLBMAP is illegal.
A CLBMAP can be either closed or open. A closed CLBMAP must specify both the
input and output signals for that CLB. MAP maps a closed CLBMAP exactly as speci-
fied, unless the indicated configuration is illegal. MAP does not add any logic to a
CLB specified with a closed CLBMAP.
An open CLBMAP specifies the minimum amount of logic to place within a CLB.
MAP attempts to place more logic within the CLB as long as the CLB remains valid.
MAP only adds logic on the inputs to the CLB. It does not add logic on the output
signals. MAP assigns those signals to the CLB output pins and maps the source logic
into the CLB as appropriate. Use an open CLBMAP to specify the minimum function
of a CLB.
Specify whether a CLBMAP is open or closed by attaching the appropriate MAP
attribute to the symbol. See the “Map Attributes for CLBMAP Symbols” table for the
exact conventions.
The default configuration for a CLBMAP is unlocked and open.

Libraries Guide, Release M1.5 12-91

Libraries Guide, Release M1.5

Table 12-11 Map Attributes for CLBMAP Symbols

Closed CLB Open CLB

Pins locked MAP=PLC MAP=PLO
Pins unlocked MAP=PUC MAP=PUO (default)

Note: Currently, pin locking is not supported. PLC and PLO are translated into PUC
and PUO, respectively.
Example 1
Schematic LOC=CLB_R1C1
UCF INST top/cntq7 LOC=CLB_R1C1 ;

Place the CLBMAP in CLB CLB_R1C1.

Example 2
Schematic LOC=AA:EE
UCF INST reg/bit7 LOC=AA:EE ;

Place the CLBMAP in the area bounded by CLB AA in the upper left corner and CLB
EE in the lower right.

FMAP and HMAP

The FMAP and HMAP symbols control mapping in an XC4000 or Spartan series
design. They are similar to the XC3000 CLBMAP symbol. The FMAP may also be
used to control mapping XC5200 or Virtex designs.
FMAP and HMAP control the mapping of logic into function generators. These
symbols do not define logic on the schematic; instead, they specify how portions of
logic shown elsewhere on the schematic should be mapped into a function generator.
The FMAP symbol defines mapping into a four-input (F) function generator. The
mapper assigns this function to an F or G function generator for XC4000 and Spartans,
so you are not required to specify whether it belongs in F or G. For the XC5200, the
four-input function generator defined by the FMAP will be assigned to one of the four
slices of the CLB. For Virtex, the four-input function generator defined by the FMAP
will be assigned to one of the two slices of the CLB.
The HMAP symbol defines mapping into a three-input (H) function generator for
XC4000 and Spartans. If the HMAP has two FMAP outputs and, optionally, one
normal (non-FMAP) signal as its inputs, The mapper places all the logic related to
these symbols into one CLB.
An example of how to use these symbols in your schematic appears in the “FMAP
and HMAP Schematics” figure and the “Implementation of FMAP and HMAP”
figure.
For the FMAP symbol as with the CLBMAP primitive, MAP=PUC or PUO is
supported, as well as the LOC constraint. (Currently, pin locking is not supported.
MAP=PLC or PLO is translated into PUC and PUO, respectively.)
For the HMAP symbol, only MAP=PUC is supported.

12-92 Xilinx Development System

Attributes, Constraints, and Carry Logic

Example 1

Schematic LOC=clb_r7c3
UCF INST $1I323 LOC=clb_r7c3;
Place the FMAP or HMAP symbol in the CLB at row 7, column 3.
Example 2

Schematic LOC=clb_r2c4,clb_r3c4
UCF INST top/dec0011 LOC=clb_r2c4,clb_r3c4;
Place the FMAP or HMAP symbol in either the CLB at row 2, column 4 or the CLB at
row 3, column 4.
Example 3

Schematic LOC=clb_r5c5:clb_r10c8
UCF INST $3I27 LOC=clb_r5c5:clb_r10c8;
Place the FMAP or HMAP symbol in the area bounded by CLB R5C5 in the upper left
corner and CLB R10C8 in the lower right.
Example 4 (XC4000, Spartans)

Schematic LOC=clb_r10c11.f
UCF INST top/done LOC=clb_r1011.f ;
Place the FMAP in the F function generator of CLB R10C11. The .G extension specifies
the G function generator. An HMAP can only go into the H function generator, so
there is no need to specify this placement explicitly.
The XC5200 CLB is divided into four specific slices for every row and column location
in the array. In order to place a function generator in a specific slice, use the .LC0,
.LC1, .LC2., or LC3 extension on the location constraint on the FMAP as shown in the
following example.
Example 5 (XC5200)

Schematic LOC=clb_r10c11.LC3
UCF INST /top/done LOC=clb_r10c11.LC3 ;
Place the FMAP in the top slice of the XC5200 CLB in row 10, column 11.
The Virtex CLB is divided into two specific slices for every row and column location
in the array. In order to place a function generator in a specific slice, use the .S0 (left-
most slice) or .S1 (right-most slice) extension on the location constraint on the FMAP
as shown in the following example.
Example 6 (Virtex)

Schematic LOC=clb_r10c11.S0
UCF INST /top/done LOC=clb_r10c11.S0 ;

Place the FMAP in the left-most slice of the Virtex CLB in row 10, column 11.

Libraries Guide, Release M1.5 12-93

Libraries Guide, Release M1.5

A1 F_OUT

A2 AND2
A3
A4
OR3

AND2 RESULT
B1
B2 OR2
B3
XOR3 G_OUT
AND2B1

OR2

B4
AND2B1

SEL

FMAP
A1 I4
A2 I3 F_OUT
O
A3 I2
HMAP
A4 I1
I3
RESULT
I2 O
FMAP
I1
B1 I4
B2 I3 G_OUT
O
B3 I2
B4 I1

X4403
SEL

Figure 12-2 FMAP and HMAP Schematics

IN_H1

IN_F1
IN_F2
IN_F3 F
IN_F4
H_FUNC
H
IN_G1
IN_G2
IN_G3 G
IN_G4

X1890

Figure 12-3 Implementation of FMAP and HMAP

RAM and ROM Constraint Examples

You can constrain a ROM or RAM to a specific CLB, a range of CLBs, or a row or
column of CLBs. Memory constraints can be assigned from the schematic or through
the UCF file.
From the schematic, attach the LOC constraints to the memory symbol. The
constraints are then passed into the netlist file and after mapping they are read by
PAR. For more information on attaching LOC constraints, see the appropriate inter-
face user guide.
Alternatively, in the constraints file a memory is identified by a unique instance name.
One or more memory instances of type ROM or RAM can be found in the input file.
All memory macros larger than 16 x 1 or 32 x 1 are broken down into these basic
elements in the netlist file.

12-94 Xilinx Development System

Attributes, Constraints, and Carry Logic

In the following examples, the instance name of the ROM primitive is /top-7/rq. The
instance name of the RAM primitive, which is a piece of a RAM64X8 macro, is /top-
11-ram64x8/ram-3.
Example 1
Schematic LOC=clb_r1c5
UCF INST /top-7/rq LOC=clb_r1c5 ;

Place the memory in the CLB in row 1, column 5. CLB R1C1 is in the upper left corner
of the device. You can only apply a single-CLB constraint such as this to a 16 x 1 or 32
x 1 memory.
Example 2
Schematic LOC=clb_r2c4, clb_r7c9
UCF INST /top-7/rq LOC=clb_r2c4, clb_r7c9 ;

Place the memory in either CLB R2C4 or CLB R7C9.

Example 3
Schematic LOC=clb_r1c1:clb_r5c7
UCF INST /top-17/bigram/*
LOC=clb_r1c1:clb_r5c7 ;

Place the LogiBlox module in the rectangular area bounded by the CLB R1C1 in the
upper left corner and CLB R5C7 in the lower right.
From the schematic, attach the LOC constraint to the LogiBlox symbol for the bigram
block.
In the UCF file, the /* is appended to the end of the LogiBlox symbol instance. The
wildcard (*) character here specifies all instances that begin with the /top-17/bigram/
prefix, that is, all RAM elements within the LogiBlox block.
Example 4
Schematic PROHIBIT clb_r5c*
UCF CONFIG PROHIBIT=clb_r5c* ;

Do not place the memory in any column of row 5. You can use the wildcard (*) char-
acter in place of either the row or column number in the CLB name to specify an entire
row or column of CLBs.

RAMB4 (Block RAM) Constraint Examples (Virtex Only)

You can constrain a Virtex block RAM to a specific CLB, a range of CLBs, or a row or
column of CLBs. Memory constraints can be assigned from the schematic or through
the UCF file. From the schematic, attach the LOC constraints to the memory symbol.
The constraints are then passed into the netlist file and after mapping they are read by
PAR. For more information on attaching LOC constraints, see the appropriate inter-
face user guide. Alternatively, in the constraints file a memory is identified by a
unique instance name.
A Virtex block RAM has a different row/column grid specification than CLBs and
TBUFs. It is specified using RAMB4_RnCn where the numeric row and column
numbers refer to the block RAM grid array. A block RAM located at RAMB4_R3C1 is
not located at the same site as a flip-flop located at CLB_R3C1.

Libraries Guide, Release M1.5 12-95

Libraries Guide, Release M1.5

For example, assume you have a device with two columns of block RAM, each
column containing four blocks, where one column is on the right side of the chip and
the other is on the left. The block RAM located in the upper left corner is
RAMB4_R0C0. Because there are only two columns of block RAM, the block located
in the upper right corner is RAMB4_R0C1.

Schematic LOC=RAMB4_R0C0
UCF INST /top-7/rq LOC=RAMB4_R0C0 ;

12-96 Xilinx Development System

Attributes, Constraints, and Carry Logic

Relative Location (RLOC) Constraints

Note: This section applies all FPGA families except XC3000.
The RLOC constraint groups logic elements into discrete sets. You can define the loca-
tion of any element within the set relative to other elements in the set, regardless of
eventual placement in the overall design. For example, if RLOC constraints are
applied to a group of eight flip-flops organized in a column, the mapper maintains the
columnar order and moves the entire group of flip-flops as a single unit. In contrast,
absolute location (LOC) constraints constrain design elements to specific locations on
the FPGA die with no relation to other design elements.

Benefits and Limitations of RLOC Constraints

RLOC constraints allow you to place logic blocks relative to each other to increase
speed and use die resources efficiently. They provide an order and structure to related
design elements without requiring you to specify their absolute placement on the
FPGA die. They allow you to replace any existing hard macro with an equivalent that
can be directly simulated.
In the Unified Libraries, you can use RLOC constraints with BUFT- and CLB-related
primitives, that is, DFF, HMAP, FMAP, and CY4 primitives. You can also use them on
non-primitive macro symbols. There are some restrictions on the use of RLOC
constraints on BUFT symbols; for details, see the “Fixing Members of a Set at Exact
Die Locations” section. You cannot use RLOC constraints with decoders, clocks, or I/
O primitives. LOC constraints, on the other hand, can be used on all primitives:
BUFTs, CLBs, IOBs, decoders, and clocks.
The following symbols (primitives) accept RLOCs.
1. Registers
2. FMAP
3. HMAP
4. F5MAP
5. CY4
6. CY_MUX
7. ROM
8. RAM
9. RAMS, RAMD
10. BUFT
11. WAND primitives that do not have a DECODE attribute attached
12. LUTs, F5MUX, F6MUX, MUXCY, XORCY, MULT_AND, SRL16, SRL16E

Guidelines for Specifying Relative Locations

General syntax for assigning elements to relative locations is
RLOC=RmCn [.extension]
where m and n are relative row numbers and column numbers, respectively.

Libraries Guide, Release M1.5 12-97

Libraries Guide, Release M1.5

The extension uses the LOC extension syntax as appropriate; for example .1 and .2 for
TBUF location.
The extension is required for XC5200 designs in order to fully specify the order of the
elements (.LC0, .LC1, .LC2, .LC3). It is required for Virtex designs to specify the
spatial relationship of the objects in the RPM (.S0, .S1).
The row and column numbers can be any positive or negative integer including zero.
Absolute die locations, in contrast, cannot have zero as a row or column number.
Because row and column numbers in RLOC constraints define only the order and
relationship between design elements and not their absolute die locations, their
numbering can include zero or negative numbers. Even though you can use any
integer in numbering rows and columns for RLOC constraints, it is recommended
that you use small integers for clarity and ease of use.
It is not the absolute values of the row and column numbers that is important in
RLOC specifications but their relative values or differences. For example, if design
element A has an RLOC=R3C4 constraint and design element B has an RLOC=R6C7
constraint, the absolute values of the row numbers (3 and 6) are not important in
themselves. However, the difference between them is important; in this case, 3 (6 -3)
specifies that the location of design element B is three rows away from the location of
design element A. To capture this information, a normalization process is used at
some point in the design implementation. In the example just given, normalization
would reduce the RLOC on design element A to R0C0, and the RLOC on design
element B to R3C3.
In Xilinx programs, rows are numbered in increasing order from top to bottom, and
columns are numbered in increasing order from left to right. RLOC constraints follow
this numbering convention.
The “Different RLOC Specifications for Four Flip-flop Primitives for an XC4000 or
Spartan Series Design” figure demonstrates the use of RLOC constraints. Four flip-
flop primitives named A, B, C, and D are assigned RLOC constraints as shown. These
RLOC constraints require each flip-flop to be placed in a different CLB in the same
column and stacked in the order shown — A above B, C, and D. Within a CLB,
however, they can be placed either in the FFX or FFY position.
If you wish to place more than one of these flip-flop primitives per CLB, you can
specify the RLOCs as shown in the “Different RLOC Specifications for Four Flip-flop
Primitives for an XC4000 or Spartan Series Design” figure. The arrangement in the
figure requires that A and B be placed in a single CLB and that C and D be placed in
another CLB immediately below the AB CLB. However, within a CLB, the flip-flops
can be placed in either of the two flip-flop positions, FFX or FFY.
To control the ordering of these flip-flop primitives specifically, you can use the exten-
sion field, as shown in the “Different RLOC Specifications for Four Flip-flop Primi-
tives for an XC4000 or Spartan Series Design” figure. In this figure, the same four flip-
flops are constrained to use specific resources in the CLBs. This specification always
ensures that these elements are arranged exactly as shown— A must be placed in the
FFX spot, B in the same CLB at the FFY spot, and so on.

12-98 Xilinx Development System

Attributes, Constraints, and Carry Logic

(a) (b) (c)

RLOC = R0C0 RLOC = R0C0 RLOC = R0C0.FFX

A A A

RLOC = R0C0 RLOC = R0C0.FFY

B B

RLOC = R1C0 RLOC = R1C0 RLOC = R1C0.FFX

B C C

RLOC = R1C0 RLOC = R1C0.FFY

D D

RLOC = R2C0
C

Shaded lines indicate a CLB grid.

RLOC = R3C0
D

X4292

Figure 12-4 Different RLOC Specifications for Four Flip-flop Primitives for an
XC4000 or Spartan Series Design

RLOC Sets
RLOC constraints give order and structure to related design elements. This section
describes RLOC sets, which are groups of related design elements to which RLOC
constraints have been applied. For example, the four flip-flops in the “Different
RLOC Specifications for Four Flip-flop Primitives for an XC4000 or Spartan Series
Design” figure are related by RLOC constraints and form a set. Elements in a set are
related by RLOC constraints to other elements in the same set. Each member of a set
must have an RLOC constraint, which relates it to other elements in the same set. You
can create multiple sets, but a design element can belong to one set only.
Sets can be defined explicitly through the use of a set parameter or implicitly through
the structure of the design hierarchy.
Four distinct types of rules are associated with each set.
• Definition rules define the requirements for membership in a set.
• Linkage rules specify how elements can be linked to other elements to form a
single set.
• Modification rules dictate how to specify parameters that modify RLOC values of
all the members of the set.
• Naming rules specify the nomenclature of sets.
These rules are discussed in the sections that follow.
The following sections discuss three different set constraints— U_SET, H_SET, and
HU_SET. Elements must be tagged with both the RLOC constraint and one of these
set constraints to belong to a set.

U_SET
U_SET constraints enable you to group into a single set design elements with attached
RLOC constraints that are distributed throughout the design hierarchy. The letter U in
the name U_SET indicates that the set is user-defined. U_SET constraints allow you to
group elements, even though they are not directly related by the design hierarchy. By

Libraries Guide, Release M1.5 12-99

Libraries Guide, Release M1.5

attaching a U_SET constraint to design elements, you can explicitly define the
members of a set. The design elements tagged with a U_SET constraint can exist
anywhere in the design hierarchy; they can be primitive or non-primitive symbols.
When attached to non-primitive symbols, the U_SET constraint propagates to all the
primitive symbols with RLOC constraints that are below it in the hierarchy.
The syntax of the U_SET constraint is the following.
U_SET=set_name
where set_name is the user-specified identifier of the set. All design elements with
RLOC constraints tagged with the same U_SET constraint name belong to the same
set. Names therefore must be unique among all the sets in the design.

H_SET
In contrast to the U_SET constraint, which you explicitly define by tagging design
elements, the H_SET (hierarchy set) is defined implicitly through the design hier-
archy. The combination of the design hierarchy and the presence of RLOC constraints
on elements defines a hierarchical set, or H_SET set. You do not use an HSET
constraint to tag the design elements to indicate their set membership. The set is
defined automatically by the design hierarchy.
All design elements with RLOC constraints at a single node of the design hierarchy
are considered to be in the same H_SET set unless they are tagged with another type
of set constraint such as RLOC_ORIGIN or RLOC_RANGE. If you explicitly tag any
element with an RLOC_ORIGIN, RLOC_RANGE, U_SET, or HU_SET constraint, it is
removed from an H_SET set. Most designs contain only H_SET constraints, since they
are the underlying mechanism for relationally placed macros. The RLOC_ORIGIN or
RLOC_RANGE constraints are discussed further in the “Fixing Members of a Set at
Exact Die Locations” section.
NGDBuild recognizes the implicit H_SET set, derives its name, or identifier, attaches
the H_SET constraint to the correct members of the set, and writes them to the output
file.
The syntax of the H_SET constraint as generated by NGDBuild follows.
H_SET=set_name
set_name is the identifier of the set and is unique among all the sets in the design. The
base name for any H_SET is “hset,” to which NGDBuild adds a hierarchy path prefix
to obtain unique names for different H_SET sets in the NGDBuild output file.

HU_SET
The HU_SET constraint is a variation of the implicit H_SET (hierarchy set). Like
H_SET, HU_SET is defined by the design hierarchy. However, you can use the
HU_SET constraint to assign a user-defined name to the HU_SET.
The syntax of the HU_SET constraint is the following.
HU_SET=set_name
where set_name is the identifier of the set; it must be unique among all the sets in the
design. You must define the base names to ensure unique hierarchically qualified
names for the sets after the mapper resolves the design and attaches the hierarchical
names as prefixes.

12-100 Xilinx Development System

Attributes, Constraints, and Carry Logic

This user-defined name is the base name of the HU_SET set. Like the H_SET set, in
which the base name of “hset” is prefixed by the hierarchical name of the lowest
common ancestor of the set elements, the user-defined base name of an HU_SET set is
prefixed by the hierarchical name of the lowest common ancestor of the set elements.
The HU_SET constraint defines the start of a new set. All design elements at the same
node that have the same user-defined value for the HU_SET constraint are members
of the same HU_SET set. Along with the HU_SET constraint, elements can also have
an RLOC constraint. The presence of an RLOC constraint in an H_SET constraint links
the element to all elements tagged with RLOCs above and below in the hierarchy.
However, in the case of an HU_SET constraint, the presence of an RLOC constraint
along with the HU_SET constraint on a design element does not automatically link
the element to other elements with RLOC constraints at the same hierarchy level or
above.

Design-top

Inst1 Inst2
Macro A

Macro A

RLOC RLOC
A = >H_SET = Inst1/hset A = >H_SET = Inst2/hset

RLOC RLOC
B = >H_SET = Inst1/hset B = >H_SET = Inst2/hset

RLOC RLOC
C = >H_SET = Inst1/hset C = >H_SET = Inst2/hset

RLOC RLOC
D = >H_SET = Inst1/hset D = >H_SET = Inst2/hset

X4294

Figure 12-5 Macro A Instantiated Twice

Note: In the “Macro A Instantiated Twice” figure and the other related figures shown
in the subsequent sections, the italicized text prefixed by => is added by NGDBuild
during the design flattening process. You add all other text.
The “Macro A Instantiated Twice” figure demonstrates a typical use of the implicit
H_SET (hierarchy set). The figure shows only the first “RLOC” portion of the
constraint. In a real design, the RLOC constraint must be specified completely with
RLOC=RmCn. In this example, macro A is originally designed with RLOC constraints
on four flip-flops — A, B, C, and D. The macro is then instantiated twice in the design
— Inst1 and Inst2. When the design is flattened, two different H_SET sets are recog-
nized because two distinct levels of hierarchy contain elements with RLOC
constraints. NGDBuild creates and attaches the appropriate H_SET constraint to the
set members: H_SET=Inst1/hset for the macro instantiated in Inst1, and
H_SET=Inst2/hset for the macro instantiated in Inst2. The design implementation

Libraries Guide, Release M1.5 12-101

Libraries Guide, Release M1.5

programs place each of the two sets individually as a unit with relative ordering
within each set specified by the RLOC constraints. However, the two sets are regarded
to be completely independent of each other.
The name of the H_SET set is derived from the symbol or node in the hierarchy that
includes all the RLOC elements. In the “Macro A Instantiated Twice” figure, Inst1 is
the node (instantiating macro) that includes the four flip-flop elements with RLOCs
shown on the left of the figure. Therefore, the name of this H_SET set is the hierarchi-
cally qualified name of “Inst1” followed by “hset.” The Inst1 symbol is considered the
“start” of the H_SET, which gives a convenient handle to the entire H_SET and
attaches constraints that modify the entire H_SET. Constraints that modify sets are
discussed in the “Set Modifiers” section.
The “Macro A Instantiated Twice” figure demonstrates the simplest use of a set that is
defined and confined to a single level of hierarchy. Through linkage and modification,
you can also create an H_SET set that is linked through two or more levels of hier-
archy. Linkage allows you to link elements through the hierarchy into a single set. On
the other hand, modification allows you to modify RLOC values of the members of a
set through the hierarchy.

RLOC Set Summary

The following table summarizes the RLOC set types and the constraints that identify
members of these sets.

Table 12-12 Summary of Set Types

Type Definition Naming Linkage Modification

Set A set is a collec-
tion of elements
to which rela-
tive location
constraints are
applied.
U_SET= name All elements The name of U_SET links U_SET is modi-
with the same the set is the elements to all fied by
user-tagged same as the other elements applying
U_SET user-defined with the same RLOC_ORIGIN
constraint name without value for the or
value are any hierarchical U_SET RLOC_RANGE
members of the qualification. constraint. constraints on,
same U_SET at most, one of
set. the U_SET
constraint-
tagged
elements.

12-102 Xilinx Development System

Attributes, Constraints, and Carry Logic

Table 12-12 Summary of Set Types

Type Definition Naming Linkage Modification

H_SET RLOC on the The lowest H_SET links H_SET is modi-
(implicit node. Any common elements to fied by
through hier- other ancestor of the other elements applying
archy) is not constraint members at the same RLOC_ORIGIN
available as a removes a defines the start node that do and
constraint that node from the of the set. The not have other RLOC_RANGE
you can attach H_SET set. name is the constraints. It at the start of
to symbols. hierarchically links down to the set: the
qualified name all elements lowest common
of the start that have ancestor of all
followed by RLOC the elements of
the base name, constraints and the set.
“hset.” no other
constraints.
Similarly, it
links to other
elements up the
hierarchy that
have RLOC
constraints but
no other
constraints.
HU_SET= All elements The lowest HU_SET links The start of the
name with the same common to other set is made up
hierarchically ancestor of the elements at the of the elements
qualified name members is same node with on the same
are members of prefixed to the the same node that are
the same set. user-defined HU_SET tagged with
name to obtain constraint the same
the name of the value. It links to HU_SET
set. elements with constraint
RLOC value. An
constraints RLOC_ORIGIN
below. or an
RLOC_RANGE
can be applied
to, at most, one
of these start
elements of an
HU_SET set.

Set Linkage
The example in the “Three H_SET Sets” figure explains and illustrates the process of
linking together elements through the design hierarchy. Again, the complete RLOC
specification, RLOC=RmCn, is required for a real design.
Note: In this and other illustrations in this section, the sets are shaded differently to
distinguish one set from another.

Libraries Guide, Release M1.5 12-103

Libraries Guide, Release M1.5

Design-top

A B

C RLOC D RLOC E

F RLOC J RLOC M RLOC

= > H_SET = A/hset = > H_SET = A/hset = > H_SET = A/E/hset

G RLOC K RLOC N RLOC

= > H_SET = A/hset = > H_SET = A/hset = > H_SET = A/E/hset

H RLOC L
= > H_SET = A/hset

RLOC
I = > H_SET = A/hset
RLOC
Q = > H_SET = A/D/L/hset

O RLOC
= > H_SET = A/hset RLOC
R = > H_SET = A/D/L/hset

P RLOC
= > H_SET = A/hset
S

X4295

Figure 12-6 Three H_SET Sets

As noted previously, all design elements with RLOC constraints at a single node of
the design hierarchy are considered to be in the same H_SET set unless they are
assigned another type of set constraint, an RLOC_ORIGIN constraint, or an
RLOC_RANGE constraint. In the “Three H_SET Sets” figure, RLOC constraints have
been added on primitives and non-primitives C, D, F, G, H, I, J, K, M, N, O, P, Q, and
R. No RLOC constraints were placed on B, E, L, or S. Macros C and D have an RLOC
constraint at node A, so all the primitives below C and D that have RLOCs are
members of a single H_SET set. Furthermore, the name of this H_SET set is “A/hset”
because it is at node A that the set starts. The start of an H_SET set is the lowest
common ancestor of all the RLOC-tagged constraints that constitute the elements of
that H_SET set. Because element E does not have an RLOC constraint, it is not linked
to the A/hset set. The RLOC-tagged elements M and N, which lie below element E,
are therefore in their own H_SET set. The start of that H_SET set is A/E, giving it the
name “A/E/hset.”
Similarly, the Q and R primitives are in their own H_SET set because they are not
linked through element L to any other design elements. The lowest common ancestor
for their H_SET set is L, which gives it the name “A/D/L/hset.” After the flattening,
NGDBuild attaches H_SET=A/hset to the F, G, H, O, P, J, and K primitives;
H_SET=A/D/L/hset to the Q and R primitives; and H_SET=A/E/hset to the M and
N primitives.

12-104 Xilinx Development System

Attributes, Constraints, and Carry Logic

Consider a situation in which a set is created at the top of the design. In the “Three
H_SET Sets” figure, there would be no lowest common ancestor if macro A also had
an RLOC constraint, since A is at the top of the design and has no ancestor. In this
case, the base name “hset” would have no hierarchically qualified prefix, and the
name of the H_SET set would simply be “hset.”

Set Modification
The RLOC constraint assigns a primitive an RLOC value (the row and column
numbers with the optional extensions), specifies its membership in a set, and links
together elements at different levels of the hierarchy. In the “Three H_SET Sets”
figure, the RLOC constraint on macros C and D links together all the objects with
RLOC constraints below them. An RLOC constraint is also used to modify the RLOC
values of constraints below it in the hierarchy. In other words, RLOC values of
elements affect the RLOC values of all other member elements of the same H_SET set
that lie below the given element in the design hierarchy.

The Effect of the Hierarchy on Set Modification

When the design is flattened, the row and column numbers of an RLOC constraint on
an element are added to the row and column numbers of the RLOC constraints of the
set members below it in the hierarchy. This feature gives you the ability to modify
existing RLOC values in submodules and macros without changing the previously
assigned RLOC values on the primitive symbols. This modification process also
applies to the optional extension field. However, when using extensions for modifica-
tions, you must ensure that inconsistent extensions are not attached to the RLOC
value of a design element that may conflict with RLOC extensions placed on under-
lying elements. For example, if an element has an RLOC constraint with the FFX
extension, all the underlying elements with RLOC constraints must either have the
same extension, in this case FFX, or no extension at all; any underlying element with
an RLOC constraint and an extension different from FFX, such as FFY or F, is flagged
as an error.
After resolving all the RLOC constraints, extensions that are not valid on primitives
are removed from those primitives. For example, if NGDBuild generates an FFX
extension to be applied on a primitive after propagating the RLOC constraints, it
applies the extension if and only if the primitive is a flip-flop. If the primitive is an
element other than a flip-flop, the extension is ignored. Only the extension is ignored
in this case, not the entire RLOC constraint.
The “Adding RLOC Values Down the Hierarchy” figure illustrates the process of
adding RLOC values down the hierarchy. The row and column values between the
parentheses show the addition function performed by the mapper. The italicized text
prefixed by => is added by MAP during the design resolution process and replaces
the original RLOC constraint that you added.

Libraries Guide, Release M1.5 12-105

Libraries Guide, Release M1.5

Design-top
NGDBuild adds
R2C3 below to RLOC = R2C3
create new RLOC A

RLOC = R0C0 (+R2C3)

B = >RLOC = R2C3

RLOC = R1C0 (+R2C3)

C = >RLOC = R3C3

RLOC = R2C0 (+R2C3)

D
= >RLOC = R4C3

NGDBuild adds
R5C3.FFX below to RLOC = R3C0.FFX (+R2C3)
E
create new RLOC = >RLOC = R5C3.FFX

RLOC = R0C0 (+R5C3.FFX)

F = >RLOC = R5C3.FFX

RLOC = R1C0 (+R5C3.FFX)

G
= >RLOC = R6C3.FFX

X4296

Figure 12-7 Adding RLOC Values Down the Hierarchy

The ability to modify RLOC values down the hierarchy is particularly valuable when
instantiating the same macro more than once. Typically, macros are designed with
RLOC constraints that are modified when the macro is instantiated. The “Modifying
RLOC Values of Same Macro and Linking Together as One Set” figure is a variation of
the sample design in the “Macro A Instantiated Twice” figure. The RLOC constraint
on Inst1 and Inst2 now link all the objects in one H_SET set. Because the RLOC=R0C0
modifier on the Inst1 macro does not affect the objects below it, the mapper only adds
the H_SET tag to the objects and leaves the RLOC values as they are. However, the
RLOC=R0C1 modifier on the Inst2 macro causes MAP to change the RLOC values on
objects below it, as well as to add the H_SET tag, as shown in the italicized text.

12-106 Xilinx Development System

Attributes, Constraints, and Carry Logic

Design-top
Inst1 Inst2

RLOC = R0C0 RLOC = R0C1

add R0C0—no add R0C1 to shift
change the set 1 column
to the right

Macro A

Macro A
RLOC = R0C0 RLOC = R0C0 (+R0C1)
A = >H_SET = hset A = >H_SET = hset
= >RLOC = R0C1

RLOC = R1C0 (+R0C1)

RLOC = R1C0
B = >H_SET = hset
B = >H_SET = hset
= >RLOC = R1C1

RLOC = R2C0 (+R0C1)

RLOC = R2C0
C = >H_SET = hset C = >H_SET = hset
= >RLOC = R2C1

RLOC = R3C0 (+R0C1)

RLOC = R3C0
D D = >H_SET = hset
= >H_SET = hset
= >RLOC = R3C1

X4297

Figure 12-8 Modifying RLOC Values of Same Macro and Linking Together as
One Set

Separating Elements from H_SET Sets

The HU_SET constraint is a variation of the implicit H_SET (hierarchy set). The
HU_SET constraint defines the start of a new set. Like H_SET, HU_SET is defined by
the design hierarchy. However, you can use the HU_SET constraint to assign a user-
defined name to the HU_SET.
The “HU_SET Constraint Linking and Separating Elements from H_SET Sets” figure
demonstrates how HU_SET constraints designate elements as set members, break
links between elements tagged with RLOC constraints in the hierarchy to separate
them from H_SET sets, and generate names as identifiers of these sets.

Libraries Guide, Release M1.5 12-107

Libraries Guide, Release M1.5

Design-top

B RLOC
= > H_SET = A/hset

C RLOC
= > H_SET = A/hset

D RLOC E HU_SET = bar

F RLOC H RLOC
= > H_SET = A/hset = > HU_SET = A/bar

G RLOC I RLOC
= > H_SET = A/hset = > HU_SET = A/bar

J RLOC K HU_SET = bar

L RLOC M RLOC
= > HU_SET = A/bar = > HU_SET = A/E/bar

X4298

Figure 12-9 HU_SET Constraint Linking and Separating Elements from H_SET
Sets
The user-defined HU_SET constraint on E separates its underlying design elements,
namely H, I, J, K, L, and M from the implicit H_SET=A/hset that contains primitive
members B, C, F, and G. The HU_SET set that is defined at E includes H, I, and L
(through the element J). The mapper hierarchically qualifies the name value “bar” on
element E to be A/bar, since A is the lowest common ancestor for all the elements of
the HU_SET set, and attaches it to the set member primitives H, I, and L. An HU_SET
constraint on K starts another set that includes M, which receives the HU_SET=A/E/
bar constraint after processing by the mapper. In the “HU_SET Constraint Linking
and Separating Elements from H_SET Sets” figure, the same name field is used for the
two HU_SET constraints, but because they are attached to symbols at different levels
of the hierarchy, they define two different sets.

12-108 Xilinx Development System

Attributes, Constraints, and Carry Logic

Design-top

B RLOC
= > H_SET = A/hset

C RLOC

= > H_SET = A/hset

D HU_SET = bar E HU_SET = bar

RLOC RLOC
F H
= > HU_SET = A/bar = > HU_SET = A/bar

RLOC I RLOC
G
= > HU_SET = A/bar = > HU_SET = A/bar

X4299

Figure 12-10 Linking Two HU_SET Sets

The “Linking Two HU_SET Sets” figure shows how HU_SET constraints link
elements in the same node together by naming them with the same identifier. Because
of the same name, “bar,” on two elements, D and E, the elements tagged with RLOC
constraints below D and E become part of the same HU_SET.

Set Modifiers
A modifier, as its name suggests, modifies the RLOC constraints associated with
design elements. Since it modifies the RLOC constraints of all the members of a set, it
must be applied in a way that propagates it to all the members of the set easily and
intuitively. For this reason, the RLOC modifiers of a set are placed at the start of that
set. The following set modifiers apply to RLOC constraints.
• RLOC
The RLOC constraint associated with a design element modifies the values of
other RLOC constraints below the element in the hierarchy of the set. Regardless
of the set type, RLOC row, column, and extension values on an element always
propagate down the hierarchy and are added at lower levels of the hierarchy to
RLOC constraints on elements in the same set.
• RLOC_ORIGIN (see the “RLOC_ORIGIN” section)
• RLOC_RANGE (see the “RLOC_RANGE” section)

Libraries Guide, Release M1.5 12-109

Libraries Guide, Release M1.5

Using RLOCs with Xilinx Macros

Xilinx-supplied flip-flop macros include an RLOC=R0C0 constraint on the underlying
primitive, which allows you to attach an RLOC to the macro symbol. This symbol
links the underlying primitive to the set that contains the macro symbol. Simply
attach an appropriate RLOC constraint to the instantiation of the actual Xilinx flip-
flop macro. The mapper adds the RLOC value that you specified to the underlying
primitive so that it has the desired value.

FDRE Macro

CE Q
FD
D
R
C
RLOC=R0C0

Inst 1
Propagate R1C1
RLOC = R1C1

RLOC = R0C0 (+R1C1)

FDRE

= > RLOC = R1C1

X4304

Figure 12-11 Typical Use of a Xilinx Macro

For example, in the “Typical Use of a Xilinx Macro” figure, the RLOC = R1C1
constraint is attached to the instantiation (Inst1) of the FDRE macro. It is added to the
R0C0 value of the RLOC constraint on the flip-flop within the macro to obtain the new
RLOC values.
If you do not put an RLOC constraint on the flip-flop macro symbol, the underlying
primitive symbol is the lone member of a set. the mapper removes RLOC constraints
from a primitive that is the only member of a set or from a macro that has no RLOC
objects below it.

LOC and RLOC Propagation through Design Flattening

NGDBuild continues to propagate LOC constraints down the design hierarchy. It
adds this constraint to appropriate objects that are not members of a set. While RLOC
constraint propagation is limited to sets, the LOC constraint is applied from its start
point all the way down the hierarchy.
When the design is flattened, the row and column numbers of an RLOC constraint on
an element are added to the row and column numbers of the RLOC constraints of the
set members below it in the hierarchy. This feature gives you the ability to modify
existing RLOC values in submodules and macros without changing the previously
assigned RLOC values on the primitive symbols.

12-110 Xilinx Development System

Attributes, Constraints, and Carry Logic

Specifying RLOC constraints to describe the spatial relationship of the set members to
themselves allows the members of the set to float anywhere on the die as a unit. You
can, however, fix the exact die location of the set members. The RLOC_ORIGIN
constraint allows you to change the RLOC values into absolute LOC constraints that
respect the structure of the set.
The design resolution program, NGDBuild, translates the RLOC_ORIGIN constraint
into LOC constraints. The row and column values of the RLOC_ORIGIN are added
individually to the members of the set after all RLOC modifications have been made
to their row and column values by addition through the hierarchy. The final values are
then turned into LOC constraints on individual primitives.

Fixing Members of a Set at Exact Die Locations

As noted in the previous section, you can fix the members of a set at exact die loca-
tions with the RLOC_ORIGIN constraint. You must use the RLOC_ORIGIN constraint
with sets that include BUFT symbols. However, for sets that do not include BUFT
symbols, you can limit the members of a set to a certain range on the die. In this case,
the set could “float” as a unit within the range until a final placement. Since every
member of the set must fit within the range, it is important that you specify a range
that defines an area large enough to respect the spatial structure of the set.
The syntax of this constraint is the following.
RLOC_RANGE=Rm1Cn1:Rm2Cn2
where the relative row numbers (m1, m2) and column numbers (n1, n2) can be non-
zero positive numbers, or the wildcard (*) character. This syntax allows for three kinds
of range specifications as follows.
• Rr1Cc1:Rr2Cc2 — A rectangular region enclosed by rows r1, r2, and columns c1,
c2
• R*Cc1:R*Cc2 — A region enclosed by the columns c1 and c2 (any row number)
• Rr1C*:Rr2C* — A region enclosed by the rows r1 and r2 (any column number)
For the second and third kinds of specifications with wildcards, applying the wild-
card character (*) differently on either side of the separator colon creates an error. For
example, specifying R*C1:R2C* is an error since the wildcard asterisk is applied to
rows on one side and to columns on the other side of the separator colon.

Specifying a Range or Area

To specify a range or area, use the following syntax, which is equivalent to placing an
RLOC_RANGE constraint on the schematic.
set_name RLOC_RANGE=Rm1Cn1:Rm2Cn2
The range identifies a rectangular area. You can substitute a wildcard (*) character for
either the row number or the column number of both corners of the range.
Note: The bounding rectangle applies to all elements in a relationally placed macro,
not just to the origin of the set. See the “Relationally Placed Macros (RPMs)” section
for more information.
The values of the RLOC_RANGE constraint are not simply added to the RLOC values
of the elements. In fact, the RLOC_RANGE constraint does not change the values of
the RLOC constraints on underlying elements. It is an additional constraint that is
attached automatically by the mapper to every member of a set. The RLOC_RANGE
constraint is attached to design elements in exactly the same way as the

Libraries Guide, Release M1.5 12-111

Libraries Guide, Release M1.5

RLOC_ORIGIN constraint. The values of the RLOC_RANGE constraint, like

RLOC_ORIGIN values, must be non-zero positive numbers since they directly corre-
spond to die locations.
If a particular RLOC set is constrained by an RLOC_ORIGIN or an RLOC_RANGE
constraint in the design netlist and is also constrained in the UCF file, the UCF file
constraint overrides the netlist constraint.

Toggling the Status of RLOC Constraints

Another important set modifier is the USE_RLOC constraint. It turns the RLOC
constraints on and off for a specific element or section of a set. RLOC can be either
TRUE or FALSE.
The application of the USE_RLOC constraint is strictly based on hierarchy. A
USE_RLOC constraint attached to an element applies to all its underlying elements
that are members of the same set. If it is attached to a symbol that defines the start of a
set, the constraint is applied to all the underlying member elements, which represent
the entire set. However, if it is applied to an element below the start of the set (for
example, E in the “Using the USE_RLOC Constraint to Control RLOC Application on
H_SET and HU_SET Sets” figure), only the members of the set (H and I) below the
specified element are affected.You can also attach the USE_RLOC constraint directly
to a primitive symbol so that it affects only that symbol.

Design-top

apply A USE_RLOC = FALSE

USE_RLOC
to H_SET

RLOC = R0C0
B
Parameters removed
= > H SET = A/hset

C RLOC = R1C0
Parameters removed
= > H SET = A/hset

HU_SET = bar propagate

D HU_SET = bar E RLOC = R0C1 USE_RLOC
USE_RLOC = FALSE and remove
set parameters
below

F RLOC = R0C0 H RLOC = R0C0

Parameters
= > HU_SET = A/bar = > HU_SET = A/bar removed

G RLOC = R1C0 I RLOC = R1C0

Parameters
= HU_SET = A/bar = > HU_SET = A/bar removed

X4302

Figure 12-12 Using the USE_RLOC Constraint to Control RLOC Application on

H_SET and HU_SET Sets
When the USE_RLOC=FALSE constraint is applied, the RLOC and set constraints are
removed from the affected symbols in the NCD file. This process is different than that
followed for the RLOC_ORIGIN constraint. For RLOC_ORIGIN, the mapper gener-
ates and outputs a LOC constraint in addition to all the set and RLOC constraints in
the PCF file. The mapper does not retain the original constraints in the presence of a

12-112 Xilinx Development System

Attributes, Constraints, and Carry Logic

USE_RLOC=FALSE constraint because these cannot be turned on again in later

programs.
The “Using the USE_RLOC Constraint to Control RLOC Application on H_SET and
HU_SET Sets” figure illustrates the use of the USE_RLOC constraint to mask an entire
set as well as portions of a set.
Applying the USE_RLOC constraint on U_SET sets is a special case because of the
lack of hierarchy in the U_SET set. Because the USE_RLOC constraint propagates
strictly in a hierarchical manner, the members of a U_SET set that are in different parts
of the design hierarchy must be tagged separately with USE_RLOC constraints; no
single USE_RLOC constraint is propagated to all the members of the set that lie in
different parts of the hierarchy. If you create a U_SET set through an instantiating
macro, you can attach the USE_RLOC constraint to the instantiating macro to allow it
to propagate hierarchically to all the members of the set. You can create this instanti-
ating macro by placing a U_SET constraint on a macro and letting the mapper propa-
gate that constraint to every symbol with an RLOC constraint below it in the
hierarchy.
The “Using the USE_RLOC Constraint to Control RLOC Application on U_SET Sets”
figure illustrates an example of the use of the USE_RLOC=FALSE constraint. The
USE_RLOC=FALSE on primitive E removes it from the U_SET set, and
USE_RLOC=FALSE on element F propagates to primitive G and removes it from the
U_SET set.

Design-top

A B

U_SET = bar
U_SET = bar F
C RLOC = R0C0 USE_RLOC = FALSE propagate USE_RLOC
and remove set parameters
below

U_SET = bar
D RLOC = R1C0
U_SET = bar
G Parameters
RLOC = R3C0 removed

U_SET = bar Parameters

E RLOC = R2C0 removed
USE_RLOC = FALSE

X4303

Figure 12-13 Using the USE_RLOC Constraint to Control RLOC Application on

U_SET Sets
While propagating the USE_RLOC constraint, the mapper ignores underlying
USE_RLOC constraints if it encounters elements higher in the hierarchy that already
have USE_RLOC constraints. For example, if the mapper encounters an underlying
element with a USE_RLOC=TRUE constraint during the propagation of a
USE_RLOC=FALSE constraint, it ignores the newly encountered TRUE constraint.

Libraries Guide, Release M1.5 12-113

Libraries Guide, Release M1.5

Choosing an RLOC Origin when Using Hierarchy Sets

To specify a single origin for an RLOC set, use the following syntax, which is equiva-
lent to placing an RLOC_ORIGIN attribute on the schematic.
set_name RLOC_ORIGIN=RmCn
The set_name can be the name of any type of RLOC set — a U_SET, an HU_SET, or a
system-generated H_SET.
The origin itself is expressed as a row number and a column number representing the
location of the elements at RLOC=R0C0.
When the RLOC_ORIGIN constraint is used in conjunction with an implicit H_SET
(hierarchy set), it must be placed on the element that is the start of the H_SET set, that
is, on the lowest common ancestor of all the members of the set.
If you apply an RLOC_ORIGIN constraint to an HU_SET constraint, place it on the
element at the start of the HU_SET set, that is, on an element with the HU_SET
constraint. However, since there could be several elements linked together with the
HU_SET constraint at the same node, the RLOC_ORIGIN constraint can be applied to
only one of these elements to prevent more than one RLOC_ORIGIN constraint from
being applied to the HU_SET set.
Similarly, when used with a U_SET constraint, the RLOC_ORIGIN constraint can be
placed on only one element with the U_SET constraint. If you attach the
RLOC_ORIGIN constraint to an element that has only an RLOC constraint, the
membership of that element in any set is removed, and the element is considered the
start of a new H_SET set with the specified RLOC_ORIGIN constraint attached to the
newly created set.

12-114 Xilinx Development System

Attributes, Constraints, and Carry Logic

Design-top

A RLOC_ORIGIN = R2C3
Mapper adds RLOC_ORIGIN
(R2C3) below to get final
LOC constraint

RLOC = R0C0 (+R2C3)

B
= >LOC = CLB_R2C3

RLOC = R1C0 (+R2C3)

C = >LOC = CLB_R3C3

RLOC = R2C0 (+R2C3)

D = >LOC = CLB_R4C3

E RLOC = R0C1
Mapper adds ROC1 and
RLOC_ORIGIN
(R2C3) below to get final
LOC constraint

RLOC = R0C0 (+R0C1 + R2C3)

F
= >LOC = CLB_R2C4

RLOC = R1C0 (+R0C1 + R2C3)

G
= >LOC = CLB_R3C4

X6950

Figure 12-14 Using an RLOC_ORIGIN Constraint to Modify an H_SET Set

In the “Using an RLOC_ORIGIN Constraint to Modify an H_SET Set” figure, the
elements B, C, D, F, and G are members of an H_SET set with the name A/hset. This
figure is the same as the “Adding RLOC Values Down the Hierarchy” figure except
for the presence of an RLOC_ORIGIN constraint at the start of the H_SET set (at A).
The RLOC_ORIGIN values are added to the resultant RLOC values at each of the
member elements to obtain the values that are then converted by the mapper to LOC
constraints. For example, the RLOC value of F, given by adding the RLOC value at E
(R0C1) and that at F (R0C0), is added to the RLOC_ORIGIN value (R2C3) to obtain
the value of (R2C4), which is then converted to a LOC constraint, LOC = CLB_R2C4.

Libraries Guide, Release M1.5 12-115

Libraries Guide, Release M1.5

Design-top

A RLOC_ORIGIN = R1C2
add RLOC_ORIGIN
to H_SET

RLOC = R0C0 (+R1C2)

B = > H_SET = A/hset
= > LOC = CLB_R1C2

C RLOC = R1C0 (+R1C2)

= > H_SET = A/hset
= > LOC = CLB_R2C2

HU_SET = bar add RLOC_ORIGIN

and RLOC below
D HU_SET = bar E RLOC_ORIGIN = R3C3
add RLOC_ORIGIN RLOC = R0C1
to H_SET

F RLOC = R0C0 (+R3C3) H RLOC = R0C0 (+R0C1 + R3C3)

= > HU_SET = A/bar = > HU_SET = A/bar
= > LOC = CLB_R3C3 = > LOC = CLB_R3C4

G RLOC = R1C0 (+R3C3) I RLOC = R1C0 (+R0C1 + R3C3)

= > HU_SET = A/bar = > HU_SET = A/bar
= > LOC = CLB_R4C3 = > LOC = CLB_R4C4

X4301

Figure 12-15 Using an RLOC_ORIGIN to Modify H_SET and HU_SET Sets

The “Using an RLOC_ORIGIN to Modify H_SET and HU_SET Sets” figure shows an
example of an RLOC_ORIGIN constraint modifying an HU_SET constraint. The start
of the HU_SET A/bar is given by element D or E. The RLOC_ORIGIN attached to E,
therefore, applies to this HU_SET set. On the other hand, the RLOC_ORIGIN at A,
which is the start of the H_SET set A/hset, applies to elements B and C, which are
members of the H_SET set.

12-116 Xilinx Development System

Attributes, Constraints, and Carry Logic

Timing Constraints
This section describes the syntax for using timing constraints in a UCF file. Timing
constraints allow you to specify the maximum allowable delay or skew on any given
set of paths or nets in your design.
There are three steps for applying timing specifications to a design.
1. Add TNM attributes to symbols on your schematic to group them into sets. This
step is not necessary if you are using only predefined sets. This step can be
performed in the schematic or in a constraints file. See the “Timing Specifications”
section of the “Using Timing Constraints” chapter in the Development Systems
Reference Guide for instructions.
2. Add a TIMEGRP symbol and add attributes to the symbol. These attributes can
combine the sets defined in step 1 or by pattern matching into additional, more
complex, sets, or they can match patterns. This step is optional. You can define
these groups on the schematic or in the constraints file.
3. Add a TIMESPEC symbol and add attributes to the symbol, defining the timing
requirements for the sets defined in steps 1 and 2. You can define the timing
requirements on the schematic or in the constraints file.

TNM Attributes
Timing name (TNM) attributes can be used to identify the elements that make up a
group and give them a name that can later be used in an actual timing specification.
The value of the attribute can take several forms and there are several attachment
mechanisms by which the attribute can identify the elements that make up a group.
TNM attributes can be attached to a net, an element pin, a primitive, or a macro.

TNMs on Nets
The TNM attribute can be placed on any net in the design. It is used to indicate that
the TNM value should be attached to all valid elements fed by all paths that fan
forward from the tagged net. Forward tracing stops at any flip-flop, latch, RAM or
pad. TNMs do not propagate across IBUFs if they are attached to the input pad net.
(Use TNM_NET if you want to trace forward from an input pad net.)

TNMs on Macro or Primitive Pins

The TNM attribute can be placed on any macro or component pin in the design if the
design entry package allows placement of attributes on macro or primitive pins. It is
used to indicate that the TNM value should be attached to all valid elements fed by all
paths that fan forward from the tagged pin. Forward tracing stops at any flip-flop,
latch, RAM or pad.

TNMs on Primitives
Attaching a TNM attribute directly to a primitive defines that primitive as part of the
named group.

TNMs on Macro Symbols

A TNM attribute attached to a macro indicates that all elements inside the macro (at
all levels of hierarchy below the tagged macro) are part of the named group.

Libraries Guide, Release M1.5 12-117

Libraries Guide, Release M1.5

TIMEGRP Constraints
It is sometimes convenient to use existing TNMs to create new groups or to define a
group based on the output nets that the group sources. A set of grouping mechanisms
has been created to do this. The Timing Group primitive (TIMEGRP) serves as the
host for these attributes. Because they contain no keyword, the attributes make no
sense when used alone.
You can either attach a TIMEGRP constraint to the TIMEGRP schematic symbol or
specify it with the TIMEGRP keyword in the UCF file. In the UCF file, the statement
syntax is as follows.
TIMEGRP timegrp_name=timegrp_parameter
where timegrp_parameter is identical to the text you would attach to the TIMEGRP
schematic symbol.
You can create groups using the following four methods.
1. Combine multiple groups into one; use the following syntax.
new_group=group1: group2:... groupn
where new_group is the group being defined; group1, group2, and so forth can be a
valid TNM-defined group, predefined group (FFS, PADS, RAMS, LATCHES), or
group defined with another TIMEGRP attribute. You can create a time group
attribute that references another TIMEGRP attribute that appears after the initial
definition. Do not use reserved words such as FFS, PADS, RISING, FALLING, or
EXCEPT as group names.
Example

Schematic NEWGRP=OLD1:OLD2
UCF TIMEGRP NEWGRP=OLD1:OLD2 ;
2. Create groups by exclusion; use the following syntax.
new_group=group1:EXCEPT group2
where new_group is the group being defined; group1 and group2 can be a valid
TNM-defined group, predefined group (FFS, PADS, RAMS, LATCHES), or group
defined with another TIMEGRP attribute. Do not use reserved words such as FFS,
PADS, RISING, FALLING, or EXCEPT as group names.
Example

Schematic FFGRP2=FFS:EXCEPT FFGRP1

UCF TIMEGRP FFGRP2=FFS:EXCEPT FFGRP1 ;

You can also specify multiple groups to include or exclude when creating the new
group.
new_group=group1:group2:EXCEPT group3:... groupn
where group1, group2, group3, and groupn can be a valid TNM-defined group,
predefined group (FFS, PADS, RAMS, LATCHES), or group defined with another
TIMEGRP attribute. Do not use reserved words such as FFS, PADS, RISING,
FALLING, or EXCEPT as group names.

12-118 Xilinx Development System

Attributes, Constraints, and Carry Logic

3. Define groups of flip-flops triggered by rising and falling clock edges; use the
following syntax.
new_group={RISING | FALLING group | ffs}
where group must be a group that includes only flip-flops. FFS is a predefined
group.
Example
Defining a group of flip-flops that switch on the falling edge of the clock.
Schematic newfall=FALLING ffs
UCF TIMEGRP newfall=FALLING ffs ;

4. Use wildcard characters to define groups of symbols whose associated signal

names match a specific pattern; use this syntax.
group=predefined_group pattern
where predefined_group can be one of the following predefined groups: FFS, PADS,
RAMS, LATCHES.
pattern is the string characterizing the output net names of the blocks that you
want to include in the new group. It can be any string of characters used with one
or more wildcard characters, which can be either of the following.
An asterisk (*) matches any string of zero or more characters.
A question mark (?) matches one character.
Example
Group created by pattern matching.
Schematic newfall=FALLING ffs(A*)
UCF TIMEGRP newfall=FALLING ffs(A*) ;

TIMESPEC Constraints
After you have defined appropriate groups by attaching TNM attributes to symbols
and, optionally, by combining these groups using the TIMEGRP symbol, the next step
is to add the timing specifications to the constraints file with the TSidentifier
constraint. You can define these timing requirements by the following means.
The actual timing specifications take the form of attributes that are attached to a
timing specification (TIMESPEC) primitive. The TIMESPEC primitive acts as a place
to attach attributes and keeps the attributes together. More than one TIMESPEC prim-
itive can be used in a design at any level of the hierarchy.
The sources and destinations can be any synchronous point in the design. The timing
allowance specified is used explicitly by the timing analysis tools. There is no hidden
accounting for any clock inversions between registers clocked by the same clock, etc.
If paths are not specified, they are ignored for the purposes of timing analysis. The
forms described here require the definition of a source and a destination for a specifi-
cation.

Libraries Guide, Release M1.5 12-119

Libraries Guide, Release M1.5

Basic Form
Syntax for defining a maximum allowable delay is as follows.
TSidentifier=FROM:source_group:TO:dest_group allowable_delay[units]
where
identifier is an ASCII string made up of the characters A...Z, a...z, 0...9.
source_group and dest_group are user-defined or predefined groups.
allowable_delay is the timing requirement.
units is an optional field to indicate the units for the allowable delay. Default units are
nanoseconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or
kHz to indicate the intended units.
In a schematic the timespec attribute is attached to the TIMESPEC symbol.

Defining Intermediate Points on a Path

It is sometimes convenient to define intermediate points on a path to which a specifi-
cation applies. This defines the maximum allowable delay and has the following
syntax.
TSidentifier=FROM:source_group THRU thru_point[THRU thru_point1...
thru_pointn]:TO:dest_group allowable_delay[units]
where
identifier is an ASCII string made up of the characters A...Z, a...z, 0...9.
source_group and dest_group are user-defined or predefined groups.
thru_point is an intermediate point used to qualify the path, defined using a TPTHRU
attribute.
allowable_delay is the timing requirement.
units is an optional field to indicate the units for the allowable delay. Default units are
nanoseconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or
kHz to indicate the intended units.

Worst Case Allowable Delay (MAXDELAY)

Syntax for maximum delay is as follows.
TSidentifier=MAXDELAY FROM:source_group:TO:dest_group allowable_delay[units]
Syntax for maximum delay using a through point is as follows.
TSidentifier=MAXDELAY FROM:source_group THRU thru_point [THRU thru_point1...
thru_pointn]:TO:dest_group allowable_delay[units]
where
identifier is an ASCII string made up of the characters A...Z, a...z, 0...9.
source_group and dest_group are user-defined or predefined groups.
thru_point is an intermediate point used to qualify the path, defined using a TPTHRU
attribute.
allowable_delay is the timing requirement.
units is an optional field to indicate the units for the allowable delay.

12-120 Xilinx Development System

Attributes, Constraints, and Carry Logic

Linked Specifications
This allows you to link the timing number used in one specification to another specifi-
cation in terms of fractions or multiples.
Note: Circular links are not allowed.
Syntax is as follows.
TSidentifier=FROM:source_group:TO:dest_group another_Tsid [/ | *]number
where
identifier is an ASCII string made up of the characters A...Z, a...z, 0...9.
source_group and dest_group are user-defined or predefined groups.
another_Tsid is a the name of another timespec.
number is a floating point number.

Defining Priority for Equivalent Level Specifications

A conflict between two specifications at the same level of priority can be resolved by
defining their priority. You can do this by adding the following text to each of the
conflicting specifications.
normal_timespec_syntax PRIORITY integer
where
normal_timespec_syntax is the timing specification.
integer represents the priority. The smaller the number, the higher the priority.

Ignoring Paths
Paths exercising a certain net can be ignored because from a timing specification point
of view, all paths through a net, instance, or instance pin may not be important.
Syntax is as follows.
TIG=TSidentifier
where identifier is the timing specification name of the specific timespec for which any
paths through the tagged object should be ignored. The attribute can be attached to a
net, macro pin or primitive pin. Paths that fan forward from the attribute’s point of
application are treated as if they don’t exist from the viewpoint of timing analysis
against the timing specification.
Examples
The following attribute would be attached to a net to inform the timing analysis tools
that it should ignore paths through the net for specification TS43.
TIG=TS43
The following attribute would be created in a UCF file to inform the timing analysis
tools that it should ignore paths through the net $1I567/sometimes_slow for specifica-
tion TS_fast and TS_really_fast.
NET $1I567/sometimes_slow TIG=TS_fast , TS_really_fast;

Libraries Guide, Release M1.5 12-121

Libraries Guide, Release M1.5

Ignoring Paths Through Primitives

The tracing rules for how PAR’s timing analysis handles the traversal of primitives are
the same as those used for user driven timing analysis. If a user wishes to override the
default behavior for an element, the element can be tagged with an override attribute
in the PCF file. For more information, see the “Ignoring Selected Paths (TIG)” section
of the “Using Timing Constraints” chapter in the Development System Reference Guide.

Defining a Clock Period

A clock period specification is used to define to the timing analysis tools the allowable
time for paths between elements clocked by the flagged clock signal.
Note: The definition of a clock period is different from a FROM:TO style specification,
because the timing analysis tools will automatically take into account any inversions
of the clock signal at register clock pins.
There are two methods for specifying clock periods.
1. The quick, convenient way to define the clock period for registers attached to a
particular clock net is to attach the following parameter directly to a net in the
path that drives the register clock pin(s).
PERIOD=period[units] [{HIGH | LOW} [high_or_low_time [hi_lo_units]]]
where
period is the required clock period.
units is an optional field to indicate the units for the clock period. The default
units are nanoseconds, but the timing number can be followed by ps, ns, us, or ms
to indicate the intended units.
HIGH or LOW can be optionally specified to indicate whether the first pulse is to
be High or Low.
high_or_low_time is the optional High or Low time depending on the preceding
keyword. If an actual time is specified it must be less than the period. If no High
or Low time is specified the default duty cycle is 50%.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default
is nanoseconds (ns), but the High or Low time number can be followed by ps, us,
ms, or % if the High or Low time is an actual time measurement.
The PERIOD constraint is forward-traced in exactly the same fashion as a TNM
would be and attaches itself to all of the flip-flops that the forward tracing
reaches. There are no rules about not tracing through certain elements. If you
need a more complex form of tracing behavior, for example, where gated clocks
are used in the design, you must place the PERIOD on a particular net, or use the
preferred method as described in the following paragraphs.
2. The preferred method for defining a clock period allows more complex derivative
relationships to be defined as well as a simple clock period. The following
attribute is attached to a TIMESPEC symbol in conjunction with a TNM attribute
attached to the relevant clock net.
TSidentifier=PERIOD TNM_reference period[units][{HIGH | LOW} [high_or_low_time
[hi_lo_units]]]
where
identifier is a reference identifier that has a unique name.

12-122 Xilinx Development System

Attributes, Constraints, and Carry Logic

TNM_reference is the identifier name that is attached to a clock net (or a net in the
clock path) using a TNM attribute.
period is the required clock period.
units is an optional field to indicate the units for the clock period. Default units are
nanoseconds, but the timing number can be followed by ps, ns, us, or ms to indi-
cate the intended units.
HIGH or LOW can be optionally specified to indicate whether the first pulse is to
be High or Low.
high_or_low_time is the optional High or Low time depending on the preceding
keyword. If an actual time is specified it must be less than the period. If no High
or Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default
is ns, but the High or Low time number can be followed by ps, ns, us, ms, or % if
the High or Low time is an actual time measurement.
Example
Clock net sys_clk has the attribute tnm=master_clk attached to it and the
following attribute is attached to a TIMESPEC primitive.
TS_master=PERIOD master_clk 50 HIGH 30

Specifying Derived Clocks

The preferred method of defining a clock period uses an identifier, allowing another
clock period specification to reference it. To define the relationship in the case of a
derived clock, use the following syntax.
TSidentifier=PERIOD TNM_reference another_PERIOD_identifier [/ | *] number
[{HIGH | LOW} [high_or_low_time [hi_lo_units]]]
where
identifier is a reference identifier that has a unique name.
TNM_reference is the identifier name that is attached to a clock net or a net in the clock
path using a TNM attribute.
another_PERIOD_identifier is a the name of the identifier used on another period spec-
ification.
number is a floating point number.
HIGH or LOW can be optionally specified to indicate whether the first pulse is to be
High or Low.
high_or_low_time is the optional High or Low time. This must be less than the period,
depending on the preceding keyword. The default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.
Example
Clock net sub_clk has the attribute tnm=slave_clk attached to it and the following
attribute is attached to a TIMESPEC primitive.
ts_slave1=PERIOD slave_clk master_clk * 4

Libraries Guide, Release M1.5 12-123

Libraries Guide, Release M1.5

Controlling Net Skew

You can control the maximum allowable skew on a net by attaching the MAXSKEW
attribute directly to the net. Syntax is as follows.
MAXSKEW=allowable_skew [units]
where
allowable_skew is the timing requirement.
units is an optional field to indicate the units for the allowable delay. Default units are
nanoseconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or
kHz to indicate the intended units.

Controlling Net Delay

You can control the maximum allowable delay on a net by attaching the MAXDELAY
attribute directly to the net. Syntax is as follows.
MAXDELAY=allowable_delay [units]
where
allowable_delay is the timing requirement.
units is an optional field to indicate the units for the allowable delay. Default units are
nanoseconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or
kHz to indicate the intended units.

12-124 Xilinx Development System

Attributes, Constraints, and Carry Logic

Physical Constraints
Note: The information in this section applies only to FPGA families.
When a design is mapped, the logical constraints found in the netlist and the UCF file
are translated into physical constraints; that is, constraints that apply to a specific
architecture. These constraints are found in a mapper-generated file called the Phys-
ical Constraints File (PCF). The file contains two sections, the schematic section and
the user section. The schematic section contains the physical constraints based on the
logical constraints found in the netlist and the UCF file. The user section can be used
to add any physical constraints.

PCF File Syntax

Syntax
NET “net_name” OUTREG;
where net_name is the name of the net that connects the IOB to the OUTREG instance.

PATH
Description
Assigns a path specification to a path.

Syntax
PATH “path_name”=path_spec;
where
path_spec is one of the following,
• FROM group_item THRU group_item1... group_itemn
• FROM group_item THRU group_item1... group_itemn TO group_item
• THRU group_item1... group_itemn TO group_item.
group_item is one of the following,
• PIN “pin_name”
• NET “net_name”
• COMP “comp_name”
• MACRO “macro_name”
• TIMEGRP “group_name”
• BEL “instance_name”
BEL instance_name is the instance name of a basic element. Basic elements are the
building blocks that make up a CLB— function generators, flip-flops, carry logic,
and RAMs.

12-130 Xilinx Development System

Attributes, Constraints, and Carry Logic

PENALIZE TILDE
Description
Penalizes those delays that are reported as only approximate (signified with a tilde (~)
in delay reports) by a user-specified percentage. When the penalize tilde constraint is
applied to an approximate delay, the delay will be penalized by the designated
percentage in subsequent timing checks. Default for percent value is zero.

Syntax
PENALIZE TILDE=percent

PERIOD
Description
Assigns a timing period to a timing specification.

Syntax
TSidentifer=PERIOD period_item period_value [{LOW | HIGH}{time [units]| percent}];
period_item PERIOD=period_value [{LOW | HIGH}{time [units]| percent}];
where
period_item is one of the following,
• NET “net_name”
• TIMEGRP “group_name”
• ALLCLOCKNETS
period_value is one of the following,
• time [units]
• units defaults to nanoseconds, but the timing number can be followed by ps,
ns, us, or ms (picoseconds, nanoseconds, microseconds, or milliseconds) to
indicate the intended units.
• TS identifier [{/ | *} real_number]
HIGH or LOW can be optionally specified to indicate whether the first pulse is to be
High or Low.
high_or_low_time is the optional High or Low time, depending on the preceding
keyword. If an actual time is specified, it must be less than the period. If no High or
Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.

Libraries Guide, Release M1.5 12-131

Libraries Guide, Release M1.5

PIN
Description
Identifies a specific pin.

Syntax
PIN “pin_name”=pin_spec;
where
pin_spec is one of the following,
• NET "net_name" BEL "instance_name"
• NET "net_name" COMP "comp_name"
• COMP "comp_name" NET "net_name"
• NET "net_name" MACRO "macro_name"
• MACRO "macro_name" NET "net_name"
• BEL "instance_name" NET "net_name"
BEL instance_name is the instance name of a basic element. Basic elements are the
building blocks that make up a CLB— function generators, flip-flops, carry logic, and
RAMs.

PRIORITIZE
Description
Assigns a weighted importance to a net or bus. Values range from 0 through 100, with
100 being the highest priority and 0 the lowest. The default is 3. Any net with a
priority of 3 is not considered critical; no constraint will be generated. The prioritize
constraint is used by PAR, which assigns longlines by net priority and routes higher-
priority nets before routing lower-priority nets. The prioritize constraint is also used
by BITGEN to determine which nets not to use for tiedown. A net with a priority
greater than 3 will only be used for tiedown as a last resort.

Syntax
NET "net_name" PRIORITIZE=integer;

PROHIBIT
Description
Disallows the use of a site or multiple sites within PAR, EPIC, and the CPLD fitter.

Syntax

Single or multiple single locations

PROHIBIT= site_group;
PROHIBIT= site_group1... ,site_groupn;

12-132 Xilinx Development System

Attributes, Constraints, and Carry Logic

Range of locations
PROHIBIT= site_group : site_group;
where
site_group is one of the following,
• SITE "site_name"
• SITEGRP "site_group_name"
site_name must be a valid site for the targeted device. (For example, CLB_R1C1.FFX is
not a valid site for the XC4000X or SpartanXL.)
Note: CPLDs do not support the "Range of locations" form of PROHIBIT.

SITEGRP
Description
Identifies a group of sites.

Syntax
SITEGRP site_group_name=site_group1... site_groupn ; [EXCEPT site_group];
where
site_group is one of the following,
• SITE "site_name"
• SITEGRP "site_group_name"
site_name must be a valid site for the targeted device. (For example, CLB_R1C1.FFX is
not a valid site for the XC4000X or SpartanXL.)

TEMPERATURE
Description
Allows the specification of the operating temperature.
Note: Each architecture has its own specific range of valid operating temperatures. If
the entered temperature does not fall within the supported range, the constraint is
ignored and an architecture-specific default value is used instead.

Syntax
TEMPERATURE=value[C |F| K]
where
value is an integer or a real number specifying the temperature.
C, K, and F are the temperature units. F is degrees Fahrenheit, K is degrees Kelvin,
and C is degrees Celsius, the default.

Libraries Guide, Release M1.5 12-133

Libraries Guide, Release M1.5

TIMEGRP (Timing Group)

Description
Defines objects that are to be treated as a group for timing considerations.You can
refer to a group of flip-flops, input latches, pads, or RAMs by using the corresponding
keywords.

Keyword Description
FFS CLB or IOB flip-flops only; not flip-flops built from function genera-
tors
LATCHES CLB or IOB latches only; not latches built from function generators
PADS Input/output pads
RAMS For architectures with RAMS

Syntax
TIMEGRP "group_name"=[qualifier1] group_spec1... [qualifiern] group_specn [EXCEPT
group_spec1... group_specn];
where
qualifier is RISING or FALLING.
group_spec is one of the following,
• PIN "pin_name"
• NET "net_name"
• BEL "instance_name"
• COMP "comp_name"
• MACRO "macro_name"
• TIMEGRP "group_name"
• FFS ["pattern"]
• LATCHES ["pattern"]
• RAMS [“pattern”]
• PADS [“pattern”]
BEL instance_name is the instance name of a basic element. Basic elements are the
building blocks that make up a CLB— function generators, flip-flops, carry logic, and
RAMs.
This example shows you one way to use the TIMEGRP attribute. If you have some
outputs that can be slower than others, you can create timespecs similar to those
shown below for output signals obc_data(7:0) and ingr_irq_n.
First create the Timegroups.
TIMEGRP slow_outs=PADS(obc_data* : ingr_irq_n) ;
TIMEGRP fast_outs=PADS : EXCEPT : slow_outs ;

12-134 Xilinx Development System

Attributes, Constraints, and Carry Logic

Then apply a timing spec to the Timegroups.

TIMESPEC TS08=FROM : FFS : TO : fast_outs : 22 ;
TIMESPEC TS09=FROM : FFS : TO : slow_outs : 75 ;

TIG (Timing Ignore)

Description
Identifies paths that can be ignored for timing purposes.

Syntax
ignore_item TIG [=TSidentifier1... TSidentifiern];
where
ignore_item is one of the following,
• PIN “pin_name”
• NET “net_name”
• COMP “comp_name”
• MACRO “macro_name”
• PATH “path_name”
• BEL “instance_name”
• FROM group_item THRU group_item1... group_itemn
• FROM group_item THRU group_item1... group_itemnTO group_item
• THRU group_item... group_itemn TO group_item }
BEL instance_name is the instance name of a basic element. Basic elements are the
building blocks that make up a CLB— function generators, flip-flops, carry logic, and
RAMs.
For a detailed description of TIG, see the “Timing Specifications” section of the
“Using Timing Constraints” chapter in the Development System Reference Guide.

TSidentifier
Description
Assigns a timing period or frequency to a timing specification.

Syntax

Period
TSidentifer=PERIOD period_item period_value [{LOW | HIGH}{time [units]| percent}];
period_item PERIOD=period_value [{LOW | HIGH}{time [units]| percent}];

Libraries Guide, Release M1.5 12-135

Libraries Guide, Release M1.5

where
period_item is one of the following,
• NET “net_name”
• TIMEGRP “group_name”
• ALLCLOCKNETS
period_value is one of the following,
• time [units]
• units defaults to nanoseconds, but the timing number can be followed by ps,
ns, us, or ms (picoseconds, nanoseconds, microseconds, or milliseconds) to
indicate the intended units.
• TS identifier [{/ | *} real_number]
HIGH or LOW can be optionally specified to indicate whether the first pulse is to be
High or Low.
high_or_low_time is the optional High or Low time, depending on the preceding
keyword. If an actual time is specified, it must be less than the period. If no High or
Low time is specified, the default duty cycle is 50 percent.
hi_lo_units is an optional field to indicate the units for the duty cycle. The default is
nanoseconds (ns), but the High or Low time number can be followed by ps, us, ms, or
% if the High or Low time is an actual time measurement.

Frequency
TSidentifier=FREQUENCY frequency_item frequency_value ;
frequency_item FREQUENCY=frequency_value;
where
frequency_item is one of the following,
• NET “net_name”
• TIMEGRP “group_name”
• ALLCLOCKNETS
frequency_value is one of the following,
• frequency_number units
• units can be GHz, MHz, or kHz (gigahertz, megahertz, or kilohertz)
• TSidentifier [{/ |*} real_number]

VOLTAGE
Description
Allows the specification of the operating voltage. This provides a means of prorating
delay characteristics based on the specified voltage.
Note: Each architecture has its own specific range of supported voltages. If the
entered voltage does not fall within the supported range, the constraint is ignored and
an architecture-specific default value is used instead.

12-136 Xilinx Development System

Attributes, Constraints, and Carry Logic

Syntax
VOLTAGE=value[V]
where
value is an integer or real number specifying the voltage.
V specifies volts, the default voltage unit.

Libraries Guide, Release M1.5 12-137

Libraries Guide, Release M1.5

Relationally Placed Macros (RPMs)

The Xilinx libraries contain three types of elements.
• Primitives are basic logical elements such as AND2 and OR2 gates
• Soft macros are schematics made by combining primitives and sometimes other
soft macros
• Relationally placed macros (RPMs) are soft macros that contain relative location
constraint (RLOC) information, carry logic symbols, and FMAP/HMAP symbols,
where appropriate
The last item mentioned above, RPMs, applies only to FPGA families.
The relationally placed macro (RPM) library uses RLOC constraints to define the
order and structure of the underlying design primitives. Because these macros are
built upon standard schematic parts, they do not have to be translated before simula-
tion. The components that are implemented as RPMs are listed in the “Relationally
Placed Macros” section of the “Selection Guide” chapter.
Designs created with RPMs can be functionally simulated. RPMs can, but need not,
include all the following elements.
• FMAPs, HMAPs, and CLB-grouping attributes to control mapping. FMAPs and
HMAPs have pin-lock attributes, which allow better control over routing. FMAPs
and HMAPs are described in the “Mapping Constraint Examples” section.
• Relative location (RLOC) constraints to provide placement structure. They allow
positioning of elements relative to each other. They are discussed in the “Benefits
and Limitations of RLOC Constraints” section.
• Carry logic primitive symbols. Carry logic is discussed in the “Carry Logic in
XC4000 and Spartans” section.
The RPM library offers the functionality and precision of the hard macro library with
added flexibility. You can optimize RPMs and merge other logic within them. The
elements in the RPM library allow you to access carry logic easily and to control
mapping and block placement. Because RPMs are a superset of ordinary macros, you
can design them in the normal design entry environment. They can include any prim-
itive logic. The macro logic is fully visible to you and can be easily back-annotated
with timing information.

12-138 Xilinx Development System

Attributes, Constraints, and Carry Logic

Carry Logic in XC4000 and Spartans

In the XC4000 and Spartans, the CLB contains a feature called dedicated carry logic.
This carry logic is independent of the function generators, although it shares some of
the same input pins. Dedicated interconnect propagates carry signals through a
column of CLBs.
This section describes the use of carry logic in XC4000 and Spartan series CLBs and
lists all the carry logic configuration mnemonics available.

Carry Logic Overview

The carry chain in XC4000E devices can run either up or down. At the top and bottom
of columns where there are no CLBs above and below, the carry is propagated to the
right as shown in the figure below.

CLB CLB CLB CLB

X8023

Figure 12-16 Available XC4000E Carry Propagation Paths

In XC4000X, Spartan, and SpartanXL devices the carry chain travels upward only.
Standard interconnect can be used to route a signal in the downward direction. See
the figure below.

CLB CLB CLB CLB

X8024

Figure 12-17 Available XC4000X, Spartan, and SpartanXL Carry Propagation

Paths (dotted lines use general interconnect)

Libraries Guide, Release M1.5 12-139

Libraries Guide, Release M1.5

The CY4_43 carry mode component (Force-G4) forces the signal on the G4 pin to pass
through to the COUT pin. This component is available only for XC4000X and Spar-
tanXL devices.
Carry logic in each CLB can implement approximately 40 different functions, which
you can use to build faster and more efficient adders, subtracters, counters, compara-
tors, and so forth. The “XC4000 and Spartans Carry Logic” figure shows the carry
logic in an XC4000 or Spartan series CLB.

G4 COUT
M G Carry
Logic
G3
G4 G4 COUT1
G3 G1
G
G2 G2 F3
G1 COUT0

G1
M
F Carry
Logic
F4 F4 F3 COUT0
F3 F3 F2
F
F2 F2 F1
F1 F1 CIN

DOWN

M
M Configuration Memory Bit
CIN
UP
X6969

Figure 12-18 XC4000 and Spartans Carry Logic

Carry Logic Primitives and Symbols

The schematic capture libraries that Xilinx supports contain one generic carry logic
primitive and several specific carry mode primitive symbols. The generic carry logic
primitive represents the complete carry logic in a single CLB and is shown in the
“Representative Carry Logic Symbol” figure.

XXX- X- XX

A label showing the

specific carry mode
appears on the symbol X6962

Figure 12-19 Representative Carry Logic Symbol

The carry mode primitive symbols represent unique carry modes, such as ADD-FG-
CI. The “Carry Modes” table lists the carry mode names and symbols.
To specify the particular mode that you wish, connect a carry mode symbol to the C0-
C7 mode pins of the carry logic symbol. It is the pair of symbols that defines the
specific kind of carry logic desired.

12-140 Xilinx Development System

Attributes, Constraints, and Carry Logic

A carry logic symbol requires you to place either a LOC or an RLOC constraint on it. If
a LOC constraint is used, it must be a single LOC= constraint; it cannot be an area or
prohibit LOC constraint or use wildcards in its syntax.

Table 12-13 Carry Modes

Carry Mode Name Symbol

ADD-F-CI cy4_01
ADD-FG-CI cy4_02
ADD-G-F1 cy4_03
ADD-G-CI cy4_04
ADD-G-F3- cy4_05
ADDSUB-F-CI cy4_12
ADDSUB-FG-CI cy4_13
ADDSUB-G-CI cy4_15
ADDSUB-G-F1 cy4_14
ADDSUB-G-F3- cy4_16
FORCE-0 cy4_37
FORCE-1 cy4_38
FORCE-CI cy4_40
FORCE-F1 cy4_39
FORCE-F3- cy4_41
FORCE-G4 cy4_43*
EXAMINE-CI cy4_42
DEC-F-CI cy4_24
DEC-FG-0 cy4_26
DEC-FG-CI cy4_25
DEC-G-0 cy4_27
DEC-G-CI cy4_29
DEC-G-F1 cy4_28
DEC-G-F3- cy4_30
INC-F-CI cy4_17
INC-FG-1 cy4_19
INC-FG-CI cy4_18
INC-G-1 cy4_20
INC-G-CI cy4_22
INC-G-F1 cy4_21
INC-G-F3- cy4_23
SUB-F-CI cy4_06
SUB-FG-CI cy4_07
SUB-G-1 cy4_08

Libraries Guide, Release M1.5 12-141

Libraries Guide, Release M1.5

Table 12-13 Carry Modes

Carry Mode Name Symbol

SUB-G-CI cy4_09
SUB-G-F1 cy4_10
SUB-G-F3- cy4_11
INCDEC-F-CI cy4_31
INCDEC-FG-1 cy4_33
INCDEC-FG-CI cy4_32
INCDEC-G-0 cy4_34
INCDEC-G-CI cy4_36
INCDEC-G-F1 cy4_35
*Available only for XC4000X and SpartanXL devices

Carry Logic Handling

The mapper checks for legal connections between carry logic symbols and also
performs simple trimming on some carry modes. CY4 symbols might be trimmed as
follows.
• If neither the COUT0 pin nor the COUT pin is used, the CY4 symbol is removed
from the design. However, if the signal on the CIN pin connects to other logic, the
mapper converts the CY4 to the EXAMINE-CI mode. An EXAMINE-CI mode
CY4 is trimmed only if there is no other load on the signal on the CIN pin.
• If the specified mode does not require any of the A0, B0, A1, B1, and/or ADD CY4
inputs, signals are removed from these pins, which may save routing resources.

Carry Mode Configuration Mnemonics

The first step in configuring a CLB for carry logic is to choose the appropriate carry
mode configuration mnemonic. Each of the 43 possible configurations of the carry
logic has been assigned a three-part mnemonic code, for example:
ADD-FG-CI
• The first field (ADD) describes the operation performed in the CLB function
generators, in this case, a binary addition. By implication, the carry logic in this
CLB calculates the carry for this addition.
• The second field (FG) indicates which of the two function generators is used in
the specified operation, in this case, both F and G.
• The last field (CI) specifies the source of the carry-in signal to the CLB, in this case,
the CIN pin itself.
Consider another example:
INCDEC-G-F1
This mnemonic describes a CLB in which the G function generator performs an incre-
ment/decrement function. The carry-in to this CLB is sourced by the F1 pin.
All available carry mode configuration mnemonics are listed in the next section, the
“Carry Logic Configurations” section.

12-142 Xilinx Development System

Attributes, Constraints, and Carry Logic

To determine which carry mode primitive corresponds to which mnemonic, see the
“Carry Modes” table.

Carry Logic Configurations

This section lists and describes all the available carry mode configuration mnemonics.
The following information is given for each mnemonic.
• The name of the mode mnemonic.
• A brief description of the CLB function.
• The COUT0 and COUT equations performed by the carry logic.
• Default equations for the F and G function generators.
• Default assignments for the F4, G2, and G3 inputs.
The default F and G functions and default F4, G2, and G3 inputs are based on the
generic CLB function described. You can change these defaults as required, allowing
for features such as parallel enable or synchronous reset. However, if these defaults
are changed, the CLB may no longer function as the mnemonic describes.
The COUT0 and COUT equations are absolutely determined by the carry mode
configuration mnemonic. The only way to change these carry logic outputs is by
selecting a different mnemonic.

ADD-F-CI
The ADD-F-CI configuration performs a 1-bit addition of A+B in the F function gener-
ator, with the A and B inputs on the F1 and F2 pins. The carry signal enters on the CIN
pin, propagates through the F carry logic, and exits on the COUT pin. This configura-
tion can be used as the MSB of an adder, with the G function generator accessing the
carry-out signal or calculating a twos-complement overflow.
F=(F1@F2)@F4
COUT0=(F1*F2) + CIN*(F1+F2)
G=
COUT=COUT0
F4=CIN
G2=G2I (COUT0 for overflow, OFL=G2@G3, or for carry-out, CO=G2)
G3=G3I (CIN for overflow, OFL=G2@G3)

ADD-FG-CI
The ADD-FG-CI configuration performs a 2-bit addition of A+B in both the F and G
function generators, with the lower-order A and B inputs on the F1 and F2 pins, and
the higher-order A and B inputs on the G1 and G4 pins. The carry signal enters on the
CIN pin, propagates through the F and G carry logic, and exits on the COUT pin. This
configuration comprises the middle bits of an adder.
F=(F1@F2)@F4
COUT0=(F1*F2) + CIN*(F1+F2)
G=(G4@G1)@G2
COUT=(G4*G1) + COUT0*(G4+G1)

Libraries Guide, Release M1.5 12-143

Libraries Guide, Release M1.5

F4=CIN
G2=COUT0
G3=G3I

ADD-G-F1
The ADD-G-F1 configuration performs a 1-bit addition of A+B in the G function
generator, with the A and B inputs on the G1 and G4 pins. The carry signal enters on
the F1 pin, propagates through the G carry logic, and exits on the COUT pin. This
configuration comprises the LSB of an adder, where the carry-in signal is routed to F1.
The F function generator is not used.
F=
COUT0=F1
G=(G4@G1)@G2
COUT=(G4*G1) + COUT0*(G4+G1)
F4=F4I
G2=COUT0
G3=G3I

ADD-G-CI
The ADD-G-CI configuration performs a 1-bit addition of A+B in the G function
generator, with the A and B inputs on the G1 and G4 pins. The carry signal enters on
the CIN pin, propagates through the G carry logic, and exits on the COUT pin. This
configuration is for the middle bit of an adder, where the F function generator is
reserved for another purpose.
F=
COUT0=CIN
G=(G4@G1)@G2
COUT=(G4*G1) + COUT0*(G4+G1)
F4=F4I
G2=COUT0
G3=G3I

ADD-G-F3-
The ADD-G-F3- configuration performs a 1-bit addition of A+B in the G function
generator, with the A and B inputs on the G1 and G4 pins. The carry signal enters on
the F3 pin, is inverted by the F carry logic, propagates through the G carry logic, and
exits on the COUT pin. This configuration comprises the LSB of an adder, where the
inverted carry-in signal is routed to F3. The F function generator is not used.
F=
COUT0=~F3
G=(G4@G1)@G2
COUT=(G4*G1) + COUT0*(G4+G1)

12-144 Xilinx Development System

Attributes, Constraints, and Carry Logic

F4=F4I
G2=COUT0
G3=G3I

SUB-F-CI
The SUB-F-CI configuration performs a 1-bit twos-complement subtraction of A-B in
the F function generator, with the A input on F1 and the B input on F2. The carry
signal enters on the CIN pin, propagates through the F carry logic, and exits on the
COUT pin. This configuration can be used as the MSB of a subtracter, with the G func-
tion generator accessing the carry-out signal or calculating a twos-complement over-
flow.
F=(F1@F2)@~F4=~(F1@F2@F4)
COUT0=(F1*~F2) + CIN*(F1+~F2)
G=
COUT=COUT0
F4=CIN
G2=G2I (COUT0 for overflow, OFL=G2@G3, or for carry-out, CO=G2)
G3=G3I (CIN for overflow, OFL=G2@G3)

SUB-FG-CI
The SUB-FG-CI configuration performs a 2-bit twos-complement subtraction of A-B
in both the F and G function generators. For the lower bit, the A input is on F1 and the
B input is on F2. For the upper bit, the A input is on G4 and the B input is on G1. The
carry signal enters on the CIN pin, propagates through the F and G carry logic, and
exits on the COUT pin. This configuration comprises the middle bits of a subtracter.
F=(F1@F2)@~F4=~(F1@F2@F4)
COUT0=(F1*~F2) + CIN*(F1+~F2)
G=(G4@G1)@~G2=~(G4@G1@G2)
COUT=(G4*~G1) +COUT0*(G4+~G1)
F4=CIN
G2=COUT0
G3=G3I

SUB-G-1
The SUB-G-1 configuration performs a 1-bit twos-complement subtraction of A-B in
the G function generator, with the A input on G4 and the B input on G1. The carry-in
is tied High (no borrow). The carry signal propagates through the G carry logic and
exits on the COUT pin. This configuration comprises the LSB of a subtracter with no
carry-in. The F function generator is not used.
F=
COUT0=1
G=(G4@G1)

Libraries Guide, Release M1.5 12-145

Libraries Guide, Release M1.5

COUT=(G4+~G1)
F4=F4I
G2=G2I
G3=G3I

SUB-G-CI
The SUB-G-CI configuration performs a 1-bit twos-complement subtraction of A-B in
the G function generator, with the A input on G4 and the B input on G1. The carry
signal enters on the CIN pin, propagates through the G carry logic, and exits on the
COUT pin. This configuration is for the middle bit of a subtracter, where the F func-
tion generator is reserved for another purpose.
F=
COUT0=CIN
G=(G4@G1)@~G2=~(G4@G1@G2)
COUT=(G4*~G1) + COUT0*(G4+~G1)
F4=F4I
G2=COUT0
G3=G3I

SUB-G-F1
The SUB-G-F1 configuration performs a 1-bit twos-complement subtraction of A-B in
the G function generator, with the A input on G4 and the B input on G1. The carry
signal enters on the F1 pin, propagates through the G carry logic, and exits on the
COUT pin. This configuration comprises the LSB of a subtracter, where the carry-in
signal is routed to F1. The F function generator is not used.
F=
COUT0=F1
G=(G4@G1)@~G2=~(G4@G1@G2)
COUT=(G4*~G1) + COUT0*(G4+~G1)
F4=F4I
G2=COUT0
G3=G3I

SUB-G-F3-
The SUB-G-F3- configuration performs a 1-bit twos-complement subtraction of A-B in
the G function generator, with the A input on G4 and the B input on G1. The carry
signal enters on the F3 pin, is inverted by the F carry logic, propagates through the G
carry logic, and exits on the COUT pin. This configuration comprises the LSB of a
subtracter, where the inverted carry-in signal is routed to F3. The F function generator
is not used.
F=
COUT0=~F3

12-146 Xilinx Development System

Attributes, Constraints, and Carry Logic

FORCE-F3-
The FORCE-F3- configuration forces the signal on the F3 pin to pass inverted to the
COUT pin.
COUT0=~F3
COUT=COUT0=~F3

FORCE-G4
The FORCE-G4 configuration forces the signal on the G4 pin to pass through to the
COUT pin (XC4000X and SpartanXL only).
COUT0=0
COUT=G4

EXAMINE-CI
The EXAMINE-CI configuration allows the carry signal on the CIN pin to be used in
the F or G function generators. This configuration forces the signal on the CIN pin to
pass through to the COUT pin and is equivalent to the FORCE-CI configuration.
EXAMINE-CI is provided for CLBs in which the carry logic is unused but the CIN
signal is required.
COUT0=CIN
COUT=COUT0=CIN

12-156 Xilinx Development System

Attributes, Constraints, and Carry Logic

Carry Logic in XC5200

The XC5200 CLB contains a dedicated carry logic feature. This enhances the perfor-
mance of arithmetic functions such as adders, subtracters, counters, comparators, and
so forth. A carry multiplexer (CY_MUX) represents the dedicated 2:1 multiplexer in
each logic cell. The multiplexer performs a 1-bit high speed carry propagate per logic
cell (four bits per CLB).
In addition to providing a high speed carry propagate function, each CY_MUX can be
connected to the CY_MUX in the adjacent logic cell to provide cascadable decode
logic. The “XC5200 Carry Logic” figure illustrates how the four-input function gener-
ators can be configured to take advantage of the four cascaded CY_MUXes.
Note: AND and OR cascading are specific cases of a generic decode.

Carry Out

LUT

LC3

CY_MUX FD

LUT

LC2

FD
CY_MUX

LUT

LC1

FD
CY_MUX

LUT

LC0

Carry In
X6951

Figure 12-20 XC5200 Carry Logic

XC5200 Carry Logic Library Support

The design entry library contains one carry logic primitive and one carry logic macro.
The carry multiplexer primitive (CY_MUX) represents the dedicated 2:1 multiplexer
that performs the high speed carry propagate function. The carry initialize (CY_INIT)
macro is used to initialize the carry chain for all arithmetic functions. The CY_INIT is
implemented by forcing a zero onto the select line of the CY_MUX such that the DI
pin of the CY_MUX is selected to drive the CO pin. See the “Carry Initialize Function
XC5200” figure.

Libraries Guide, Release M1.5 12-157

Libraries Guide, Release M1.5

CO
S
DI CI

INIT

X6958

Figure 12-21 Carry Initialize Function XC5200

Note: The XC5200 library contains a set of RPMs designed to take advantage of the
logic. Using the macros as they are or modifying them makes it much easier to take
advantage of this feature.

Cascade Function
Each CY_MUX can be connected to the CY_MUX in the adjacent logic cell to provide
cascadable decode logic. The “CY_MUX Used for Decoder Cascade Logic XC5200”
figure illustrates how the 4-input function generators can be configured to take
advantage of these four cascaded CY_MUXes.
Note: AND and OR cascading are specific cases of a general decode. In AND
cascading, all bits are decoded equal to logic one. In OR cascading, all bits are
decoded equal to logic zero. The flexibility of the LUT achieves this result.

12-158 Xilinx Development System

Attributes, Constraints, and Carry Logic

cascade out

DI DO
out
D Q

CY_MUX FD
A15 F4 S
A14 F3
A13 F2 AND
A12 F1 X

LC3

DI DO

D Q

CY_MUX FD
A11 F4 S
A10 F3
A9 F2 AND
A8 F1 X

LC2

DI DO

D Q

FD
A7 F4 CY_MUX
S
A6 F3
A5 F2 AND
A4 F1 X

LC1

DI DO

D Q

CY_MUX FD
A3 F4 S
A2 F3
A1 F2 AND
VCC A0 F1 X
±5
CI CE CK CLR LC0
cascade in

CY_MUX
F=0 Initialization of
carry chain (One Logic Cell)

X7706
GND

Figure 12-22 CY_MUX Used for Decoder Cascade Logic XC5200

Libraries Guide, Release M1.5 12-159

Libraries Guide, Release M1.5

Carry Logic in Virtex

The Virtex CLB contains a dedicated carry logic feature. This enhances the perfor-
mance of arithmetic functions such as adders, subtracters, counters, comparators, and
so forth. For detailed information on Carry Logic in Virtex, refer to the Xilinx web site,
http://www.xilinx.com.

12-160 Xilinx Development System

Index
A BUFT, 12-23, 12-33, 12-35, 12-42, 12-61, 12-76, 12-79
ADD-F-CI, 12-141, 12-143 constraint examples, 12-45, 12-81
ADD-FG-CI, 12-141, 12-142, 12-143 creating wired-AND instance, 12-27
ADD-G-CI, 12-141, 12-144 identification of BUFT locations
ADD-G-F1, 12-141, 12-144 Virtex, 12-82
ADD-G-F3-, 12-141, 12-144 XC3000, 12-81
ADDSUB-F-C1, 12-147 XC4000, 12-82
ADDSUB-F-CI, 12-141 XC5200, 12-82
ADDSUB-FG-CI, 12-141, 12-147 with RLOC constraint, 12-62, 12-97
ADDSUB-G-CI, 12-141, 12-147 with RLOC_ORIGIN constraint, 12-62, 12-111
ADDSUB-G-F1, 12-141, 12-148 BUGDGLL, 12-65
ADDSUB-G-F3, 12-148 bus pad symbols, 12-43
ADDSUB-G-F3-, 12-141
ALLCLOCKNETS keyword in PCF C
used with FREQUENCY, 12-126, 12-136 carry logic, 12-2, 12-138, 12-139
used with MAXDELAY, 12-128 carry mode, 12-140, 12-142
used with MAXSKEW, 12-129 handling in NDGDBUILD and the mapper, 12-142
used with PERIOD, 12-131, 12-136 in XC5200 CLB, 12-43
ALLPATHS keyword in PCF LOC and RLOC constraints, 12-141
used with MAXDELAY, 12-128 primitives, 12-23, 12-34, 12-79, 12-130, 12-140
attributes, 12-1 symbols in relationally placed macros, 12-138
carry mode
B configuration mnemonics, 12-142
BASE attribute, 12-8, 12-17, 12-19, 12-21, 12-26 names and symbols, 12-141
BEL, 12-130, 12-132, 12-134, 12-135 primitive symbols, 12-140
BLKNM constraint, 12-7, 12-8, 12-17, 12-23 case sensitivity
block, 12-7 in Mentor, 12-3
block name, 12-7, 12-23, 12-34, 12-80 in UCF and NCF, 12-4, 12-81
in PCF, 12-130 CIN pin, 12-142
Block RAMs, 12-37, 12-42 see also individual carry mode configuration
Boolean operators mnemonics
XC3000, 12-31 CLBMAP
BUFFCLK, 12-89 attaching mapping constraints to, 12-48
BUFG component, 12-34, 12-89 mapping constraint examples, 12-91
BUFG constraint, 12-8, 12-17, 12-19, 12-24 CLBs
BUFGDLL, 12-30 base configuration modes, 12-21
BUFGE, 12-89 block definition, 12-7
BUFGLS, 12-89 dedicated carry logic, 12-139, 12-142
BUFGP, 12-34, 12-89 flip-flop constraint examples, 12-88
BUFGS, 12-34, 12-89 mapping gates into function generators, 12-81
mapping with BLKNM attribute, 12-23, 12-80
placement constraint examples, 12-4, 12-84
ROM and RAM constraints, 12-94, 12-95

Libraries Guide, Release M1.5 — 12-161

Libraries Guide, Release M1.5

setting logic equations for function generators, 12- DEC-FG-CI, 12-141, 12-152
31 DEC-G-0, 12-141, 12-152
Virtex slice extensions, 12-43 DEC-G-CI, 12-141, 12-152
with EQUATE_F and EQUATE_G constraint, 12-31 DEC-G-F1, 12-141, 12-153
with RLOC constraint, 12-98 DEC-G-F3-, 12-141, 12-153
XC3000 configuration options, 12-26 DECODE constraint, 12-8, 12-17, 12-19, 12-27, 12-61, 12-
XC5200 physical site locations, 12-43 97
XC5200 slice extensions, 12-61 on WAND gate, 12-86
CLK, 12-24, 12-26 decode logic, 12-86
CLKDLL, 12-24, 12-30, 12-65 DECODE macro, 12-86
CLKDLLHF, 12-24, 12-30, 12-65 decoders
CLKDV_DIVIDE constraint, 12-8, 12-17, 12-25 cannot use with RLOC constraint, 12-97
COLLAPSE constraint, 12-8, 12-17, 12-19, 12-25 dedicated carry logic, 12-139, 12-157, 12-160
colon delay locked loop (DLL),constraint examples, 12-86
in location attributes, 12-3, 12-46 design hierarchy, 12-34, 12-35, 12-76, 12-99, 12-100, 12-
in TSidentifier syntax, 12-15, 12-73, 12-76 103, 12-104, 12-105, 12-107, 12-110, 12-113
with wildcards on RLOCs, 12-111 DFF, 12-97
COMPGRP physical constraint, 12-17, 12-126, 12-127 DIVIDE1_BY constraint, 12-9, 12-17, 12-19, 12-28
COMPONENT keyword, 12-126 DIVIDE2_BY constraint, 12-9, 12-17, 12-19, 12-28
CONFIG constraint (XC3000), 12-8, 12-17, 12-19, 12-26 DOUBLE constraint, 12-9, 12-17, 12-19, 12-28
CONFIG primitive double quotes, 12-4, 12-5, 12-125
attaching PART to, 12-56 DRIVE constraint, 12-9, 12-17, 12-19, 12-29
attaching PROHIBIT to, 12-58 DROP_SPEC constraint, 12-9, 12-17, 12-19, 12-30
examples DUTY_CYCLE_CORRECTION constraint, 12-9, 12-17,
prohibiting CLBs, 12-85 12-30
prohibiting flip-flops, 12-89
prohibiting IOBs, 12-91 E
prohibiting memory placement, 12-95 edge decoders, 12-42, 12-44, 12-58
configuration files see Netlist Constraints File (NCF), constraint examples, 12-86
12-User Constraints File (UCF), 12-or Physical creating wired-AND instance, 12-27
Constraints File (PCF) file edge designations, 12-87
constraints edge indicators, 12-44
applicable files, 12-17 EDIF netlist see netlist
applied to macros and nets, 12-19 EDIF2NGD, 12-3
file name used by NGDBUILD, 12-7 EQUATE_F attribute, 12-9, 12-17, 12-19, 12-31
logical, 12-2, 12-4 EQUATE_G attribute, 12-9, 12-17, 12-19, 12-31
syntax list, 12-8 EXAMINE-CI, 12-141, 12-142, 12-156
UCF/NCF file syntax, 12-5
physical, 12-2 F
PCF syntax, 12-125 F mode, 12-21, 12-26
used by Mentor Graphics, 12-3 F5MAP, 12-22, 12-33, 12-35, 12-42, 12-48, 12-61, 12-76,
user generated, 12-4 12-79, 12-97
COUT pin, 12-142, 12-143 placement constraints, 12-81
see also individual carry mode configuration FAST constraint, 12-5, 12-9, 12-17, 12-19, 12-32, 12-125
mnemonics FFS group name, 12-68, 12-70, 12-71
COUT0 pin, 12-142, 12-143 FG mode, 12-21, 12-26
CY_MUX symbol, 12-35, 12-42, 12-43, 12-61, 12-76, 12- FGM mode, 12-21, 12-26
97, 12-157 FILE attribute, 12-10, 12-17, 12-19, 12-33
CY4 symbols, 12-35, 12-42, 12-61, 12-76, 12-97, 12-141, flip-flop, 12-22, 12-56, 12-69, 12-70, 12-79, 12-91, 12-130
12-142 and PERIOD constraint, 12-122
and TNM attribute, 12-117
D and XC5200, 12-39, 12-43, 12-55, 12-126, 12-130
DEC-F-CI, 12-141, 12-151 CLB, 12-21, 12-34, 12-45, 12-62
DEC-FG-0, 12-141, 12-151

4-162 Xilinx Development System

Index

CLB examples, 12-84, 12-88 global constraints

FFS group name, 12-68, 12-70, 12-71 in constraints file, 12-125
FFX extension and NGDBUILD, 12-105 OFFSET, 12-52
IOB, 12-51 PART, 12-56
macros with RLOCs, 12-110 TEMPERATURE, 12-66
mapper processing with RLOC constraints, 12-97 time group attributes, 12-67
RLOC constraint examples, 12-98 TSidentifier, 12-73
timing groups in PCF, 12-134 VOLTAGE, 12-78
triggering by rising/falling clock edges, 12-119
with LOC constraint, 12-84, 12-88 H
with RLOC constraint, 12-98, 12-102, 12-105 H_SET constraint, 12-100, 12-114
with RLOC sets, 12-99 and mapper processing, 12-106
X, 12-85 compared to HU_SET, 12-35
XC4000 location extensions, 12-44, 12-59 implicit, 12-101
Xilinx-supplied macros, 12-110 sets, 12-104
Y, 12-85 generated name, 12-102
FMAP, 12-22, 12-33, 12-35, 12-42, 12-48, 12-61, 12-76, 12- modification of, 12-105
79 separating elements, 12-107
grouping function generators into one CLB, 12-23, summary, 12-103
12-80 with RLOC_ORIGIN, 12-114
mapping constraint examples, 12-91, 12-92 half edge indicators, 12-44, 12-45, 12-58, 12-59
placement constraints, 12-81 HBLKNM constraint, 12-7, 12-10, 12-17, 12-34
relationally placed macros, 12-138 hierarchical design see design hierarchy
schematic example, 12-94 HMAP, 12-22, 12-33, 12-35, 12-42, 12-48, 12-61, 12-76,
using with RLOC constraints, 12-97 12-79
FORCE-0, 12-141, 12-156 mapping constraints, 12-91, 12-92
FORCE-1, 12-141, 12-156 placement constraints, 12-81
FORCE-CI, 12-141, 12-156 relationally placed macros, 12-138
FORCE-F1, 12-141, 12-156 RLOC constraints, 12-97
FORCE-F3-, 12-141, 12-156 schematic example, 12-94
FORCE-G4, 12-141 with BLKNM attribute, 12-23, 12-80
FREQUENCY physical constraint, 12-17, 12-126, 12-136 with MAP attribute, 12-48
function generators, 12-142 horizontal longline, 12-28
base configuration modes, 12-21 HU_SET constraint, 12-10, 12-17, 12-35
carry logic, 12-139 and removal from H_SET, 12-100
carry mode configuration syntax, 12-142 purpose, 12-100, 12-107
grouping with BLKNM attribute, 12-23 RLOC set hierarchy, 12-101, 12-107, 12-108, 12-109,
grouping with HBLKNM attribute, 12-34 12-112
grouping with XBLKNM attribute, 12-80 summary, 12-103
logic equations for F and G, 12-31, 12-143 with RLOC_ORIGIN constraint, 12-114
mapping constraints, 12-92
mapping into F, 12-92 I
mapping into H, 12-92 I/O
placement constraints, 12-81 buffers, 12-54, 12-90
see also individual carry mode configuration constraint examples, 12-90
mnemonics edge indicators, 12-44
specifying with LOC constraint, 12-84 element, 12-22, 12-33, 12-79
half edge indicators, 12-45, 12-59
G pads, 12-68, 12-70, 12-71, 12-90
global buffer placement, 12-44, 12-45, 12-58, 12-89 pins, 12-43
corner designations, 12-89 placement, 12-45

Libraries Guide, Release M1.5 4-163

Libraries Guide, Release M1.5

primitives LOC constraint, 12-11, 12-17, 12-19

and NODELAY attribute, 12-51 compared to RLOC constraints, 12-97
with LOC constraint, 12-42 CPLD syntax, 12-47
with RLOC constraint, 12-97 dot extensions on ranges, 12-44
registers, 12-90 examples
IBUF, 12-24, 12-69, 12-70 BUFT placement, 12-81, 12-82
INCDEC-F-CI, 12-142, 12-153 CLB placement, 12-84, 12-85
INCDEC-FG-1, 12-142, 12-154 CLBMAP placement, 12-92
INCDEC-FG-CI, 12-142, 12-154 decode logic placement, 12-86
INCDEC-G-0, 12-142, 12-154 flip-flop placement, 12-88
INCDEC-G-CI, 12-142, 12-155 FMAP and HMAP placement, 12-92
INCDEC-G-F1, 12-142, 12-155 global buffer placement, 12-89
INC-F-CI, 12-141, 12-149 I/O placement, 12-90
INC-FG-1, 12-141, 12-149 IOB placement, 12-90
INC-FG-CI, 12-141, 12-149 memory placement, 12-94, 12-95
INC-G-1, 12-141, 12-150 FPGA syntax for
INC-G-CI, 12-141, 12-150 multiple locations, 12-46
INC-G-F1, 12-141, 12-150 range of locations, 12-46
INC-G-F3-, 12-141, 12-151 single location, 12-45
INIT constraint, 12-6, 12-10, 12-17, 12-19, 12-36 in PCF see LOCATE, 12-127
INIT_0x constraint, 12-10, 12-17, 12-37 on carry logic symbol, 12-141
addresses, 12-37 on CPLDs, 12-43
usage rules, 12-38 on FPGAs, 12-42
INREG constraint, 12-10, 12-17, 12-19, 12-40 propagation down design hierarchy, 12-110
in PCF, 12-126 schematic syntax, 12-4
instance, 12-7 SOFT locations, 12-3, 12-46
instance name, 12-7 LOCATE physical constraint, 12-17, 12-127
IOB constraint, 12-10, 12-17, 12-40 LOCK physical constraint, 12-17, 12-127
IOBs, 12-22, 12-26, 12-29, 12-32, 12-33, 12-40, 12-42, 12- LogiBlox, 12-95
50, 12-55, 12-79, 12-91, 12-126, 12-130, 12-134 logic cell (LC), 12-23, 12-34, 12-80, 12-157
base configuration, 12-21 longline, 12-28, 12-83, 12-132
block definition, 12-7 LSB, 12-144, 12-145, 12-146, 12-148, 12-150, 12-151, 12-
constraint examples, 12-90 152, 12-153, 12-154, 12-155
I/O constraints, 12-90 LUTs, 12-36, 12-61, 12-97
increasing output speed with FAST attribute, 12-32
location designations, 12-44, 12-48, 12-58 M
removing default delay, 12-51 macro
with global buffers, 12-89 attaching constraints to, 12-19
XC3000 configuration options, 12-26 attaching RLOCs to, 12-110
IOPAD, 12-43 MAP constraint, 12-11, 12-17, 12-19, 12-48
IPAD, 12-43 examples, 12-91, 12-92
mapper, 12-5, 12-28, 12-32
K addition function, 12-105, 12-106
KEEP constraint, 12-10, 12-17, 12-19, 12-41 carry mode trimming, 12-142
hierarchy processing, 12-108, 12-113
L IOB constraints, 12-90
latches, 12-39, 12-55, 12-126, 12-130, 12-134 processing of CLBMAP symbol, 12-91
delay, 12-51 MAXDELAY constraint, 12-11, 12-17, 12-19, 12-49, 12-
time group, 12-69, 12-70 124
LATCHES keyword, 12-68, 12-70, 12-71, 12-118, 12-134 in PCF, 12-128
LCA block names, 12-34, 12-79 used with TSidentifier, 12-15, 12-73, 12-120
MAXSKEW constraint, 12-11, 12-17, 12-19, 12-49, 12-124
in PCF, 12-128
MEDDELAY constraint, 12-11, 12-17, 12-19, 12-50

4-164 Xilinx Development System

Index

Mentor, 12-3 PATH physical constraint, 12-18, 12-130

MSB, 12-143, 12-145, 12-147 used with MAXDELAY, 12-128
with TIG, 12-135
N PCF file see Physical Constraints File
NCD file PENALIZE TILDE physical constraint, 12-18, 12-131
set constraints removed, 12-112 PERIOD constraint, 12-12, 12-18, 12-20, 12-57, 12-122,
NCF see Netlist Constraints File, 12-2 12-123
net in PCF, 12-131, 12-135
attaching constraints to, 12-25 used with TSidentifier, 12-15, 12-74, 12-75
constraints on, 12-19, 12-32 physical constraints, 12-2, 12-125
controlling delays, 12-124 Physical Constraints File, 12-2, 12-17, 12-125
controlling skew, 12-124 physical design, 12-2
prioritizing in PCF, 12-132 applicable attributes, 12-17
S(ave) attribute, 12-64 physical location types, 12-44, 12-58
net flag attribute, 12-13, 12-20, 12-64 pin grid arrays, 12-91
netlist, 12-81, 12-86, 12-88, 12-89, 12-90, 12-94, 12-95 PIN physical constraint, 12-18, 12-132
see also Netlist Constraint File (NCF) used with PATH, 12-130
constraints overridden by UCF, 12-112 used with TIG, 12-135
conversion of Mentor and Xilinx property names, with TIMEGRP, 12-134
12-3 PLC, 12-48
instance name, 12-7 PRIORITIZE physical constraint, 12-18, 12-132
relationship of physical constraints to, 12-125 PROHIBIT constraint, 12-13, 12-18, 12-20, 12-46, 12-58
Netlist Constraints File, 12-2, 12-4, 12-17 examples, 12-85, 12-89, 12-91, 12-95
applicable constraints, 12-17 in PCF, 12-132
case sensitivity, 12-4, 12-81 properties, 12-3
rules, 12-5 prorating delay characteristics, 12-66, 12-78
NGDBUILD, 12-32, 12-34, 12-50, 12-51 PUC, 12-11, 12-48, 12-92
constraints file used, 12-7 pull-up resistors, 12-28
hierarchy for HU_SET names, 12-35 PULLUP symbols, 12-28, 12-33
NODELAY constraint, 12-11, 12-18, 12-19, 12-51 PUO, 12-11, 12-48, 12-92
NOMERGE property, 12-41 PWR_MODE constraint, 12-13, 12-18, 12-20, 12-60
NOREDUCE constraint, 12-11, 12-18, 12-19, 12-52
R
O R(eset) a register, 12-36
OE, 12-24 RAM, 12-23, 12-34, 12-35, 12-36, 12-42, 12-61, 12-76, 12-
OFFSET constraint, 12-12, 12-18, 12-52 79, 12-117
in PCF, 12-129 constraint examples, 12-44, 12-94
OPAD, 12-43 initialization, 12-36
OPT_EFFORT constraint, 12-12, 12-18, 12-20, 12-54 location extensions not supported, 12-59
OPTIMIZE constraint, 12-12, 12-18, 12-19, 12-54 timing groups, 12-69, 12-70
OUTREG constraint, 12-12, 12-18, 12-20, 12-55 with RLOCs, 12-97
in PCF, 12-130 RAMB4s, 12-42, 12-43
constraint examples, 12-95
P slice extension, 12-43
PAD symbols, 12-43, 12-69, 12-70, 12-90 RAMD, 12-23, 12-34, 12-35, 12-42, 12-61, 12-76, 12-79,
PAR, 12-3, 12-28, 12-55 12-97
CLB constraints, 12-85 RAMS, 12-23, 12-34, 12-35, 12-42, 12-61, 12-76, 12-79, 12-
enabling for XC5200 fast routing, 12-40 97, 12-134
FMAP mapping, 12-94 constraint examples, 12-44
HMAP mapping, 12-94 location extensions not supported, 12-59
placement constraints registers
schematic syntax, 12-3 attributes on XC5200 logic cell, 12-23, 12-80
PART constraint, 12-12, 12-18, 12-20, 12-56 constraints on, 12-33, 12-35, 12-36, 12-42, 12-61, 12-
76, 12-97

Libraries Guide, Release M1.5 4-165

Libraries Guide, Release M1.5

initialization, 12-36 S
input registers S(ave) attribute, 12-13, 12-18, 12-20, 12-64
constraints on, 12-50, 12-51 S(et) a register, 12-36
relationally placed macros, 12-138 schematic
reserved words, 12-5, 12-68, 12-70, 12-71, 12-118, 12-125 FMAP and HMAP example, 12-94
RLOC constraint, 12-4, 12-13, 12-18, 12-20, 12-61 instance, 12-7
affects of mapper on, 12-105, 12-106, 12-113 placing attributes on symbols, 12-3
carry logic, 12-141 semicolon
general syntax guidelines, 12-97 in UCF and NCF, 12-4
grouping logic elements, 12-97 separator characters, 12-4, 12-15, 12-73, 12-76
hierarchy sets (H_SET), 12-100 with wildcards, 12-111
in relationally placed macros, 12-138 SITEGRP physical constraint, 12-18, 12-127, 12-133
LOC propagation, 12-110 slice extension
on carry logic symbols, 12-141 Virtex, 12-43
set linkage, 12-103 XC5200 CLBs, 12-61
set modification, 12-105 SLOW constraint, 12-13, 12-18, 12-20, 12-64
set modifiers, 12-109 SOFT location, 12-3, 12-46
set types summary, 12-102 soft macros, 12-43, 12-84, 12-138
sets, 12-99, 12-102 LOC applied to, 12-90
symbols that accept RLOC, 12-97 special function access symbols, 12-51
turn off/on for specific elements, 12-77, 12-112 SR, 12-24
user defined groups (U_SET), 12-99 SRLs, 12-36, 12-97
with HU_SET, 12-101, 12-107 STARTUP_WAIT constraint, 12-13, 12-18, 12-65
with Xilinx macros, 12-110 SUB-F-CI, 12-141, 12-145
XC5200 slice placement, 12-61 SUB-FG-CI, 12-141, 12-145
RLOC_ORIGIN constraint, 12-18, 12-20 SUB-G-1, 12-141, 12-145
affects of mapper on, 12-112 SUB-G-CI, 12-142, 12-146
modifying H_SET, 12-100, 12-103, 12-104, 12-114 SUB-G-F1, 12-142, 12-146
modifying HU_SET, 12-103, 12-114 SUB-G-F3-, 12-142, 12-146
modifying U_SET, 12-102 symbols
priority in netlist vs UCF file, 12-112 attributes on schematics, 12-3
purpose, 12-62, 12-111 TIMEGRP, 12-117
syntax, 12-4, 12-5, 12-13, 12-63, 12-114 TIMESPEC, 12-119
use to change RLOC to LOC, 12-111 synchronous reset, 12-143
with sets that include BUFT symbols, 12-111 syntax
RLOC_RANGE constraint, 12-13, 12-20 constraint summary list, 12-8
affects of mapper on, 12-111 conventions, 12-8
applicability, 12-18 PCF file, 12-125
modifying H_SET, 12-100, 12-103, 12-104 schematic, 12-3
modifying HU_SET, 12-103 UCF/NCF files, 12-4
modifying U_SET, 12-102 wildcards, 12-6
priority in netlist vs UCF file, 12-112
purpose, 12-63, 12-111 T
syntax, 12-4, 12-5, 12-63, 12-111 TBUF
ROM, 12-23, 12-34, 12-35, 12-36, 12-42, 12-61, 12-76, 12- block definition, 12-7
79 Virtex slice extension, 12-43
constraint examples, 12-44, 12-94 TCK, 12-51
initialization, 12-36 TDI, 12-51
location extensions not supported, 12-59 TEMPERATURE constraint, 12-14, 12-18, 12-66
with RLOCs, 12-97 in PCF file, 12-133
RPMs, 12-138 TIG constraint, 12-14, 12-15, 12-18, 12-20, 12-67, 12-75,
RPMs see relationally placed macros 12-121
in PCF, 12-135

4-166 Xilinx Development System

Index

time group attributes, 12-14, 12-18, 12-20, 12-67, 12-69 UCF see User Constraints File, 12-2
TIMEGRP keyword, 12-67 USE_RLOC constraint, 12-15, 12-18, 12-20
TIMEGRP physical constraint, 12-134 purpose, 12-77, 12-112
with FREQUENCY, 12-136 to turn RLOCs on/off, 12-112
with FREQUENCY in PCF, 12-126 using with U_SET, 12-113
with MAXDELAY, 12-128 User Constraints File, 12-2, 12-4, 12-17
with MAXSKEW, 12-129 applicable constraints, 12-17
with PATH, 12-130 case sensitivity, 12-4, 12-81
with PERIOD, 12-131 CLB constraints, 12-84
TIMEGRP primitive, 12-118 constraints on CLBMAP, 12-91
constraints on, 12-67, 12-68, 12-117, 12-118, 12-119 DLL constraints, 12-86
TIMESPEC primitive edge decoder constraints, 12-86
constraints on, 12-73 flip-flop constraints, 12-88
use to define timing requirements, 12-117, 12-119 FMAP constraints, 12-92
timing, 12-30 global buffer constraints, 12-89, 12-90
timing names, 12-69 HMAP constraints, 12-92
timing specification, 12-67, 12-69, 12-70, 12-71, 12-72, 12- I/O constraints, 12-90
73 IOB constraints, 12-90
applying to a design, 12-117 prohibit constraints, 12-90
TMS, 12-51 RAM constraints, 12-94
TNM constraint, 12-14, 12-18, 12-20, 12-57, 12-67, 12-72, RAMB4s, 12-96
12-73, 12-74, 12-75, 12-117, 12-118, 12-119, 12-122, 12-123 ROM constraints, 12-94
TNM_NET constraint, 12-14, 12-70 rules, 12-5
TPSYNC constraint, 12-14, 12-18, 12-20, 12-71 timing constraints, 12-117
TPTHRU constraint, 12-14, 12-18, 12-72, 12-74, 12-75,
12-120 V
TS see TSidentifier constraint VHDL, 12-1
TSidentifier constraint, 12-18, 12-20 VOLTAGE constraint, 12-15, 12-18, 12-78
adding timing specifications to UCF, 12-119 in PCF file, 12-136
defining priority for timing specifications, 12-121
ignoring, 12-121 W
in PCF, 12-135 WAND, 12-27, 12-42, 12-61, 12-86, 12-87, 12-97
with ALLCLOCKNETS, 12-126, 12-131, 12-136 wide-edge decoders, 12-27
with FREQUENCY, 12-126, 12-136 wildcards, 12-63, 12-83, 12-85, 12-86, 12-95, 12-111, 12-
with MAXDELAY, 12-128 141
with PERIOD, 12-131, 12-135 for CLB rows/columns, 12-88
with TIG, 12-135 WIREAND constraint, 12-15, 12-18, 12-20, 12-79
purpose, 12-73
syntax, 12-15, 12-73
X
used with MAXDELAY, 12-73
XBLKNM constraint, 12-16, 12-18, 12-79
used with PERIOD, 12-74, 12-75, 12-122, 12-123
with DROP_SPEC, 12-9, 12-30
with PERIOD, 12-12, 12-57
with TIG, 12-14, 12-67
TSidentifier name
considerations for Mentor Graphics, 12-3

U
U_SET constraint, 12-15, 12-18, 12-20, 12-114
applying USE_RLOC to, 12-113
purpose, 12-76, 12-99
summary, 12-102
with RLOC_ORIGIN, 12-114
with USE_RLOC constraint, 12-113

Libraries Guide, Release M1.5 4-167

Libraries Guide, Release M1.5

4-168 Xilinx Development System

Xilinx 96
No ratings yet
Xilinx 96
909 pages
Data Book
No ratings yet
Data Book
750 pages
Databk
100% (2)
Databk
1,041 pages
VHDL Reference Guide From Xilinx
100% (2)
VHDL Reference Guide From Xilinx
348 pages
1989 Xilinx Databook PDF
No ratings yet
1989 Xilinx Databook PDF
380 pages
(Ebooks PDF) Download (Ebook PDF) Digital Systems Engineering Full Chapters
100% (1)
(Ebooks PDF) Download (Ebook PDF) Digital Systems Engineering Full Chapters
50 pages
1993 Xilinx Data Book PDF
No ratings yet
1993 Xilinx Data Book PDF
610 pages
Xilinx Library
No ratings yet
Xilinx Library
1,696 pages
Readme
No ratings yet
Readme
2 pages
Digital Electronics
No ratings yet
Digital Electronics
2 pages
7 Series CLB Architecture
No ratings yet
7 Series CLB Architecture
35 pages
CPLD Libaries Guide PDF
No ratings yet
CPLD Libaries Guide PDF
673 pages
XST 2
No ratings yet
XST 2
336 pages
Composition of State Machines
No ratings yet
Composition of State Machines
11 pages
Regulation - 2018 (CBCS Scheme) 18CS733-Advanced Computer Architecture
100% (1)
Regulation - 2018 (CBCS Scheme) 18CS733-Advanced Computer Architecture
48 pages
7series HDL
No ratings yet
7series HDL
445 pages
Xcell 32
No ratings yet
Xcell 32
64 pages
Edk Libs Ref Guide
No ratings yet
Edk Libs Ref Guide
160 pages
ML555 Development Kit For PCI and PCI Express Designs
No ratings yet
ML555 Development Kit For PCI and PCI Express Designs
108 pages
3 03 Ejemplos Sintetizables VHDL 2021
No ratings yet
3 03 Ejemplos Sintetizables VHDL 2021
450 pages
AXI Quad SPI Datasheet
No ratings yet
AXI Quad SPI Datasheet
120 pages
Xilinx Libraries Guide
No ratings yet
Xilinx Libraries Guide
1,128 pages
Unit 3 Notes
No ratings yet
Unit 3 Notes
90 pages
Section VII: Xilinx University Program
No ratings yet
Section VII: Xilinx University Program
23 pages
Hrdatabook PDF
No ratings yet
Hrdatabook PDF
313 pages
Chapter 8 - Sequential Circuit Design
No ratings yet
Chapter 8 - Sequential Circuit Design
107 pages
Ug 193
No ratings yet
Ug 193
114 pages
Axi BFM
No ratings yet
Axi BFM
85 pages
Pipelining: Advanced Computer Architecture
100% (1)
Pipelining: Advanced Computer Architecture
30 pages
What Is An Interrupt?
No ratings yet
What Is An Interrupt?
6 pages
EDK Concepts, Tools, and Techniques: A Hands-On Guide To Effective Embedded System Design
No ratings yet
EDK Concepts, Tools, and Techniques: A Hands-On Guide To Effective Embedded System Design
80 pages
Digital Principles and System Design
No ratings yet
Digital Principles and System Design
76 pages
1991 Xilinx Data Book PDF
No ratings yet
1991 Xilinx Data Book PDF
420 pages
Synthesis and Simulation Design Guide: UG626 (V 14.1) May 8, 2012
No ratings yet
Synthesis and Simulation Design Guide: UG626 (V 14.1) May 8, 2012
171 pages
Manual System Generator PDF
No ratings yet
Manual System Generator PDF
917 pages
Module 2
No ratings yet
Module 2
67 pages
1 Clock Domain Crossing
No ratings yet
1 Clock Domain Crossing
35 pages
AM29BL162CB Edit
No ratings yet
AM29BL162CB Edit
47 pages
Verilog FAQ Interview Questions
No ratings yet
Verilog FAQ Interview Questions
11 pages
Constraints Guide
No ratings yet
Constraints Guide
1,026 pages
Library Guide Virtex-II Pro
No ratings yet
Library Guide Virtex-II Pro
1,180 pages
7series SCM
No ratings yet
7series SCM
623 pages
Good Manual Xilinx-Fpga Fpga Timing
No ratings yet
Good Manual Xilinx-Fpga Fpga Timing
168 pages
Pg065 CLK Wiz
No ratings yet
Pg065 CLK Wiz
82 pages
Lecture 01 - Introduction To Industrial Automation
No ratings yet
Lecture 01 - Introduction To Industrial Automation
37 pages
Design Logic Programable
No ratings yet
Design Logic Programable
126 pages
Kintex 7
No ratings yet
Kintex 7
92 pages
JTAG
No ratings yet
JTAG
124 pages
Asynchronous Bus.
No ratings yet
Asynchronous Bus.
3 pages
Fpga23000 10 WKBF Rev1
No ratings yet
Fpga23000 10 WKBF Rev1
370 pages
Taking Neuromorphic Computing To The Next Level With Loihi 2
No ratings yet
Taking Neuromorphic Computing To The Next Level With Loihi 2
7 pages
Module 3
No ratings yet
Module 3
44 pages
Xilinx - Pci Databook
No ratings yet
Xilinx - Pci Databook
258 pages
XST User Guide
No ratings yet
XST User Guide
552 pages
VLSI Interview Questions and Answers
50% (2)
VLSI Interview Questions and Answers
5 pages
S3 Euserguide
No ratings yet
S3 Euserguide
32 pages
Foundation Series 2.1i User Guide
No ratings yet
Foundation Series 2.1i User Guide
330 pages
Chapter9 CounterDesign
No ratings yet
Chapter9 CounterDesign
28 pages
Ug 349
No ratings yet
Ug 349
24 pages
DL & CO - Unit 2 Material - Digital Logic Circuits-II)
No ratings yet
DL & CO - Unit 2 Material - Digital Logic Circuits-II)
21 pages
Pg022 Axi Datamover
No ratings yet
Pg022 Axi Datamover
60 pages
Constraints Guide: UG625 (V 12.1) April 19, 2010
No ratings yet
Constraints Guide: UG625 (V 12.1) April 19, 2010
248 pages
Configurable 2 Bits Per Cycle Successive Approximation Register For Analog To Digital Converter On FPGA
No ratings yet
Configurable 2 Bits Per Cycle Successive Approximation Register For Analog To Digital Converter On FPGA
5 pages
Impact
No ratings yet
Impact
186 pages
C Users HP Documents XilinxDocs ISE Documentation SW Manuals Xilinx14 5 Sim
No ratings yet
C Users HP Documents XilinxDocs ISE Documentation SW Manuals Xilinx14 5 Sim
171 pages
USB Cable Installation Guide-UG344
No ratings yet
USB Cable Installation Guide-UG344
24 pages
Axi Iic Bus Interface V2.0: Logicore Ip Product Guide
No ratings yet
Axi Iic Bus Interface V2.0: Logicore Ip Product Guide
62 pages
Xtremedsp Design Considerations User Guide: Ug073 (V1.2) February 4, 2005
No ratings yet
Xtremedsp Design Considerations User Guide: Ug073 (V1.2) February 4, 2005
114 pages
pg119 C Accum
No ratings yet
pg119 C Accum
24 pages
Shift Register&counter
No ratings yet
Shift Register&counter
14 pages
Xilinx Simulation and Synthesis Guide
No ratings yet
Xilinx Simulation and Synthesis Guide
171 pages
Sync Vs Async Resets
No ratings yet
Sync Vs Async Resets
4 pages
Handout 2016 PDF
No ratings yet
Handout 2016 PDF
4 pages
I/O Module V3.1: Logicore Ip Product Guide
No ratings yet
I/O Module V3.1: Logicore Ip Product Guide
52 pages
DSD Lab Manual
No ratings yet
DSD Lab Manual
64 pages
Ug1043 Embedded System Tools PDF
No ratings yet
Ug1043 Embedded System Tools PDF
92 pages
Design and Implementation of First in First Out Memory
No ratings yet
Design and Implementation of First in First Out Memory
64 pages
IE1204-5 20141027 Solutions Eng PDF
No ratings yet
IE1204-5 20141027 Solutions Eng PDF
12 pages
AD420
No ratings yet
AD420
16 pages
How To Convert A PLB Based Embd System To An Axi Based System
No ratings yet
How To Convert A PLB Based Embd System To An Axi Based System
13 pages
Vlsi Design Test and Testability
No ratings yet
Vlsi Design Test and Testability
17 pages
Quadrature Encoder
No ratings yet
Quadrature Encoder
5 pages
Xilinx Microblaze and Powerpc Processor Embedded Kit - Virtex-5 Fx70T Fpga Edition
No ratings yet
Xilinx Microblaze and Powerpc Processor Embedded Kit - Virtex-5 Fx70T Fpga Edition
16 pages
Synopsys
No ratings yet
Synopsys
308 pages
Zsh Essentials: Definitive Reference for Developers and Engineers
From Everand
Zsh Essentials: Definitive Reference for Developers and Engineers
Richard Johnson
No ratings yet
Linux Container Essentials with LXC: Definitive Reference for Developers and Engineers
From Everand
Linux Container Essentials with LXC: Definitive Reference for Developers and Engineers
Richard Johnson
No ratings yet
RISC-V Architecture and Implementation Guide: Definitive Reference for Developers and Engineers
From Everand
RISC-V Architecture and Implementation Guide: Definitive Reference for Developers and Engineers
Richard Johnson
No ratings yet
Comprehensive Guide to HashiCorp Technologies: Definitive Reference for Developers and Engineers
From Everand
Comprehensive Guide to HashiCorp Technologies: Definitive Reference for Developers and Engineers
Richard Johnson
No ratings yet
Pop!_OS System Administration Guide: Definitive Reference for Developers and Engineers
From Everand
Pop!_OS System Administration Guide: Definitive Reference for Developers and Engineers
Richard Johnson
No ratings yet
Oracle Quick Guides: Part 1 - Oracle Basics: Database and Tools
From Everand
Oracle Quick Guides: Part 1 - Oracle Basics: Database and Tools
Malcolm Coxall
No ratings yet