1.

Computer organisation (micro-architecture)

1.1. Definition
Computer organisation refers to as the logical arrangement of the computer hardware components and
how they are interconnected.
A computer system, like any system, consists of an interrelated set of components. It is best characterised
in terms of:
Structure: the way in which components are interconnected, and
 Function: the operation of the individual components.
Furthermore, a computer's organisation is hierarchic. Each major component can be described by
decomposing it into its major subcomponents and describing their structure and function.
Computer’s units work in coordination with each other to perform the given task. Computer takes raw
data as input from the user and processes these data under the control of set of instructions (called program) and
gives the result (output) and saves output for the future use. It can process both numerical and non-numerical
(arithmetic and logical) calculations.
The block diagram of a computer is shown in the following figure:

Figure 1: Block diagram of a computer

1.2. Types of micro-architectures

Two dominant computer architectures exist for designing microprocessors and microcontrollers. These
two architectures include Harvard and von Neumann. The Harvard and von Neumann architectures consist of
four major subsystems: memory, input/output (I/O), arithmetic/logic unit (ALU), and control unit (CU).
The ALU and control unit operate together to form the central processing unit (CPU). Instructions and data are
stored in high-speed memories called registers within the CPU. Each of these components interact together to
complete the execution of instructions.

a. The Von Neumann architecture

The term Von Neumann architecture refers to a particular design model for a stored-program digital
computer. This architecture consists of:
 Separate central processing unit (CPU) and random-access memory (RAM).
 Both instructions and data stored in RAM.
 Data to be processed is transferred from RAM to CPU, and results are transferred back to
RAM.
 Figure 2: Von Neumann architecture

b. Harvard architecture
The Harvard architecture alternatively consists of separate pathways or buses for interaction between the
CPU and memory. The separation allows for instructions and data to be accessed concurrently. Also, a new
instruction may be fetched from memory at the same time another one is finishing execution, allowing for a
primitive form of pipelining. Pipelining decreases the execution time of one instruction, but main memory
access time, in many cases, is a major bottleneck in the overall performance of the system. Outlines of Harvard
Machine architecture can be summarised as follows:
• programs are separately stored from data: programs are stored in the program (read only)
memory while data are stored in the data (read and write) memory
• The set of control signal (s) different for the instructions and data fetches
• It enables single instruction operating on multiple data (SIMD)

Figure 3: Harvard architecture

2. Instruction Set Architecture

2.1. Definitions
The Instruction set is the set of instructions that are interpreted directly in the hardware by the CPU.
These instructions are encoded as bit strings in memory and are fetched and executed one by one by the
processor. They perform primitive operations.
The computer possesses a clock that synchronises the internal operations of the CPU with other system
components. The computer can only do one thing at a time. Each action must be broken down into the most
basic steps. One round of steps from getting an instruction from main memory to getting the next instruction is
called the Machine Cycle.
The clock speed is the number of CPU cycles per second.

2.2. Types of Instruction Set Architectures

There are two main types of architectures a processor can be based on. They are:
a. CISC architecture
CISC stands for Complex Instruction Set Computer. CISC computers have a large and fancy
instruction set. In addition to a set of common operations, the instruction set has special purpose instructions
that are designed for limited situations. CISC processors tend to have a slower clock cycle, but accomplish
more in each cycle because of the sophisticated instructions. Older processors fit into the CISC family.
b. RISC architecture
 RISC stands for Reduced Instruction Set Computer. The philosophy is that most programs that run in
RISC environments do not need an excessive number of instructions to perform. Many modern processors are
in the RISC family. RISC computers have a relatively lean instruction set, containing mostly simple, general-
purpose instructions. Even basics like multiply and divide may not be present (you have to do repeated
addition/subtraction/shift/ etc.) But the clock cycle can be cranked to unbelievable speeds allowing comparable
or even better performance than CISC chips overall.
Computing schemes
Followings are classified on the basis of the notion of instruction and data streams that can be
simultaneously manipulated by the machine. A stream is just a sequence of items (instruction or data).
SISD architecture (SISD: Single Instruction, Single Data stream)
SISD refers to an Instruction Set Architecture in which a single processor (one CPU) executes exactly one
instruction stream at a time and also fetches or stores one item of data at a time to operate on data stored ina
single memory unit. Most of the CPU designs, based on the von Neumann architecture, from the beginning till
recent times are based on the SISD.
SIMD architecture (SIMD means Single Instruction, Multiple Data streams)
SIMD is an ISA that have a single control unit (CU) and more than one processing unit (PU) that operates like
a von Neumann machine by executing a single instruction stream over PUs, handled through the CU. The CU
generates the control signals for all of the PUs and by which executes the same operation on different data streams.
The SIMD architecture, in effect, is capable of achieving data level parallelism.
MISD architecture (MISD means Multiple Instruction, Single Data stream)
MISD is an ISA for parallel computing where many functional units perform different operations by
executing different instructions on the same data set. This type of architecture is common mainly in the fault-
tolerant computers executing the same instructions redundantly in order to detect and mask errors.

MIMD architecture (MIMD means Multiple Instructions, Multiple Data streams)

MIMD is an Instruction Set Architecture for parallel computing that is typical of the computers with
multiprocessors. Using the MIMD, each processor in a multiprocessor system can execute asynchronously
different set of the instructions independently on the different set of data units. The MIMD architectures are
primarily used in a number of application areas such as computer-aided design/computer-aided manufacturing,
simulation, modelling, communication switches etc.

2.3. The machine instruction cycle

Instructions are processed under the direction of the control unit in a step-by-step manner. The machine
cycle is the fundamental sequence of steps that a CPU performs. It is the time in which a single instruction is
fetched from its memory, decoded and executed. The first part (Fetch cycle) fetches the instruction, transfers it
from memory to the instruction register (IR) and decodes it. The second part (Execute cycle) executes and store
that instruction. Cycle per instruction (CPI) means the number of clock cycles to complete a single instruction.
a. Steps of instruction cycle
There are four fundamental steps in the machine instruction cycle:
Fetch the instruction
The program counter (PC) is the address which contains the next instruction that is to be executed.
Via data bus, the content of address contained in the program counter is fetched from the main memory
and stored in the CIR (Current Instruction Register). At the end of the fetch operation, the PC points to the next
instruction that will be read at the next cycle.
Decode the instruction
The instruction decoder interprets the instruction. During this cycle the instruction inside the IR
(Instruction Register) gets decoded. All required data are fetched from main memory and put in data registers.
Execute
The Control Unit of CPU passes the decoded information to the relevant function units of the CPU to
perform the actions required by the instruction (such as reading values from registers, passing them to the ALU to
perform mathematical or logic functions on them, and writing the result back to a register).
 Store result
Results of calculations in CPU are stored in main memory or sent to output devices
Program Counter could be updated to a new address from which the next instruction will be fetched.
b. Parts of a Machine Instruction
• Op-code: Specifies which operation to execute (addition, subtraction, etc.)
• Operand: Gives more detailed information about the operation (it specifies the locations of the
numbers (operands) to be used in the operation and where the result is to be stored, etc.)

3. System Design Architecture

System interconnects
A bus is a collection of parallel wires that carry address, data, and control signals. Depending on
theparticular bus design, data and address signals can share the same set of wires, or they can use differentsets.
Also, more than two devices can share the same bus. The control wires carry signals that synchronisethe
transaction and identify what kind of transaction is currently being performed. For example, is this transaction
of interest to the main memory, or to some other I/O device such as a disk controller? Is the transaction a read
or a write? Is the information on the bus an address or a data item?
Buses as Multiplexers
• Interconnections are very important to computer – Most connections are shared
• A bus is a time-shared connection or multiplexer – A bus provides a data path and control
• Buses may be serial, parallel, or a combination
• Serial buses transmit one bit at a time
• Parallel buses transmit many bits simultaneously on many wires
Types of Buses
Data Bus
• The data bus consists of 8, 16, or 32 parallel signal lines. The data bus lines are bidirectional.
• Many devices in a system will have their outputs connected to the data bus, but only one device at a
time will have its outputs enabled.
• Any device connected on the data bus must have three-state outputs so that its outputs can be disabled
when it is not being used to put data on the bus.
Address Bus
• The address bus consists of 16, 20, 24, or 32 parallel signal lines. On these lines the CPU sends out the
address of the memory location that is to be written to or read from.
• The number of memory locations that the CPU can address is determined by the number of address
lines. If the CPU has N address lines, then it can directly address 2N memory locations. CPU with 16 address
lines can address 65,536 memory CPU with 20 address lines can address 1,048,576 locations
• When the CPU reads data from or writes data to a port, it sends the port address out on the address bus.
Control Bus
• The control bus consists of 4 to 10 parallel signal lines.
• The CPU sends out signals on the control bus to enable the outputs of addressed memory devices or port
devices.
• Typical control bus signals are Memory Read, Memory Write, I/O Read, and l/O Write.
• To read a byte of data from a memory location, the CPU sends out the memory address of the desired
byte on the address bus and then sends out a Memory Read signal on the control bus.
The Memory Read signal enables the addressed memory device to output a data word onto the data bus. The
data word from memory travels along the data bus to the CPU.