MINISTRY OF EDUCATION AND TRAINING

THE UNIVERSITY OF DA NANG - UNIVERSITY

SCIENCE AND TECHNOLOGY
***

EE271
DIGITAL CIRCUITS AND SYSTEMS
- LABORATORY REPORT-

LABORATORY INSTRUCTOR: VU VAN THANH

CLASS: 21ECE
GROUP MEMBERS: NGUYEN HUYNH NHU MY
PHAN MINH PHUONG
PHAN NGUYEN DINH NGUYEN
TA THAO LINH

Danang, May 9th, 2024

 ECE 271 LAB 1
AN INTRODUCTION TO MODELING, VERILOG, AND REAL
WORLD DIGITAL PARTS
Part 1: Modeling, Simulating, and Testing a Digital Comparator
1. Each team member must include a copy his or her simulation results. Such results
must include source code, waveforms, and text file output
a. Member 1: (Minh Phuong)
 Source code:

 Waveforms:

b. Member 2: (Nhu My)

  Source code:

 Waveforms:

c. Member 3: (Thao Linh)

 Source code:
  Waveforms:

Input Output

A B C D

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

d. Member 4: (Dinh Nguyen)

 Source code:

 Waveforms:
2. One set of answers to all the questions from the team. The answers to the questions
must be typed. The diagrams must be done using a drawing tool such as Visio.

1. Draw a logic diagram using the logic gates that were used to build the digital circuit
in the Verilog source code. Use the same signal names indicated in the source code.
Use AND, OR, and NOT gates.

2. Draw the truth table for this circuit.

Input Output
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

3. When you run the simulation. Does the output of the Verilog program agree or
disagree with your truth table?

- Waveform simulation:
  The waveform result matches the expected outputs from the truth table for all test
cases, so the output of the Verilog program agrees with the truth table.

4. What advantages are there to using a program like Verilog? Name three or more.

 Less code to write.

 More of a hardware modeling language
 Succinct
 Similarities to the C language
 A lower level of programming constructs
 A better grasp on hardware modeling

Part 2: Modeling, Simulating, and Testing a MultiFunction Logic Block

1. A copy the Verilog source code for the MultiFunction Logic Block, the testbench, and the
tester.
2. A copy of the simulation results.

 CASE 1: SEL1 = 0 and sel2 = 0

 CASE 2: SEL1 = 0 and SEL2 = 1

 CASE 3: SEL1 = 1 and SEL2 = 0

 CASE 4: SEL1 = 1 and SEL2 = 1

 Summary:
Part 3: Working with Real World Devices
Working with Logic Gates

 The voltage drop across the 8.2  resistor is 0.15 mV

−3
−0.15 x 10 −5
 The current i 1= =−1.829 x 10 A
8.2
 The voltage drop across the 100  resistor is 1.85 V
−1.85
 The current i 2= =−0.0185 A
100
 Disconnect the LED and resistor from the circuit => V1 = 4.9 V
  The voltage drop across the 10 k resistor is 6.2 mV
−3
6.2 x 10 −7
 The value of the current i3: i 3= =6.2 x 10 A
10000
 The voltage drop across the 100  resistor is 2.42 V
2.42
 The value of the current i4 : i 4 = =0.0242 A
100
 Disconnect the LED and resistor from the circuit => V2 = 0.4V
Find the data sheet for the SN74LS04N.
 On the data sheet, find the values for IIL, IOH, IIH, and IOL

 What are these values (IIL, IOH, IIH, and IOL) telling us?
- IOH: Maximum output current when at logic high (-0.4 mA).
- IOL: Maximum output current when at logic low (8.0 mA).
- IIH: Maximum input current when at logic high (0.1 mA).
- IIL: Maximum input current when at logic low (-0.4 mA).
- VOH: Maximum high voltage output (2.7V - 3.5V).
- VOL: Maximum output low voltage (0.35V - 0.5V).

 Compare these values from the data sheet with what you measured for I1, I2, I3, and I4?

Parameters Value from Data

Calculated value Differrence
Table
−2
IIL -1.6 mA −1.829 x 10 mA +1.58 mA
IOH -0.4mA −18.5 A -18.1 mA
−4
IIH 40 uA 6.2 x 10 mA -0.04 mA
IOL 16 mA 24.2 mA +8.2 mA
VOH 2.7V – 3.5V 4.9 V +1.4 V
VOL 0.2V – 0.4V 0.4V 0V

 Which configuration, that in figure 11 or that in figure 12, gave the brighter LED
display? Why?
The configuration in Figure 12 gives the LED brighter light because the current is taken
directly from the source and the low level is controlled by the IC.

ECE 271 LAB 2

COMBINATIONAL CIRCUIT DESIGN
THE UNIVERSITY OF DA NANG – FACULTY OF
ADVANCED SCIENCE AND TECHNOLOGY
Laboratory Part 2 – Working with Data Sheets and Real World Parts Again

Timing Measurements:
1. As a first step, using the data sheet for an SN 74LS04, find the vendor specified values for
these two propagation delays. Observe that a typical and a maximum value are given. What do
these mean?

- The vendor’s data sheet as PHL and PLH respectively. (The data sheet for an SN 74LS04)

- Observe that a typical and a maximum value are given. What do these mean?
 In a digital device, the times for an input signal to propagate through the device and
cause the output signal to change from a high to a low or vice versa.
 A typical and a maximum value are given these show the amount of time which must
occur after a signal is delivered for it to be received.

2. Next, configure the function generator to produce a 5 V, 100 KHz, square wave.
Using the oscilloscope, make certain that you have the offset and amplitude set correctly

3. Connect the function generator to the SN 74LS04 as shown in figure 3.

 4. Using two scope probes, connect one to the gate’s input and the other to its output.
Measure and record the values for PHL and PLH. Compare the values you have measured
with those from the data sheet.

 The value of the turn-off delay is: 𝜏𝑃𝐿𝐻 = 93.3ns

 Hence, the value of the turn-on delay is: 𝜏𝑃𝐻𝐿 = 82.4ns

*Compare the values you have measured with those from the data sheet for an SN 74LS04.
 𝜏𝑃𝐿𝐻 > 𝜏𝑃𝐻𝐿
 We can easily observe that the value of two propagation delays in real world
are larger than the value in the data sheet of the vendor.
  Because:
+ Having high frequency, it can cause the propagation delay values to
differ from what is specified in the datasheet.
+ Electronic components can experience aging and degradation due to
factors such as temperature, humidity, and usage.

5. Using the oscilloscope, now measure and record the rise and fall times of the output
of the SN 74LS04. These measurements are made at the 10% and 90% points in the signal
as we see in figure 5. Record the values you have measured. Do the values seem
reasonable?

The value of the fall time of the output: ∆𝑡 = 98.5ns

 Hence, the value of the rise time of the output: ∆𝑡 = 91.3ns

Logic Reduction:
1. As a first step, draw a Karnaugh map (Qua???? I know, I know, we’ll get there) for
the circuit in figure 6.

*Truth Table:
SEL1 SEL2 A B Result
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
 0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

*K- map:

00 0 0 0
0 1 0 01
1 1 0 0
0 1 0 1
00

Group 1: SEL1 . A . B
Group 2: SEL1 . SEL2 . B
Group 3: SEL1 . SEL2 . A
Group 4: SEL1 . SEL2 . A . B
Group 5: SEL1 . SEL2 . A . B

Sum of products:
Result = SEL1 . A . B + SEL1 . SEL2 . B + SEL1 . SEL2 . A + SEL1 . SEL2 . A . B + SEL1 . SEL2 . A . B
= SEL1 . SEL2 . (A + B) + SEL1 . SEL2 . (A + B) + SEL1 . A . B
 2. From the Karnaugh map you just drew, can you see any way to swap only two of the
selection lines such that the logic for this circuit can be minimized? Why can we do this?

From the Kmap, by swapping the positions of rows 2 and 3, the logic of this circuit will be
minimized.

00 0 0 0
1 1 0 0
0 1 0 1
0 1 0 1
00

Group 1: SEL1 . A . B
Group 2: SEL1 . SEL2 . A
Group 3: SEL1 . SEL2 . A
Sum of products:
Result = SEL1 . A . B + SEL1 . SEL2 . A + SEL1 . SEL2 . A

Draw a circuit diagram for this reduced circuit.

*Create a new Verilog source file for your revised design run a simulation.
 Laboratory Part 3 – Executing a Design from a Set of Requirements
Design
Draw a block diagram for your system. Clearly identify all inputs and outputs.
Inputs
1. SYSON: the photographic system is turned on.
2. TAKE: capture the currently selected image.
3. SELFLASH: enable the advanced built-in light system.
4. NOFLASH: sensor that detects that the use of artificial lighting is
prohibited.
5. ~INFOCUS: sensor that detects if the image is in focus.
6. ~LOWLIGHT: sensor that detects a low ambient light condition.

- The inputs SYSON, TAKE, SELFLASH, and NOFLASH, are active high.
- The inputs, ~INFOCUS and ~LOWLIGHT are active low.

Outputs
- Four outputs, ~CAPTURE, ~OUTOFFOCUS, ~FLASH, and
~THERMONUCLEAR DEVICE

All outputs are low true – asserted low.

 Verilog source code:

 Simulate:
  True table:
 INPUT OUTPUT
SYSO TAK SEFLAS NOFLAS THERMONUCLE FLAS OUTOFFOCU CAPTUR
N E H H AR H S E
0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 1
0 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1
0 1 0 1 1 1 1 1
0 1 1 0 1 1 1 1
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 1
1 1 0 0 1 1 0 1
1 1 0 1 1 1 0 1
1 1 1 0 1 0 0 1
1 1 1 1 0 1 0 1
  K-map:

~ THERMONUCLEAR = 𝑆𝑌𝑆𝑂𝑁 + 𝑇𝐴𝐾𝐸 + 𝑆𝐸𝐿𝐹𝐿𝐴𝑆𝐻 + 𝑁𝑂𝐹𝐿𝐴𝑆𝐻

~ FLASH

~ FLASH = S𝑌𝑆𝑂𝑁 + 𝑇𝐴𝐾𝐸 + 𝑆𝐸𝐿𝐹𝐿𝐴𝑆𝐻 + 𝑁𝑂𝐹𝐿𝐴𝑆

~ OUTOFFOCUS
~ OUTOFFOCUS = 𝑆𝐸𝐿𝐹𝐿𝐴𝑆𝐻 + 𝑁𝑂𝐹𝐿𝐴𝑆𝐻

~ CAPTURE

~ CAPTURE = 1