Bhoj Reddy Engineering College for Women

IV B Tech I Sem Objective Question Bank

Branch and Section: ECE A, B & C Subject: VLSI Design
Units III,IV and V

1. The subsystem of the circuits should have ______ interdependence

a) minimum
b) maximum
c) no
d) more
2. Switch logic is based on
a) pass transistors
b) transmission gates
c) pass transistors and transmission gates
d) design rules
3. The switch logic approach takes _____ static current
a) low
b) more
c) no
d) very less
4. Power dissipation in switch logic is
a) less
b) more
c) high
d) very less
5. Pass transistor can be driven through _____ pass transistors
a) one
b) no
c) more
d) two
6. When one pass transistor is driven using another, threshold voltage
a) affects
b) does not affect
7. VLSI design is done in ____ approach
a) top-down
b) bottom-up
c) random
d) semi random
8. Which gate is faster?
a) AND
b) NAND
c) NOR
d) OR
9. For a pseudo nMOS design the impedance of pull up and pull down ratio is
a) 4:1
b) 1:4
 c) 3:1
d) 1:3
10.In Pseudo-nMOS logic, n transistor operates in
a) cut off region
b) saturation region
c) resistive region
d) non saturation region
11.The power dissipation in Pseudo-nMOS is reduced to about ____
compared to nMOS device
a) 50%
b) 30%
c) 60%
d) 70%
12.In dynamic CMOS logic _____ is used
a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
13.In clocked CMOS logic, output in evaluated in
a) on period
b) off period
c) both periods
d) half of on period
14.In clocked CMOS logic, rise time and fall time are
a) faster
b) slower
c) faster first and then slows down
d) slower first and then speeds up
15.In CMOS domino logic _____ is used
a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
16.CMOS domino logic is same as ______ with inverter at the output line
a) clocked CMOS logic
b) dynamic CMOS logic
c) gate logic
d) switch logic
17.CMOS domino logic occupies
a) smaller area
b) larger area
c) both of the mentioned
d) none of the mentioned
18.CMOS domino logic has
a) smaller parasitic capacitance
b) larger parasitic capacitance
c) low operating speed
d) very large parasitic capacitance
19.In CMOS domino logic _______ is possible
a) inverting structure
b) non inverting structure
 c) inverting and non inverting structure
d) very complex design
20.To minimize the design effort, regularity should be
a) low
b) high
c) very low
d) very high
21.Regularity is the ratio of
a) total transistors in the chip to total transistors that must be designed in
detail
b) total transistors that must be designed in detail to total transistors in
chip
c) total transistors to total components
d) total charge storage components to charge dissipating components
22.In the adder, sum is stored in
a) series
b) cascade
c) parallel
d) registers
23.The shifter must be connected to
a) 2-shift data line
b) 2-shift control line
c) 4-shift data line
d) 4-shift control line
24.In adders, the previous carry can also be given by
a) propogate signal pk
b) generate signal gk
c) pk and gk
d) sk
25.Adder using ____ technology can be used for speed improvement
a) CMOS
b) BiCMOS
c) nMOS
d) pMOS
26.For carry skip adder, the minimum total propogation delay can be
obtained when m is
a) sqrt (nk1/k2)
b) sqrt (2nk1/k2)
c) sqrt (2k1/nk2)
d) sqrt (nk1k2/2)
27.Multiple output domino logic has
a) two cell manchester carry chain
b) three cell manchester carry chain
c) four cell manchester carry chain
d) four cell manchester carry look ahead
28.Multipliers are built using
a) binary adders
b) binary subtractors
c) dividers
d) multiplexers
29.Which method uses reduced number of partial products?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
30.Which method is easier to manipulate accumulator content?
a) left shifting
b) right shifting
c) serial shifting
d) parallel shifting
31.Which multiplier is very well suited for twos complement numebers?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
32.The completion time for multiplication time in baugh-wooley method is
a) n
b) 2n
c) 3n
d) 4n
33.In which method minimum number of adder cells are used?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
34.The overall delay of nMOS inverter pair is
a) 4Ʈ
b) Ʈ
c) 5Ʈ
d) 2Ʈ
35.Rise time and fall time is _____ to load capacitance CL
a) directly proportional
b) inversely proportonal
c) exponentially equal
d) not related
36.The total resistance can be given as
a) nRs
b) nrRs
c) rRs
d) Rs
37.Buffer is used because
a) it increases the speed
b) decreases senstivity to noise
c) decreases speed
d) does not affect speed
38.The overall delay is ______ to the relative resistance r
a) directly proportional
b) inversely proportional
c) exponentially proportional
d) not dependent
39.The capacitances in MOSFET occurs due to:
a) Interconnects
b) Difference in Doping concentration
c) Difference in dopant materials
d) All of the mentioned
40.The capacitance that exist between Gate and Bulk is called as:
a) Oxide parasitic capacitance
b) Metal oxide capacitance
c) MOS capacitance
d) None of the mentioned
41.Interconnect capacitance is formed due to:
a) Junction capacitance between gate and substrate
b) Wire connecting the gates of 2 different inverters
c) Parasitic capacitance existing between metal and polysilicon connection
between 2 inverters
d) All of the mentioned
42.Which of the following parameters are affected using load capacitance:
a) Delay time
b) Power consumption
c) Speed of the CMOS logic
d) All of the mentioned
43.Gate logic is also called as
a) transistor logic
b) switch logic
c) complementary logic
d) restoring logic
44.In CMOS NAND gate, p transistors are connected in
a) series
b) parallel
c) cascade
d) random
45.BiCMOS is used for ____ fan-out
a) less
b) more
c) no
d) very less
46.Which can handle high capacitance load?
a) NAND
b) nMOS NAND
c) CMOS NAND
d) BiCMOS NAND
47.Flash memory is a non-volatile storage device in which data
a) can be erased physically
b) can be erased magnetically
c) can be erased electrically
d) cannot be erased
48.The addition of ______ improves the observability
a) adders
b) multiplexers
c) multipliers
d) demultiplexers
49.Built-in self test aims to
a) reduce test pattern generation cost
b) reduce volume of test data
c) reduce test time
d) all of the mentioned
50.Which fault causes output floating?
a) stuck-open
b) stuck-at
c) stuck-on
d) IDDQ
51.IDDQ fault occurs when there is
a) increased voltage
b) increased quiescent current
c) increased power supply
d) increased discharge
52.Which relation is correct?
a) failure – error – fault
b) fault – error – failure
c) error – fault – failure
d) error – failure – fault
53.Which are processing faults?
a) missing contact window
b) parasitic transistor
c) oxide breakdown
d) all of the mentioned
54.The functions performed during chip testing are:
a) Detect faults in fabrication.
b) Detect faults in design
c) Failures in functionality
d) All of the mentioned
55.ATPG stands for:
a) Attenuated Transverse wave Pattern Generation
b) Automatic Test Pattern Generator
c) Aligned Test Parity Generator
d) None of the mentioned
56.Delay fault is considered as:
a) Electrical fault
b) Logical fault
c) Physical defect
d) None of the Mentioned
57.The fault simulation detects faults by:
a) Test generation
b) Construction of fault Dictionaries
c) Design analysis under faults
d) All of the mentioned
58.The ease with which the controller establish specific signal value at each
node by setting input values is known as:
a) Testability
b) Observability
c) Controllability
d) Manufacturability
59.The poor controllability circuits are:
a) Decoders
b) Clock generators
c) Circuits with feedback
d) All of the mentioned
60.The circuits with poor observability are:
a) ROM
b) PLA
c) Sequential circuits with long feedback loops
d) All of the mentioned

Fill In The Blanks

1. Refresh cycle is required in _______________ memory.
Ans: DRAM

2. Standard Cells in CBIC are ____________.

Ans: Flexible blocks

3. Standard cells can be placed __________ on the chip.

Ans: Anywhere

4. __________ Memory cell consists of bi-stable flip flop.

Ans: DRAM

5. Power buses are also known as ___________.

Ans: Rails

6. Connecting _______ to form a ________ results in faster and denser

layout using standard cells.
Ans: Datapath Cells, Datapath

7. The small squares on the edge of the cell are raised for__________.
Ans: Connecting to pins

8. In Carry save multiplier, the carry bit is passed ___________.

Ans: Diagonally

9. Device sizes in gate array are __________.

Ans: Fixed

10.Predesigned logic cells are known as ___________.

Ans: Standard Cells
11.__________ are programmable in FPGA.
Ans: Interconnects

12.In PAL, OR array is __________ and AND array is __________.

Ans: Fixed, Programmable
13. A ______________ uses a cascade of pass transistors to implement the
carry chain.
Ans: Manchester carry chain

14.The delay in the addition operation can be reduced by using ________

property.
Ans: Inverting

15. In __________ adder, every full adder cell has to wait for the incoming
carry before an outgoing carry can be generator.
Ans: Ripple carry adder

16._____________ Test is used to find the faults in interconnects.

Ans: Boundary scan

17.DRAM is made up of ______ and ________.

Ans: NMOS transistor, capacitor

18. DRAM has to be ________ to retain logic.

Ans: refreshed

19.___________ test is defined by IEEE 1149.1 standard.

Ans: Boundary Scan

20. BILBO stands for ___________

Ans: Built in logic block observation

21. BIST stands for ________

Ans: Built in self test

22.__________ technique increases observability and controllability.

Ans: Adhoc DFT

23.____________ is defined as the capability of a node being driven to 1 or

0 through the circuit’s inputs.
Ans: controllability

24._______________ are the examples of fault models.

Ans: Stuck at faults and short/ open circuit faults.

25.________________ are the disadvantages of BIST.

Ans: Reduced access times, additional silicon area

26.Yield rate is defined as _________________

Ans: No of acceptable parts/ total no of parts fabricated.

27.___________ is an example of Psedo random pattern generator.

Ans: LFSR

28. LFSR stands for ____________.

Ans: Linear feedback shift register.
29.____________ based FPGAs are one time programmable.
Ans: Antifuse

30.In ___________ testing, every entry in the truth table is verified.

Ans: Functional

31.A _________ is a flaw or physical imperfection that may lead to a fault.

Ans: defect

32.A __________ is a representation of a defect reflecting a physical

condition that causes a circuit to fail.
Ans: Fault

33.__________ testing involves testing the circuit with all possible input
patterns.
Ans: Exhaustive

34.A _________ is a deviation in the performance of a circuit or system from

its specified behaviour.
Ans: Failure

35.VHDL stands for __________

Ans: Very high speed integrated circuit hardware description language

Solutions:
1 B 21 A 41 C
2 C 22 C 42 D
3 C 23 D 43 D
4 A 24 C 44 B
5 B 25 B 45 B
6 A 26 B 46 D
7 A 27 C 47 C
8 C 28 A 48 B
9 A 29 D 49 D
10 B 30 B 50 A
11 C 31 A 51 B
12 D 32 B 52 B
13 A 33 C 53 D
14 B 34 C 54 D
15 C 35 A 55 B
16 B 36 B 56 B
17 A 37 A 57 D
18 A 38 A 58 C
19 B 39 D 59 D
20 B 40 A 60 C