4 Digital Logic (273)

Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed
and floating point)

Mark Distribution in Previous GATE

Year 2021-1 2021-2 2020 2019 2018 2017-1 2017-2 2016-1 2016-2 Minimum Average Maximum
1 Mark Count 2 3 2 4 2 3 2 3 3 2 2.6 4
2 Marks Count 2 2 1 2 2 0 4 2 0 0 1.6 4
Total Marks 6 7 4 8 6 3 10 7 3 3 6 10

4.1 Adder (10) top☝

4.1.1 Adder: GATE CSE 1988 | Question: 4ii top☝ ☛ https://gateoverflow.in/94360

Using binary full adders and other logic gates (if necessary), design an adder for adding 4-bit number (including sign) in 2′ s
complement notation.

gate1988 digital-logic descriptive adder

Answer ☟

4.1.2 Adder: GATE CSE 1990 | Question: 1-i top☝ ☛ https://gateoverflow.in/83829

Fill in the blanks:

In the two bit full-adder/subtractor unit shown in below figure, when the switch is in position 2 ___________ using _________
arithmetic.

gate1990 digital-logic adder fill-in-the-blanks

Answer ☟

4.1.3 Adder: GATE CSE 1993 | Question: 9 top☝ ☛ https://gateoverflow.in/2306

Assume that only half adders are available in your laboratory. Show that any binary function can be implemented using half
adders only.

gate1993 digital-logic combinational-circuits adder descriptive

Answer ☟

4.1.4 Adder: GATE CSE 1997 | Question: 2.5 top☝ ☛ https://gateoverflow.in/2231

An N-bit carry lookahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 ( 4 bit carry
lookahead generator).

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 The minimum addition time using the best architecture for this adder is
A. proportional to N
B. proportional to log N
C. a constant
D. None of the above

gate1997 digital-logic normal adder

Answer ☟

4.1.5 Adder: GATE CSE 1999 | Question: 2.16 top☝ ☛ https://gateoverflow.in/1494

The number of full and half-adders required to add 16-bit numbers is

A. 8 half-adders, 8 full-adders
B. 1 half-adder, 15 full-adders
C. 16 half-adders, 0 full-adders
D. 4 half-adders, 12 full-adders

gate1999 digital-logic normal adder

Answer ☟

4.1.6 Adder: GATE CSE 2003 | Question: 46 top☝ ☛ https://gateoverflow.in/937

Consider the ALU shown below.

If the operands are in 2′ s complement representation, which of the following operations can be performed by suitably setting the
control lines K and C0 only (+ and – denote addition and subtraction respectively)?
A. A + B , and A– B, but not A + 1
B. A + B , and A + 1 , but not A– B
C. A + B , but not A– B or A + 1
D. A + B , and A– B, and A + 1

gate2003-cse digital-logic normal adder

Answer ☟

4.1.7 Adder: GATE CSE 2004 | Question: 62 top☝ ☛ https://gateoverflow.in/1057

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only.
Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time

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 unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level
AND-OR logic.
A. 4 time units
B. 6 time units
C. 10 time units
D. 12 time units

gate2004-cse digital-logic normal adder

Answer ☟

4.1.8 Adder: GATE CSE 2015 Set 2 | Question: 48 top☝ ☛ https://gateoverflow.in/8250

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate.
The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2
microseconds. A 4-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit
binary adder in microseconds is ______.

gate2015-cse-set2 digital-logic adder normal numerical-answers

Answer ☟

4.1.9 Adder: GATE CSE 2016 Set 1 | Question: 33 top☝ ☛ https://gateoverflow.in/39688

Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform
addition using this adder is

A. Θ(1)
B. Θ(log(n))
C. Θ(√−n)
D. Θ(n) )

gate2016-cse-set1 digital-logic adder normal

Answer ☟

4.1.10 Adder: GATE CSE 2016 Set 2 | Question: 07 top☝ ☛ https://gateoverflow.in/39575

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2's
complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize
is ___________

gate2016-cse-set2 digital-logic adder normal numerical-answers

Answer ☟

Answers: Adder

4.1.1 Adder: GATE CSE 1988 | Question: 4ii top☝ ☛ https://gateoverflow.in/94360


Overflow condition in
2′ s complement number system:-

1. c3 = 1, c4 =1 ⟹ No overflow
2. c3 = 0, c4 =0 ⟹ No overflow
3. c3 = 1, c4 =0 ⟹ Overflow (a3 = b3 = 0)
4. c3 = 0, c4 =1 ⟹ Overflow (a3 = b3 = 1)

We can conclude that the overflow condition for 2′ s complement number system is:

c3 ⊕ c4 = 1(OR)a¯3 ⋅ b¯3 ⋅ s3 + a3 ⋅ b3 ⋅ s¯3 = 1

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 Here, we used 4 − bit binary full adder and Ex-OR gate.
The Ex-OR gate is used to check the overflow condition.

 10 votes -- Lakshman Patel (65.7k points)

4.1.2 Adder: GATE CSE 1990 | Question: 1-i top☝ ☛ https://gateoverflow.in/83829


When the switch is at position 2, it is connected to Vcc thus, the value of control input M = 1 which is fed to XOR gates
as well. So
¯¯¯¯¯¯
B1 ⊕ 1 = B1 and
¯¯¯¯¯¯
B0 ⊕ 1 = B0

And the basic hardware is of adder only.

Now Cin is connected to Vcc as well. Hence, Cin = 1.
¯¯¯¯¯¯
Net operation can be denoted as : S0 = A0 + B0 + 1 and similarly for S1 as well.
¯¯¯¯¯¯
This is nothing but an expression of subtraction using 2′ s complement. ( Had it been A0 + B0 , it would have been addition of
1′ s complement merely, but for subtraction we need to have 2′ s complement of other operand which is B here)
Hence, the correct answer should be : subtraction, 2's complement

 34 votes -- HABIB MOHAMMAD KHAN (67.5k points)

4.1.3 Adder: GATE CSE 1993 | Question: 9 top☝ ☛ https://gateoverflow.in/2306


Half Adder gives two outputs:

S = A⊕B
C = A. B

We can perform any operation using Half adder if we can implement basic gates using half adder.

AND operation C = A. B
Not operation = S(with A and 1) = A ⊕ 1 = A′ .1 + A.1′ = A′
OR operation = ((A ⊕ 1). (B ⊕ 1)) ⊕ 1 = (A′ . B′ )′ = A + B

 26 votes -- Praveen Saini (41.9k points)

4.1.4 Adder: GATE CSE 1997 | Question: 2.5 top☝ ☛ https://gateoverflow.in/2231


For N = 64 bits .

Suppose you want to build a 64 bit adder then you need 16 4-bit ALU and 16 4-bit carry generator, at this point there will be 16
carries that will ripple through these 16 ALU modules, to speed up the adder we need to get rid of these 16 rippling carries, now
we can again use 4 4-bit carry generator to generate these 16 carries, now we have only 4 carries to ripple through, again we can
use the same trick to minimize the rippling of these 4 carries, we can use an additional 4-bit carry generator which will generate
these carry and we are done :) there will be no more propagation of carry among the ALU modules.

So, we have used 3 level of 4-bit carry generator, and the time taken to add 64 bits will be proportional to 3 which is log4 64 .

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 So, in general to add N – bits it takes log4 N time.

Correct Answer: B
 44 votes -- Vikrant Singh (11.2k points)

4.1.5 Adder: GATE CSE 1999 | Question: 2.16 top☝ ☛ https://gateoverflow.in/1494


Answer is B.

For LSB addition we do not need a full adder.

For addition of subsequent bits we need full adders since carry from previous addition has to be fed into the addition operation.
 55 votes -- Ankit Rokde (6.9k points)

4.1.6 Adder: GATE CSE 2003 | Question: 46 top☝ ☛ https://gateoverflow.in/937


Correct Option: A
There are two control line one is K and another is C0 .

When K = 1 , C0 = 1 we can perform A − B

When K = 0 , C0 = 0 we can perform A + B

But without manipulating B(B0 , B1 , …) we cannot perform A+1. But here we have only two control lines which is K, C0 .
Therefore the answer is A.

Note:
For A+B : C0 = 0 , K = 0 , and 0 ⊕ x = x

A3 A2 A1 A0
+ B3 B2 B1 B0
S3 S2 S1 S0

C3 C2 C1 C0=0
A3 A2 A1 A0
+ B3 B2 B1 B0
Sum Output: S3 S2 S1 S0
Carry Output: C4 C3 C2 C1

For A-B : C0 = 1 , K = 1 , and 1 ⊕ x = x̄

given that numbers are in 2's complement representations, So A - B = A + 2's complement of B
How to get 2's complement of B ?
2's complement of B = 1's complement of B + 1
So, by keeping K=1, we get 1's complement of B and By keeping C 0 = 1, we are adding 1 to 1's complement of B.

 41 votes -- Riya Roy(Arayana) (5.3k points)

4.1.7 Adder: GATE CSE 2004 | Question: 62 top☝ ☛ https://gateoverflow.in/1057


It would take 6 time units.
We know that:
G i = A i Bi ,
Pi = Ai ⊕ Bi and
Si = Pi ⊕ Ci
Also
C1 = G0 + P0 C0
C2 = G1 + P1 G0 + P1 P0 C0

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 C3 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
XOR can be implemented in 2 levels; level-1 ANDs and Level-2 OR. Hence it would take 2 time units to calculate Pi and Si
The 4-bit addition will be calculated in 3 stages
1. (2 time units) In 2 time units we can compute Gi and Pi in parallel. 2 time units for Pi since its an XOR operation and 1
time unit for Gi since its an AND operation.
2. (2 time units) Once Gi and Pi are available, we can calculate the caries, Ci , in 2 time units.
Level-1 we compute all the conjunctions (AND). Example P3 G2 , P3 P2 G1 , P3 P2 P1 G0 and P3 P2 P1 P0 C0 which are required
for C4 .
Level-2 we get the carries by computing the disjunction (OR).
3. (2 time units) Finally we compute the Sum in 2 time units, as its an XOR operation.
Hence, the total is 2 + 2 + 2 = 6 time units.

 133 votes -- ryan sequeira (3k points)

4.1.8 Adder: GATE CSE 2015 Set 2 | Question: 48 top☝ ☛ https://gateoverflow.in/8250

S1 should wait for C1 to be ready. Delay for generating C is 1 EXOR +1 AND +1 OR = 2.4 + 1.2 + 1.2 = 4.8 μs
Delay for sum is XOR + XOR = 2.4 + 2.4 = 4.8μs
But for the second adder, there the first EXOR can be done even before waiting for the previous output. So, we can get the sum
in Another 2.4μs and carry in another 2.4μs . In this way, 4-bit sum can be obtained after
4.8μs + 3 ∗ 2.4μs = 12μs.
But the question says we use ripple-carry adder. So, each adder must wait for the full output from the previous adder. This would
make the total delay = 4 ∗ 4.8 = 19.2μs and this is the key given by GATE, so obviously they meant this.

 116 votes -- Arjun Suresh (332k points)

4.1.9 Adder: GATE CSE 2016 Set 1 | Question: 33 top☝ ☛ https://gateoverflow.in/39688


Look ahead carry generator gives output in constant time if fan in = number of inputs.
Example, it will take O(1) to calculate c4 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 c0 , if OR gate with 5 inputs is
present.
If we have 8 inputs, and OR gate with 2 inputs, to build an OR gate with 8 inputs, we will need 4 gates in level-1, 2 in level- 2
and 1in level- 3. Hence, 3 gate delays, for each level.
Similarly an n-input gate constructed with 2-input gates, total delay will be O(log n).
Hence, answer is option B.

 103 votes -- ryan sequeira (3k points)

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 4.1.10 Adder: GATE CSE 2016 Set 2 | Question: 07 top☝ ☛ https://gateoverflow.in/39575


Answer is -1.

In case of -1 we get bit sequence 11111111 adding this we get a carry upto carry flag, so largest time to ripple!
 57 votes -- viv696 (1.7k points)

4.2 Array Multiplier (2) top☝

4.2.1 Array Multiplier: GATE CSE 1999 | Question: 1.21 top☝ ☛ https://gateoverflow.in/1474

The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit numbers is

A. O(n2 )
B. O(n)
C. O(log n)
D. O(1)

gate1999 digital-logic normal array-multiplier

Answer ☟

4.2.2 Array Multiplier: GATE CSE 2003 | Question: 11 top☝ ☛ https://gateoverflow.in/902

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of
the multiplier is

A. Θ(1)
B. Θ(log n)
C. Θ(n)
D. Θ(n2 )

gate2003-cse digital-logic normal array-multiplier

Answer ☟

Answers: Array Multiplier

4.2.1 Array Multiplier: GATE CSE 1999 | Question: 1.21 top☝ ☛ https://gateoverflow.in/1474


In an N × M array multiplier we have N × M AND gates and (M − 1), N − bit adders are used.

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 Total delay in N × M(N ≥ M) array multiplier due to AND gate in partial products at all level is just 1 unit AND gate delay
as the operation is done parallel wise at each step. Now delays at level 1 to (M − 1) = (M − 1)× delay due to 1 unit of
N − bit adder. Therefore the maximum gate delay is O(M) but here M = N ∴ O(N).

http://www.dauniv.ac.in/downloads/CArch_PPTs/CompArchCh03L06ArrayMult.pdf or archive
Refer this article page 16.
Correct Answer: B
References

 23 votes -- Riya Roy(Arayana) (5.3k points)

© Copyright GATE Overflow. Some rights reserved.

 4.2.2 Array Multiplier: GATE CSE 2003 | Question: 11 top☝ ☛ https://gateoverflow.in/902

© Copyright GATE Overflow. Some rights reserved.

 Now to MULTIPLY these two Numbers:

1. 4 AND GATEs REQUIRED B0 MULTIPLY WITH A3 A2 A1 A0 .

2. 4 AND GATEs REQUIRED B1 MULTIPLY WITH A3 A2 A1 A0 .
3. 4 BIT ADDER
4. 4 AND GATEs REQUIRED B2 MULTIPLY WITH A3 A2 A1 A0 .
5. 4 BIT ADDER
6. 4 AND GATEs REQUIRED B3 MULTIPLY WITH A3 A2 A1 A0 .
7. 4 BIT ADDER

For 4 bits, Total Delay= 3 + 4 = 7

For n bits, Total Delay= n − 1 + n = 2n − 1

So, Total Delay = Θ(n).

Correct Answer: C

 52 votes -- Vidhi Sethi (8.3k points)

4.3 Binary Codes (2) top☝

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 4.3.1 Binary Codes: GATE CSE 2006 | Question: 40 top☝ ☛ https://gateoverflow.in/1816

Consider numbers represented in 4-bit Gray code. Let h3 h2 h1 h0 be the Gray code representation of a number n and let
g3 g2 g1 g0 be the Gray code of (n + 1)(modulo16) value of the number. Which one of the following functions is correct?

A. g0 (h3 h2 h1 h0 ) = ∑(1, 2, 3, 6, 10, 13, 14, 15)

B. g1 (h3 h2 h1 h0 ) = ∑(4, 9, 10, 11, 12, 13, 14, 15)
C. g2 (h3 h2 h1 h0 ) = ∑(2, 4, 5, 6, 7, 12, 13, 15)
D. g3 (h3 h2 h1 h0 ) = ∑(0, 1, 6, 7, 10, 11, 12, 13)

gate2006-cse digital-logic number-representation binary-codes normal

Answer ☟

4.3.2 Binary Codes: GATE CSE 2017 Set 2 | Question: 34 top☝ ☛ https://gateoverflow.in/118376

Consider the binary code that consists of only four valid codewords as given below:
00000, 01011, 10101, 11110
Let the minimum Hamming distance of the code p and the maximum number of erroneous bits that can be corrected by the code be
q . Then the values of p and q are
A. p = 3 and q = 1
B. p = 3 and q = 2
C. p = 4 and q = 1
D. p = 4 and q = 2

gate2017-cse-set2 digital-logic binary-codes

Answer ☟

Answers: Binary Codes

4.3.1 Binary Codes: GATE CSE 2006 | Question: 40 top☝ ☛ https://gateoverflow.in/1816


The answer is C.

Decimal n Binary n H(x) =Gray(n) G(x) =Gray[(n + 1) mod 16]

0 0000 0000(00) 0001
1 0001 0001(01) 0011
2 0010 0011(03) 0010
3 0011 0010(02) 0110
4 0100 0110(06) 0111
5 0101 0111(07) 0101
6 0110 0101(05) 0100
7 0111 0100(04) 1100
8 1000 1100(12) 1101
9 1001 1101(13) 1111
10 1010 1111(15) 1110
11 1011 1110(14) 1010
12 1100 1010(10) 1011
13 1101 1011(11) 1001
14 1110 1001(09) 1000
15 1111 1000(08) 0000

We need to map min terms of g3 g2 g1 g0 with respect to h3 h2 h1 h0 .

Hence as highlighted g2 matches with option C.

Edit :
We have to map h(x) with g(x). Mod 16 is used in g(x) only because since we have 4 bits, the maximum possible no that can
be represented is 15, so after 15 we shouldn't get 16 and go back to 0. that's why.
Now, mapping is simple. We just have to map such that h(x) → g(x + 1)
This means if h represents gray code of 0 then g will represent the gray code of 1

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 If h represents the gray code of 1 then g will represent 2 and so on.
For the last number h(15) mod 16 actually comes into the picture which will make it represent as g(0)
So, drawing the table as mentioned above.
Now, write g as a function of f . Simply how we do minimization. See the minterms.
Be careful only in one thing here.
An example for 2 gray code representations is 0011 meaning 3 in decimal. So, if we select this row as a minterm(just an
example) then we have selected 3 and not 2, means row numbers are not representing minterms. Rest everything is fine!

 66 votes -- ryan sequeira (3k points)

4.3.2 Binary Codes: GATE CSE 2017 Set 2 | Question: 34 top☝ ☛ https://gateoverflow.in/118376


00000(code1), 01011(code2), 10101(code3), 11110 (code4)
Haming distance = min of all hamming distances.
Which is 3 b/w (code1) and (code2) so,
p=3
Now to correct d bit error we need hamming distance = 2d + 1
So, 2d + 1 = 3 will gives d = 1 .
A is answer.

 41 votes -- Prashant Singh (47.2k points)

4.4 Boolean Algebra (31) top☝

4.4.1 Boolean Algebra: GATE CSE 1987 | Question: 1-II top☝ ☛ https://gateoverflow.in/80032

The total number of Boolean functions which can be realised with four variables is:
A. 4
B. 17
C. 256
D. 65, 536

gate1987 digital-logic boolean-algebra functions combinatory

Answer ☟

4.4.2 Boolean Algebra: GATE CSE 1987 | Question: 12-a top☝ ☛ https://gateoverflow.in/82556

The Boolean expression A ⊕ B ⊕ A is equivalent to

¯¯¯¯
A. AB + A ¯B
¯¯¯
¯¯¯¯ ¯¯¯¯
B. A B+A B
C. B
¯¯¯¯
D. A

gate1987 digital-logic boolean-algebra easy

Answer ☟

4.4.3 Boolean Algebra: GATE CSE 1988 | Question: 2-iii top☝ ☛ https://gateoverflow.in/91679

¯¯ ȳ
Let ∗ be defined as a Boolean operation given as x ∗ y = x̄ ¯¯ + xy and let C = A ∗ B . If C = 1 then prove that A = B .

gate1988 digital-logic descriptive boolean-algebra

Answer ☟

4.4.4 Boolean Algebra: GATE CSE 1989 | Question: 4-x top☝ ☛ https://gateoverflow.in/88166

A switching function is said to be neutral if the number of input combinations for which its value is 1 is equal to the number of

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 input combinations for which its value is 0. Compute the number of neutral switching functions of n variables (for a given n).

gate1989 descriptive digital-logic boolean-algebra

Answer ☟

4.4.5 Boolean Algebra: GATE CSE 1989 | Question: 5-a top☝ ☛ https://gateoverflow.in/88230

Find values of Boolean variables A, B, C which satisfy the following equations:

A+ B = 1
AC = BC
A+C=1
AB = 0

gate1989 descriptive digital-logic boolean-algebra

Answer ☟

4.4.6 Boolean Algebra: GATE CSE 1992 | Question: 02-i top☝ ☛ https://gateoverflow.in/555

The operation which is commutative but not associative is:

A. AND
B. OR
C. EX-OR
D. NAND

gate1992 easy digital-logic boolean-algebra multiple-selects

Answer ☟

4.4.7 Boolean Algebra: GATE CSE 1994 | Question: 4 top☝ ☛ https://gateoverflow.in/2500

¯¯¯¯ ¯¯¯¯
A. Let ∗ be a Boolean operation defined as A ∗ B = AB + A B . If C = A ∗ B then evaluate and fill in the blanks:
i. A ∗ A = ______
ii. C ∗ A = ______
B. Solve the following boolean equations for the values of A, B and C :
¯¯¯¯
AB + AC = 1
AC + B = 0

gate1994 digital-logic normal boolean-algebra descriptive

Answer ☟

4.4.8 Boolean Algebra: GATE CSE 1995 | Question: 2.5 top☝ ☛ https://gateoverflow.in/2617

What values of A, B, C and D satisfy the following simultaneous Boolean equations?

¯¯¯¯ ¯¯¯¯ ¯¯¯¯
A + AB = 0, AB = AC, AB + AC + CD = C D
A. A = 1, B = 0, C = 0, D = 1
B. A = 1, B = 1, C = 0, D = 0
C. A = 1, B = 0, C = 1, D = 1
D. A = 1, B = 0, C = 0, D = 0

gate1995 digital-logic boolean-algebra easy

Answer ☟

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 4.4.9 Boolean Algebra: GATE CSE 1997 | Question: 2-1 top☝ ☛ https://gateoverflow.in/2227

Let ∗ be defined as x ∗ y = x̄ + y . Let z = x ∗ y . Value of z ∗ x is

A. x̄ + y
B. x
C. 0
D. 1

gate1997 digital-logic normal boolean-algebra

Answer ☟

4.4.10 Boolean Algebra: GATE CSE 1998 | Question: 1.13 top☝ ☛ https://gateoverflow.in/1650

What happens when a bit-string is XORed with itself n-times as shown:

[B ⊕ (B ⊕ (B ⊕ (B … n times]
A. complements when n is even
B. complements when n is odd
C. divides by 2n always
D. remains unchanged when n is even

gate1998 digital-logic normal boolean-algebra

Answer ☟

4.4.11 Boolean Algebra: GATE CSE 1998 | Question: 2.8 top☝ ☛ https://gateoverflow.in/1680

Which of the following operations is commutative but not associative?

A. AND
B. OR
C. NAND
D. EXOR

gate1998 digital-logic easy boolean-algebra

Answer ☟

4.4.12 Boolean Algebra: GATE CSE 1999 | Question: 1.7 top☝ ☛ https://gateoverflow.in/1460

Which of the following expressions is not equivalent to x̄?

A. x NAND x
B. x NOR x
C. x NAND 1
D. x NOR 1

gate1999 digital-logic easy boolean-algebra

Answer ☟

4.4.13 Boolean Algebra: GATE CSE 2000 | Question: 2.10 top☝ ☛ https://gateoverflow.in/657

The simultaneous equations on the Boolean variables x, y, z and w,

x+y+z = 1
xy = 0
xz + w = 1
xy + z̄w̄ = 0

have the following solution for x, y, z and w, respectively:

A. 0 1 0 0
1101

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 B. 1 1 0 1
C. 1 0 1 1
D. 1 0 0 0

gate2000-cse digital-logic boolean-algebra easy

Answer ☟

4.4.14 Boolean Algebra: GATE CSE 2002 | Question: 2-3 top☝ ☛ https://gateoverflow.in/833

Let f(A, B) = A′ + B . Simplified expression for function f(f(x + y, y), z) is

A. x′ + z
B. xyz
C. xy′ + z
D. None of the above

gate2002-cse digital-logic boolean-algebra normal

Answer ☟

4.4.15 Boolean Algebra: GATE CSE 2004 | Question: 17 top☝ ☛ https://gateoverflow.in/1014

A Boolean function x′ y ′ + xy + x′ y is equivalent to

A. x′ + y′
B. x+y
C. x + y′
D. x′ + y

gate2004-cse digital-logic easy boolean-algebra

Answer ☟

4.4.16 Boolean Algebra: GATE CSE 2007 | Question: 32 top☝ ☛ https://gateoverflow.in/1230

Let f(w, x, y, z) = ∑ (0, 4, 5, 7, 8, 9, 13, 15) . Which of the following expressions are NOT equivalent to f ?
P: x′ y ′ z ′ + w′ xy ′ + wy ′ z + xz
Q: w′ y ′ z ′ + wx′ y ′ + xz
R: w′ y ′ z ′ + wx′ y ′ + xyz + xy ′ z
S: x′ y ′ z ′ + wx′ y ′ + w′ y
A. P only
B. Q and S
C. R and S
D. S only

gate2007-cse digital-logic normal boolean-algebra

Answer ☟

4.4.17 Boolean Algebra: GATE CSE 2007 | Question: 33 top☝ ☛ https://gateoverflow.in/1231

Define the connective ∗ for the Boolean variables X and Y as:

X ∗ Y = XY + X ′ Y ′ .

Let Z = X ∗ Y . Consider the following expressions P , Q and R.

P : X = Y ∗ Z, Q : Y = X ∗ Z, R : X ∗ Y ∗ Z = 1

Which of the following is TRUE?

A. Only P and Q are valid.
Q R

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 B. Only Q and R are valid.
C. Only P and R are valid.
D. All P , Q, R are valid.

gate2007-cse digital-logic normal boolean-algebra

Answer ☟

4.4.18 Boolean Algebra: GATE CSE 2008 | Question: 26 top☝ ☛ https://gateoverflow.in/424

If P, Q, R are Boolean variables, then

(P + Q̄)(P. Q̄ + P. R)(P¯. R̄ + Q̄) simplifies to

A. P. Q̄

B. P. R̄

C. P. Q̄ + R

D. P. R̄ + Q

gate2008-cse easy digital-logic boolean-algebra

Answer ☟

4.4.19 Boolean Algebra: GATE CSE 2012 | Question: 6 top☝ ☛ https://gateoverflow.in/38

X Y (X,Y)
0 0 0
The truth table 0 1 0 represents the Boolean function
1 0 1
1 1 1

A. X
B. X+Y
C. X⊕Y
D. Y

gate2012-cse digital-logic easy boolean-algebra

Answer ☟

4.4.20 Boolean Algebra: GATE CSE 2013 | Question: 21 top☝ ☛ https://gateoverflow.in/1532

Which one of the following expressions does NOT represent exclusive NOR of x and y?
A. xy + x'y'
B. x ⊕ y'
C. x' ⊕ y
D. x' ⊕ y'

gate2013-cse digital-logic easy boolean-algebra

Answer ☟

4.4.21 Boolean Algebra: GATE CSE 2014 Set 3 | Question: 55 top☝ ☛ https://gateoverflow.in/2090

Let ⊕ denote the exclusive OR (XOR) operation. Let '1' and '0' denote the binary constants. Consider the following Boolean
expression for F over two variables P and Q:

F(P, Q) = ((1 ⊕ P) ⊕ (P ⊕ Q)) ⊕ ((P ⊕ Q) ⊕ (Q ⊕ 0))

The equivalent expression for F is

A. P + Q
¯¯¯¯¯¯¯¯¯¯¯¯¯¯

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 ¯¯¯¯¯¯¯¯¯¯¯¯¯¯
B. P + Q
C. P ⊕ Q
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
D. P ⊕ Q

gate2014-cse-set3 digital-logic normal boolean-algebra

Answer ☟

4.4.22 Boolean Algebra: GATE CSE 2015 Set 1 | Question: 39 top☝ ☛ https://gateoverflow.in/8294

Consider the operations

f (X, Y, Z) = X'YZ + XY' + Y'Z' and g (X, Y, Z) = X'YZ + X'YZ' + XY
Which one of the following is correct?

A. Both {f} and {g} are functionally complete

B. Only {f} is functionally complete
C. Only {g} is functionally complete
D. Neither {f} nor {g} is functionally complete

gate2015-cse-set1 boolean-algebra difficult

Answer ☟

4.4.23 Boolean Algebra: GATE CSE 2015 Set 2 | Question: 37 top☝ ☛ https://gateoverflow.in/8162

The number of min-terms after minimizing the following Boolean expression is _______.

[D'+AB'+A'C+AC'D+A'C'D]'

gate2015-cse-set2 digital-logic boolean-algebra normal numerical-answers

Answer ☟

4.4.24 Boolean Algebra: GATE CSE 2016 Set 1 | Question: 06 top☝ ☛ https://gateoverflow.in/39629

Consider the Boolean operator # with the following properties :

¯¯,x#x=0 and x# x̄
x#0=x, x#1= x̄ ¯¯=1. Then x#y is equivalent to

A. xȳ¯¯ + x̄¯¯y
B. xȳ¯¯ + x̄¯¯ ȳ¯¯
C. x̄¯¯y + xy
D. xy + x̄¯¯ ȳ¯¯

gate2016-cse-set1 digital-logic boolean-algebra easy

Answer ☟

4.4.25 Boolean Algebra: GATE CSE 2016 Set 2 | Question: 08 top☝ ☛ https://gateoverflow.in/39540

Let, x1 ⊕ x2 ⊕ x3 ⊕ x4 = 0 where x1 , x2 , x3 , x4 are Boolean variables, and ⊕ is the XOR operator.

Which one of the following must always be TRUE?

A. x1 x2 x3 x4 = 0
B. x1 x3 + x2 = 0
C. x̄1 ⊕ x̄3 = x̄2 ⊕ x̄4
D. x1 + x2 + x3 + x4 = 0

gate2016-cse-set2 digital-logic boolean-algebra normal

Answer ☟

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 4.4.26 Boolean Algebra: GATE CSE 2017 Set 2 | Question: 27 top☝ ☛ https://gateoverflow.in/118494

If w, x, y, z are Boolean variables, then which one of the following is INCORRECT?

A. wx + w(x + y) + x(x + y) = x + wy
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
B. wx̄(y + z̄ ) + w̄x = w̄ + x + ȳ z
C. (wx̄(y + xz̄ ) + w̄x̄)y = xȳ
D. (w + y)(wxy + wyz) = wxy + wyz

gate2017-cse-set2 digital-logic boolean-algebra normal

Answer ☟

4.4.27 Boolean Algebra: GATE CSE 2018 | Question: 4 top☝ ☛ https://gateoverflow.in/204078

Let ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT
CORRECT?
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
A. P ⊕Q = P ⊙Q
¯¯¯¯
B. P ⊕Q = P ⊙Q
¯¯¯¯ ¯¯¯¯
C. P ⊕Q = P ⊕Q
¯¯¯¯ ¯¯¯¯ ¯¯¯¯
D. P ⊕ P ⊕ Q = (P ⊙ P ⊙ Q)

gate2018-cse digital-logic normal boolean-algebra

Answer ☟

4.4.28 Boolean Algebra: GATE CSE 2019 | Question: 6 top☝ ☛ https://gateoverflow.in/302842

Which one of the following is NOT a valid identity?

A. (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)
B. (x + y) ⊕ z = x ⊕ (y + z)
C. x ⊕ y = x + y, if xy = 0
D. x ⊕ y = (xy + x′ y′ )′

gate2019-cse digital-logic boolean-algebra

Answer ☟

4.4.29 Boolean Algebra: GATE CSE 2021 Set 1 | Question: 42 top☝ ☛ https://gateoverflow.in/357409

Consider the following Boolean expression.

¯¯¯¯ ¯¯¯¯
F = (X + Y + Z)(X + Y )(Y + Z)
¯¯¯¯
Which of the following Boolean expressions is/are equivalent to F (complement of F )?
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
A. (X + Y + Z )(X + Y )(Y + Z )
¯¯¯¯ ¯¯¯¯
B. XY + Z
¯¯¯¯ ¯¯¯¯ ¯¯¯¯
C. (X + Z )(Y + Z )
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯¯¯¯¯
D. XY + Y Z + X Y Z

gate2021-cse-set1 multiple-selects digital-logic boolean-algebra

Answer ☟

4.4.30 Boolean Algebra: GATE IT 2004 | Question: 44 top☝ ☛ https://gateoverflow.in/3687

The function AB̄C + ĀBC + ABC̄ + ĀB̄C + AB̄C̄ is equivalent to

A. AC̄ + AB + ĀC
B. AB̄ + AC̄ + ĀC
¯B + A ¯ + A ¯

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 C. ĀB + AC̄ + AB̄
D. ĀB + AC + AB̄

gate2004-it digital-logic boolean-algebra easy

Answer ☟

4.4.31 Boolean Algebra: GATE IT 2005 | Question: 7 top☝ ☛ https://gateoverflow.in/3752

Which of the following expressions is equivalent to (A ⊕ B) ⊕ C

A. (A + B + C)(Ā + B̄ + C̄ )
B. (A + B + C)(Ā + B̄ + C)
C. ABC + Ā(B ⊕ C) + B̄(A ⊕ C)
D. None of these

gate2005-it digital-logic normal boolean-algebra

Answer ☟

Answers: Boolean Algebra

4.4.1 Boolean Algebra: GATE CSE 1987 | Question: 1-II top☝ ☛ https://gateoverflow.in/80032


A Boolean function of 4 variables is a function from a set of 24 = 16 elements (all combinations of 4 variables) to a set
of 2({0, 1}) elements. So, number of such functions will be 216 = 65, 536
Correct Answer: D
References

 26 votes -- Prashant Singh (47.2k points)

4.4.2 Boolean Algebra: GATE CSE 1987 | Question: 12-a top☝ ☛ https://gateoverflow.in/82556


Option (C) B
A ⊕ A = 0 and 0 ⊕ A = A
A ⊕ B ⊕ A = (A ⊕ A) ⊕ B = 0 ⊕ B = B

 25 votes -- Prajwal Bhat (7.6k points)

4.4.3 Boolean Algebra: GATE CSE 1988 | Question: 2-iii top☝ ☛ https://gateoverflow.in/91679


C =A∗B
¯¯¯¯ ¯¯¯¯
⟹ C = A B + AB
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
⟹ C = A XOR B

⟹ C = A XNOR B

Truth table is:

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 A B C
0 0 1
0 1 0
1 0 0
1 1 1

When C = 1 , observing the truth table we can say A = B.

 16 votes -- Arnab Bhadra (3.7k points)

4.4.4 Boolean Algebra: GATE CSE 1989 | Question: 4-x top☝ ☛ https://gateoverflow.in/88166

For an 'n' variable function, total number of possible minterms(input combinations) will be 2n . Half of them will be one i.e,
2n−1 .
n
Thus total number of neutral functions possble = Choosing any 2n−1 combinations to be 1 out of 2n combination. i.e (22n−1) .
 17 votes -- Jeeten (95 points)

4.4.5 Boolean Algebra: GATE CSE 1989 | Question: 5-a top☝ ☛ https://gateoverflow.in/88230


From A + B = 1 and AB = 0 we get either of A, B is 1 and another is 0

Now, AC = BC , here C has to be 0 (because A, B has different values)

C=0

Now, A + C = 1

So, A = 1 and AB = 0 so, B = 0

So, we get:

A=1,B=0,C =0

These are the values.

 21 votes -- Aboveallplayer (12.5k points)

4.4.6 Boolean Algebra: GATE CSE 1992 | Question: 02-i top☝ ☛ https://gateoverflow.in/555


The answer is D.
Remark:

1. Every logic gate follows Commutative law.

2. AND, OR, Ex-OR, EX-NOR follows Associative law also. NAND, NOR doesn’t follow Associative law.

 31 votes -- Ankit Rokde (6.9k points)

4.4.7 Boolean Algebra: GATE CSE 1994 | Question: 4 top☝ ☛ https://gateoverflow.in/2500


A.
i. A ∗ A = AA + A′ A′ = A + A′ = 1
ii. C ∗ A = (A ∗ B) ∗ A = (AB + A′ B′ ) ∗ A = (AB + A′ B′ )A + (AB + A′ B′ )′ A′
= (AB + A′ B′ )A + (A′ B + AB′ )A′ = AB + 0 + A′ B + 0 = B.

B. AB + A′ C = 1, AC + B = 0

⟹ AC + B = 0, means both B = 0 and AC = 0

′
⟹ AB + C=1

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 ⟹ AB + A′ C = 1

⟹ A′ C = 1 [∵ B = 0, AB = 0]

So, C = 1 and A = 0

A = 0, B = 0 and C = 1

 27 votes -- Praveen Saini (41.9k points)

4.4.8 Boolean Algebra: GATE CSE 1995 | Question: 2.5 top☝ ☛ https://gateoverflow.in/2617


A′ + AB = 0 ⟹ A′ + B = 0

∴ A′ = 0 and B = 0

A=1

AB = AC ⟹ B = C ⟹ C = 0

AB + AC ′ + CD = C ′ D

⟹ 0+1+0 = D

⟹ D=1

Correct Answer: A
 16 votes -- Sutanay Bhattacharjee (3.1k points)

4.4.9 Boolean Algebra: GATE CSE 1997 | Question: 2-1 top☝ ☛ https://gateoverflow.in/2227


Answer is option B.

z ∗ x = (x ∗ y) ∗ x

= (x̄ + y) ∗ x

= ¯x̄¯¯¯+
¯¯¯¯¯¯¯
y +x

x. ȳ + x = x
 29 votes -- Arjun Suresh (332k points)

4.4.10 Boolean Algebra: GATE CSE 1998 | Question: 1.13 top☝ ☛ https://gateoverflow.in/1650


It should be (D).

Let number of ⊕ be two (even case):

B ⊕ B ⊕ B = B ⊕ 0 = B (remains unchanged)

Let number of ⊕ be three (odd case):

B ⊕ B ⊕ B ⊕ B = B ⊕ B ⊕ 0 = B ⊕ B = 0( gives 0)

 37 votes -- Rajarshi Sarkar (27.9k points)

4.4.11 Boolean Algebra: GATE CSE 1998 | Question: 2.8 top☝ ☛ https://gateoverflow.in/1680


We all know AND ,OR are both associative and commutative.we dont know about EXOR and NAND

We can consume some time and prove it by truth table..and come up with the results that EXOR is also associative and
commutative so the only left out is NAND its commutative but not associative

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 Correct Answer: C
 17 votes -- Bhagirathi Nayak (11.7k points)

4.4.12 Boolean Algebra: GATE CSE 1999 | Question: 1.7 top☝ ☛ https://gateoverflow.in/1460


A. ¯xx
¯¯¯¯¯ = x̄
¯¯¯¯¯¯¯¯¯¯¯¯
B. x + x = x̄. x̄ = x̄
¯¯¯¯¯¯¯
C. x.1 = x̄ + 0 = x̄
¯¯¯¯¯¯¯¯¯¯¯
D. x + 1 = x̄. 0 = 0

Here, x NOR 1 will not be equal to x̄.

Hence, option (D) x NOR 1 .

 11 votes -- Leen Sharma (28.7k points)

4.4.13 Boolean Algebra: GATE CSE 2000 | Question: 2.10 top☝ ☛ https://gateoverflow.in/657


Take each option one by one and try to put the values of x, y, z and w in question:
1.

0+1+0 = 1
0.1 = 0
0.0 + 0 = 0 (went wrong) So, this is not the right option

2.

1+1+0 = 1
1.1 = 1 (went wrong) not right

3.

1+0+1 = 1
1.0 = 0
1.1 + 1 = 1
1.0 + 1.0 = 0 This is the right option

Correct Answer: C

 31 votes -- shekhar chauhan (32.8k points)

4.4.14 Boolean Algebra: GATE CSE 2002 | Question: 2-3 top☝ ☛ https://gateoverflow.in/833


f(f(x + y, y), z) = f((x + y)′ + y), z)

= ((x + y)′ + y)′ + z

= (x + y). y ′ + z(∵ (a + b)′ = a′ . b′ )

= xy ′ + z

Correct Answer: C
 30 votes -- Arjun Suresh (332k points)

4.4.15 Boolean Algebra: GATE CSE 2004 | Question: 17 top☝ ☛ https://gateoverflow.in/1014


Answer is option D.
x y + x′ y = x′ (y + y′ ) = x′
′ ′

x′ + xy = x′ + y

© Copyright GATE Overflow. Some rights reserved.

  26 votes -- Arjun Suresh (332k points)

4.4.16 Boolean Algebra: GATE CSE 2007 | Question: 32 top☝ ☛ https://gateoverflow.in/1230

K-map

So, minimized expression will be

xz + w′ y ′ z ′ + wx′ y′ which is Q. From the K-map, we can also get P and R. So, only S is NOT equivalent to f .
http://www.eecs.berkeley.edu/~newton/Classes/CS150sp98/lectures/week4_2/sld011.htm

Alternatively,
Go with Minterm representation of each option, (Note that order of W, X, Y , Z should be preserved.)
Here, x means do not care (x takes value either 0 or 1)
P : X ′ Y ′ Z ′ + W ′ XY ′ + W Y ′ Z + XZ
= xX ′ Y ′ Z ′ + W ′ XY ′ x + WxY ′ Z + xXxZ
= x000 + 010x + 1x01 + x1x1
= 0000 + 1000 + 0100 + 0101 + 1001 + 1101 + 0101 + 0111 + 1101 + 1111
= 0 + 8 + 4 + 5 + 9 + 13 + 5 + 7 + 13 + 15
= ∑ m(0, 4, 5, 7, 8, 9, 13, 15)
Q : W ′ Y ′ Z ′ + W X ′ Y ′ + XZ
= W ′ xY ′ Z ′ + W X ′ Y ′ x + xXxZ
= 0x00 + 100x + x1x1
= 0000 + 0100 + 1000 + 1001 + 0101 + 0111 + 1101 + 1111
= 0 + 4 + 8 + 9 + 5 + 7 + 13 + 15
= ∑ m(0, 4, 5, 7, 8, 9, 13, 15)
R : W ′ Y ′ Z ′ + W X ′ Y ′ + XY Z + XY ′ Z
= W ′ xY ′ Z ′ + W X ′ Y ′ x + xXY Z + xXY ′ Z
= 0x00 + 100x + x111 + x101
= 0000 + 0100 + 1000 + 1001 + 0111 + 1111 + 0101 + 1101
= 0 + 4 + 8 + 9 + 7 + 15 + 5 + 13
= ∑ m(0, 4, 5, 7, 8, 9, 13, 15)
S : X ′ Y ′Z ′ + W X ′ Y ′ + W ′ Y
= xX ′ Y ′ Z ′ + W X ′ Y ′ x + W ′ xY x
= x000 + 100x + 0x1x
= 0000 + 1000 + 1000 + 1001 + 0010 + 0011 + 0110 + 0111
= 0+8+8+9+2+3+6+7
= ∑ m(0, 2, 3, 6, 7, 8, 9)
Correct Answer: D
References

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  42 votes -- Arjun Suresh (332k points)

4.4.17 Boolean Algebra: GATE CSE 2007 | Question: 33 top☝ ☛ https://gateoverflow.in/1231


P:

Y ∗ Z = Y ∗ (X ∗ Y )
= Y ∗ (XY + X ′ Y ′ )
= Y (XY + X ′ Y ′ ) + Y ′ (XY + X ′ Y ′ )′
= XY + Y ′ ((X ′ + Y ′ )(X + Y ))
= XY + Y ′ (X ′ Y + XY ′ )
= XY + XY ′
= X(Y + Y ′ )
=X

So, P is valid.

Q:

X ∗ Z = X ∗ (X ∗ Y )
= X ∗ (XY + X ′ Y ′ )
= X(XY + X ′ Y ′ ) + X ′ (XY + X ′ Y ′ )′
= XY + X ′ ((X ′ + Y ′ )(X + Y ))
= XY + X ′ (X ′ Y + XY ′ )
= XY + X ′ Y
= Y (X + X ′ )
=Y

So, Q is also valid.

R:

X ∗ Y ∗ Z = (X ∗ Y ) ∗ (X ∗ Y )
= (XY + X ′ Y ′ ) ∗ (XY + X ′ Y ′ )
= (XY + X ′ Y ′ )(XY + X ′ Y ′ ) + (XY + X ′ Y ′ )′ (XY + X ′ Y ′ )′
= (XY + X ′ Y ′ ) + (XY + X ′ Y ′ )′ (∵ AA = A)
= 1(∵ A + A′ = 1)

So, R is also valid.

Hence, D choice.
 42 votes -- Arjun Suresh (332k points)

4.4.18 Boolean Algebra: GATE CSE 2008 | Question: 26 top☝ ☛ https://gateoverflow.in/424


Ans is (A) PQ̄

(P + Q̄)(P Q̄ + PR)(P¯R̄ + Q̄)

= (PP Q̄ + PPR + P Q̄ + P Q̄R)(P¯R̄ + Q̄)

= (P Q̄ + PR + P Q̄ + P Q̄R)(P¯R̄ + Q̄)

= P Q̄ + P Q̄R

= PQ̄

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  41 votes -- Keith Kr (4.5k points)

4.4.19 Boolean Algebra: GATE CSE 2012 | Question: 6 top☝ ☛ https://gateoverflow.in/38


Whenever X is true (X, Y ) is true and whenever X is false (X, Y ) is false, so the answer is (A) X.
 39 votes -- Omesh Pandita (1.9k points)

4.4.20 Boolean Algebra: GATE CSE 2013 | Question: 21 top☝ ☛ https://gateoverflow.in/1532


A : means both are either true OR both are false. then it will be true = ExNOR
B & C : whenever any one of the literal is complemented then ExOR can be turned to ExNOR and complement sign on the
literal can be removed. So these two also represents ExNOR operation of x and y.
Answer is option D. It is the ExOR operation b/w the two.

 29 votes -- Amar Vashishth (25.2k points)

4.4.21 Boolean Algebra: GATE CSE 2014 Set 3 | Question: 55 top☝ ☛ https://gateoverflow.in/2090

 ¯¯¯¯
XOR is associative and commutative. Also, A ⊕ A = 0 and A ⊕ 1 = A and A ⊕ 0 = A . So
((1 ⊕ P) ⊕ (P ⊕ Q)) ⊕ ((P ⊕ Q) ⊕ (Q ⊕ 0))
⟹ (1 ⊕ P) ⊕ ((P ⊕ Q) ⊕ (P ⊕ Q)) ⊕ (Q ⊕ 0)
⟹ (1 ⊕ 0) ⊕ (P ⊕ Q)
⟹ 1 ⊕ (P ⊕ Q)
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
⟹ (P ⊕ Q)

Correct Answer: D
 40 votes -- Arjun Suresh (332k points)

4.4.22 Boolean Algebra: GATE CSE 2015 Set 1 | Question: 39 top☝ ☛ https://gateoverflow.in/8294


g is preserving 0 as when all inputs are zero, output is always 0 and so g cannot be functionally complete.
f is not preserving 0.
f is not preserving 1. ( when all inputs are 1, output is 0).
f is not linear as in XY ′ only one (odd) input (X = 1, Y = Z = 0) needs to be 1 and in X ′ Y Z two inputs (even)
(X = 0, Y = Z = 1) need to be 1.
f is not monotone as changing Y from 0 to 1, can take f from 1 to 0.
f is not self dual as f(X, Y , Z) ≠ ⌐f(⌐X, ⌐Y , ⌐Z)
So, f satisfies all 5 conditions required for functional completeness.
Hence, B is the answer.
http://cs.ucsb.edu/~victor/ta/cs40/posts-criterion.pdf
References

 93 votes -- Arjun Suresh (332k points)

4.4.23 Boolean Algebra: GATE CSE 2015 Set 2 | Question: 37 top☝ ☛ https://gateoverflow.in/8162


F = [ D ′ + A B′ + A ′ C + A C ′ D + A ′ C ′ D ] ′
F ′ = D ′ + A B′ + A ′ C + A C ′ D + A ′ C ′ D
Now we have F', so fill 0's (maxterms) in K-map for each term

© Copyright GATE Overflow. Some rights reserved.

 As for D'

Similarly for AB′ , A′ C, AC ′ D and A′ C ′ D . We will get

We get one place for minterm and that is ABCD

 62 votes -- Praveen Saini (41.9k points)

4.4.24 Boolean Algebra: GATE CSE 2016 Set 1 | Question: 06 top☝ ☛ https://gateoverflow.in/39629


These are properties of XOR function.. so answer is A) xȳ¯¯+x̄
¯¯y

 35 votes -- Abhilash Panicker (7.6k points)

4.4.25 Boolean Algebra: GATE CSE 2016 Set 2 | Question: 08 top☝ ☛ https://gateoverflow.in/39540


Let x1 = 1 x2 = 1 x3 = 1 and x4 = 1
such that x1 ⊕ x2 ⊕ x3 ⊕ x4 = 1 ⊕ 1 ⊕ 1 ⊕ 1 = 0

A. x1 x2 x3 x4 = 1.1.1.1 = 1 , False
B. x1 x3 + x2 = 1.1 + 1 = 1 , False
C. is always True.
D. x1 + x2 + x3 + x4 = 1 + 1 + 1 + 1 = 1 , False

Correct Answer: C

 61 votes -- Praveen Saini (41.9k points)

4.4.26 Boolean Algebra: GATE CSE 2017 Set 2 | Question: 27 top☝ ☛ https://gateoverflow.in/118494


Let us try to simplify (minimize) the expression given in each option
Option - A: wx + w(x + y) + x(x + y) = x + wy
wx + wx + wy + x

© Copyright GATE Overflow. Some rights reserved.

 wx + wy + x
x(1 + w) + wy
x + wy
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Option - B: wx̄(y + z̄ ) + w̄x = w̄ + x + ȳ z
¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
wx̄ + (y + z̄ ) + w̄x
w̄ + x + ȳ z + w̄x
w̄ + w̄x + x + ȳ z
w̄ + x + ȳ z
Option - D: (w + y)(wxy + wyz) = wxy + wyz
wxy + wyz + wxy + wyz
wxy + wyz
Option A, B, D are matching fine.
Hence, Option - C is the answer

 29 votes -- Arunav Khare (3.9k points)

4.4.27 Boolean Algebra: GATE CSE 2018 | Question: 4 top☝ ☛ https://gateoverflow.in/204078


Consider Option(D). LHS can be simplified as,
¯¯¯¯ ¯¯¯¯
(P ⊕ P ) ⊕ Q = 1 ⊕ Q = Q

Similarly, for RHS

¯¯¯¯ ¯¯¯¯ ¯¯¯¯
(P ⊙ P ) ⊙ Q = 0 ⊙ Q = Q

LHS ≠ RHS therefore, Option (D) is the correct answer.

Other options can be simplified as follows.

¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯
¯¯¯¯¯¯
1. P ⊕ Q = P Q + P Q = (PQ ) (P Q) = (P + Q) (P + Q) = PQ + P Q = P ⊙ Q
¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯

¯¯¯¯¯¯¯¯¯¯
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
2. P ⊕ Q = (P ) Q + (P ) Q = PQ + P Q = P ⊙ Q
¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
3. P ⊕ Q = (P ) (Q) + (P ) (Q) = P Q + P Q = P ⊕ Q

 18 votes -- Prateek Dwivedi (3.5k points)

4.4.28 Boolean Algebra: GATE CSE 2019 | Question: 6 top☝ ☛ https://gateoverflow.in/302842


1. XOR is associative so (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)
′ ′ ′
2. For 2 input, XOR and XNOR are complement to each other i.e. x ⊕ y = (xy + x y )
3. x ⊕ y = x + y if xy = 0

Only false statement is option B.

 26 votes -- Digvijay (44.9k points)

4.4.29 Boolean Algebra: GATE CSE 2021 Set 1 | Question: 42 top☝ ☛ https://gateoverflow.in/357409

 ¯¯¯¯ ¯¯¯¯
F = (X + Y + Z)(X + Y )(Y + Z)
Taking complement of above expression;
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯ ¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
F = (X + Y + Z)(X + Y )(Y + Z)
Applying De-Morgan’s law;
¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯
¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯
F = (X + Y + Z) + (X + Y ) + (Y + Z)
¯¯¯¯¯ ¯¯¯¯¯
=( . . )+ . + .
© Copyright GATE Overflow. Some rights reserved.
 ¯¯¯¯¯ ¯¯¯¯¯
F = (X̄. Y¯. Z̄ ) + X . Y + Y . Z
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯

¯¯¯¯¯
¯¯¯¯
[∵ X = X, Using double negation law]

∴ F = (X̄. Y¯. Z̄ ) + (X. Y ) + (Y . Z )

¯¯¯¯ ¯¯¯¯ ¯¯¯¯
→ Option (D)
¯¯¯¯
Taking Y as common we get;
¯¯¯¯ ¯¯¯¯ ¯¯¯¯
F = Y [(X̄Z̄ ) + X] + Y Z
[∵ A + BC = (A + B)(A + C) Applying distributive law here]
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
F = Y [(X + X )(X + Z )] + Y Z
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
F = Y [X + Z ] + Y Z
¯¯¯¯ ¯¯¯¯ ¯¯¯¯¯¯¯¯ ¯¯¯¯
F = XY + Y Z + Y Z
¯¯¯¯
Taking Z as common
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
F = XY + Z (Y + Y )
¯¯¯¯
∵ (Y+Y =1) using complement law
¯¯¯¯ ¯¯¯¯ ¯¯¯¯
∴ F = XY + Z → Option (B)
Applying distributive law here we get;
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
F = (X + Z )(Y + Z ) → Option (C)
So, correct options are B, C, D.

Option A is false and can be proved as follows:

Take X = 0, Y = 1, Z = 0
Now, F = 0, since (Y¯ + Z) term will be zero. So, F¯ must be 1.
But option A gives 0 as the term X + Y¯ evaluates to 0. So, option A is not equal to F¯.
Properties of Boolean Algebra
References

 1 votes -- Hira (14.1k points)

4.4.30 Boolean Algebra: GATE IT 2004 | Question: 44 top☝ ☛ https://gateoverflow.in/3687

So, the equivalent expression will be ĀC + AC̄ + AB̄

(B) option

© Copyright GATE Overflow. Some rights reserved.

  36 votes -- Arjun Suresh (332k points)

4.4.31 Boolean Algebra: GATE IT 2005 | Question: 7 top☝ ☛ https://gateoverflow.in/3752


Correct answer is C

(A ⊕ B) ⊕ C

At C = 0 ,(A ⊕ B) ⊕ C = (A ⊕ B) ----(I) [ as 0 ⊕ x = 0.x′ + 0.′ x = x ]

At C = 0 , ABC + A′ (B ⊕ C) + B′ (A ⊕ C)

= 0 + A′ (B ⊕ 0) + B′ (A ⊕ 0) = A′ B + AB′ = A ⊕ B -----(II)

At C = 1 , (A ⊕ B) ⊕ C = (A ⊙ B) --- (III) [as 1 ⊕ x = 1.x′ + 1′ . x = x′ ]

At C = 1 , ABC + A′ (B ⊕ C) + B′ (A ⊕ C)

= AB + A′ (B ⊕ 1) + B′ (A ⊕ 1) = AB + A′ B′ = (A ⊙ B) --(IV)

from eq (I), (II), (III) and (IV) it is clear

(A ⊕ B) ⊕ C = ABC + A′ (B ⊕ C) + B′ (A ⊕ C)
 39 votes -- Praveen Saini (41.9k points)

4.5 Booths Algorithm (6) top☝

4.5.1 Booths Algorithm: GATE CSE 1990 | Question: 8b top☝ ☛ https://gateoverflow.in/85671

State the Booth's algorithm for multiplication of two numbers. Draw a block diagram for the implementation of the Booth's
algorithm for determining the product of two 8-bit signed numbers.

gate1990 descriptive digital-logic booths-algorithm

Answer ☟

4.5.2 Booths Algorithm: GATE CSE 1996 | Question: 1.23 top☝ ☛ https://gateoverflow.in/2727

Booth’s algorithm for integer multiplication gives worst performance when the multiplier pattern is
A. 101010 … 1010
B. 100000 … 0001
C. 111111 … 1111
D. 011111 … 1110

gate1996 digital-logic booths-algorithm normal

Answer ☟

4.5.3 Booths Algorithm: GATE CSE 1999 | Question: 1.20 top☝ ☛ https://gateoverflow.in/1473

Booth's coding in 8 bits for the decimal number −57 is:

A. 0 − 100 + 1000
B. 0 − 100 + 100 − 1
C. 0 − 1 + 100 − 10 + 1
D. 00 − 10 + 100 − 1

gate1999 digital-logic number-representation booths-algorithm normal

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.5.4 Booths Algorithm: GATE IT 2005 | Question: 8 top☝ ☛ https://gateoverflow.in/3753

Using Booth's Algorithm for multiplication, the multiplier −57 will be recoded as
A. 0 -1 00 1 0 0 -1
B. 11000111
C. 0 -1 0 0 10 0 0
D. 0 1 0 0 -1 0 0 1

gate2005-it digital-logic booths-algorithm normal

Answer ☟

4.5.5 Booths Algorithm: GATE IT 2006 | Question: 38 top☝ ☛ https://gateoverflow.in/3577

When multiplicand Y is multiplied by multiplier X = xn−1 xn−2 … x0 using bit-pair recoding in Booth's algorithm, partial
products are generated according to the following table.

Row xi+1 xi xi−1 Partial Product

1 0 0 0 0
2 0 0 1 Y
3 0 1 0 Y
4 0 1 1 2Y
5 1 0 0 ?
6 1 0 1 -Y
7 1 1 0 -Y
8 1 1 1 ?

The partial products for rows 5 and 8 are

A. 2Y and Y
B. −2Y and 2Y
C. −2Y and 0
D. 0 and Y

gate2006-it digital-logic booths-algorithm difficult

Answer ☟

4.5.6 Booths Algorithm: GATE IT 2008 | Question: 42 top☝ ☛ https://gateoverflow.in/3352

The two numbers given below are multiplied using the Booth's algorithm.
Multiplicand : 0101 1010 1110 1110
Multiplier: 0111 0111 1011 1101
How many additions/Subtractions are required for the multiplication of the above two numbers?
A. 6
B. 8
C. 10
D. 12

gate2008-it digital-logic booths-algorithm normal

Answer ☟

Answers: Booths Algorithm

4.5.1 Booths Algorithm: GATE CSE 1990 | Question: 8b top☝ ☛ https://gateoverflow.in/85671


Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's
complement notation.
The block diagram for the implementation of the Booth's algorithm for determining the product of two 8-bit signed numbers is as
shown below.

© Copyright GATE Overflow. Some rights reserved.

 The Multiplier and Multiplicand are placed in the Q and M registers, respectively. There is also a 1-bit register placed logically
to the right of the least significant bit(Q0 ) of the Q register and designated Q−1 .
The results of the multiplication will appear in the A and Q registers. A and Q−1 are initialized to 0. The control logic scans the
bits of the multiplier one at a time. Now, as each bit is examined, the bit to its right is also examined. If the two bits are the same
(11 or 00), then all of the bits of the A, Q, and Q−1 registers are shifted to the right 1 bit. If the two bits differ, then the
multiplicand is added to or subtracted from the A register, depending on whether the two bits are 01 or 10. Following, the
addition or subtraction, the right shift occurs.
In either case, the right shift is such that the leftmost bit of A, namely An−1 , not only is shifted into An−2 ,but also remains in
An−1 . This is required to preserve the sign of the number in A and Q. It is known as an arithmetic shift, because it preserves the
sign bit.
References

 6 votes -- Satbir Singh (21k points)

4.5.2 Booths Algorithm: GATE CSE 1996 | Question: 1.23 top☝ ☛ https://gateoverflow.in/2727


Answer: A

The worst case of an implementation using Booth’s algorithm is when pairs of 01s or 10s occur very frequently in the multiplier.
 30 votes -- Rajarshi Sarkar (27.9k points)

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 4.5.3 Booths Algorithm: GATE CSE 1999 | Question: 1.20 top☝ ☛ https://gateoverflow.in/1473


Convert 57 to Binary & Get 2′ s complement. It is " 11000111 " & Attach one extra 0 to right of it

110001110

To calculate booth code subtract right digit from left digit in every consecutive 2 digits.

So, 11 → 0, 10 → +1 . Finally, 10 → +1

So, answer is (B).

There is another way to solve this question.

0 − 100 + 100 − 1 → If you check binary weigted sum of this code you will get −57 . This is trick to quick check. Booth code
is always equivalent to it's original value if checked as weighted code. If you check it before doing above procedure & if only
one of option maps, you don't need to do above procedure, just mark the answer.

Here, (−1) × 64 + (+1) × 8 + (−1) × 1 = −57 .

 37 votes -- Akash Kanase (36k points)

4.5.4 Booths Algorithm: GATE IT 2005 | Question: 8 top☝ ☛ https://gateoverflow.in/3753


2's complement of −57 is (11000111)
Booth multiplier :

1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 0 (put 0 in 1st and shift multiplier left by 1 bit)
0 −1 0 0 1 0 0 −1
Use this encoded scheme: 00 → 0, 01 → +1, 10 → −1, 11 → 0
Correct Answer: A.

 21 votes -- Prashant Singh (47.2k points)

4.5.5 Booths Algorithm: GATE IT 2006 | Question: 38 top☝ ☛ https://gateoverflow.in/3577


We can have 1 bit or 2 bit Booth codes. This question is about 2 bit Booth codes. In Booth's algorithm, we get partial
products by multiplying specific codes with the multiplicand. These partial products are used to get the actual product. We
initially calculate 2 bit booth code of the multiplier in this question. Then each bit of the code is multiplied with the multiplicand
to get the partial product as shown in the last column of the given table.
Here, the multiplicand is Y . So, notice that each row of partial product column is multiplied with Y .

Now, the question is how to get these codes i.e., how to represent a multiplier with a 2 bit booth code. For that we need to look at
the pair of 3 bits as shown in the table below. To get code Ci , look for 3 bits as shown.

xi+1 xi xi+1 Boothcode(Ci )

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 2
1 0 0 −2
1 0 1 −1
1 1 0 −1
1 1 1 0

Now, multiply ith code to get partial product.

Therefore, Option C is correct.
 6 votes -- Monanshi Jain (7k points)

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 4.5.6 Booths Algorithm: GATE IT 2008 | Question: 42 top☝ ☛ https://gateoverflow.in/3352

Answer is B.
Append 0 the end of multiplier : 0111 0111 1011 1101 0
Now,Paired bits from right end as 00-(0), 01-(+1), 10(-1) and 11-(0)
note:- pairs are overlapped.
Count +1=4 (additions required)
Count -1=4 (subtractions required)
So, total 8 pair hence addition/subtraction required = 8.

 27 votes -- Rajarshi Sarkar (27.9k points)

4.6 Canonical Normal Form (7) top☝

4.6.1 Canonical Normal Form: GATE CSE 2002 | Question: 2-1 top☝ ☛ https://gateoverflow.in/831

Consider the following logic circuit whose inputs are functions f1 , f2 , f3 and output is f

Given that

f1 (x, y, z) = Σ(0, 1, 3, 5)
f2 (x, y, z) = Σ(6, 7), and
f(x, y, z) = Σ(1, 4, 5).

f3 is
A. Σ(1, 4, 5)
B. Σ(6, 7)
C. Σ(0, 1, 3, 5)
D. None of the above

gate2002-cse digital-logic normal canonical-normal-form circuit-output

Answer ☟

4.6.2 Canonical Normal Form: GATE CSE 2008 | Question: 8 top☝ ☛ https://gateoverflow.in/406

Given f1 , f3 and f in canonical sum of products form (in decimal) for the circuit

f1 = Σm(4, 5, 6, 7, 8)
f3 = Σm(1, 6, 15)
f = Σm(1, 6, 8, 15)
then f2 is

A. Σm(4, 6)
B. Σm(4, 8)
C. Σm(6, 8)
Σm(4, 6, 8)

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 D. Σm(4, 6, 8)

gate2008-cse digital-logic canonical-normal-form easy

Answer ☟

4.6.3 Canonical Normal Form: GATE CSE 2010 | Question: 6 top☝ ☛ https://gateoverflow.in/2177

The minterm expansion of f(P, Q, R) = PQ + QR̄ + P R̄ is

A. m2 + m4 + m6 + m7
B. m0 + m1 + m3 + m5
C. m0 + m1 + m6 + m7
D. m2 + m3 + m4 + m5

gate2010-cse digital-logic canonical-normal-form normal

Answer ☟

4.6.4 Canonical Normal Form: GATE CSE 2015 Set 3 | Question: 43 top☝ ☛ https://gateoverflow.in/8503

The total number of prime implicants of the function f(w, x, y, z) = ∑(0, 2, 4, 5, 6, 10) is __________

gate2015-cse-set3 digital-logic canonical-normal-form normal numerical-answers

Answer ☟

4.6.5 Canonical Normal Form: GATE CSE 2015 Set 3 | Question: 44 top☝ ☛ https://gateoverflow.in/8504

Given the function F = P ′ + QR , where F is a function in three Boolean variables P, Q and R and P ′ =!P , consider the
following statements.
(S1)F = ∑(4, 5, 6)
(S2)F = ∑(0, 1, 2, 3, 7)
(S3)F = Π(4, 5, 6)
(S4)F = Π(0, 1, 2, 3, 7)
Which of the following is true?

A. (S1)-False, (S2)-True, (S3)-True, (S4)-False

B. (S1)-True, (S2)-False, (S3)-False, (S4)-True
C. (S1)-False, (S2)-False, (S3)-True, (S4)-True
D. (S1)-True, (S2)-True, (S3)-False, (S4)-False

gate2015-cse-set3 digital-logic canonical-normal-form normal

Answer ☟

4.6.6 Canonical Normal Form: GATE CSE 2019 | Question: 50 top☝ ☛ https://gateoverflow.in/302798

What is the minimum number of 2-input NOR gates required to implement a 4 -variable function expressed in sum-of-
minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available. Answer:
_______

gate2019-cse numerical-answers digital-logic canonical-normal-form

Answer ☟

4.6.7 Canonical Normal Form: GATE CSE 2020 | Question: 28 top☝ ☛ https://gateoverflow.in/333203

Consider the Boolean function z(a, b, c) .

© Copyright GATE Overflow. Some rights reserved.

 Which one of the following minterm lists represents the circuit given above?

A. z = ∑(0, 1, 3, 7)
B. z = ∑(1, 4, 5, 6, 7)
C. z = ∑(2, 4, 5, 6, 7)
D. z = ∑(2, 3, 5)

gate2020-cse digital-logic canonical-normal-form

Answer ☟

Answers: Canonical Normal Form

4.6.1 Canonical Normal Form: GATE CSE 2002 | Question: 2-1 top☝ ☛ https://gateoverflow.in/831


f = ((f1 f2 )′ f3′ )′ = f1 f2 + f3

In minimum sum of products form, AND of two expressions will contain the common terms. Since f1 and f2 don't have any
common term, f1 f2 is 0 and hence f = f3 = Σ(1, 4, 5).

Correct Answer: A
 81 votes -- Arjun Suresh (332k points)

4.6.2 Canonical Normal Form: GATE CSE 2008 | Question: 8 top☝ ☛ https://gateoverflow.in/406


Answer is C.

Wth AND gates we will choose intersection of min-terms.

With OR gates we will take union of min-terms.

 45 votes -- Ankit Rokde (6.9k points)

4.6.3 Canonical Normal Form: GATE CSE 2010 | Question: 6 top☝ ☛ https://gateoverflow.in/2177


PQ + QR′ + P R′ = PQR + PQR′ + PQR′ + P ′ QR′ + PQR′ + P Q′ R′
= PQR + PQR′ + P ′ QR′ + P Q′ R′ (111 + 110 + 010 + 100)
= m7 + m6 + m2 + m4
Option A.

Alternatively,
Using K-map

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  34 votes -- Arjun Suresh (332k points)

4.6.4 Canonical Normal Form: GATE CSE 2015 Set 3 | Question: 43 top☝ ☛ https://gateoverflow.in/8503

As you can see that there is one 4 -set and two 2 -set that are covering the star marked 1′ s (i.e. the ones that are not covered by
any other combinations).
So, the answer is 3.

 53 votes -- Tamojit Chatterjee (1.9k points)

4.6.5 Canonical Normal Form: GATE CSE 2015 Set 3 | Question: 44 top☝ ☛ https://gateoverflow.in/8504


F = P ′ + QR , draw the Kmap for this

We can find the minterm ∑(0, 1, 2, 3, 7) and maxterm Π(4, 5, 6)

So, option A is correct: (S1) -False, (S2) -True, (S3) -True, (S4) -False
 33 votes -- Anoop Sonkar (4.1k points)

F = P ′ + QR
for SOP we have :
F = P.1.1 + 1.QR′ = P ′ (Q + Q′ )(R + R′ ) + (P + P ′ )QR
P ′ QR + P ′ QR′ + P ′ Q′ R + P ′ Q′ R′ + PQR + P ′ QR
P ′ QR + P ′ QR′ + P ′ Q′ R + P ′ Q′ R′ + PQR
F = ∑(0, 1, 2, 3, 7) (considering barred terms as 0 and unbarred as 1 and converting them to binary and then to
decimal).
now for POS we have :

F = P ′ + QR = (P ′ + Q)(P ′ + R) = (P ′ + Q + 0)(P ′ + R + 0)

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 F = P ′ + QR = (P ′ + Q)(P ′ + R) = (P ′ + Q + 0)(P ′ + R + 0)
(P ′ + Q + R. R′ )(P ′ + R + Q. Q′ )
(P ′ + Q + R)(P ′ + Q + R)(P ′ + Q + R′ )(P ′ + Q′ + R)
(P ′ + Q + R)(P ′ + Q + R′ )(P ′ + Q′ + R)
F = ∏(4, 5, 6) (considering barred terms as 1 and unbarred as 0 and converting them to binary and then to decimal).
http://mcs.uwsuper.edu/sb/461/PDF/sop.html
References

 15 votes -- Tamojit Chatterjee (1.9k points)

4.6.6 Canonical Normal Form: GATE CSE 2019 | Question: 50 top☝ ☛ https://gateoverflow.in/302798

f = (B′ + D). (B + D′ )
It is mentioned that both Complimentary as well as Uncomplimentary forms are available.
B′ NOR D = (B′ + D)′
B NOR D′ = (B + D′ )′
(B′ NOR D) NOR (B NOR D′ )
= ((B′ + D)′ + (B + D′ )′ )′
= ((B′ + D)′′ . (B + D′ )′′ )
= ((B′ + D). (B + D′ ))
=f
Thus, 3 NOR Gates are required.

 32 votes -- Balaji Jegan (3.5k points)

4.6.7 Canonical Normal Form: GATE CSE 2020 | Question: 28 top☝ ☛ https://gateoverflow.in/333203


From given circuit z = a + b′ c
K-Map for the above expression is:

© Copyright GATE Overflow. Some rights reserved.

 Minterms are ∑(1, 4, 5, 6, 7)
Hence, option (B) is correct

 7 votes -- Ashwani Kumar (13k points)

4.7 Carry Generator (2) top☝

4.7.1 Carry Generator: GATE CSE 2006 | Question: 36 top☝ ☛ https://gateoverflow.in/1294

Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c the carry in, the function that represents the carry generate function
when these two numbers are added is:

A. a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0
B. a2 b2 + a2 b1 b0 + a2 a1 b1 b0 + a1 a0 b2 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0
C. a2 + b2 + (a2 ⊕ b2 )(a1 + b1 + (a1 ⊕ b1 ) + (a0 + b0 ))
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯¯¯¯¯¯
D. a2 b2 + ¯a¯¯¯2¯a1 b1 + ¯a¯¯¯2¯¯a¯¯¯1¯a0 b0 + ¯a¯¯¯2¯a0 b1 b0 + a1 b2 b1 + ¯a¯¯¯1¯a0 b2 b0 + a0 b2 b1 b0

gate2006-cse digital-logic normal carry-generator

Answer ☟

4.7.2 Carry Generator: GATE CSE 2007 | Question: 35 top☝ ☛ https://gateoverflow.in/1233

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs Ai and Bi are
given by:

Pi = Ai ⊕ Bi and Gi = Ai Bi

The expressions for the sum bit Si and the carry bit Ci+1 of the look ahead carry adder are given by:

Si = Pi ⊕ Ci and Ci+1 = Gi + Pi Ci , where C0 is the input carry.

Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi and Gi are available for the carry
generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to
implement the look-ahead carry generator for a 4-bit adder with S3 , S2 , S1 , S0 and C4 as its outputs are respectively:
A. 6, 3
B. 10, 4
C. 6, 4
D. 10, 5

gate2007-cse digital-logic normal carry-generator adder

Answer ☟

Answers: Carry Generator

4.7.1 Carry Generator: GATE CSE 2006 | Question: 36 top☝ ☛ https://gateoverflow.in/1294


c1 = a0 b0

c2 = a1 b1 + a1 c1 + b1 c1

c3 = a2 b2 + a2 c2 + b2 c2
= a2 b2 + a2 a1 b1 + a2 a1 c1 + a2 b1 c1 + b2 a1 b1 + b2 a1 c1 + b2 b1 c1

© Copyright GATE Overflow. Some rights reserved.

 = a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 b1 a0 b0 + b2 a1 b1 + b2 a1 a0 b0 + b2 b1 a0 b0

Option is A.

Considering the carry in function c, c1 = a0 b0 + a0 c + b0 c , but c is missing in all options and hence ignored.

 65 votes -- Arjun Suresh (332k points)

4.7.2 Carry Generator: GATE CSE 2007 | Question: 35 top☝ ☛ https://gateoverflow.in/1233


C1 = G0 + C0.P0

C2 = G1 + G0.P1 + C0.P0.P1

C3 = G2 + G1.P2 + G0.P1.P2 + C0.P0.P1.P2

C4 = G3 + G2.P3 + G1.P2.P3 + G0.P1.P2.P3 + C0.P0.P1.P2.P3 // read this as carry is generated in 3rd stage OR
carry is generated in 2 stage AND propagated to 3 stage OR carry is generated in 1st stage AND carry is propagated through
nd rd

2nd AND 3rd stage OR carry is generated in 0th stage AND propagated through 1st 2nd AND 3rd stage OR initial carry is
propagated through 0th , 1st , 2nd AND 3rd stage.

4 OR gates are required for C1, C2, C3, C4

1 AND gate for C1

2 AND gate for C2
3 AND gate for C3
4 AND gate for C4
AND = 10
OR = 4

Correct Answer: B.

 60 votes -- Vikrant Singh (11.2k points)

4.8 Circuit Output (38) top☝

4.8.1 Circuit Output: GATE CSE 1989 | Question: 4-ix top☝ ☛ https://gateoverflow.in/88164

Explain the behaviour of the following logic circuit with level input A and output B.

gate1989 descriptive digital-logic circuit-output

Answer ☟

4.8.2 Circuit Output: GATE CSE 1990 | Question: 3-i top☝ ☛ https://gateoverflow.in/84051

Choose the correct alternatives (More than one may be correct).

Two NAND gates having open collector outputs are tied together as shown in below figure.

© Copyright GATE Overflow. Some rights reserved.

 The logic function Y , implemented by the circuit is,
A. Y = ABC + DE
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
B. Y = ABC + DE
C. Y = ABC. DE
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
D. Y = ABC. DE

gate1990 normal digital-logic circuit-output

Answer ☟

4.8.3 Circuit Output: GATE CSE 1991 | Question: 5-a top☝ ☛ https://gateoverflow.in/531

Analyse the circuit in Fig below and complete the following table

a b Qn
0 0
0 1
1 0
1 1

gate1991 digital-logic normal circuit-output sequential-circuit descriptive

Answer ☟

4.8.4 Circuit Output: GATE CSE 1993 | Question: 19 top☝ ☛ https://gateoverflow.in/2316

A control algorithm is implemented by the NAND – gate circuitry given in figure below, where A and B are state variable
implemented by D flip-flops, and P is control input. Develop the state transition table for this controller.

© Copyright GATE Overflow. Some rights reserved.

 gate1993 digital-logic sequential-circuit flip-flop circuit-output normal descriptive

Answer ☟

4.8.5 Circuit Output: GATE CSE 1993 | Question: 6-3 top☝ ☛ https://gateoverflow.in/17237

For the initial state of 000, the function performed by the arrangement of the J-K flip-flops in figure is:

A. Shift Register
B. Mod- 3 Counter
C. Mod- 6 Counter
D. Mod- 2 Counter
E. None of the above

gate1993 digital-logic sequential-circuit flip-flop digital-counter circuit-output multiple-selects

Answer ☟

4.8.6 Circuit Output: GATE CSE 1993 | Question: 6.1 top☝ ☛ https://gateoverflow.in/2288

Identify the logic function performed by the circuit shown in figure.

© Copyright GATE Overflow. Some rights reserved.

 A. exclusive OR
B. exclusive NOR
C. NAND
D. NOR
E. None of the above

gate1993 digital-logic combinational-circuits circuit-output normal

Answer ☟

4.8.7 Circuit Output: GATE CSE 1993 | Question: 6.2 top☝ ☛ https://gateoverflow.in/17235

If the state machine described in figure should have a stable state, the restriction on the inputs is given by

A. a. b = 1
B. a+b = 1
C. ā + b̄ = 0
¯¯¯¯¯¯¯
D. a. b = 1
¯¯¯¯¯¯¯¯¯¯¯
E. a+b = 1

gate1993 digital-logic normal circuit-output sequential-circuit

Answer ☟

4.8.8 Circuit Output: GATE CSE 1994 | Question: 1.8 top☝ ☛ https://gateoverflow.in/2445

The logic expression for the output of the circuit shown in figure below is:

¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯
A. AC + BC + CD
¯¯¯¯ ¯¯¯¯
B. AC + BC + CD
¯¯¯¯ ¯¯¯¯
C. ABC + C D
¯¯¯¯ ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
D. A B + B C + CD

gate1994 digital-logic circuit-output normal

Answer ☟

4.8.9 Circuit Output: GATE CSE 1994 | Question: 11 top☝ ☛ https://gateoverflow.in/2507

Find the contents of the flip-flop Q2 , Q1 and Q0 in the circuit of figure, after giving four clock pulses to the clock terminal.
Assume Q2 Q1 Q0 = 000 initially.

© Copyright GATE Overflow. Some rights reserved.

 gate1994 digital-logic sequential-circuit digital-counter circuit-output normal descriptive

Answer ☟

4.8.10 Circuit Output: GATE CSE 1996 | Question: 2.21 top☝ ☛ https://gateoverflow.in/2750

Consider the circuit in below figure which has a four bit binary number b3 b2 b1 b0 as input and a five bit binary number,
d4 d3 d2 d1 d0 as output.

A. Binary to Hex conversion

B. Binary to BCD conversion
C. Binary to Gray code conversion
D. Binary to radix − 12 conversion

gate1996 digital-logic circuit-output normal

Answer ☟

4.8.11 Circuit Output: GATE CSE 1996 | Question: 24-a top☝ ☛ https://gateoverflow.in/2776

Consider the synchronous sequential circuit in the below figure

© Copyright GATE Overflow. Some rights reserved.

 Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of
flip-flops as given below.

Q1 Q2 Q3 State
0 0 0 S0
0 0 1 S1
– – – –
– – – –
– – – –
1 1 1 S7

gate1996 digital-logic circuit-output normal descriptive

Answer ☟

4.8.12 Circuit Output: GATE CSE 1996 | Question: 24-b top☝ ☛ https://gateoverflow.in/203691

Consider the synchronous sequential circuit in the below figure

Given that the initial state of the circuit is S4 , identify the set of states, which are not reachable.

gate1996 normal digital-logic circuit-output descriptive

Answer ☟

4.8.13 Circuit Output: GATE CSE 1997 | Question: 5.5 top☝ ☛ https://gateoverflow.in/2256

Consider a logic circuit shown in figure below. The functions f1 , f2 and f (in canonical sum of products form in decimal
notation) are :
f1 (w, x, y, z) = ∑ 8, 9, 10
f2 (w, x, y, z) = ∑ 7, 8, 12, 13, 14, 15
f(w, x, y, z) = ∑ 8, 9

© Copyright GATE Overflow. Some rights reserved.

 The function f3 is

A. ∑ 9, 10
B. ∑ 9
C. ∑ 1, 8, 9
D. ∑ 8, 10, 15

gate1997 digital-logic circuit-output normal

Answer ☟

4.8.14 Circuit Output: GATE CSE 1999 | Question: 2.8 top☝ ☛ https://gateoverflow.in/1486

Consider the circuit shown below. In a certain steady state, the line Y is at ′ 1′ . What are the possible values of A, B and C in
this state?

A. A = 0, B = 0, C = 1
B. A = 0, B = 1, C = 1
C. A = 1, B = 0, C = 1
D. A = 1, B = 1, C = 1

gate1999 digital-logic circuit-output normal

Answer ☟

4.8.15 Circuit Output: GATE CSE 2000 | Question: 2.12 top☝ ☛ https://gateoverflow.in/659

The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
A. 1, 0
B. 1, 1
0, 0

© Copyright GATE Overflow. Some rights reserved.

 C. 0, 0
D. 0, 1

gate2000-cse digital-logic circuit-output normal flip-flop

Answer ☟

4.8.16 Circuit Output: GATE CSE 2001 | Question: 2.8 top☝ ☛ https://gateoverflow.in/726

Consider the following circuit with initial state Q0 = Q1 = 0 . The D Flip-flops are positive edged triggered and have set up
times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C. The clock period of C ≥ 40 nanosecond. Which one is the correct plot of Y?

A.

B.

C.

D.

gate2001-cse digital-logic circuit-output normal

Answer ☟

4.8.17 Circuit Output: GATE CSE 2002 | Question: 2.2 top☝ ☛ https://gateoverflow.in/832

Consider the following multiplexer where I0, I1, I2, I3 are four data input lines selected by two address line combinations
A1A0 = 00, 01, 10, 11 respectively and f is the output of the multiplexor. EN is the Enable input.

© Copyright GATE Overflow. Some rights reserved.

 The function f(x, y, z) implemented by the above circuit is

A. xyz ′
B. xy + z
C. x+y
D. None of the above

gate2002-cse digital-logic circuit-output normal

Answer ☟

4.8.18 Circuit Output: GATE CSE 2004 | Question: 61 top☝ ☛ https://gateoverflow.in/1056

Consider the partial implementation of a 2 − bit counter using T flip-flops following the sequence 0 − 2 − 3 − 1 − 0, as
shown below.

To complete the circuit, the input X should be

A. Qc2
B. Q2 + Q1
C. (Q1 + Q2 ) c
D. Q1 ⊕ Q2

gate2004-cse digital-logic circuit-output normal

Answer ☟

4.8.19 Circuit Output: GATE CSE 2005 | Question: 15 top☝ ☛ https://gateoverflow.in/1351

Consider the following circuit.

© Copyright GATE Overflow. Some rights reserved.

 Which one of the following is TRUE?
A. f is independent of x
B. f is independent of y
C. f is independent of z
D. None of x, y, z is redundant

gate2005-cse digital-logic circuit-output normal

Answer ☟

4.8.20 Circuit Output: GATE CSE 2005 | Question: 62 top☝ ☛ https://gateoverflow.in/264

Consider the following circuit involving a positive edge triggered D FF.

Consider the following timing diagram. Let Ai represents the logic level on the line a in the i-th clock period.

Let A′ represent the compliment of A. The correct output sequence on Y over the clock periods 1 through 5 is:
A. A0 A1 A′1 A3 A4
B. A0 A1 A′2 A3 A4
C. A1 A2 A′2 A3 A4
D. A1 A′2 A3 A4 A′5

gate2005-cse digital-logic circuit-output normal

Answer ☟

4.8.21 Circuit Output: GATE CSE 2005 | Question: 64 top☝ ☛ https://gateoverflow.in/1387

Consider the following circuit:

© Copyright GATE Overflow. Some rights reserved.

 The flip-flops are positive edge triggered D FFs. Each state is designated as a two-bit string Q0 Q1 . Let the initial state be 00. The
state transition sequence is

A.

B.

C.

D.

gate2005-cse digital-logic circuit-output

Answer ☟

4.8.22 Circuit Output: GATE CSE 2006 | Question: 35 top☝ ☛ https://gateoverflow.in/1292

Consider the circuit above. Which one of the following options correctly represents f (x, y, z)

A. xz̄ + xy + ȳ z
B. xz̄ + xy + ¯yz
¯¯¯¯
C. xz + xy + ¯yz
¯¯¯¯
D. xz + xȳ + ȳ z

gate2006-cse digital-logic circuit-output normal

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.8.23 Circuit Output: GATE CSE 2006 | Question: 37 top☝ ☛ https://gateoverflow.in/1295

Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared).

The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2 q1 q0 are:
A. 000
B. 001
C. 010
D. 101

gate2006-cse digital-logic circuit-output easy

Answer ☟

4.8.24 Circuit Output: GATE CSE 2006 | Question: 8 top☝ ☛ https://gateoverflow.in/887

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative
edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?

A.

B.

C.

D.

gate2006-cse digital-logic normal circuit-output

Answer ☟

4.8.25 Circuit Output: GATE CSE 2007 | Question: 36 top☝ ☛ https://gateoverflow.in/1234

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”):

© Copyright GATE Overflow. Some rights reserved.

 Clear Clock Load Count Function
1 X X X Clear to 0
0 X 0 0 No Change
0 ↑ 1 X Load Input
0 ↑ 0 1 Count Next

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:
A. 0, 3, 4
B. 0, 3, 4, 5
C. 0, 1, 2, 3, 4
D. 0, 1, 2, 3, 4, 5

gate2007-cse digital-logic circuit-output normal

Answer ☟

4.8.26 Circuit Output: GATE CSE 2010 | Question: 31 top☝ ☛ https://gateoverflow.in/2205

What is the boolean expression for the output f of the combinational logic circuit of NOR gates given below?

¯¯¯¯¯¯¯¯¯¯¯¯¯¯
A. Q + R
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
B. P +Q
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
C. P +R
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
D. P +Q+R

gate2010-cse digital-logic circuit-output normal

Answer ☟

4.8.27 Circuit Output: GATE CSE 2010 | Question: 32 top☝ ☛ https://gateoverflow.in/2206

In the sequential circuit shown below, if the initial value of the output Q1 Q0 is 00. What are the next four values of Q1 Q0 ?

© Copyright GATE Overflow. Some rights reserved.

 A. 11, 10, 01, 00
B. 10, 11, 01, 00
C. 10, 00, 01, 11
D. 11, 10, 00, 01

gate2010-cse digital-logic circuit-output normal

Answer ☟

4.8.28 Circuit Output: GATE CSE 2010 | Question: 9 top☝ ☛ https://gateoverflow.in/2182

The Boolean expression of the output f of the multiplexer shown below is

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
A. P ⊕ Q ⊕ R
B. P ⊕ Q ⊕ R
C. P + Q + R
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
D. P + Q + R

gate2010-cse digital-logic circuit-output easy

Answer ☟

4.8.29 Circuit Output: GATE CSE 2011 | Question: 50 top☝ ☛ https://gateoverflow.in/2157

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

© Copyright GATE Overflow. Some rights reserved.

 If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the
value of PQR after the clock edge?
A. 000
B. 001
C. 010
D. 011

gate2011-cse digital-logic circuit-output flip-flop normal

Answer ☟

4.8.30 Circuit Output: GATE CSE 2011 | Question: 51 top☝ ☛ https://gateoverflow.in/43318

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated
by the counter?
A. 3
4

© Copyright GATE Overflow. Some rights reserved.

 B. 4
C. 5
D. 6

gate2011-cse digital-logic circuit-output normal

Answer ☟

4.8.31 Circuit Output: GATE CSE 2014 Set 3 | Question: 45 top☝ ☛ https://gateoverflow.in/2079

The above synchronous sequential circuit built using JK flip-flops is initialized with Q2 Q1 Q0 = 000 . The state sequence for this
circuit for the next 3 clock cycles is
A. 001, 010, 011
B. 111, 110, 101
C. 100, 110, 111
D. 100, 011, 001

gate2014-cse-set3 digital-logic circuit-output normal

Answer ☟

4.8.32 Circuit Output: GATE IT 2005 | Question: 10 top☝ ☛ https://gateoverflow.in/3755

A two-way switch has three terminals a, b and c. In ON position (logic value 1), a is connected to b, and in OFF position, a is
connected to c. Two of these two-way switches S1 and S2 are connected to a bulb as shown below.

Which of the following expressions, if true, will always result in the lighting of the bulb ?
¯¯¯¯¯¯
A. S1.S2
B. S1 + S2
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
C. S1 ⊕ S2
D. S1 ⊕ S2

gate2005-it digital-logic circuit-output normal

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.8.33 Circuit Output: GATE IT 2005 | Question: 43 top☝ ☛ https://gateoverflow.in/3804

Which of the following input sequences will always generate a 1 at the output z at the end of the third cycle?

A B C
0 0 0
A.
1 0 1
1 1 1
A B C
1 0 1
B.
1 1 0
1 1 1
A B C
0 1 1
C.
1 0 1
1 1 1
A B C
0 0 1
D.
1 1 0
1 1 1

gate2005-it digital-logic circuit-output normal

Answer ☟

4.8.34 Circuit Output: GATE IT 2006 | Question: 36 top☝ ☛ https://gateoverflow.in/3575

The majority function is a Boolean function f(x, y, z) that takes the value 1 whenever a majority of the variables x, y, z are 1.
In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively,

© Copyright GATE Overflow. Some rights reserved.

 A. XOR , AND
B. XOR , XOR
C. OR, OR
D. OR, AND

gate2006-it digital-logic circuit-output normal

Answer ☟

4.8.35 Circuit Output: GATE IT 2007 | Question: 38 top☝ ☛ https://gateoverflow.in/3471

The following expression was to be realized using 2-input AND and OR gates. However, during the fabrication all 2-input
AND gates were mistakenly substituted by 2-input NAND gates. (a. b). c + (a′ . c). d + (b. c). d + a. d
What is the function finally realized ?
A. 1
B. a′ + b′ + c′ + d ′
C. a′ + b + c′ + d ′
D. a′ + b′ + c + d ′

gate2007-it digital-logic circuit-output normal

Answer ☟

4.8.36 Circuit Output: GATE IT 2007 | Question: 40 top☝ ☛ https://gateoverflow.in/3473

What is the final value stored in the linear feedback shift register if the input is 101101 ?

A. 0110
B. 1011
C. 1101
D. 1111

gate2007-it digital-logic circuit-output normal

Answer ☟

4.8.37 Circuit Output: GATE IT 2007 | Question: 45 top☝ ☛ https://gateoverflow.in/3480

The line T in the following figure is permanently connected to the ground.

© Copyright GATE Overflow. Some rights reserved.

 Which of the following inputs (X1 X2 X3 X4 ) will detect the fault ?

A. 0000
B. 0111
C. 1111
D. None of these

gate2007-it digital-logic circuit-output normal

Answer ☟

4.8.38 Circuit Output: GATE IT 2008 | Question: 9 top☝ ☛ https://gateoverflow.in/3269

What Boolean function does the circuit below realize?

A. xz + x̄z̄
B. xz̄ + x̄z
C. x̄ȳ + yz
D. xy + ȳz̄

gate2008-it digital-logic circuit-output normal

Answer ☟

Answers: Circuit Output

4.8.1 Circuit Output: GATE CSE 1989 | Question: 4-ix top☝ ☛ https://gateoverflow.in/88164


This is a sequential circuit (whose output depends not only on the present value of its input signals but on the
sequence of past inputs) not a combinational one (whose output depends only on the present inputs), therefore solving using just
input variable does not yields correct output.
First we need to simplify the circuit.
The two NOT gates at the input end of the NOR gate can be combined with the gate to get: (A′ + B′ )′ = AB
Now, since we have two variables we will have 4 combinations 00 01 10 11.
On analyzing each we will see that for every combination where

A = 0 we have the stable output of 0

A = 1 we will have a RACE condition

© Copyright GATE Overflow. Some rights reserved.

  7 votes -- Abbas Haider (1.7k points)

4.8.2 Circuit Output: GATE CSE 1990 | Question: 3-i top☝ ☛ https://gateoverflow.in/84051


From wikipedia (third paragraph),

' By tying the output of several open collectors together, the common line becomes a "wired AND" (positive-true
logic) or "wired OR" (negative-true logic) gate. A "wired AND" behaves like the boolean AND of the two (or more)
gates in that it will be logic 1 whenever (all) are in the high impedance state, and 0 otherwise. A "wired OR" behaves like
the Boolean OR for negative-true logic, where the output is LOW if any of its inputs are low.

So, after tying the open-collector NAND Gates, the common line becomes a wired AND.
¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯
So, Y = (ABC ) ⋅ (DE )
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
By D’ Morgan’s law, Y = ABC + DE
Hence,
Correct Answer: Option (B)
References

 7 votes -- undefined (2.2k points)

4.8.3 Circuit Output: GATE CSE 1991 | Question: 5-a top☝ ☛ https://gateoverflow.in/531


The output of the circuit given as : Q = aQn−1 + ab + bQn−1

Hence, Qn = Qn−1 (a + b) + ab

00 ⟹ Qn−1 (0 + 0) + 0.0 = Qn−1 (0) + 0 = 0 + 0 = 0

01 ⟹ Qn−1 (0 + 1) + 0.1 = Qn−1 (1) + 0 = Qn−1 + 0 = Qn−1

10 ⟹ Qn−1 (1 + 0) + 1.0 = Qn−1 (1) + 0 = Qn−1 + 0 = Qn−1

11 ⟹ Qn−1 (1 + 1) + 1.1 = Qn−1 (1) + 1 = Qn−1 + 1 = 1

a b Qn
0 0 0
0 1 Qn−1
1 0 Qn−1
1 1 1

 22 votes -- Kalpna Bhargav (2.5k points)

4.8.4 Circuit Output: GATE CSE 1993 | Question: 19 top☝ ☛ https://gateoverflow.in/2316


A(t + 1) = Da = A′ B + A′ P ′

B(t + 1) = Db = P B′ + P ′ A

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 Present State Input Next State
A B P A(t+1) B(t+1)
0 0 0 1 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 0 0

Note: Recheck the table by putting the values ofA, B and P in equations of A(t + 1) and B(t + 1) .
 24 votes -- Praveen Saini (41.9k points)

4.8.5 Circuit Output: GATE CSE 1993 | Question: 6-3 top☝ ☛ https://gateoverflow.in/17237


Circuit behaves as shift register and mod 6 counter

Clock Cycle Output

1 100
2 110
3 111
4 011
5 001
6 000

This is Johnson counter which is an application of Shift Register. And Johnson counter is mod 2N counter.

 50 votes -- Pooja Palod (24.1k points)

4.8.6 Circuit Output: GATE CSE 1993 | Question: 6.1 top☝ ☛ https://gateoverflow.in/2288


(x + x′ y′ ). (y + x′ y′ ) = (x + y′ )(x′ + y) = xy + x′ y′ = Exclusive-NOR
 16 votes -- Praveen Saini (41.9k points)

4.8.7 Circuit Output: GATE CSE 1993 | Question: 6.2 top☝ ☛ https://gateoverflow.in/17235


If a = 0 state changes from S1 to S2 and if b = 0 state changes from S2 to S1 .

So, a = 0, b = 0 is surely not a stable state as then the states will be oscillating. So, the condition for stability is that both a and
¯¯¯¯¯
b should not be 0 together which is given by a + b = 1 or ab = 0.

Options A and C are equivalent and both ensures stable states albeit by enforcing stricter than required conditions.

Correct Answer: Option B.

 13 votes -- Arjun Suresh (332k points)

4.8.8 Circuit Output: GATE CSE 1994 | Question: 1.8 top☝ ☛ https://gateoverflow.in/2445


(((AB)′ C )′ (CD)′ )′ = ((AB)′ C) + CD) = (A′ + B′ )C + CD = A′ C + B′ C + CD
 39 votes -- Arjun Suresh (332k points)

4.8.9 Circuit Output: GATE CSE 1994 | Question: 11 top☝ ☛ https://gateoverflow.in/2507


Initial Q2 = 0, Q1 = 0, Q0 = 0

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 Clock 1 :

Q2 = 1 [J = ( old Q0 )′ = 1, K = 1, New Q2 = Complement of old Q2 = 1]

Q1 = 0 [D =old Q2 = 0, new Q1 = D = 0]
Q0 = 0 [T = old Q1 = 0, New Q0 = old Q0 = 0]

Clock 2 :

Q2 = 0 [J = ( old Q0 )′ = 1, K = 1, New Q2 = Complement of old Q2 = 0]

Q1 = 1 [D =old Q2 = 1, new Q1 = D = 1]
Q0 = 0 [T = old Q1 = 0, New Q0 = old Q0 = 0]

Clock 3 :

Q2 = 1 [J = ( old Q0 )′ = 1, K = 1, New Q2 = Complement of old Q2 = 1]

Q1 = 0 [D = old Q2 = 0, New Q1 = D = 0]
Q0 = 1 [T = old Q1 = 1, New Q0 = complement of old Q0 = 1]

Clock 4 :

Q2 = 0 [J =( old Q0 )′ = 0, K = 1 , new Q2 = Reset= 0]

Q1 = 1 [D =old Q2 = 1, new Q1 = D = 1]
Q0 = 1 [T =old Q1 = 0, new Q0 = old Q0 = 1]

After 4 clock pulses Q2Q1Q0 is 011

Note : for JK flipflops, Q(t+1) = J Q′ + K ′ Q , for D flipflops, Q(t+1) = D , and for T flipflops Q(t+1) = T ⊕ Q Where Q(t+1)
represent new value of Q.

 31 votes -- Praveen Saini (41.9k points)

4.8.10 Circuit Output: GATE CSE 1996 | Question: 2.21 top☝ ☛ https://gateoverflow.in/2750


Whenever, b2 = b3 = 1, then only 0100 i.e., 4 is added to the given binary number. Let's write all possibilities for b.

b3 b2 b1 b0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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 Note that the last 4 combinations (1100 , 1101 , 1110 , 1111 ) leads to b3 and b2 as 1. So, in these combinations only 0100 will be
added.

1100 is 12
1101 is 13
1110 is 14
1111 is 15
in binary unsigned number system.

1100 + 0100 = 10000 .

1101 + 0100 = 10001 and so on.
This is conversion to radix 12.

Correct Answer: D
 21 votes -- Monanshi Jain (7k points)

4.8.11 Circuit Output: GATE CSE 1996 | Question: 24-a top☝ ☛ https://gateoverflow.in/2776


State Diagram :
S7 → S3 → S1 → S4 → S2 → S5 → S6 → S7
b. Given the initial state S4 , S0 state will not be reachable. If the system enters S0 state then Q0 =Q1 =Q2 = 0 and after that it
will stay in S0 state indefinitely and can't go to any other state.

 18 votes -- shreya ghosh (2.8k points)

4.8.12 Circuit Output: GATE CSE 1996 | Question: 24-b top☝ ☛ https://gateoverflow.in/203691


Q3N = D3 ⇒ Q3N = Q2
Q2N = D2 ⇒ Q2N = Q1
Q1N = D1 ⇒ Q1N = Q3 ⊕ Q2

Q1 Q2 Q3 Q1N Q2N Q3N

0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 0 1 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 1 1

Given that the initial state = S4 = 100.

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 Unreachable state is S0
So, set of states which are not reachable = {S0 }

 9 votes -- Pinaki Dash (1.5k points)

4.8.13 Circuit Output: GATE CSE 1997 | Question: 5.5 top☝ ☛ https://gateoverflow.in/2256


f = (f1 ∧ f2 ) ∨ f3

Since f1 and f2 are in canonical sum of products form, f1 ∧ f2 will only contain their common terms- that is f1 ∧ f2 = Σ8

Now, Σ8 ∨ f3 = Σ8, 9
So, f3 = Σ9

Correct Answer: B
 31 votes -- Arjun Suresh (332k points)

4.8.14 Circuit Output: GATE CSE 1999 | Question: 2.8 top☝ ☛ https://gateoverflow.in/1486


The figure is not clear- I assume there is a NOT gate just before taking Y making the final AND gate a NAND gate.

We have a steady state- meaning output is not changing. Y is 1 and remains 1 in the next state(s). So, we can write

¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯ ¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯
Y = ((AY ). B) . C
¯¯¯¯ ¯¯¯¯
1 = A. B + C
¯¯¯¯
So, C = 0 or A. B = 1

So, option B is TRUE.

 19 votes -- Arjun Suresh (332k points)

4.8.15 Circuit Output: GATE CSE 2000 | Question: 2.12 top☝ ☛ https://gateoverflow.in/659


Here, clocks are applied to both flip flops simultaneously. Outputs for 3 cycles will proceed as follows:

When 11 is applied to JK flip flop it toggles the value of P. So, output at P will be 1.
Input to D flip flop will be 0 (initial value of P). So, output at Q will be 0.

JK flip flop it toggles the value of P. So, output at P will be 0.

Input to D flip flop will be 1 (current value of P) . So, output at Q will be 1.

JK flip flop it toggles the value of P. So, output at P will be 1.

Input to D flip flop will be 0 (initial value of P) so output at Q will be 0.

So, answer is A.

 56 votes -- Pooja Palod (24.1k points)

4.8.16 Circuit Output: GATE CSE 2001 | Question: 2.8 top☝ ☛ https://gateoverflow.in/726


Answer is (a).

Given clock is + edge triggered.

See the first positive edge. X is 0, and hence, the output is 0. Q0 is 0 and Q′0 is 1.
Second + edge, X is 1 and Q′0 is also 1. So, output is 1. (When second positive edge of the clock arrives, Q′0 would surely be 1
because the setup time of flip-flop is given as 20 ns and the clock period is ≥ 40 ns)
Third + edge, X is 1 and Q′0 is 0, So, output is 0. (Q′0 becomes 0 before the third positive edge, but output Y would not change

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 as the flip-flop is positive edge triggered)
Now, output never changes back to 1 as Q′0 is always 0 and when Q′0 finally becomes 1, X is 0.

Set up time and hold times are given just to ensure that edge triggering works properly.

 50 votes -- Arjun Suresh (332k points)

4.8.17 Circuit Output: GATE CSE 2002 | Question: 2.2 top☝ ☛ https://gateoverflow.in/832


As x is connected to I0 & I1, y connected to I2, y ′ connected to I3 & A1, z connected to A0 and z ′ connected to
ENABLE (EN),

¯¯¯¯¯¯ ¯¯¯¯¯¯ ¯¯¯¯¯¯ ¯¯¯¯¯¯

f = (A1. A0. I0 + A1. A0.I1 + A1.A0. I2 + A1.A0.I3). EN

⟹ f = (xyz ′ + xyz + y′ z ′ y + zy′ )z ′

= (xyz ′ + xyz + zy′ )z ′ = xyz ′

Correct Answer: A
 58 votes -- Digvijay (44.9k points)

4.8.18 Circuit Output: GATE CSE 2004 | Question: 61 top☝ ☛ https://gateoverflow.in/1056


Sequence is 0 − 2 − 3 − 1 − 0

From the given sequence, we have state table as

Q2 Q1 Q+
2 Q+
1
0 0 1 0
0 1 0 0
1 0 1 1
1 1 0 1

Now we have present state and next state, use excitation table of T flip-flop

Q2 Q1 Q+
2 Q+
1 T2 T1
0 0 1 0 1 0
0 1 0 0 0 1
1 0 1 1 0 1
1 1 0 1 1 0

From state table, T2 = Q2 ⊙ Q1 , and T1 = Q2 ⊕ Q1

X = T1 = Q2 ⊕ Q1

Correct Answer: D
 85 votes -- Praveen Saini (41.9k points)

4.8.19 Circuit Output: GATE CSE 2005 | Question: 15 top☝ ☛ https://gateoverflow.in/1351


The expression will be

f = [(x. y ′ )′ . (y. z)]′ = [(x′ + y). (y. z)]′ = [x′ . y. z + y. z]′ = [(x′ + 1). (y. z)]′ = [1.(y. z)]′ = [y. z]′ = y′ + z ′

The final expression only contains y and z,

Therefore, answer will be (a) f is Independent of x

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  28 votes -- jec.himanshu (189 points)

4.8.20 Circuit Output: GATE CSE 2005 | Question: 62 top☝ ☛ https://gateoverflow.in/264


D = AX + X ′ Q′
Y =D

Ai represent the logic level on the line A at the ith clock period. If we see the timing diagram carefully, we can see that during
the rising edge, the output Y is determined by the X value just before that rising edge. i.e., during the rising edge say for clk2, X
value that determines the output is 1 and not 0 (because it takes some propagation delay for the 0 to reach the flip flop).
Similarly, the A output that determines the output for clk i, is Ai−1 .

For clk1, X is 1, so, D = A = A0

For clk2, X is 1, so D = A = A1
For clk3, X is 0, so D = Q′2 = A′1
For clk4, X is 1, so D = A = A3
For clk5, X is 1, so D = A = A4

So, answer is A choice.

 69 votes -- Arjun Suresh (332k points)

4.8.21 Circuit Output: GATE CSE 2005 | Question: 64 top☝ ☛ https://gateoverflow.in/1387


Clearly, Q0 alternates in every clk cycle as Q′0 is fed as input and it is D flipflop.
Q1 becomes 1 if its prev value and current Q0 differs (EXOR).

So, the sequence of transitions will be : 00 → 11 → 01 → 10 → 00 , (D) choice.

 34 votes -- Arjun Suresh (332k points)

4.8.22 Circuit Output: GATE CSE 2006 | Question: 35 top☝ ☛ https://gateoverflow.in/1292


Result of MUX (first one), is, say f1 = xz̄ + ȳ z
Result of MUX(second one), f = f1 ȳ + xy

= (xz̄ + ȳ z)ȳ + xy
= xȳz̄ + ȳ z + xy
= x(ȳz̄ + y) + ȳ z
= x(ȳ + y)(z̄ + y) + ȳ z
= xz ′ + xy + y′ z.

Option A.

Note:

1. f = I0 S̄ + I1 S, for 2 : 1 MUX, where I0 and I1 are inputs, S is the select line

2. Distributive property, A + BC = (A + B)(A + C)
3. A + Ā = 1

 52 votes -- Praveen Saini (41.9k points)

4.8.23 Circuit Output: GATE CSE 2006 | Question: 37 top☝ ☛ https://gateoverflow.in/1295

© Copyright GATE Overflow. Some rights reserved.

 Data Q0 Q1 Q2
1 1 Q0start XOR Q2start = 0 XOR 0 = 0 Q1start = 0
0 0 1 XOR 0 = 1 0
0 0 0 XOR 0 = 0 1
1 1 0XOR 1 = 1 0
1 1 1 XOR 0 = 1 1
0 0 1 XOR 1 = 0 1
0 0 0XOR 1 = 1 0
0 0 0 XOR 0 = 0 1
0 0 0 XOR 1 = 1 0

So, option C.
 40 votes -- Arjun Suresh (332k points)

4.8.24 Circuit Output: GATE CSE 2006 | Question: 8 top☝ ☛ https://gateoverflow.in/887

Ans- C.

 42 votes -- Aaditya Pundir (361 points)

B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a

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 phase difference of 180 degrees.
 11 votes -- Arjun Suresh (332k points)

4.8.25 Circuit Output: GATE CSE 2007 | Question: 36 top☝ ☛ https://gateoverflow.in/1234


Whenever A4A3A2A1 = 0101, clear line will be enabled as A3 and A1 are set.

Given table says that whenever clear control signal is set, it clears to 0000, before the current clock cycle completes.

So, 5 is cleared to 0 in the same clock cycle and counter sequence is 0, 1, 2, 3, 4

Hence, option C .
 40 votes -- pramod (2.8k points)

(C) is the correct answer!

Remark :
1. If clear = 1 , counter will be reset to 0000 without any delay, and counter doesn't count 5 .
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
2. If load = 1 , counter will be loaded with the input 0011, but note that −
counter
−−−−−−counts
−−−−−− 5−in
−−this
−−−case
−−− unlike clear input.
3. Counter counts from 0 to 4.
4. Clear and Load are direct inputs, it means they can be applied to the counter without using any pulse.

When the output reaches the count of 1001, both A0 and A3 become 1, making the output of the AND gate equal to 1.
This condition activates the Load input; therefore, on the next clock edge the register does not
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
count, but is loaded from its four inputs . Since all four inputs are connected to logic 0,
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
an all‐0’s value is loaded into the register following the count of 1001. Thus, the circuit goes through the count from 0000
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
through 1001 and back to 0000, as is required in a BCD counter.
In Fig (b), the NAND gate detects the count of 1010, but as soon as this count occurs,
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
the register is cleared. The count 1010 has no chance of staying
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
on for any appreciable time, because the register goes immediately to 0
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
1. If clear = 1 , then clear the counter.
2. If clear = 0, load = 0, count = 1, counter counts.
3. load = 1, loads the input to the counter.

If load = 1 , then counter will be loaded with i/p = 0011

to the given counter, count = 1load = 0clock =↑

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 Note:
−−−−− If o/p of AND gate is led to load , then counter will be loaded with 0011 .
 29 votes -- Manu Thakur (34k points)

4.8.26 Circuit Output: GATE CSE 2010 | Question: 31 top☝ ☛ https://gateoverflow.in/2205


Level 1:
¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
(P + Q )(Q + R )(P + R )(Q + R )

Level 2:
¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯
(P + Q ) + (Q + R ) = (P + Q)(Q + R) = PQ + PR + Q + QR
¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯
(P + R )(Q + R ) = (P + R)(Q + R) = PQ + R + QR + PR

Level 3:
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
PR + QR + PQ + Q + R = Q + R ∴ Answer: Option A
 24 votes -- Sona Praneeth Akula (3.4k points)

4.8.27 Circuit Output: GATE CSE 2010 | Question: 32 top☝ ☛ https://gateoverflow.in/2206


Option A.

2nd flip-flop will be active only when 1st flip flop produces output 1. For clocks 2 and 4 old output is retained by Flip-Flop 2.
T0 Q0 T1 Q1
Q1 Q0
0 0
T Qn+1 1 1
1 1 1 1
0 Qn 1 0
¯¯¯¯¯¯¯ 1 0 1 1
1 Qn 0 1
1 1 1 0
0 0
1 0 1 0
For rows 2 and 4, Clk for T1 is 0 and hence old o/p is retained

 47 votes -- Akhil Nadh PC (16.5k points)

4.8.28 Circuit Output: GATE CSE 2010 | Question: 9 top☝ ☛ https://gateoverflow.in/2182


f = S0′ S1′ R + S0′ S1 R′ + S0 S1′ R′ + S0 S1 R
= Q′ P ′ R + Q′ P R′ + QP ′ R′ + QPR
= Q′ (P ⊕ R) + Q(P ⊕ R)′
= Q⊕P ⊕R = P ⊕Q⊕R

Doing truth value substitution,

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 P Q R f P⊕Q⊕R
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Correct Answer: B
 32 votes -- Arjun Suresh (332k points)

4.8.29 Circuit Output: GATE CSE 2011 | Question: 50 top☝ ☛ https://gateoverflow.in/2157


Answer - D
As in D-flip-flop , next output is Q+ = D

Pi+1 = Ri
Qi+1 = (Pi + Ri )′
Ri+1 = R′i Qi

CLOCK Inputs Outputs

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯
D1 = R D2 =(P + R) D3 = Q R P Q R
1 0 1 0 0 1 0
2 0 1 1 0 1 1
3 1 0 0 1 0 0
4 0 0 0 0 0 0
5 0 1 0 0 1 0

So, total number of distinct outputs = 4.

 28 votes -- Ankit Rokde (6.9k points)

4.8.30 Circuit Output: GATE CSE 2011 | Question: 51 top☝ ☛ https://gateoverflow.in/43318


Characteristic equation of D FF is , Q(t + 1) = D

¯¯¯¯¯¯¯¯¯¯¯¯¯¯
So, P + = R, Q+ = P + R , and R+ = Q. R′

Sequence of states will be as:

Clock Pulse PQR

Initially 000
1 010
2 011
3 100
4 000

4 is the number of distinct states.

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 Correct Answer: B
 27 votes -- Praveen Saini (41.9k points)

4.8.31 Circuit Output: GATE CSE 2014 Set 3 | Question: 45 top☝ ☛ https://gateoverflow.in/2079

Option C

 39 votes -- Gate_15_isHere (459 points)

4.8.32 Circuit Output: GATE IT 2005 | Question: 10 top☝ ☛ https://gateoverflow.in/3755


If we look carefully, bulb will be ON when both switches S1 and S2 are in the same state, either off or on.

S1 S2 Bulb
0 0 On
0 1 Off
1 0 Off
1 1 On

This is Ex-NOR operation, hence (C) is the correct option.

 53 votes -- Manu Thakur (34k points)

4.8.33 Circuit Output: GATE IT 2005 | Question: 43 top☝ ☛ https://gateoverflow.in/3804

A B C Q1 Q2 Z Comment
st
After 1 Cycle X X X X X X
After 2nd Cycle 0 0 X 0 X X Q1 is 0 making A and B 0
rd
After 3 Cycle X X 1 1 1 1 Z is 1 making Q1 and Q2 1,
Either A or B is 1.
Q1′ of previous cycle is 1.

The filling is done in reverse order. Here, none of the options match. So, something wrong somewhere.
 41 votes -- Arjun Suresh (332k points)

4.8.34 Circuit Output: GATE IT 2006 | Question: 36 top☝ ☛ https://gateoverflow.in/3575


Given expression:

xP + x̄Q = f

Or, x(y op1 z) + x̄(y op2 z) = f → (1)

© Copyright GATE Overflow. Some rights reserved.

 X Y Z Output(f)
0 0 0 0
0 0 1 0
0 1 0 0 x\yz 00 01 11 10
0 1 1 1 0 ... ... 1 ...
1 0 0 0 1 ... 1 1 1
1 0 1 1
1 1 0 1
1 1 1 1

f ⟹ xz + xy + yz

⟹ xz + xy + (x + x̄)yz

⟹ xz + xy + xyz + x̄yz

⟹ x(z + y + yz) + x̄yz

⟹ x[z + y(1 + z)] + x̄(y ∙ z)

⟹ x(z + y) + x̄(y ∙ z) → (2)

Comparing (1) and (2) we get,

OP1 = +(OR)

OP2 = ∙(AND)

Correct Answer: D
 63 votes -- Subhankar Das (357 points)

4.8.35 Circuit Output: GATE IT 2007 | Question: 38 top☝ ☛ https://gateoverflow.in/3471


The final answer will come as:

a′ + c′ + d ′ + a′ c + ab + bc

= a′ (c + 1) + c′ + d ′ + ab + bc

= a′ + c′ + d ′ + ab + bc

= (a′ + a)(a′ + b) + (c′ + c)(c′ + b) + d ′

= a′ + b + c′ + b + d ′

= a′ + b + c′ + d ′

Option is C.

 29 votes -- Manali (2.1k points)

4.8.36 Circuit Output: GATE IT 2007 | Question: 40 top☝ ☛ https://gateoverflow.in/3473


Answer: (A)
The four bit register contains: 1011, 1101, 0110, 1011, 1101, 0110 after each shift.

 29 votes -- Rajarshi Sarkar (27.9k points)

© Copyright GATE Overflow. Some rights reserved.

 4.8.37 Circuit Output: GATE IT 2007 | Question: 45 top☝ ☛ https://gateoverflow.in/3480


To detect the fault, we should get an unexpected output. The final gate here is a NOR gate which produces output 0 if
either of its input is 1 and else 1. i.e., the output will be 0 for inputs (0, 1), (1, 0) and (1, 1) and output will be 1 for (0,0).
By grounding T is at 0. So, we can ignore the inputs (1, 0) and (0, 0) to the final NOR gate as they won't be detecting faults.
Now, expected (1, 1) input will become (1, 0) due to grounding of T but produces same output 0 as for (1, 1) . Hence this also
cannot detect the defect. So, to detect the defect, the input to the final gate must be (0, 1) which is expected to produce a 0 but
will produce a 1 due to grounding of T .
Now, for (0, 1) input for the final gate, we must have,
X3 = X4 = 1
But if X4 = 1, the OR gate makes 1 output and we won't get (0, 1) input for the final gate. This means, no input sequence can
detect the fault of the circuit.

Alternatively, we can write equation for the circuit as

(((x1 . x2 . x3 )′ + x4 ) + x3 . x4 )′ = ((x1 . x2 . x3 )′ + x4 )′ . (x3 . x4 )′ = x1 . x2 . x3 . x′4 . (x′3 + x′4 ) = x1 . x2 . x3 . x′4
For the faulty circuit output will be
((x1 . x2 . x3 )′ + x4 )′ = x1 . x2 . x3 . x′4
So, there is no effect of T being grounded here. Answer is D option.

 69 votes -- Arjun Suresh (332k points)

4.8.38 Circuit Output: GATE IT 2008 | Question: 9 top☝ ☛ https://gateoverflow.in/3269


Answer: B

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
F = (x̄z̄ + xz) = xz̄ + x̄z
 35 votes -- Rajarshi Sarkar (27.9k points)

4.9 Conjunctive Normal Form (1) top☝

4.9.1 Conjunctive Normal Form: GATE CSE 2007 | Question: 48 top☝ ☛ https://gateoverflow.in/1246

Which of the following is TRUE about formulae in Conjunctive Normal Form?

A. For any formula, there is a truth assignment for which at least half the clauses evaluate to true.
B. For any formula, there is a truth assignment for which all the clauses evaluate to true.
C. There is a formula such that for each truth assignment, at most one-fourth of the clauses evaluate to true.
D. None of the above.

gate2007-cse digital-logic normal conjunctive-normal-form

Answer ☟

Answers: Conjunctive Normal Form

4.9.1 Conjunctive Normal Form: GATE CSE 2007 | Question: 48 top☝ ☛ https://gateoverflow.in/1246


Answer is option A.

To Prove: For any formula, there is a truth assignment for which at least half the clauses evaluate to true
Proof:
Consider an arbitrary truth assignment. For each of its clause i, introduce a random variable.

1 if clause i is satisfied;
Xi = {
0 otherwise.

© Copyright GATE Overflow. Some rights reserved.

 Then, X = ∑i Xi is the number of satisfied clauses.
Given any clause c, it is unsatisfied only if all of its k constituent literals evaluates to false; as they are joined by OR operator coz
the formula is in CNF.
Now, because each literal within a clause has a 12 chance of evaluating to true independently of any of the truth value of any of
k
the other literals, the probability that they are all false is ( 12 ) = 1
.
2k
1
Thus, the probability that c is satisfied(true) is 1 −
2k

So, E(Xi ) = 1 × (1 − 1
) =1− 1
2k 2k
This means that E(Xi ) ≥ 12
(try putting arbitrary valid values of k to see that)
Summation on both sides to get E(X) ,
Therefore, we have E(X) = ∑i E(Xi ) ≥ m 2 ; where m is the number of clauses.
E(X) represents expected number of satisfied(to true) clauses.
So, there must exist an assignment that satisfies(to true) at least half of the clauses.

 52 votes -- Amar Vashishth (25.2k points)

4.10 Decoder (2) top☝

4.10.1 Decoder: GATE CSE 2007 | Question: 8, ISRO2011-31 top☝ ☛ https://gateoverflow.in/1206

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other
logic gates?
A. 7
B. 8
C. 9
D. 10

gate2007-cse digital-logic normal isro2011 decoder

Answer ☟

4.10.2 Decoder: GATE CSE 2020 | Question: 20 top☝ ☛ https://gateoverflow.in/333211

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then
the minimum value of m + n is ________ .

gate2020-cse numerical-answers digital-logic decoder

Answer ☟

Answers: Decoder

4.10.1 Decoder: GATE CSE 2007 | Question: 8, ISRO2011-31 top☝ ☛ https://gateoverflow.in/1206


Answer is C:

To get 6 : 64 we need 64 o/p

We have 3 : 8 decode with 8 o/p . So, we need 64/8 = 8 decoders.

Now, to select any of this 8 decoder we need one more decoder.

Total= 8 + 1 = 9 decoders

 45 votes -- jayendra (6.7k points)

4.10.2 Decoder: GATE CSE 2020 | Question: 20 top☝ ☛ https://gateoverflow.in/333211

© Copyright GATE Overflow. Some rights reserved.

 
Given that we need to address every byte of a 1 KB RAM.
Therefore 1K addresses are needed.

By using decoder, output lines should be n = 1 K = 1024.

This means we should have number of input lines, m = log2 1024 = 10.

Thus, m + n = 10 + 1024 = 1034.

 12 votes -- Shaik Masthan (50.4k points)

4.11 Digital Circuits (7) top☝

4.11.1 Digital Circuits: GATE CSE 1992 | Question: 02-ii top☝ ☛ https://gateoverflow.in/556

All digital circuits can be realized using only

A. Ex-OR gates
B. Multiplexers
C. Half adders
D. OR gates

gate1992 normal digital-logic digital-circuits multiple-selects

Answer ☟

4.11.2 Digital Circuits: GATE CSE 1996 | Question: 5 top☝ ☛ https://gateoverflow.in/2757

A logic network has two data inputs A and B, and two control inputs C0 and C1 . It implements the function F according to
the following table.

C1 C0 F
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
0 0 A+B
0 1 A+B
1 0 A⊕B

Implement the circuit using one 4 to 1 Multiplexer, one 2− input Exclusive OR gate, one 2− input AND gate, one 2− input OR gate
and one Inverter.

gate1996 digital-logic normal digital-circuits descriptive

Answer ☟

4.11.3 Digital Circuits: GATE CSE 2002 | Question: 7 top☝ ☛ https://gateoverflow.in/860

A. Express the function f(x, y, z) = xy ′ + yz ′ with only one complement operation and one or more AND/OR operations.
Draw the logic circuit implementing the expression obtained, using a single NOT gate and one or more AND/OR gates.
B. Transform the following logic circuit (without expressing its switching function) into an equivalent logic circuit that employs
only 6 NAND gates each with 2-inputs.

gate2002-cse digital-logic normal descriptive digital-circuits

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.11.4 Digital Circuits: GATE CSE 2003 | Question: 47 top☝ ☛ https://gateoverflow.in/29098

Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays δ1 = 2ns and δ2 = 4ns as shown in the figure. Both XOR gates and all wires have zero
delays. Assume that all gate inputs, outputs, and wires are stable at logic level 0 at time 0. If the following waveform is applied at
input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns?

A. 1
B. 2
C. 3
D. 4

gate2003-cse digital-logic digital-circuits

Answer ☟

4.11.5 Digital Circuits: GATE CSE 2011 | Question: 13 top☝ ☛ https://gateoverflow.in/2115

Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR ) gate?

A.

B.

C.

D.

gate2011-cse digital-logic normal digital-circuits

Answer ☟

4.11.6 Digital Circuits: GATE CSE 2013 | Question: 5 top☝ ☛ https://gateoverflow.in/1414

In the following truth table, V = 1 if and only if the input is valid.

Inputs Outputs
D0 D1 D2 D3 X0 X1 V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1

© Copyright GATE Overflow. Some rights reserved.

 What function does the truth table represent?
A. Priority encoder
B. Decoder
C. Multiplexer
D. Demultiplexer

gate2013-cse digital-logic normal digital-circuits

Answer ☟

4.11.7 Digital Circuits: GATE CSE 2014 Set 3 | Question: 8 top☝ ☛ https://gateoverflow.in/2042

Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs
and y is the output.
f(x, a, b, y)
{
if(x is 1) y = a;
else y = b;
}

Which one of the following digital logic blocks is the most suitable for implementing this function?
A. Full adder
B. Priority encoder
C. Multiplexor
D. Flip-flop

gate2014-cse-set3 digital-logic easy digital-circuits

Answer ☟

Answers: Digital Circuits

4.11.1 Digital Circuits: GATE CSE 1992 | Question: 02-ii top☝ ☛ https://gateoverflow.in/556


Answer: B, C

NOR gate, NAND gate, Multiplexers and Half adders can also be used to realise all digital circuits.
 19 votes -- Rajarshi Sarkar (27.9k points)

4.11.2 Digital Circuits: GATE CSE 1996 | Question: 5 top☝ ☛ https://gateoverflow.in/2757

This is the implementation asked in question

C0 = 0, C1 =0 line 00 will be selected and F will give (A + B)′

C0 = 0, C1 =1 line 01 will be selected and F will give (A ⊕ B)
C0 = 1, C1 =0 line 10 will be selected and F will give (A + B)
C0 = 1, C1 =1 line 11 will be selected and F will give (A + B)′ . (A + B) = 0

 26 votes -- Praveen Saini (41.9k points)

© Copyright GATE Overflow. Some rights reserved.

 4.11.3 Digital Circuits: GATE CSE 2002 | Question: 7 top☝ ☛ https://gateoverflow.in/860


f(x, y, z) = xy′ + yz ′ = xy′ z ′ + xy′ z + x′ yz ′ + xyz ′
f(x, y, z) = ∑m (2, 4, 5, 6)

K-map

By pairing of 1′ s , we get two pairs (2, 6), (4, 5) resulting in same expression F = xy ′ + yz ′
But by pairing of 0′ s , we get two pairs (0, 1), (2, 7), we get F ′ = yz + x′ y ′
¯¯¯¯¯¯¯¯¯
Take complement, F = (yz). (x + y)
so we can implement the function with 1 NOT , 1 OR and 2 AND gates.
For the second part , we need to implement given circuit using NANDs only.
¯¯¯¯¯¯¯¯¯¯¯
so best way is to replace OR with Invert NAND, A + B = (ĀB̄)

© Copyright GATE Overflow. Some rights reserved.

  44 votes -- Praveen Saini (41.9k points)

4.11.4 Digital Circuits: GATE CSE 2003 | Question: 47 top☝ ☛ https://gateoverflow.in/29098

Let us plot the logic states at the various points of interests in this circuit.

© Copyright GATE Overflow. Some rights reserved.

 Explanation :
−−−−−−−−−−−

Note that, is not an inverter but a buffer used for introducing delay.
∴ Output at 'P' and 'R' will be obtained at 2 ns and 4 ns respectively after the change in their inputs.
Hence, waveforms of 'P' and 'R' are shifted by 2 ns and 4 ns as compared to their inputs.
Also, note that 'Q' and 'B' are plotted using their corresponding input waveforms.
Finally, we can see that there are 4 changes in logic levels in the waveforms of 'B'.
Answer is : Option D

 108 votes -- tvkkk (1.1k points)

4.11.5 Digital Circuits: GATE CSE 2011 | Question: 13 top☝ ☛ https://gateoverflow.in/2115


A. (AB′ + A′ B)′ = A ⊙ B
B. (A′ (B′ )′ + (A′ )′ B′ )′ = (A ⊕ B)′ = A ⊙ B
C. A′ B′ + (A′ )′ B = A ⊙ B
D. ((AB′ )′ . (A + B′ ))′ = (AB′ ) + (A + B′ )′ = AB′ + A′ B = A ⊕ B

So, Answer is (D)

 26 votes -- srestha (85.2k points)

4.11.6 Digital Circuits: GATE CSE 2013 | Question: 5 top☝ ☛ https://gateoverflow.in/1414


Answer is A.
For 2n inputs we are having n outputs. Here n=2.
http://en.wikipedia.org/wiki/Priority_encoder
References

 27 votes -- Sona Praneeth Akula (3.4k points)

4.11.7 Digital Circuits: GATE CSE 2014 Set 3 | Question: 8 top☝ ☛ https://gateoverflow.in/2042


If X=1 Y = a;
else (X = 0) Y = b;
Input : (a, b, X) Output : Y

Y = X̄b + Xa.

© Copyright GATE Overflow. Some rights reserved.

 Correct Answer: C

 38 votes -- Prateek kumar (6.7k points)

4.12 Digital Counter (10) top☝

4.12.1 Digital Counter: GATE CSE 1987 | Question: 10c top☝ ☛ https://gateoverflow.in/82452

Give a minimal DFA that performs as a mod − 3, 1's counter, i.e. outputs a 1 each time the number of 1's in the input
sequence is a multiple of 3.

gate1987 digital-logic digital-counter descriptive

Answer ☟

4.12.2 Digital Counter: GATE CSE 2002 | Question: 8 top☝ ☛ https://gateoverflow.in/861

Consider the following circuit. A = a2 a1 a0 and B = b2 b1 b0 are three bit binary numbers input to the circuit. The output is
Z = z3 z2 z1 z0 . R0, R1 and R2 are registers with loading clock shown. The registers are loaded with their input data with the falling
edge of a clock pulse (signal CLOCK shown) and appears as shown. The bits of input number A, B and the full adders are as shown
in the circuit. Assume Clock period is greater than the settling time of all circuits.

a. For 8 clock pulses on the CLOCK terminal and the inputs A, B as shown, obtain the output Z (sequence of 4 − bit values of Z).
Assume initial contents of R0 , R1 and R2 as all zeros.

A 110 011 111 101 000 000 000 000

B 101 101 011 110 000 000 000 000
Clock No 1 2 3 4 5 6 7 8

b. What does the circuit implement?

gate2002-cse digital-logic normal descriptive digital-counter

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.12.3 Digital Counter: GATE CSE 2011 | Question: 15 top☝ ☛ https://gateoverflow.in/2117

The minimum number of D flip-flops needed to design a mod-258 counter is

A. 9
B. 8
C. 512
D. 258

gate2011-cse digital-logic normal digital-counter

Answer ☟

4.12.4 Digital Counter: GATE CSE 2014 Set 2 | Question: 7 top☝ ☛ https://gateoverflow.in/1959

Let k = 2n . A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is
equivalent to a
A. k -bit binary up counter.
B. k -bit binary down counter.
C. k --bit ring counter.
D. k -bit Johnson counter.

gate2014-cse-set2 digital-logic normal digital-counter

Answer ☟

4.12.5 Digital Counter: GATE CSE 2015 Set 1 | Question: 20 top☝ ☛ https://gateoverflow.in/8219

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
A. 0, 1, 3, 7, 15, 14, 12, 8, 0
B. 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
C. 0, 2, 4, 6, 8, 10, 12, 14, 0
D. 0, 8, 12, 14, 15, 7, 3, 1, 0

gate2015-cse-set1 digital-logic digital-counter easy

Answer ☟

4.12.6 Digital Counter: GATE CSE 2015 Set 2 | Question: 7 top☝ ☛ https://gateoverflow.in/8054

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3,
3, 0, 0, ...) is _______.

gate2015-cse-set2 digital-logic digital-counter normal numerical-answers

Answer ☟

4.12.7 Digital Counter: GATE CSE 2016 Set 1 | Question: 8 top☝ ☛ https://gateoverflow.in/39670

We want to design a synchronous counter that counts the sequence

0 − 1 − 0 − 2 − 0 − 3 and then repeats. The minimum number of
J-K flip-flops required to implement this counter is _____________.

gate2016-cse-set1 digital-logic digital-counter flip-flop normal numerical-answers

Answer ☟

4.12.8 Digital Counter: GATE CSE 2017 Set 2 | Question: 42 top☝ ☛ https://gateoverflow.in/118557

The next state table of a 2− bit saturating up-counter is given below.

© Copyright GATE Overflow. Some rights reserved.

 Q1 Q0 Q+
1 Q+
0
0 0 0 1
0 1 1 0
1 0 1 1
1 1 1 1
The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are

A. T1 = Q1 Q0 , T0 = Q¯1 Q¯0
B. T1 = Q¯1 Q0 , T0 = Q¯1 + Q¯0
C. T1 = Q1 + Q0 , T0 = Q¯1 Q¯0
D. T1 = Q¯1 Q0 , T0 = Q1 + Q0

gate2017-cse-set2 digital-logic digital-counter

Answer ☟

4.12.9 Digital Counter: GATE IT 2005 | Question: 11 top☝ ☛ https://gateoverflow.in/3756

How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the
LSB)?
A. 134
B. 133
C. 124
D. 123

gate2005-it digital-logic digital-counter normal

Answer ☟

4.12.10 Digital Counter: GATE IT 2008 | Question: 37 top☝ ☛ https://gateoverflow.in/3347

Consider the following state diagram and its realization by a JK flip flop

The combinational circuit generates J and K in terms of x, y and Q.

The Boolean expressions for J and K are :
¯¯¯¯¯¯¯¯¯¯¯
A. x⊕y and ¯x
¯¯¯¯¯¯¯¯¯¯
⊕y
¯¯¯¯¯¯¯¯¯¯¯
B. x⊕y and x ⊕ y
C. x⊕y and ¯x
¯¯¯¯¯¯¯¯¯¯
⊕y
D. x⊕y and x ⊕ y

gate2008-it digital-logic boolean-algebra normal digital-counter

Answer ☟

Answers: Digital Counter

4.12.1 Digital Counter: GATE CSE 1987 | Question: 10c top☝ ☛ https://gateoverflow.in/82452


Since it is given that the minimal DFA outputs 1 ⟹ we have to make a minimal DFA and then convert it into mealy/
moore machine by associating output with each input or state.

© Copyright GATE Overflow. Some rights reserved.

 the minimal DFA will be as shown below :-

I am associating output with each input i.e. creating a mealy machine. It will print 1 each time the number of 1's in the input
sequence is a multiple of 3.

 7 votes -- Satbir Singh (21k points)

4.12.2 Digital Counter: GATE CSE 2002 | Question: 8 top☝ ☛ https://gateoverflow.in/861


(A)

output Z
Clock-1 0000
Clock-2 0000
Clock-3 1011
Clock-4 1000
Clock-5 1010
Clock-6 1011
Clock-7 0000
Clock-8 0000

(B) The circuit is a 3 − bit ripple binary adder.

 9 votes -- Himanshu Agarwal (12.4k points)

4.12.3 Digital Counter: GATE CSE 2011 | Question: 15 top☝ ☛ https://gateoverflow.in/2117


Mod 258 counter has 258 states. We need to find no. of bits to represent 257 at max. 2n ≥258 ⟹ n ≥ 9 .
Answer is A.

 28 votes -- Sona Praneeth Akula (3.4k points)

© Copyright GATE Overflow. Some rights reserved.

 4.12.4 Digital Counter: GATE CSE 2014 Set 2 | Question: 7 top☝ ☛ https://gateoverflow.in/1959


Binary counter of n bits can count up to 2n numbers. When this output from counter is fed as input (n bit) to decoder one
out of 2n output lines will be activated. So, this arrangement of counter and decoder is behaving as 2n or k − bit ring counter.

Correct Answer: C
 36 votes -- Pooja Palod (24.1k points)

4.12.5 Digital Counter: GATE CSE 2015 Set 1 | Question: 20 top☝ ☛ https://gateoverflow.in/8219


Johnson Counter is a switch‐tail ring counter in which a circular shift register with the complemented output of the
last flip‐flop connected to the input of the first flip‐flop.
(D) is the correct answer!

 25 votes -- Manu Thakur (34k points)

4.12.6 Digital Counter: GATE CSE 2015 Set 2 | Question: 7 top☝ ☛ https://gateoverflow.in/8054


First, lets design a counter for 0, 1, 2, 3 . It is a MOD - 4 counter. Hence, number of Flip Flops required will be two.
Count sequence will be:

00 → 01 → 10 → 11

Count sequence mentioned in question is:

00 → 00 → 01 → 01 → 10 → 10 → 11 → 11

Now, two flip flops won't suffice. Since we are confronted with repeated sequence, we may add another bit to the above
sequence:

000 → 100 → 001 → 101 → 010 → 110 → 011 → 111

Now each and every count is unique, occurring only once. Meanwhile, our machine has been extended to a MOD - 8 counter.
Hence, three Flip Flops suffice.

Just neglect the MSB flip flop output and take the o/p of other two only. So, we have :

0, 0, 1, 1, 2, 2, 3, 3, …

So, correct answer: 3.

 151 votes -- Mithlesh Upadhyay (4.3k points)

4.12.7 Digital Counter: GATE CSE 2016 Set 1 | Question: 8 top☝ ☛ https://gateoverflow.in/39670


We need four JK flipflops.
0→1→0→2→0→3
0000 → 0001 → 0100 → 0010 → 1000 → 0011
There are 6 states and 3 of them correspond to same states.
To differentiate between 0, 1, 2, 3 we need 2 bits.
To differentiate between 3 0′ s we need another 2 bits.
So, total 4 − bits → 4FFs

Edit:
whether using extra combinational logic for output is allowed in a counter?
Page No. 10/11 http://textofvideo.nptel.iitm.ac.in/117105080/lec23.pdf or archive

Now, if you see the counters, now a counter we can define in this way the counter is a degenerate finite state machine, where the
state is the only output. So, there is no other primary output from this machine, so the counter is defined like that.

ALSO

Page No. 3 http://textofvideo.nptel.iitm.ac.in/117106086/lec24.pdf or archive

© Copyright GATE Overflow. Some rights reserved.

 Counter you know what counter it is, that’s what we want we count the output of counter what is the particular count what is the
current count that is the output of a count so no external output. The counter is a case of a state machine in which there are no
external inputs, no external outputs.

Page No. 10 http://textofvideo.nptel.iitm.ac.in/117106086/lec24.pdf or archive

At 35:30 www[dot]youtube[dot]com/watch?v=MiuMYEn3dpg

Here In Counter, we cannot use external variable, that purpose will be served by FF's only
We have four distinct states 0, 1, 2, 3 so, 2FF for them for 3 0′ s to distinguish we need 2 more F F ′ s
http://www.youtube.com/watch?v=MiuMYEn3dpg

4FF required.
References

 118 votes -- Abhilash Panicker (7.6k points)

4.12.8 Digital Counter: GATE CSE 2017 Set 2 | Question: 42 top☝ ☛ https://gateoverflow.in/118557


Answer is B)

Q1 Q0 Q1 + Q0 + T1 T2
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 0 0

By using above excitation table,

T1 = Q1 ′ Q0 ,
′
T2 = (Q1 Q0 ) = Q1 ′ + Q0 ′

 23 votes -- jatin saini (4.2k points)

4.12.9 Digital Counter: GATE IT 2005 | Question: 11 top☝ ☛ https://gateoverflow.in/3756


D.123 Pulses.

As in a 28 Counter, the range would be from 0 − 255 . Hence to go from 10101100(172) to 00100111(39) , the counter has to
go initially from 172 to 255 and then from 0 to 39.

Hence to go from 172 to 255, 255 − 172 = 83 Clock pulses would be required. then from 255 to 0, again 1 clock pulse would
be required. Then, from 0 to 39, 39 clock pulses would be required. Hence in total 83 + 1 + 39 = 123 Clock pulses would be

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 required.

 73 votes -- Afaque Ahmad (727 points)

4.12.10 Digital Counter: GATE IT 2008 | Question: 37 top☝ ☛ https://gateoverflow.in/3347


From state diagram:

Q X Y Qn+1 J K
0 0 0 0 0 X
0 0 1 1 1 X
0 1 0 1 1 X
0 1 1 0 0 X
1 0 0 1 X 0
1 0 1 0 X 1
1 1 0 0 X 1
1 1 1 1 X 0

Excitation table of JK

Q Qn+1 J K
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0

Option D.

 71 votes -- Riya Roy(Arayana) (5.3k points)

4.13 Dual Function (1) top☝

4.13.1 Dual Function: GATE CSE 2014 Set 2 | Question: 6 top☝ ☛ https://gateoverflow.in/1958

The dual of a Boolean function F(x1 , x2 , … , xn , +, . ,′ ) , written as F D is the same expression as that of F with + and ⋅
swapped. F is said to be self-dual if F = F D . The number of self-dual functions with n Boolean variables is
A. 2n
B. 2n−1
n
C. 22
n−1
D. 22

gate2014-cse-set2 digital-logic normal dual-function

Answer ☟

Answers: Dual Function

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 4.13.1 Dual Function: GATE CSE 2014 Set 2 | Question: 6 top☝ ☛ https://gateoverflow.in/1958


A function is self dual if it is equal to its dual (A dual function is obtained by interchanging . and +).
For self-dual functions,

1. Number of min terms equals number of max terms

2. Function should not contain two complementary minterms - whose sum equals 2n − 1 , where n is the number of
variables.

A B C
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

So, here (0, 7)(1, 6)(2, 5)(3, 4) are complementary terms so in self-dual we can select any one of them but not both.
Totally 2 × 2 × 2 × 2 = 24 possibility because say from (0, 7) we can pick anyone in minterm but not both.
For example, let f = ∑(0, 6, 2, 3)
NOTE: here I have taken only one of the complementary term for min term from the sets.
So, remaining numbers will go to MAXTERMS
For above example, 24 = 16 self dual functions are possible
So, if we have N variables, total Minterms possible is 2n
Then half of them we selected so 2n−1 .
Now we have 2 choices for every pair for being selected.


So total such choices = 2 × 2 × 2 × 2 … 2
2n−1 times
n−1
∴ 22 (option D)

 64 votes -- Kalpish Singhal (1.6k points)

4.14 Fixed Point Representation (2) top☝

4.14.1 Fixed Point Representation: GATE CSE 2017 Set 1 | Question: 7 top☝ ☛ https://gateoverflow.in/118287

The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i = n − f . The range
of decimal values for X in this representation is

A. 2−f to 2i
B. 2−f to (2i − 2−f )
C. 0 to 2i
D. 0 to (2i − 2−f )

gate2017-cse-set1 digital-logic number-representation fixed-point-representation

Answer ☟

4.14.2 Fixed Point Representation: GATE CSE 2018 | Question: 33 top☝ ☛ https://gateoverflow.in/204107

Consider the unsigned 8-bit fixed point binary number representation, below,

b7 b6 b5 b4 b3 ⋅ b2 b1 b0

where the position of the primary point is between b3 and b2 . Assume b7 is the most significant bit. Some of the decimal numbers

© Copyright GATE Overflow. Some rights reserved.

 listed below cannot be represented exactly in the above representation:

i. 31.500
ii. 0.875
iii. 12.100
iv. 3.001

Which one of the following statements is true?

A. None of i, ii, iii, iv can be exactly represented

B. Only ii cannot be exactly represented
C. Only iii and iv cannot be exactly represented
D. Only i and ii cannot be exactly represented

gate2018-cse digital-logic number-representation fixed-point-representation normal

Answer ☟

Answers: Fixed Point Representation

4.14.1 Fixed Point Representation: GATE CSE 2017 Set 1 | Question: 7 top☝ ☛ https://gateoverflow.in/118287

Unsigned real number x.

Let n = 5, f = 2, i = 5 − 2 = 3.
1. Minimum value of x :

Value on decimal = 0.
2. Maximum value of x :

Value on decimal = 23 − 2−2 = 8 − 0.25 = 7.75 ( Or 22 + 21 + 20 + 2−1 + 2−2 = 7.75)

So (D) is the answer.

 92 votes -- 2018 (5.5k points)

4.14.2 Fixed Point Representation: GATE CSE 2018 | Question: 33 top☝ ☛ https://gateoverflow.in/204107


31.500 can be represented as 11111.100 in the above mentioned fixed form representation

0.875 can be represented as 00000.111 .

We can't represent 3 and 4.

Hence, C is the correct answer.

© Copyright GATE Overflow. Some rights reserved.

  19 votes -- Prashant Kumar (1k points)

4.15 Flip Flop (6) top☝

4.15.1 Flip Flop: GATE CSE 2001 | Question: 11 top☝ ☛ https://gateoverflow.in/752

A sequential circuit takes an input stream of 0′ s and 1′ s and produces an output stream of 0′ s and 1′ s. Initially it replicates
the input on its output until two consecutive 0′ s are encountered on the input. From then onward, it produces an output stream,
which is the bit-wise complement of input stream until it encounters two consecutive 1's, whereupon the process repeats. An
example input and output stream is shown below.

The input stream: 101100 | 01001011 | 011

The desired output: 101100 | 10110100 | 011

J-K master-slave flip-flops are to be used to design the circuit.

a. Give the state transition diagram

b. Give the minimized sum-of-product expression for J and K inputs of one of its state flip-flops

gate2001-cse digital-logic normal descriptive flip-flop

Answer ☟

4.15.2 Flip Flop: GATE CSE 2004 | Question: 18, ISRO2007-31 top☝ ☛ https://gateoverflow.in/1015

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

A. Q = 0, Q′ = 1
B. Q = 1, Q′ = 0
C. Q = 1, Q′ = 1
D. Indeterminate states

gate2004-cse digital-logic easy isro2007 flip-flop

Answer ☟

4.15.3 Flip Flop: GATE CSE 2015 Set 1 | Question: 37 top☝ ☛ https://gateoverflow.in/8287

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D
flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the
input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared.
Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the
flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state
holding mode of the JK flip-flops. Both the flip-flops have non-zero propagation delays.
A. 0110110 …
B. 0100100 …
C. 011101110 …
D. 011001100 …

gate2015-cse-set1 digital-logic flip-flop normal

Answer ☟

4.15.4 Flip Flop: GATE CSE 2017 Set 1 | Question: 33 top☝ ☛ https://gateoverflow.in/118315

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the
input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.

© Copyright GATE Overflow. Some rights reserved.

 Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs

A. Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively.
B. Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively.
C. Q1 Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively.
D. Q1 Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively.

gate2017-cse-set1 digital-logic flip-flop normal

Answer ☟

4.15.5 Flip Flop: GATE CSE 2018 | Question: 22 top☝ ☛ https://gateoverflow.in/204096

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in"
is ____

gate2018-cse digital-logic flip-flop numerical-answers normal

Answer ☟

4.15.6 Flip Flop: GATE IT 2007 | Question: 7 top☝ ☛ https://gateoverflow.in/3440

Which of the following input sequences for a cross-coupled R − S flip-flop realized with two NAND gates may lead to an
oscillation?
A. 11, 00
B. 01, 10
C. 10, 01
D. 00, 11

gate2007-it digital-logic normal flip-flop

Answer ☟

Answers: Flip Flop

4.15.1 Flip Flop: GATE CSE 2001 | Question: 11 top☝ ☛ https://gateoverflow.in/752


We can design a Mealy Machine as per the requirement given in the question.
From which we will get state table, and we can design sequential circuit using any Flip-flop from the state table (with the help of
excitation table) :

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 As we get 4 states (renaming state component to binary states), we need two FFs to implement it.
Let A and B be present states, x be the input and y be the output.

Present State Input Next State Output FF FF

inputs inputs
AB X A′ B′ Y JA KA JB KB
00 0 01 0 0 X 1 X
00 1 00 1 0 X 0 X
01 0 10 0 1 X X 1
01 1 00 1 0 X X 1
10 0 10 1 X 0 0 X
10 1 11 0 X 0 1 X
11 0 10 1 X 0 X 1
11 1 00 0 X 1 X 1

Qt Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

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  29 votes -- Praveen Saini (41.9k points)

4.15.2 Flip Flop: GATE CSE 2004 | Question: 18, ISRO2007-31 top☝ ☛ https://gateoverflow.in/1015


Answer should be C. The reasoning is as follows:

When both R and S are set as 0, we will get both Q and Q′ as 1 (these must be ideally mutually complementary). This output
will be permanent and is not dependent on any sequence of events but just the input values (so no race condition). But after this
state if we enter both R and S as 1, the output will be indeterminate depending on which NAND gate processes first (either Q or
Q′ will become 0 but we can't determine which (race condition) and it will lead to an indeterminate state.

PS: R = 0, S = 0 in an SR latch made by cross coupling 2 NAND gates will lead to a forbidden state. Forbidden state means,
this state is invalid and must not be entered. This is different from an indeterminate state which means a state where we are not
sure of the output. Again this is different from a toggling state where the output changes continuously.
 57 votes -- Prateek Arora (285 points)

4.15.3 Flip Flop: GATE CSE 2015 Set 1 | Question: 37 top☝ ☛ https://gateoverflow.in/8287

Qprev D Q(JK) Explanation

- 1 0 Now, the D output is 1, meaning J and K = 1; for next cycle
0 0 1 J = K = 1(D output from prev state), so output toggles from 0 to 1
1 1 1 J = K = 0, so output remains 1
1 1 0 J = K = 0, so output remains 1
0 0 1 J = K = 1, so output toggles from 0 to 1
1 1 1 J = K = 0, so output remains 1

D flipflop output will be same as its input and JK flipflop output toggles when 1 is given to both J and K inputs.
i.e., Q = Dprev (Qprev ′ ) + (Dprev ′ )Qprev

Correct Answer: A
 35 votes -- Arjun Suresh (332k points)

© Copyright GATE Overflow. Some rights reserved.

 4.15.4 Flip Flop: GATE CSE 2017 Set 1 | Question: 33 top☝ ☛ https://gateoverflow.in/118315


Since it is synchronous so, after every clock cycle T will toggle if input is 1 and will be in Hold State if input is 0. D
flip-flop’s output always follows input

After 1 clock cycles : Q1=0 (Toggle) Q0=1

After 2 clock cycles : Q1=1 (Toggle) Q0=0
After 3 clock cycles: Q1=1 (Hold) Q0=1
After 4 clock cycles: Q1=0 (Toggle) Q0=1

Hence, option (B) is correct.

 31 votes -- sriv_shubham (2.8k points)

4.15.5 Flip Flop: GATE CSE 2018 | Question: 22 top☝ ☛ https://gateoverflow.in/204096


Answer Is 2.

Here 00 on input 0 and 11 on input 1 have transition back to itself. So, answer is 2.

 55 votes -- Suraj Sajeev (311 points)

4.15.6 Flip Flop: GATE IT 2007 | Question: 7 top☝ ☛ https://gateoverflow.in/3440


For a cross-coupled R − S flip flop with two NAND gates 11 is no change and 00 is forbidden. 00 is forbidden (not
allowed but not indeterminate) because in this state both Q and Q′ equals 1. Moreover, in this state if inputs are changed to 11,
next state is indeterminate (meaning we cannot determine the output)- Q can be 0 and Q′ can be 1 or Q = 1 and Q′ = 0. There
is also a chance that outputs can oscillate here when the following happens:

1. Inputs are set to 11

2. When both inputs of NAND gates are 1 output is 0
3. Suppose NAND gate 1 becomes 0 first.
4. This 0 goes as input to NAND gate 2.
5. By this time NAND gate 2 produces its own output as 0.
6. Now, this 0 goes as input to NAND gate 1 which makes its output 1.
7. The 0 input to NAND gate 2 (from step 4) now makes its output 1.
8. Whole cycle can repeat and output toggles between 1 and 0.

This is just a possibility and that is why question says "may oscillate."
The input sequence 00,11 (Option D) may oscillate.
https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch
References

© Copyright GATE Overflow. Some rights reserved.

  29 votes -- Arjun Suresh (332k points)

4.16 Floating Point Representation (9) top☝

4.16.1 Floating Point Representation: GATE CSE 1987 | Question: 1-vii top☝ ☛ https://gateoverflow.in/80201

The exponent of a floating-point number is represented in excess- N code so that:

A. The dynamic range is large.
B. The precision is high.
C. The smallest number is represented by all zeros.
D. Overflow is avoided.

gate1987 digital-logic number-representation floating-point-representation

Answer ☟

4.16.2 Floating Point Representation: GATE CSE 1989 | Question: 1-vi top☝ ☛ https://gateoverflow.in/87053

Consider an excess -50 representation for floating point numbers with 4 BCD digit mantissa and 2 BCD digit exponent in
normalised form. The minimum and maximum positive numbers that can be represented are __________ and _____________
respectively.

descriptive gate1989 digital-logic number-representation floating-point-representation

Answer ☟

4.16.3 Floating Point Representation: GATE CSE 1990 | Question: 1-iv-a top☝ ☛ https://gateoverflow.in/83830

A 32-bit floating-point number is represented by a 7-bit signed exponent, and a 24-bit fractional mantissa. The base of the
scale factor is 16,
The range of the exponent is ___________

gate1990 digital-logic number-representation floating-point-representation fill-in-the-blanks

Answer ☟

4.16.4 Floating Point Representation: GATE CSE 1990 | Question: 1-iv-b top☝ ☛ https://gateoverflow.in/203832

A 32-bit floating-point number is represented by a 7-bit signed exponent, and a 24-bit fractional mantissa. The base of the
scale factor is 16,
The range of the exponent is ___________, if the scale factor is represented in excess-64 format.

gate1990 digital-logic number-representation floating-point-representation fill-in-the-blanks

Answer ☟

4.16.5 Floating Point Representation: GATE CSE 1997 | Question: 72 top☝ ☛ https://gateoverflow.in/19702

Following floating point number format is given

f is a fraction represented by a 6 − bit mantissa (includes sign bit) in sign magnitude form, e is a 4 − bit exponent (includes sign
hit) in sign magnitude form and n = (f, e) = f. 2e is a floating point number. Let A = 54.75 in decimal and B = 9.75 in decimal

a. Represent A and B as floating point numbers in the above format.

b. Show the steps involved in floating point addition of A and B.
c. What is the percentage error (up to one position beyond decimal point) in the addition operation in (b)?

gate1997 digital-logic floating-point-representation normal descriptive

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.16.6 Floating Point Representation: GATE CSE 2003 | Question: 43 top☝ ☛ https://gateoverflow.in/934

The following is a scheme for floating point number representation using 16 bits.

Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point
number represented is:

(−1)s (1 + m × 2−9 ) 2e−31 , if the exponent ≠ 111111

{
0, otherwise

What is the maximum difference between two successive real numbers representable in this system?

A. 2−40
B. 2−9
C. 222
D. 231

gate2003-cse digital-logic number-representation floating-point-representation normal

Answer ☟

4.16.7 Floating Point Representation: GATE CSE 2005 | Question: 85-a top☝ ☛ https://gateoverflow.in/1407

Consider the following floating-point format.

Mantissa is a pure fraction in sign-magnitude form.

The decimal number 0.239 × 213 has the following hexadecimal representation (without normalization and rounding off):
A. 0D 24
B. 0D 4D
C. 4D 0D
D. 4D 3D

gate2005-cse digital-logic number-representation floating-point-representation normal

Answer ☟

4.16.8 Floating Point Representation: GATE CSE 2005 | Question: 85-b top☝ ☛ https://gateoverflow.in/82139

Consider the following floating-point format.

Mantissa is a pure fraction in sign-magnitude form.

© Copyright GATE Overflow. Some rights reserved.

 The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary
(radix) point. Assume that only 0′ s are padded in while shifting a field.
The normalized representation of the above number (0.239 × 213 ) is:

A. 0A 20
B. 11 34
C. 49 D0
D. 4A E8

gate2005-cse digital-logic number-representation floating-point-representation normal

Answer ☟

4.16.9 Floating Point Representation: GATE CSE 2020 | Question: 29 top☝ ☛ https://gateoverflow.in/333202

Consider three registers R1, R2, and R3 that store numbers in IEEE-754 single precision floating point format. Assume that
R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000 , respectively.
R1
If R3 = R2
, what is the value stored in R3?

A. 0x40800000
B. 0xC0800000
C. 0x83400000
D. 0xC8500000

gate2020-cse floating-point-representation digital-logic

Answer ☟

Answers: Floating Point Representation

4.16.1 Floating Point Representation: GATE CSE 1987 | Question: 1-vii top☝ ☛ https://gateoverflow.in/80201


Answer : C) The smallest number is represented by all zeros.

In computer system, a floating-point number is represented as S E M, i.e. using Sign bit, Exponent bits and Mantissa bits.

The exponent can be a positive as well as a negative number. So to represent negative number we can use 1′ s complement or 2′ s
complement. Better choice would be 2′ s complement.

If we use 2′ s complement system to represent exponent, then problem will arise while comparing 2 floating point numbers. For
example, if exponent of the 2 numbers are negative then for comparing we will have to convert them into positive number.

So, to avoid this extra work, excess-N code is used so that all exponent can be represented in positive numbers, starting with 0.
 28 votes -- Kantikumar (3.4k points)

4.16.2 Floating Point Representation: GATE CSE 1989 | Question: 1-vi top☝ ☛ https://gateoverflow.in/87053


In binary we have normalized number of the form (−1)S × 1.M × 2E− Bias where,

S : sign bit
M : Mantissa
E : Exponent

Similarly for for Binary Coded Decimal (BCD) numbers the normalized number representation will be
: (−1)S × 1.M × 10E− Bias
Here bias is given to be excess - 50 meaning that we need to subtract 50 from the base exponent field to get the actual exponent.
So, maximum mantissa value with 4 BCD digits = 9999
Maximum base exponent value with 2 BCD digits = 99
So, maximum actual exponent value possible with 2 BCD digits = 99 - Bias
= 99 − 50
= 49
49
= 9.9999 ×

© Copyright GATE Overflow. Some rights reserved.

 So, the magnitude of the largest positive number = 9.9999 × 1049
Similarly,
To get a minimum positive number, we have to set mantissa = 0 and exponent field = 0
So, doing that we get exponent = 0 − 50 = −50
So, magnitude of minimum positive number = 1.0000 × 1050
Therefore, maximum positive number = 9.9999 × 1049
Minimum positive number = 1.0000 × 10−50

 8 votes -- HABIB MOHAMMAD KHAN (67.5k points)

4.16.3 Floating Point Representation: GATE CSE 1990 | Question: 1-iv-a top☝ ☛ https://gateoverflow.in/83830


PS: It is an old question and IEEE format was not there then. Currently we use IEEE format if anything is unspecified.

As given exponent bits are 7 bits.

So, minimum it could be all 7 bit are 0′ s and maximum it could all 1′ s .
Assuming 2′ s complement representation minimum value = −26 = −64 and maximum value = 26 − 1 = 63.

 18 votes -- minal (13.1k points)

4.16.4 Floating Point Representation: GATE CSE 1990 | Question: 1-iv-b top☝ ☛ https://gateoverflow.in/203832


Minimum number = 0 , maximum number = 127 ,

Given excess 64 so, bias number is 64,

Range will be 0 − 64 = −64 to (127 − 64 = 63)63 .

Here, in question given that base is 16, so the actual value represented will be (−1)s (0.M) × 16E−bias .
 10 votes -- minal (13.1k points)

4.16.5 Floating Point Representation: GATE CSE 1997 | Question: 72 top☝ ☛ https://gateoverflow.in/19702

PART A
A = 54.75 = 110110.11 2
Coming to the floating point representation we need to know whether to use "implied 1" in normalized representation or not.
This is a 1997 question and IEEE-754 was not there and hence we cannot assume implied one.
So, A = 110110.11 = 0.11011011 × 26
Thus mantissa = 11011011 and exponent = 110. We use sign magnitude representation for both mantissa and exponent,
mantissa bits are 6 including sign and exponent bits are 4 including sign. So, we get
mantissa = 011011 and exponent = 0110 which means A = (011011, 0110)
B = 9.75 = 1001.11 2
= 0.100111 × 24
So, mantissa bits = 010011 (truncated to 6 bits) and exponent bits = 0100.
⟹ B = (010011, 0100)
PART B
To add two floating point numbers we must first make their exponents same and then add the mantissas. To make the exponents
same we must make the smaller one equal to the larger (we cannot do the other way around as we can only shift the mantissa bits
to right but not the left).
Here, A = (011011, 0110) and B = (010011, 0100).

B = (000100, 0110).

© Copyright GATE Overflow. Some rights reserved.

 Since, exponent of A is larger we change B to B = (000100, 0110).
Now, adding the mantissa parts of A and B (MSB is sign bit and not added as in 2′ s complement representation) we get
11011 + 00100 = 11111. Thus we get A + B = (011111, 0110).
PART C
Precise Result of A + B = 54.75 + 9.75 = 64.5
Result got in Part (b) = 0.10010 × 27 = 1001000 2 = 7210 .
So, error = 72 − 64.5 = 7.5
Error 7.5
Percentage Error = × 100 = × 100 = 11.63%
Original Value 64.5

 7 votes -- Arjun Suresh (332k points)

4.16.6 Floating Point Representation: GATE CSE 2003 | Question: 43 top☝ ☛ https://gateoverflow.in/934


The maximum difference between two successive real numbers will occur at extremes. This is because numbers are
represented up to mantissa bits and as the exponent grows larger, the difference gets multiplied by a larger value. (The minimum
difference happens for the least positive exponent value).
Biasing will be done by adding 31 as given in the question. So, actual value of exponent will be represented value −31. Also, we
can not have exponent field as all 1’s as given in question (usually taken for representing infinity, NAN etc). So, largest value
that can be stored is 111110 = 62.
Largest number will be 1.111111111 × 262−31 = (2 − 2−9 ) × 231
Second largest number will be 1.111111110 × 262−31 = (2 − 2−8 ) 231
So, difference between these two numbers
= (2 − 2−9 ) × 231 − (2 − 2−8 ) × 231 = 231 [(2 − 2−9 ) − (2 − 2−8 )] = 231 [2−8 − 2−9 ] = 231 × 2−9 = 222

Correct Answer: C.
 69 votes -- Ashish Gupta (759 points)

4.16.7 Floating Point Representation: GATE CSE 2005 | Question: 85-a top☝ ☛ https://gateoverflow.in/1407


Answer is option D in both questions.
0.239 = (0.00111101)2
(a) Stored exponent = actual + biasing
13 + 64 = 77
(77)10 = (1001101)2

  

Answer is: 0 1001101 00111101 = 0x 4D 3D
sign exponent mantissa

(b) For normalized representation

0.00111101 ∗ 213 = 1.11101 ∗ 210
Stored exponent = 10 + 64 = 74
(74)10 = (1001010)2

  

Answer: 0 1001010 11101000 = 0x 4A E8 .
sign exponent mantissa

 47 votes -- Pooja Palod (24.1k points)

4.16.8 Floating Point Representation: GATE CSE 2005 | Question: 85-b top☝ ☛ https://gateoverflow.in/82139


For finding normalised representation we need to find unnormalised one first. So, we have:

0.239 × 213 as the number. So, we find the binary equivalent of 0.239 till 8 digits as capacity of mantissa field is 8 bits.
We follow the following procedure:

© Copyright GATE Overflow. Some rights reserved.

 0.239 × 2 = 0.478
0.478 × 2 = 0.956
0.956 × 2 = 1.912
0.912 × 2 = 1.824
0.824 × 2 = 1.648
0.648 × 2 = 1.296
0.296 × 2 = 0.512
0.512 × 2 = 1.024

We stop here as we have performed 8 iterations and hence, 8 digits of mantissa of unnormalised number is obtained. Now we
have:
Mantissa of given number = 0011 1101

So, the number can be written as: 0.00111101 × 213

Now we need to align the mantissa towards left to get normalised number. And in the question it is mentioned that during
alignment process 0′ s will be padded in the right side as a result of mantissa alignment to left.

So, to get normalised number, we align to left 3 times, to get new mantissa = 11101000

Exponent will also decrease by 3 hence, new exponent = 10

So, normalised number= 1.11101000 × 210

Actual exponent = 10

Given excess 64 is used which means bias value = 64

So, exponent field value = 10 + 64 = 74

And of course sign bit = 0 being a positive number.

Thus the final representation of number

= 0 1001010 11101000
= 0100 1010 1110 1000
= (4AE8)16

Hence, (D) should be the correct answer.

 32 votes -- HABIB MOHAMMAD KHAN (67.5k points)

4.16.9 Floating Point Representation: GATE CSE 2020 | Question: 29 top☝ ☛ https://gateoverflow.in/333202

For more elaboration, please refer: General Floating-Point Division

References

© Copyright GATE Overflow. Some rights reserved.

  23 votes -- Vijay Verma (195 points)

R1 = 0x42200000 = 0100 0010 0010 0000 0000 0000 0000 0000

As per IEEE -754 single precision format,

S=0 ==> +ve number

Exponent = (10000100)2 = 128+4 = 132

true exponent = 132-127 = 5

Mantissa = (010 000000000)2

value = (−1)0 . (1.01000000000. . . ) ∗ 25 = (101000.000000. . . )2 = 40

R2 = 0xC1200000 = 1100 0001 0010 0000 0000 0000 0000 0000

As per IEEE -754 single precision format,

S=1 ==> -ve number

Exponent = (10000010)2 = 128+2 = 130

true exponent = 130-127 = 3

Mantissa = (010 000000000)2

value = (−1)1 . (1.01000000000. . . ) ∗ 23 = (1010.000000. . . )2 = −10

40
R3 = −10 = −4

represent -4 in IEEE-754 single precision format

S=1

V alue = (100.0000) ∗ 20 = (1.00000000...) ∗ 22

true exponent = 2 ==> exponent = 2+127=129 = (10000001)2

Mantissa = 000000..0

-4 in IEEE format : 1100 0000 1000 0000 0000 0000 0000 0000

in Hexa decimal format : 0xC0800000

option B is correct
 33 votes -- Shaik Masthan (50.4k points)

4.17 Functional Completeness (4) top☝

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 4.17.1 Functional Completeness: GATE CSE 1989 | Question: 4-iii top☝ ☛ https://gateoverflow.in/87883

Show that {NOR} is a functionally complete set of Boolean operations.

gate1989 descriptive digital-logic functional-completeness

Answer ☟

4.17.2 Functional Completeness: GATE CSE 1998 | Question: 5 top☝ ☛ https://gateoverflow.in/1696

The implication gate, shown below has two inputs (x and y) ; the output is 1 except when
x = 1 and y = 0, realize f = x̄y + xȳ using only four implication gates.

Show that the implication gate is functionally complete.

gate1998 digital-logic functional-completeness descriptive

Answer ☟

4.17.3 Functional Completeness: GATE CSE 1999 | Question: 2.9 top☝ ☛ https://gateoverflow.in/1487

Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function?

A. XOR gates, NOT gates

B. 2 to 1 multiplexers
C. AND gates, XOR gates
D. Three-input gates that output (A. B) + C for the inputs A, B and C .

gate1999 digital-logic normal functional-completeness multiple-selects

Answer ☟

4.17.4 Functional Completeness: GATE IT 2008 | Question: 1 top☝ ☛ https://gateoverflow.in/3222

A set of Boolean connectives is functionally complete if all Boolean functions can be synthesized using those. Which of the
following sets of connectives is NOT functionally complete?
A. EX-NOR
B. implication, negation
C. OR, negation
D. NAND

gate2008-it digital-logic easy functional-completeness

Answer ☟

Answers: Functional Completeness

4.17.1 Functional Completeness: GATE CSE 1989 | Question: 4-iii top☝ ☛ https://gateoverflow.in/87883


The functionally complete set is by which you can perform all operations. So, if any logical set is able to implement the
operation {And , NOT} or {OR, NOT}; it is known as functionally complete.

Now come to NOR gate.

A(NOR)B = (A + B)′

A = (A + A)′ = (A)′

© Copyright GATE Overflow. Some rights reserved.

 A(NOR)A = (A + A)′ = (A)′ , so we can perform the NOT operation .
(A + B)′ NOR (A + B)′ = ((A + B)′ + (A + B)′ )′ = ((A + B)′ )′ = (A + B) , so OR operation is also performed
successfully .

So, NOR is functionally complete.

 16 votes -- Amit Pal (3k points)

4.17.2 Functional Completeness: GATE CSE 1998 | Question: 5 top☝ ☛ https://gateoverflow.in/1696


Implication gate is A->B which becomes A'+B

So, let f(A, B) = A′ + B

f(A, 0) = A′ (we get complement )

f(f(A, 0), B) = f(A′ , B) = A + B (we get OR gate)

Thus it is functionally complete.

Let F(X, Y ) = X ′ + Y

F(Y , X) = Y ′ + X

F(F(Y ′ + X), 0) = X ′ Y

F(F(X, Y ), X ′ Y ) = XY ′ + XY ′ Therefore, the above function is implemented with 4 implication gates.

 16 votes -- Riya Roy(Arayana) (5.3k points)

4.17.3 Functional Completeness: GATE CSE 1999 | Question: 2.9 top☝ ☛ https://gateoverflow.in/1487


1. XOR and NOT gates can only make XOR and XNOR which are not functionally complete- a ⊕ ā = 1, a ⊕ a = 0.

2. 2-1 multiplexer is functionally complete provided we have external 1 and 0 available. For NOT gate, use x as select line and
use 0 and 1 as inputs. For AND gate, use y and 0 as inputs and x as select. With {AND, NOT} any other gate can be made.

3. XOR can be used to make a NOT gate (a ⊕ 1 = ā ) and {AND, NOT} is functionally complete. Again this requires external 1.

4. We have AB + C . Using C = 0 , we get an AND gate. Using B = 1 we get an OR gate. But we cannot derive a NOT gate
here.

So, options B and C are true provided external 1 and 0 are available.
 49 votes -- Arjun Suresh (332k points)

4.17.4 Functional Completeness: GATE IT 2008 | Question: 1 top☝ ☛ https://gateoverflow.in/3222


EX-NOR is not functionally complete.

NOR and NAND are functionally complete logic gates, OR , AND, NOT any logic gate can be implemented using them.

And (Implication, Negation) is also functionally complete

First complement q to get q' then
p -> q' = p' + q'
Now complement the result to get AND gate
(p' + q')' => pq
 43 votes -- Manu Thakur (34k points)

4.18 Ieee Representation (7) top☝

4.18.1 Ieee Representation: GATE CSE 2008 | Question: 4 top☝ ☛ https://gateoverflow.in/402

In the IEEE floating point representation the hexadecimal value 0x00000000 corresponds to
−127

© Copyright GATE Overflow. Some rights reserved.

 A. The normalized value 2−127
B. The normalized value 2−126
C. The normalized value +0
D. The special value +0

gate2008-cse digital-logic floating-point-representation ieee-representation easy

Answer ☟

4.18.2 Ieee Representation: GATE CSE 2012 | Question: 7 top☝ ☛ https://gateoverflow.in/39

The decimal value 0.5 in IEEE single precision floating point representation has

A. fraction bits of 000 … 000 and exponent value of 0

B. fraction bits of 000 … 000 and exponent value of −1
C. fraction bits of 100 … 000 and exponent value of 0
D. no exact representation

gate2012-cse digital-logic normal number-representation ieee-representation

Answer ☟

4.18.3 Ieee Representation: GATE CSE 2014 Set 2 | Question: 45 top☝ ☛ https://gateoverflow.in/2011

The value of a float type variable is represented using the single-precision 32-bit floating point format of IEEE-754 standard
that uses 1 bit for sign, 8 bits for biased exponent and 23 bits for the mantissa. A float type variable X is assigned the decimal
value of −14.25 . The representation of X in hexadecimal notation is
A. C1640000H
B. 416C0000H
C. 41640000H
D. C16C0000H

gate2014-cse-set2 digital-logic number-representation normal ieee-representation

Answer ☟

4.18.4 Ieee Representation: GATE CSE 2017 Set 2 | Question: 12 top☝ ☛ https://gateoverflow.in/118434

Given the following binary number in 32-bit (single precision) IEEE-754 format :

00111110011011010000000000000000
The decimal value closest to this floating-point number is :

A. 1.45 ∗ 101
B. 1.45 ∗ 10−1
C. 2.27 ∗ 10−1
D. 2.27 ∗ 101

gate2017-cse-set2 digital-logic number-representation floating-point-representation ieee-representation

Answer ☟

4.18.5 Ieee Representation: GATE CSE 2021 Set 1 | Question: 24 top☝ ☛ https://gateoverflow.in/357427

Consider the following representation of a number in IEEE 754 single-precision floating point format with a bias of 127.

S:1 E : 10000001 F : 11110000000000000000000

Here S, E and F denote the sign, exponent, and fraction components of the floating point representation.

The decimal value corresponding to the above representation (rounded to 2 decimal places) is ____________.

gate2021-cse-set1 digital-logic number-representation ieee-representation numerical-answers

© Copyright GATE Overflow. Some rights reserved.

 Answer ☟

4.18.6 Ieee Representation: GATE CSE 2021 Set 2 | Question: 4 top☝ ☛ https://gateoverflow.in/357536

The format of the single-precision floating point representation of a real number as per the IEEE 754 standard is as follows:

sign exponent mantissa

Which one of the following choices is correct with respect to the smallest normalized positive number represented using the
standard?

A. exponent = 00000000 and mantissa = 0000000000000000000000000

B. exponent = 00000000 and mantissa = 0000000000000000000000001
C. exponent = 00000001 and mantissa = 0000000000000000000000000
D. exponent = 00000001 and mantissa = 0000000000000000000000001

gate2021-cse-set2 digital-logic number-representation ieee-representation

Answer ☟

4.18.7 Ieee Representation: GATE IT 2008 | Question: 7 top☝ ☛ https://gateoverflow.in/3267

The following bit pattern represents a floating point number in IEEE 754 single precision format
1 10000011 101000000000000000000000
The value of the number in decimal form is
A. −10
B. −13
C. −26
D. None of the above

gate2008-it digital-logic number-representation floating-point-representation ieee-representation normal

Answer ☟

Answers: Ieee Representation

4.18.1 Ieee Representation: GATE CSE 2008 | Question: 4 top☝ ☛ https://gateoverflow.in/402

S BE M Value
0/1 All 0’s All 0’s 0
0 All 1’s All 0’s +∞
1 All 1’s All 0’s −∞
0/1 All 1’s Non-zero NaN

The answer is option D.

Reference: http://steve.hollasch.net/cgindex/coding/ieeefloat.html
References

 48 votes -- Amar Vashishth (25.2k points)

4.18.2 Ieee Representation: GATE CSE 2012 | Question: 7 top☝ ☛ https://gateoverflow.in/39


(B) is the answer. IEEE 754 representation uses normalized representation when the exponent bits are all non zeroes and
hence an implicit '1' is used before the decimal point.So, if mantissa is:

© Copyright GATE Overflow. Some rights reserved.

 0000..0

Ut would be treated as:

1.000..0

and hence, the exponent need to be −1 for us to get 0.1 which is the binary representation of 0.5.

More into IEEE floating point representation:

http://steve.hollasch.net/cgindex/coding/ieeefloat.html
References

 36 votes -- gatecse (63.3k points)

4.18.3 Ieee Representation: GATE CSE 2014 Set 2 | Question: 45 top☝ ☛ https://gateoverflow.in/2011


IEEE-754 representation for float (single-precision) type is as follows

0 1−8 9−31
Sign Exponent Mantissa

Thus, the exponent field is of 8 bits and mantissa is of 23 bits (precision is actually of 24 bits due to an implied 1 mandated in
normalized representation; IEEE 754 also allows denormalized numbers which are close to 0 but this is not applicable to the
given question).
The exponent field also requires sign to represent fractions. IEEE 754 does this by giving a bias -- 127 for single-precision which
means we simply subtract 127 from the represented value to get the actual value. Thus, 0 becomes −127 and 255 (maximum
value representable using 8 bits becomes 128.
Now, coming to the given question we need to represent −14.25 which equals −1110.01 in binary.
Converting to normalized form (only one 1 to the left of . ) we get
−1110.01 = −1.11001 × 23
Since we omit the implied 1 in IEEE-754 representation we get

Mantissa bits = 11001

Exponent bits = 11 + 0111111 = 10000010 (Adding bias 127)
Sign bit = 1 (since number is negative)

This will be 1 10000010 11001000000000000000000

Grouping in 4 bits to convert ot Hexadecimal we get
1100 0001 0110 0100 0000 0000 0000 0000
= C1640000H
Option A.
More Reference: http://steve.hollasch.net/cgindex/coding/ieeefloat.html
References

 11 votes -- Arjun Suresh (332k points)

© Copyright GATE Overflow. Some rights reserved.

 4.18.4 Ieee Representation: GATE CSE 2017 Set 2 | Question: 12 top☝ ☛ https://gateoverflow.in/118434


In 32 bit (single precision) IEEE-754 format, binary number is represented as
S (1 bit) E(8 bit) M (23 bits) with implicit normalization and exponent is represented with Excess-127 code.
Here, Sign bit = 0 ⇒ Number is positive.
Exponent bits = 01111100 = 124 ⇒ E = 124 − 127 = −3 (Excess-127)
Mantissa bits = 11011010000000000000000 ⇒ Number = 1.1101101 (Implicit normalization).
∴ Number = 1.1101101 ∗ 2 −3 = 0.0011101101 = 0.227 = 2.27 x 10−1
∴ Answer should be C.

 38 votes -- Kantikumar (3.4k points)

4.18.5 Ieee Representation: GATE CSE 2021 Set 1 | Question: 24 top☝ ☛ https://gateoverflow.in/357427


-7.75 is correct answer.
Here, Sign bit = 1 → Number is negative.
Exponent bits = 10000001 = 12910 → E = 129 − 127 = 2 as IEEE-754 single precision format uses 127 as the exponent
bias.
Mantissa bits = 11110000000000000000000
Number =– 1.111100 … 00 × 22 = −111.11
∴ Number = (−7.75)10 .
Reference: https://steve.hollasch.net/cgindex/coding/ieeefloat.html
References

 4 votes -- Himanshu (929 points)

4.18.6 Ieee Representation: GATE CSE 2021 Set 2 | Question: 4 top☝ ☛ https://gateoverflow.in/357536


In IEEE 754 representation all 1s in exponent field is reserved for special numbers

+ (when sign bit is positive) and − (when sign bit is negative) infinities when all manitssa bits are zeroes.
SNAN (Signaling Not A Number): when leading mantissa bit is 0 and at least one other mantissa bit is non-zero
NAN (Quiet NAN): when leading mantissa bit is 1

More read on QNAN vs SNAN: https://stackoverflow.com/questions/18118408/what-is-the-difference-between-quiet-nan-and-

signaling-nan
Also, all 0s for exponent field is reserved for denormalized numbers (small numbers between 0 and ±1 which cannot be
represented using normalized numbers). That is, a normalized IEEE 754 represented number (both single and double precision)
must have at least one bit set in the exponent field and for the smallest exponent this will be the right most bit. Now, to make it
the smallest positive normalized number in single-precision format, we can have all mantissa bits 0 which will give the

numerical value as 1.000 … 0 × 21−127 = 2−126 . (Here, 1 before "." is implied in IEEE 754 representation for every
23 zeroes
normalized numbers and 127 is the exponent bias used to have negative exponents without an explicit sign bit)
Reference: https://steve.hollasch.net/cgindex/coding/ieeefloat.html
References

© Copyright GATE Overflow. Some rights reserved.

  2 votes -- gatecse (63.3k points)

4.18.7 Ieee Representation: GATE IT 2008 | Question: 7 top☝ ☛ https://gateoverflow.in/3267


Sign bit is 1 ⟹ number is negative
Exponent bits- 10000011
Exponent is added with 127 bias in IEEE single precision format. So, actual exponent = 10000011 − 127 = 131 − 127 = 4
Mantissa bits- 101000000000000000000000
In IEEE format, an implied 1 is before mantissa, and hence the actual number is:
−1.101 × 24
=− (11010)2 = −26
http://steve.hollasch.net/cgindex/coding/ieeefloat.html
Correct Answer: C
References

 44 votes -- Arjun Suresh (332k points)

4.19 K Map (19) top☝

4.19.1 K Map: GATE CSE 1987 | Question: 16-a top☝ ☛ https://gateoverflow.in/82698

A Boolean function f is to be realized only by NOR gates. Its K -map is given below:

The realization is
A.

B.

© Copyright GATE Overflow. Some rights reserved.

 C.

D.

gate1987 digital-logic k-map

Answer ☟

4.19.2 K Map: GATE CSE 1988 | Question: 3a-b top☝ ☛ https://gateoverflow.in/94358

The Karnaugh map of a function of (A, B, C) is shown on the left hand side of the above figure.
The reduced form of the same map is shown on the right hand side, in which the variable C is entered in the map itself. Discuss,

a. The methodology by which the reduced map has been derived and
b. the rules (or steps) by which the boolean function can be derived from the entries in the reduced map.

gate1988 descriptive digital-logic k-map

Answer ☟

4.19.3 K Map: GATE CSE 1992 | Question: 01-i top☝ ☛ https://gateoverflow.in/545

The Boolean function in sum of products form where K-map is given below (figure) is _______

© Copyright GATE Overflow. Some rights reserved.

 gate1992 digital-logic k-map normal fill-in-the-blanks

Answer ☟

4.19.4 K Map: GATE CSE 1995 | Question: 15-a top☝ ☛ https://gateoverflow.in/2651

Implement a circuit having the following output expression using an inverter and a nand gate
¯¯¯¯ ¯¯¯¯
Z = A+B+C

gate1995 digital-logic k-map normal descriptive

Answer ☟

4.19.5 K Map: GATE CSE 1995 | Question: 15-b top☝ ☛ https://gateoverflow.in/203837

What is the equivalent minimal Boolean expression (in sum of products form) for the Karnaugh map given below?

gate1995 digital-logic boolean-algebra k-map normal descriptive

Answer ☟

4.19.6 K Map: GATE CSE 1996 | Question: 2.24 top☝ ☛ https://gateoverflow.in/2753

What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given in Fig

¯¯¯¯ ¯¯¯¯
A. BD + BD

¯¯¯¯
(B + + D)(¯¯¯¯ + C + ¯¯¯¯)

© Copyright GATE Overflow. Some rights reserved.

 ¯¯¯¯ ¯¯¯¯ ¯¯¯¯
B. (B + C + D)(B + C + D)
¯¯¯¯ ¯¯¯¯
C. (B + D)(B + D)
¯¯¯¯ ¯¯¯¯
D. (B + D)(B + D)

gate1996 digital-logic k-map easy

Answer ☟

4.19.7 K Map: GATE CSE 1998 | Question: 2.7 top☝ ☛ https://gateoverflow.in/1679

The function represented by the Karnaugh map given below is

A. A. B
B. AB + BC + CA
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
C. B⊕C
D. A. BC

gate1998 digital-logic k-map normal

Answer ☟

4.19.8 K Map: GATE CSE 1999 | Question: 1.8 top☝ ☛ https://gateoverflow.in/1461

Which of the following functions implements the Karnaugh map shown below?

A. ĀB + CD
B. D(C + A)
C. AD + ĀB
D. (C + D)(C̄ + D) + (A + B)

gate1999 digital-logic k-map easy

Answer ☟

4.19.9 K Map: GATE CSE 2000 | Question: 2.11 top☝ ☛ https://gateoverflow.in/658

Which functions does NOT implement the Karnaugh map given below?

© Copyright GATE Overflow. Some rights reserved.

 A. (w + x)y
B. xy + yw
C. (w + x)(w̄ + y)(x̄ + y)
D. None of the above

gate2000-cse digital-logic k-map normal

Answer ☟

4.19.10 K Map: GATE CSE 2001 | Question: 1.11 top☝ ☛ https://gateoverflow.in/704

Given the following karnaugh map, which one of the following represents the minimal Sum-Of-Products of the map?

A. XY + Y ′ Z
B. W X ′ Y ′ + XY + XZ
C. W ′ X + Y ′ Z + XY
D. XZ + Y

gate2001-cse k-map digital-logic normal

Answer ☟

4.19.11 K Map: GATE CSE 2002 | Question: 1.12 top☝ ☛ https://gateoverflow.in/816

Minimum sum of product expression for f(w, x, y, z) shown in Karnaugh-map below

© Copyright GATE Overflow. Some rights reserved.

 A. xz + y ′ z
B. xz ′ + zx′
C. x′ y + zx′
D. None of the above

gate2002-cse digital-logic k-map normal

Answer ☟

4.19.12 K Map: GATE CSE 2003 | Question: 45 top☝ ☛ https://gateoverflow.in/936

The literal count of a Boolean expression is the sum of the number of times each literal appears in the expression. For
example, the literal count of (xy + xz ′ ) is 4. What are the minimum possible literal counts of the product-of-sum and sum-of-
product representations respectively of the function given by the following Karnaugh map? Here, X denotes "don't care"

A. (11, 9)
B. (9, 13)
C. (9, 10)
D. (11, 11)

gate2003-cse digital-logic k-map normal

Answer ☟

4.19.13 K Map: GATE CSE 2008 | Question: 5 top☝ ☛ https://gateoverflow.in/403

In the Karnaugh map shown below, X denotes a don’t care term. What is the minimal form of the function represented by the
Karnaugh map?

© Copyright GATE Overflow. Some rights reserved.

 A. b̄ . d¯ + ā. d¯

B. ā. b̄ + b̄ . d¯ + ā. b. d¯

C. b̄ . d¯ + ā. b. d¯

D. ā. b̄ + b̄ . d¯ + ā. d¯

gate2008-cse digital-logic k-map easy

Answer ☟

4.19.14 K Map: GATE CSE 2012 | Question: 30 top☝ ☛ https://gateoverflow.in/1615

What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t care term

A. b̄d¯
B. b̄d¯ + b̄c̄
C. b̄d¯ + ab̄c̄ d
D. b̄d¯ + b̄c̄ + c̄ d¯

gate2012-cse digital-logic k-map easy

Answer ☟

4.19.15 K Map: GATE CSE 2017 Set 1 | Question: 21 top☝ ☛ https://gateoverflow.in/118301

Consider the Karnaugh map given below, where X represents "don't care" and blank represents 0.

© Copyright GATE Overflow. Some rights reserved.

 Assume for all inputs (a, b, c, d), the respective complements (ā, b̄ , c̄ , d¯) are also available. The above logic is implemented using
2-input NOR gates only. The minimum number of gates required is ____________ .

gate2017-cse-set1 digital-logic k-map numerical-answers normal

Answer ☟

4.19.16 K Map: GATE CSE 2019 | Question: 30 top☝ ☛ https://gateoverflow.in/302818

Consider three 4-variable functions f1 , f2 , and f3 , which are expressed in sum-of-minterms as

f1 = Σ(0, 2, 5, 8, 14),
f2 = Σ(2, 3, 6, 8, 14, 15),
f3 = Σ(2, 7, 11, 14)
For the following circuit with one AND gate and one XOR gate the output function f can be expressed as:

A. Σ(7, 8, 11)
B. Σ(2, 7, 8, 11, 14)
C. Σ(2, 14)
D. Σ(0, 2, 3, 5, 6, 7, 8, 11, 14, 15)

gate2019-cse digital-logic k-map digital-circuits

Answer ☟

4.19.17 K Map: GATE IT 2006 | Question: 35 top☝ ☛ https://gateoverflow.in/3574

The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh map.

© Copyright GATE Overflow. Some rights reserved.

 Which of the product terms given below is an essential prime implicant of the function?
A. QRS
B. PQS
C. PQ'S'
D. Q'S'

gate2006-it digital-logic k-map normal

Answer ☟

4.19.18 K Map: GATE IT 2007 | Question: 78 top☝ ☛ https://gateoverflow.in/3530

Consider the following expression

ad¯ + āc̄ + bc̄ d
Which of the following Karnaugh Maps correctly represents the expression?
A.

B.

C.

D.

© Copyright GATE Overflow. Some rights reserved.

 gate2007-it digital-logic k-map normal

Answer ☟

4.19.19 K Map: GATE IT 2007 | Question: 79 top☝ ☛ https://gateoverflow.in/3531

Consider the following expression

ad¯ + āc̄ + bc̄ d
Which of the following expressions does not correspond to the Karnaugh Map obtained for the given expression?

A. c̄ d¯ + ad¯ + abc̄ + āc̄ d

B. āc̄ + c̄ d¯ + ad¯ + abc̄ d
C. āc̄ + ad¯ + abc̄ + c̄ d
D. b̄c̄ d¯ + acd¯ + āc̄ + abc̄

gate2007-it digital-logic k-map normal

Answer ☟

Answers: K Map

4.19.1 K Map: GATE CSE 1987 | Question: 16-a top☝ ☛ https://gateoverflow.in/82698


Two Max Terms are:

(a + b)(a + c) so, “a " is common here only possibility is option D.

K-map will give min terms = a[41′ s circle] + bc[21′ s box]

Option D circuit will give = (a + b)(a + c) = a + bc

D will be answer.

 20 votes -- papesh (18k points)

4.19.2 K Map: GATE CSE 1988 | Question: 3a-b top☝ ☛ https://gateoverflow.in/94358

© Copyright GATE Overflow. Some rights reserved.

 

We can get the truth table as

A B C F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Now, to reduce the K-map to a Variable Entrant Map we can write the function F in terms of C . i.e., wherever F is becoming 1
dependent on C (i.e. when C complements F must become 0), we replace 1 with C or C̄ based on whichever is giving output
1. So, we can rewrite the truth table as

A B F
0 0 C̄
0 1 1
1 0 C
1 1 C

In the above truth table F = 1 for second row, because when A = 0, B = 1, F = 1 for both C and C̄ making F independent of
C. Now, if we draw the K -map for the above truth table we get the reduced Variant Entrant map given.

 10 votes -- Arjun Suresh (332k points)

4.19.3 K Map: GATE CSE 1992 | Question: 01-i top☝ ☛ https://gateoverflow.in/545


Answer - ABC + B′ C ′ + A′ C ′

Expand this K map of 2 variables (4 cells) to K map of three variable (8 cells)

Entries which are non zero are: A′ B′ C ′ , AB′ C ′ , A′ BC ′ and ABC

Minimize SOP expression using that K map.

 22 votes -- Ankit Rokde (6.9k points)

4.19.4 K Map: GATE CSE 1995 | Question: 15-a top☝ ☛ https://gateoverflow.in/2651


The circuit can be implemented as follows:

© Copyright GATE Overflow. Some rights reserved.

  16 votes -- Leen Sharma (28.7k points)

4.19.5 K Map: GATE CSE 1995 | Question: 15-b top☝ ☛ https://gateoverflow.in/203837

SUM OF PRODUCT is equal to XNOR GATE

¯¯¯¯¯¯¯¯¯¯¯¯¯¯
SOP = BD + B̄D̄ = B ⊕ D = B ⊙ D

 10 votes -- Lakshman Patel (65.7k points)

4.19.6 K Map: GATE CSE 1996 | Question: 2.24 top☝ ☛ https://gateoverflow.in/2753


Following two K-Maps are equivalent and represent the same boolean function.
While the first K-Map gives us the boolean expression in Sum-of-Product form, and the second K-Map gives us the same
boolean function in Product-of-Sum form:

(i) (ii)

(C) is correct option!

PS: If SOP is asked answer will be (A).

 11 votes -- Manu Thakur (34k points)

© Copyright GATE Overflow. Some rights reserved.

 4.19.7 K Map: GATE CSE 1998 | Question: 2.7 top☝ ☛ https://gateoverflow.in/1679


The given K-map is not standard as after "01" we have "10" and two variables are changing for consecutive column. This
means it is not safe to merge adjacent 1s. By converting the K-map to standard form we get

which gives
BC + B̄C̄ = B XNOR C = B ⊙ C
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
This can be represented as negation of XOR = B ⊕ C

Option C is correct.

 24 votes -- shekhar chauhan (32.8k points)

4.19.8 K Map: GATE CSE 1999 | Question: 1.8 top☝ ☛ https://gateoverflow.in/1461

CD + AD
= D(C + A)
Correct Answer: B

 11 votes -- Rameez Raza (1.8k points)

4.19.9 K Map: GATE CSE 2000 | Question: 2.11 top☝ ☛ https://gateoverflow.in/658


Answer is D.
See we can simplify each equation given in the option and get that all of them gives xy + wy . But let think in another way.
1st option is written in POS form, as we can check we get the same if we consider the following implicants.

(w + x)y

© Copyright GATE Overflow. Some rights reserved.

 which is (w + x)y
for the second one

Which gives wy + xy

now for 3rd one, we can verify like this

which is (w + x)(w̄ + y)(x̄ + y)
So as we can verify each equation in a given K-Map, so the answer is option D

 14 votes -- akshat sinha (609 points)

4.19.10 K Map: GATE CSE 2001 | Question: 1.11 top☝ ☛ https://gateoverflow.in/704

Answer: A

 22 votes -- Priya Sukumaran (141 points)

4.19.11 K Map: GATE CSE 2002 | Question: 1.12 top☝ ☛ https://gateoverflow.in/816

© Copyright GATE Overflow. Some rights reserved.

 Two quads are getting formed xz̄ and zx̄
Ans is Option B

 15 votes -- GATE_2016 (469 points)

4.19.12 K Map: GATE CSE 2003 | Question: 45 top☝ ☛ https://gateoverflow.in/936

We will be getting two different grouping..

Grouping 1 : (9, 8)

SOP : 2 + 3 POS : 2 + 2 + 2
+3 = 8 +3 = 9

GROUPING 2 : (9, 10)

POS : 2 + 2 + 2
+3 = 9

© Copyright GATE Overflow. Some rights reserved.

 SOP : 2 + 2 + 3
+ 3 = 10

Both the grouping are correct representation of the function f(wxyz)

PS: Some wrong beliefs about don't cares

1. "once you have assumed a don't care as '1' u can't use the same don't care for grouping zeros and vice versa"
2. "if don't care has been used in POS than can't be used in SOP"

Both these statements are wrong. Don't care simply means just don't care -- say we use don't care d3 for grouping 1 in SOP we
can use d3 for grouping 0 in POS. (The literals in SOP and POS may not be the same)

K-Map grouping is not unique. And the question says about minimal literals. So, the best answer would be (9,8) Since there is
no option in GATE we can go with (9, 10) (the question setter might have missed Grouping 1)

 77 votes -- Akhil Nadh PC (16.5k points)

4.19.13 K Map: GATE CSE 2008 | Question: 5 top☝ ☛ https://gateoverflow.in/403


2 quads are getting formed:

Value for first one is a′ d ′ and value for 2nd one is b′ d ′ .

Answer is Option A.

 26 votes -- GATE_2016 (469 points)

4.19.14 K Map: GATE CSE 2012 | Question: 30 top☝ ☛ https://gateoverflow.in/1615

2 quads are getting formed.

Value for First one is b′ d ′ and value for 2nd one is b′ c′ . So, answer is option B.

 31 votes -- GATE_2016 (469 points)

4.19.15 K Map: GATE CSE 2017 Set 1 | Question: 21 top☝ ☛ https://gateoverflow.in/118301

© Copyright GATE Overflow. Some rights reserved.

 
From K-map simplification we get the min-term as CA′ . So We can simplyfy it for NOR gate expression
I.e. C' NOR A = (C ′ + A)′ = C A′
Now complemented inputs are also given to us so, for 2 input NOR gate we need only 1 NOR gate.

1 is correct answer .

 51 votes -- Aboveallplayer (12.5k points)

4.19.16 K Map: GATE CSE 2019 | Question: 30 top☝ ☛ https://gateoverflow.in/302818


Perform f1 ⋅ f2 first, then with the result perform XOR with f3 .

f1 ⋅ f2 means just take common minterms in f1 and f2 (WHY? due to AND gate present, the minterm should be present in both
functions.)

f1 . f2 = Σ(0, 2, 5, 8, 14) ⋅ Σ(2, 3, 6, 8, 14, 15) = Σ(2, 8, 14)

Σ(2, 8, 14) ⊕ Σ(2, 7, 11, 14) = Σ(7, 8, 11)

 34 votes -- Shaik Masthan (50.4k points)

4.19.17 K Map: GATE IT 2006 | Question: 35 top☝ ☛ https://gateoverflow.in/3574

Only the top leftmost and bottom rightmost 1s have no alternate groupings. So, they form the essential prime implicants.
Answer is D. Q′ S ′

 22 votes -- Ankit Kumar (265 points)

4.19.18 K Map: GATE IT 2007 | Question: 78 top☝ ☛ https://gateoverflow.in/3530

 m8 m10 m12 m14

ad¯ + āc̄ + bc̄ d = ab̄c̄ d¯ + ab̄ cd¯ + abc̄ d¯ + abcd¯
m0 m4 m1 m5
+āb̄c̄ d¯ + ābc̄ d¯ + āb̄c̄ d + ābc̄ d
m5 m13
+ābc̄ d + abc̄ d

When we minimize a K-map, we can assume either 0 or 1 for don't cares. But here they have asked for the expression

© Copyright GATE Overflow. Some rights reserved.

 represented by the K-map. So we can consider X as 1 and not as a don't care. Also the given expression is equivalent to the
above K-map but not the minimal one. Minimal expression will be āc̄ + bc̄ + ad¯.
Hence, Option A.

 10 votes -- Arjun Suresh (332k points)

4.19.19 K Map: GATE IT 2007 | Question: 79 top☝ ☛ https://gateoverflow.in/3531


ad ′ [fill minterm in K-map in front for a and d ′ ]

Similarly, fill all minterms for ad ′ + a′ c′ + bc′ d , resulting K-map will be:

Option (a) c′ d ′ + ad ′ + abc′ + a′ c′ d

is equivalent to given expression

Option (b) a′ c′ + c′ d ′ + ad ′ + abc′ d

© Copyright GATE Overflow. Some rights reserved.

 is equivalent to given expression.

Option (c) a′ c′ + ad ′ + abc′ + c′ d

is not equivalent to given expression.

Option (d) b′ c′ d ′ + acd ′ + a′ c′ + abc′

is equivalent to given expression.

So, answer is C.

 29 votes -- Praveen Saini (41.9k points)

4.20 Little Endian Big Endian (1) top☝

4.20.1 Little Endian Big Endian: GATE CSE 2021 Set 2 | Question: 44 top☝ ☛ https://gateoverflow.in/357496

If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer,
which of the following choices represent(s) the unsigned integer on a little endian computer?
A. 0x6665

0x0001

© Copyright GATE Overflow. Some rights reserved.

 B. 0x0001
C. 0x4243
D. 0x0100

gate2021-cse-set2 multiple-selects digital-logic number-representation little-endian-big-endian

Answer ☟

Answers: Little Endian Big Endian

4.20.1 Little Endian Big Endian: GATE CSE 2021 Set 2 | Question: 44 top☝ ☛ https://gateoverflow.in/357496


This question is poorly framed and has interpretation ambiguity. Refer to the discussion on this question in the below link
:
https://cs.stackexchange.com/questions/135713/representation-of-unsigned-integer-on-a-little-endian-big-endian-computer
All kinds of “interpretations” are available in that discussion.
The following is my interpretation of the question :
It is asking “which of the following choices represent(s) the unsigned integer on a little-endian computer?”
Take Option ‘‘0x6665 ” :
It is saying that 0x6665 is the representation of an integer on a little-endian computer, so, it means that the original number must
have been 0x6566 .
So, for the original number 0x6566 :

On little endian(LE) : 0x6665

On Big endian(BE) : 0x6566

Clearly, LE = 255 + BE
Similarly, for 0x0100 .
Take 0x0100 :
It is saying that 0x0100 is the representation of an integer on a little-endian computer, so, it means that the original number must
have been 0x0001 .
So, for the number 0x0001 :

On little endian(LE) : 0x0100

On Big endian(BE) : 0x0001

Clearly,LE = 255 + BE
Similarly for 0x4243 and 0x0001 , They do not satisfy ‘‘LE = 255 + BE ” , So, answer is option A,D.
Refer to Slide 26 in the below article :
Nice Reference: https://www.cs.utexas.edu/~byoung/cs429/slides2-bits-bytes.pdf
Representing Integers:
int A = 15213;
int B = -15213;
long int C = 15213;

1521310 = 0011101101101101 2 = 3B6D16

Linux (little endian) Alpha (little endian) Sun (big endian)

A 6D 3B 00 00 6D 3B 00 00 00 00 3B 6D
B 93 C4 FF FF 93 C4 FF FF FF FF C4 93
C 6D 3B 00 00 00 00 00 00 6D 3B 00 00 00 00 00 00 00 00 00 00 00 00 3B 6D

Byte Ordering Examples:

1. Big Endian: Most significant byte has lowest (first) address.

2. Little Endian: Least significant byte has lowest address.

Example:

Int variable x has 4-byte representation 0x01234567 .

© Copyright GATE Overflow. Some rights reserved.

 Address gives by &x is 0x100.

Big Endian:
Address: 0x100 0x101 0x102 0x103
Value: 01 23 45 67
Little Endian:
Address: 0x100 0x101 0x102 0x103
Value: 67 45 23 01
Note that different people are having different interpretations of this question. I have asked this question on cs.StackExchange,
and you can read the discussion in the below link :
https://cs.stackexchange.com/questions/135713/representation-of-unsigned-integer-on-a-little-endian-big-endian-computer
References

 12 votes -- Deepak Poonia (23.4k points)

4.21 Memory Interfacing (3) top☝

4.21.1 Memory Interfacing: GATE CSE 1995 | Question: 2.2 top☝ ☛ https://gateoverflow.in/2614

The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate
address and data lines are needed for a memory of 4K × 16 ?
A. 10 address, 16 data lines
B. 11 address, 8 data lines
C. 12 address, 16 data lines
D. 12 address, 12 data lines

gate1995 digital-logic memory-interfacing normal

Answer ☟

4.21.2 Memory Interfacing: GATE CSE 2010 | Question: 7 top☝ ☛ https://gateoverflow.in/2178

The main memory unit with a capacity of 4 megabytes is built using 1M× 1-bit DRAM chips. Each DRAM chip has 1K
rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds . The time required to
perform one refresh operation on all the cells in the memory unit is
A. 100 nanoseconds
B. 100 × 210 nanoseconds
C. 100 × 220 nanoseconds
D. 3200 × 220 nanoseconds

gate2010-cse digital-logic memory-interfacing normal

Answer ☟

4.21.3 Memory Interfacing: GATE IT 2005 | Question: 9 top☝ ☛ https://gateoverflow.in/3754

A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100
nsec . What percentage of the memory cycle time is used for refreshing?
A. 10
B. 6.4
C. 1
D. 0.64

© Copyright GATE Overflow. Some rights reserved.

 gate2005-it digital-logic memory-interfacing normal

Answer ☟

Answers: Memory Interfacing

4.21.1 Memory Interfacing: GATE CSE 1995 | Question: 2.2 top☝ ☛ https://gateoverflow.in/2614


ROM memory size = 2m × n

m = no. of address lines n = no. of data lines

Given, 4K × 16

= 22 × 210 × 16

= 212 × 16

Address lines = 12

Data lines= 16

Correct Answer: C
 36 votes -- Sanket_ (3.1k points)

4.21.2 Memory Interfacing: GATE CSE 2010 | Question: 7 top☝ ☛ https://gateoverflow.in/2178


There are 4*8 = 32 DRAM chips to get 4MB from 1M × 1-bit chips. Now, all chips can be refreshed in parallel so do all
cells in a row. So, the total time for refresh will be number of rows times the refresh time

= 1K × 100

= 100 × 210 nanoseconds

Reference: http://www.downloads.reactivemicro.com/Public/Electronics/DRAM/DRAM%20Refresh.pdf
Correct Answer: B
References

 60 votes -- Arjun Suresh (332k points)

4.21.3 Memory Interfacing: GATE IT 2005 | Question: 9 top☝ ☛ https://gateoverflow.in/3754


Ans : (C) 1
In 1 ms refresh 100 times
100
In 64 ns – refresh × 64 × 10−9 times
10−3
= 105 × 10−9 × 64 = 64 × 10−4 times
In 1 memory cycle, refresh 64 × 10−4 times
1 refresh takes 100 ns
64 × 10−4 refreshes take 100 × 10−9 × 64 × 10−4
= 64 × 10−11 s
refreshing time in cycle
∴ % refreshing time = total time
× 100
−11
×
= × 100
© Copyright GATE Overflow. Some rights reserved.
 64 ×10−11
= × 100
64 ×10−9

1
= × 100 = 1%
102

 65 votes -- Afaque Ahmad (727 points)

4.22 Min No Gates (4) top☝

4.22.1 Min No Gates: GATE CSE 2000 | Question: 9 top☝ ☛ https://gateoverflow.in/680

Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):

A. Write the truth table for all bits. Label the input bits I1 , I2 , … with I1 as the least significant bit. Label the output bits
R1 , R2 … with R1 as the least significant bit. Use 1 to signify truth.
B. Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input OR gate and two NOT gates.

gate2000-cse digital-logic min-no-gates descriptive

Answer ☟

4.22.2 Min No Gates: GATE CSE 2004 | Question: 58 top☝ ☛ https://gateoverflow.in/1053

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, … , 9 by 1001 . A combinational circuit is
to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates
may be used, what is the minimum number of gates required?
A. 2
B. 3
C. 4
D. 5

gate2004-cse digital-logic normal min-no-gates

Answer ☟

4.22.3 Min No Gates: GATE CSE 2009 | Question: 6 top☝ ☛ https://gateoverflow.in/1298

What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only
2-input NOR gates?
A. 2
B. 3
C. 4
D. 5

gate2009-cse digital-logic min-no-gates normal

Answer ☟

4.22.4 Min No Gates: GATE IT 2004 | Question: 8 top☝ ☛ https://gateoverflow.in/3649

What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using
any other logic gate?
A. 2
B. 4
C. 5
D. 6

gate2004-it digital-logic min-no-gates normal

Answer ☟

Answers: Min No Gates

© Copyright GATE Overflow. Some rights reserved.

 4.22.1 Min No Gates: GATE CSE 2000 | Question: 9 top☝ ☛ https://gateoverflow.in/680

I4 I3 I2 I1 R3 R2 R1
0 0 0 0 0 0 0 0
0 0 0 1 1 0 0 1
0 0 1 0 2 0 1 0
0 0 1 1 3 0 1 1
0 1 0 0 4 1 0 0
0 1 0 1 5 1 0 1
0 1 1 0 6 0 0 0
0 1 1 1 7 0 0 1
1 0 0 0 8 0 1 0
1 0 0 1 9 0 1 1

R1 = I1
¯¯¯¯
R2 = I2 I3 + I4
¯¯¯¯
R3 = I3 I2

This requires 2 NOT gates, 2 two-input AND gates and 1 two-input OR gate.

 14 votes -- Savir husen khan (305 points)

After using Don't care (10,11,12,13,14,15) and after K-Map simplification you will get
R1=I1
R2=I2.I3' + I4
R3= I3.I2'
R4 = 0

Here, 2 input AND Gate used=2

2 input OR Gate used=1
NOT Gate used=2

 11 votes -- Krishn Kumar Gupta (1.1k points)

4.22.2 Min No Gates: GATE CSE 2004 | Question: 58 top☝ ☛ https://gateoverflow.in/1053


Answer should be (B). As according to question, truth table will be like:

© Copyright GATE Overflow. Some rights reserved.

 A B C D f
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 don’t care
1 0 1 1 don’t care
1 1 0 0 don’t care
1 1 0 1 don’t care
1 1 1 0 don’t care
1 1 1 1 don’t care

Using this truth table we get 3 sub cube which are combined with following minterms A(8, 9, 10, 11, 12, 13, 14, 15) ,
BD(5, 13, 7, 15) and BC(6, 7, 14, 15)
So, f = A + BD + BC = A + B(C + D)
So, minimum gate required 2 OR gate and 1 AND gate = 3 minimum gates.

 42 votes -- minal (13.1k points)

4.22.3 Min No Gates: GATE CSE 2009 | Question: 6 top☝ ☛ https://gateoverflow.in/1298


Given boolean function is
f = AB + C
= (A + C). (B + C)
= ((A + C )′ + (B + C )′ )′

© Copyright GATE Overflow. Some rights reserved.

 Therefore, 3 NOR gates required .
Correct Answer: B

 77 votes -- Mithlesh Upadhyay (4.3k points)

4.22.4 Min No Gates: GATE IT 2004 | Question: 8 top☝ ☛ https://gateoverflow.in/3649


Correct Option B 4.

A B Output
0 0 0
0 1 1
1 0 1
1 1 0

 20 votes -- Manu Madhavan (827 points)

4.23 Min Product Of Sums (2) top☝

4.23.1 Min Product Of Sums: GATE CSE 1990 | Question: 5-a top☝ ☛ https://gateoverflow.in/85396

Find the minimum product of sums of the following expression

¯¯¯¯ ¯¯¯¯ ¯¯¯¯

f = ABC + A B C

gate1990 digital-logic boolean-algebra min-product-of-sums canonical-normal-form descriptive

Answer ☟

4.23.2 Min Product Of Sums: GATE CSE 2017 Set 2 | Question: 28 top☝ ☛ https://gateoverflow.in/118370

Given f(w, x, y, z) = Σm (0, 1, 2, 3, 7, 8, 10) + Σd (5, 6, 11, 15) ; where d represents the 'don't-care' condition in Karnaugh
maps. Which of the following is a minimum product-of-sums (POS) form of f(w, x, y, z) ?

A. f = (w̄ + z̄ )(x̄ + z)
B. f = (w̄ + z)(x + z)
C. f = (w + z)(x̄ + z)
D. f = (w + z̄ )(x̄ + z)

gate2017-cse-set2 digital-logic min-product-of-sums

Answer ☟

Answers: Min Product Of Sums

© Copyright GATE Overflow. Some rights reserved.

 4.23.1 Min Product Of Sums: GATE CSE 1990 | Question: 5-a top☝ ☛ https://gateoverflow.in/85396


Minimal POS

f = (Ā + B)(A
+ C̄ )(B̄ + C)

 26 votes -- Lokesh Dafale (8.2k points)

4.23.2 Min Product Of Sums: GATE CSE 2017 Set 2 | Question: 28 top☝ ☛ https://gateoverflow.in/118370


A. (x̄ + z) (z̄ + w̄)

 34 votes -- Joker (1.6k points)

4.24 Min Sum Of Products Form (13) top☝

4.24.1 Min Sum Of Products Form: GATE CSE 1988 | Question: 2-v top☝ ☛ https://gateoverflow.in/91685

Three switching functions f1 , f2 and f3 are expressed below as sum of minterms.

f1 (w, x, y, z) = ∑ 0, 1, 2, 3, 5, 12
f2 (w, x, y, z) = ∑ 0, 1, 2, 10, 13, 14, 15
f3 (w, x, y, z) = ∑ 2, 4, 5, 8

Express the function f realised by the circuit shown in the below figure as the sum of minterms (in decimal notation).

© Copyright GATE Overflow. Some rights reserved.

 gate1988 descriptive digital-logic easy circuit-output min-sum-of-products-form

Answer ☟

4.24.2 Min Sum Of Products Form: GATE CSE 1991 | Question: 5-b top☝ ☛ https://gateoverflow.in/26437

Find the minimum sum of products form of the logic function f(A, B, C, D) = Σm (0, 2, 8, 10, 15) + Σd (3, 11, 12, 14)
where m and d represent minterm and don't care term respectively.

gate1991 digital-logic boolean-algebra min-sum-of-products-form descriptive

Answer ☟

4.24.3 Min Sum Of Products Form: GATE CSE 1997 | Question: 71 top☝ ☛ https://gateoverflow.in/19701

Let f = (w̄ + y)(x̄ + y)(w + x̄ + z)(w̄ + z)(x̄ + z)

A. Express f as the minimal sum of products. Write only the answer.

B. If the output line is stuck at 0, for how many input combinations will the value of f be correct?

gate1997 digital-logic min-sum-of-products-form numerical-answers

Answer ☟

4.24.4 Min Sum Of Products Form: GATE CSE 2001 | Question: 10 top☝ ☛ https://gateoverflow.in/751

a. Is the 3-variable function f = Σ(0, 1, 2, 4) its self-dual? Justify your answer.

b. Give a minimal product-of-sum form of the b output of the following excess-3 to BCD converter.

gate2001-cse digital-logic normal descriptive min-sum-of-products-form

Answer ☟

4.24.5 Min Sum Of Products Form: GATE CSE 2005 | Question: 18 top☝ ☛ https://gateoverflow.in/1354

The switching expression corresponding to f(A, B, C, D) = Σ(1, 4, 5, 9, 11, 12) is:

A. BC ′ D′ + A′ C ′ D + AB′ D
B. ABC ′ + ACD + B′ C ′ D
C. AC D′ + A′ BC ′ + AC ′ D′
D. A′ BD + AC D′ + BC D′

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 gate2005-cse digital-logic normal min-sum-of-products-form

Answer ☟

4.24.6 Min Sum Of Products Form: GATE CSE 2007 | Question: 9 top☝ ☛ https://gateoverflow.in/1207

Consider the following Boolean function of four variables:

f(w, x, y, z) = Σ(1, 3, 4, 6, 9, 11, 12, 14)

The function is
A. independent of one variables.
B. independent of two variables.
C. independent of three variables.
D. dependent on all variables

gate2007-cse digital-logic normal min-sum-of-products-form

Answer ☟

4.24.7 Min Sum Of Products Form: GATE CSE 2011 | Question: 14 top☝ ☛ https://gateoverflow.in/2116

The simplified SOP (Sum of Product) from the Boolean expression

(P + Q̄ + R̄). (P + Q̄ + R). (P + Q + R̄)

is

A. (P¯. Q + R̄)
B. (P + Q̄. R̄)
C. (P¯. Q + R)
D. (P. Q + R)

gate2011-cse digital-logic normal min-sum-of-products-form

Answer ☟

4.24.8 Min Sum Of Products Form: GATE CSE 2014 Set 1 | Question: 45 top☝ ☛ https://gateoverflow.in/1923

Consider the 4-to-1 multiplexer with two select lines S1 and S0 given below

The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is

A. P¯Q + QR̄ + P Q̄R

B. P¯Q + P¯QR̄ + PQR̄ + P Q̄R
C. P¯QR + P¯QR̄ + QR̄ + P Q̄R

PQ ¯

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 D. PQR̄

gate2014-cse-set1 digital-logic normal multiplexer min-sum-of-products-form

Answer ☟

4.24.9 Min Sum Of Products Form: GATE CSE 2014 Set 1 | Question: 7 top☝ ☛ https://gateoverflow.in/1764

Consider the following Boolean expression for F:

F(P, Q, R, S) = PQ + P¯QR + P¯QR̄S
The minimal sum−of−products form of F is
A. PQ + QR + QS
B. P +Q+R+S
C. P¯ + Q̄ + R̄ + S̄
D. P¯R + R̄P¯S + P

gate2014-cse-set1 digital-logic normal min-sum-of-products-form

Answer ☟

4.24.10 Min Sum Of Products Form: GATE CSE 2014 Set 3 | Question: 7 top☝ ☛ https://gateoverflow.in/2041

Consider the following minterm expression for F :

F(P, Q, R, S) = ∑ 0, 2, 5, 7, 8, 10, 13, 15

The minterms 2, 7, 8 and 13 are 'do not care' terms. The minimal sum-of-products form for F is

A. QS̄ + Q̄S
B. Q̄S̄ + QS
C. Q̄R̄S̄ + Q̄RS̄ + QR̄S + QRS
D. P¯Q̄S̄ + P¯QS + PQS + P Q̄S̄

gate2014-cse-set3 digital-logic min-sum-of-products-form normal

Answer ☟

4.24.11 Min Sum Of Products Form: GATE CSE 2018 | Question: 49 top☝ ☛ https://gateoverflow.in/204124

Consider the minterm list form of a Boolean function F given below.

F(P, Q, R, S) = Σm(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12, 14)

Here, m denotes a minterm and d denotes a don't care term. The number of essential prime implicants of the function F is ___

gate2018-cse digital-logic min-sum-of-products-form numerical-answers

Answer ☟

4.24.12 Min Sum Of Products Form: GATE CSE 2021 Set 2 | Question: 52 top☝ ☛ https://gateoverflow.in/357485

Consider a Boolean function f(w, x, y, z) such that

f(w, 0, 0, z) = 1
f(1, x, 1, z) = x+z
f(w, 1, y, z) = wz + y

The number of literals in the minimal sum-of-products expression of f is _________

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 gate2021-cse-set2 digital-logic boolean-algebra min-sum-of-products-form numerical-answers

Answer ☟

4.24.13 Min Sum Of Products Form: GATE IT 2008 | Question: 8 top☝ ☛ https://gateoverflow.in/3268

Consider the following Boolean function of four variables

f(A, B, C, D) = Σ(2, 3, 6, 7, 8, 9, 10, 11, 12, 13)
The function is
A. independent of one variable
B. independent of two variables
C. independent of three variable
D. dependent on all the variables

gate2008-it digital-logic normal min-sum-of-products-form

Answer ☟

Answers: Min Sum Of Products Form

4.24.1 Min Sum Of Products Form: GATE CSE 1988 | Question: 2-v top☝ ☛ https://gateoverflow.in/91685


Final output = ∑ 0, 1, 2, 4, 5, 8

f1 (w, x, y, z) = ∑ 0, 1, 2, 3, 5, 12
f2 (w, x, y, z) = ∑ 0, 1, 2, 10, 13, 14, 15
f3 (w, x, y, z) = ∑ 2, 4, 5, 8

f1 AND f2 will give the common minterms - f12 = ∑ 0, 1, 2.

Now f12 OR f3 = ∑ 0, 1, 2, 4, 5, 8.

 16 votes -- kunal chalotra (13.6k points)

4.24.2 Min Sum Of Products Form: GATE CSE 1991 | Question: 5-b top☝ ☛ https://gateoverflow.in/26437

The minimum SOP form of the logic function is given as : f(A, B, C, D) = B′ D′ + AC.

 18 votes -- Kalpna Bhargav (2.5k points)

4.24.3 Min Sum Of Products Form: GATE CSE 1997 | Question: 71 top☝ ☛ https://gateoverflow.in/19701

© Copyright GATE Overflow. Some rights reserved.

 

Answer of question A: w′ x′ + yz

Answer of question B:

Stuck at 0, means output is fixed at 0 (No matter what the input is). We got 0 for 9 input combinations (Check K-Map). So,
answer is 9.

 28 votes -- Akash Kanase (36k points)

4.24.4 Min Sum Of Products Form: GATE CSE 2001 | Question: 10 top☝ ☛ https://gateoverflow.in/751


There are two conditions for a function being self dual.

1. it should be a neutral function. (no. of minterms = no. of max terms)

2. no two mutually exclusive terms should be there like (0 − 7 are mutually exclusive 1 − 6, 2 − 5, 3 − 4 ) from these pairs
only one should be there.

Clearly, there are 4 minterms, so number of minterms = no. of maxterms.

And second condition is also satisfied. So, it is a self dual function .
(b) Excess-3 to BCD
Truth Table
Inputs Outputs
W X Y Z A B C D
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

MAPS:

© Copyright GATE Overflow. Some rights reserved.

  26 votes -- Ravi Singh (11.8k points)

4.24.5 Min Sum Of Products Form: GATE CSE 2005 | Question: 18 top☝ ☛ https://gateoverflow.in/1354


Answer is: [A]

 15 votes -- Desert_Warrior (6k points)

4.24.6 Min Sum Of Products Form: GATE CSE 2007 | Question: 9 top☝ ☛ https://gateoverflow.in/1207


The K-map would be

© Copyright GATE Overflow. Some rights reserved.

 So, the minimized expression would be
x′ z + xz ′ = x ⊕ z.
Option B.

 21 votes -- Arjun Suresh (332k points)

4.24.7 Min Sum Of Products Form: GATE CSE 2011 | Question: 14 top☝ ☛ https://gateoverflow.in/2116

K-map

Answer is B

 26 votes -- Sona Praneeth Akula (3.4k points)

4.24.8 Min Sum Of Products Form: GATE CSE 2014 Set 1 | Question: 45 top☝ ☛ https://gateoverflow.in/1923


S0 and S1 are used to select the input given to be given as output.

S0 S1 Output
0 0 0
0 1 1
1 0 R
1 1 R'

So, output becomes 1 for

S0′ S1 + S0 S1′ R + S0 S1 R′

= P ′ Q + P Q′ R + PQR′

= P ′ Q + PQR′ + P Q′ R

= Q(P ′ + P R′ ) + P Q′ R

= Q(P ′ + R′ ) + P Q′ R (∵ A + A′ B = A + B)
= P ′ Q + Q R′ + P Q ′ R

Option (A)
 31 votes -- Arjun Suresh (332k points)

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 4.24.9 Min Sum Of Products Form: GATE CSE 2014 Set 1 | Question: 7 top☝ ☛ https://gateoverflow.in/1764

Minimal SOP = PQ + QR + QS
Hence, option A is correct.

 32 votes -- Amar Vashishth (25.2k points)

4.24.10 Min Sum Of Products Form: GATE CSE 2014 Set 3 | Question: 7 top☝ ☛ https://gateoverflow.in/2041


While putting the terms to K-map the 3rd and 4th columns are swapped so, do 3rd and 4th rows. So, term 2 is going to
(0, 3) column instead of (0, 2) , 8 is going to (3, 0) instead of (2, 0) etc.

Solving this k-map gives B) as the answer.

Reference: http://www.cs.uiuc.edu/class/sp08/cs231/lectures/04-Kmap.pdf
References

 22 votes -- Srinath Jayachandran (2.9k points)

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 4.24.11 Min Sum Of Products Form: GATE CSE 2018 | Question: 49 top☝ ☛ https://gateoverflow.in/204124

Implicant: Any product term p in SOP form such that p ⟹ f is an implicant of f. So, we have 9 implicants for F here one
corresponding to each 1 or d in the K-map.

Prime Implicant: A minimal implicant is called a prime implicant (no extra literals than required). So, we have 5 prime
implicants for F − {ĀBD, B̄D̄, AB̄, ĀCD, B̄C}. (for each 1 or d in K − map try to combine with near by 1s and do not
care conditions)
Essential Prime Implicant: A prime implicant which cannot be replaced by any other for getting the output. i.e., essential prime
implicants cover the output that no other combination of other prime implicants can. In K-map, this means an essential prime
implicant must cover a 1 (we do not consider don't care as essential ) which is not covered by any other prime
implicant. Here, we have 3 essential prime implicants corresponding to 3 selections shown in the below K − map .

So, 3 Essential Prime Implicants.

References

 41 votes -- Digvijay (44.9k points)

4.24.12 Min Sum Of Products Form: GATE CSE 2021 Set 2 | Question: 52 top☝ ☛ https://gateoverflow.in/357485

© Copyright GATE Overflow. Some rights reserved.

 

We can see 3 squares, so number of literals = 3 × 2 = 6.

 8 votes -- zxy123 (2.8k points)

4.24.13 Min Sum Of Products Form: GATE IT 2008 | Question: 8 top☝ ☛ https://gateoverflow.in/3268

(2, 3, 6, 7) : ĀC
(2, 3, 10, 11) : B̄C
(8, 9, 12, 13) : AC̄
y=ĀC+B̄C+AC̄

Option A.

 21 votes -- Aditi Tiwari (879 points)

4.25 Multiplexer (13) top☝

4.25.1 Multiplexer: GATE CSE 1987 | Question: 1-IV top☝ ☛ https://gateoverflow.in/80193

The output F of the below multiplexer circuit can be represented by

© Copyright GATE Overflow. Some rights reserved.

 A. AB + BC̄ + C̄ A + B̄C̄
B. A⊕B⊕C
C. A⊕B
D. ĀB̄C + ĀBC̄ + AB̄C̄

gate1987 digital-logic combinational-circuits multiplexer circuit-output

Answer ☟

4.25.2 Multiplexer: GATE CSE 1990 | Question: 5-b top☝ ☛ https://gateoverflow.in/85398

Show with the help of a block diagram how the Boolean function :

f = AB + BC + CA

can be realised using only a 4 : 1 multiplexer.

gate1990 descriptive digital-logic combinational-circuits multiplexer

Answer ☟

4.25.3 Multiplexer: GATE CSE 1996 | Question: 2.22 top☝ ☛ https://gateoverflow.in/2751

Consider the circuit in figure. f implements

¯¯¯¯¯¯¯¯ ¯¯¯¯ ¯¯¯¯

A. ABC + ABC + ABC
B. A + B + C
C. A ⊕ B ⊕ C
D. AB + BC + CA

gate1996 digital-logic circuit-output easy multiplexer

© Copyright GATE Overflow. Some rights reserved.

 Answer ☟

4.25.4 Multiplexer: GATE CSE 1998 | Question: 1.14 top☝ ☛ https://gateoverflow.in/1651

A multiplexer with a 4 − bit data select input is a

A. 4 : 1 multiplexer
B. 2 : 1 multiplexer
C. 16 : 1 multiplexer
D. 8 : 1 multiplexer

gate1998 digital-logic multiplexer easy

Answer ☟

4.25.5 Multiplexer: GATE CSE 2001 | Question: 2.11 top☝ ☛ https://gateoverflow.in/729

Consider the circuit shown below. The output of a 2 : 1 MUX is given by the function (ac′ + bc) .

Which of the following is true?

A. f = X1′ + X2
B. f = X1′ X2 + X1 X2′
C. f = X1 X2 + X1′ X2′
D. f = X1 + X2′

gate2001-cse digital-logic normal multiplexer

Answer ☟

4.25.6 Multiplexer: GATE CSE 2004 | Question: 60 top☝ ☛ https://gateoverflow.in/1055

Consider a multiplexer with X and Y as data inputs and Z the as the control input. Z = 0 selects input X, and Z = 1 selects
input Y . What are the connections required to realize the 2-variable Boolean function f = T + R , without using any additional
hardware?
A. R to X, 1 to Y, T to Z
B. T to X, R to Y, T to Z
C. T to X, R to Y, 0 to Z
D. R to X, 0 to Y, T to Z

gate2004-cse digital-logic normal multiplexer

Answer ☟

4.25.7 Multiplexer: GATE CSE 2007 | Question: 34 top☝ ☛ https://gateoverflow.in/1232

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables.
What is the minimum size of the multiplexer needed?
A. 2n line to 1 line

B. 2n+1 line to 1line

n−1

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 C. 2n−1 line to 1line

D. 2n−2 line to 1line

gate2007-cse digital-logic normal multiplexer

Answer ☟

4.25.8 Multiplexer: GATE CSE 2016 Set 1 | Question: 30 top☝ ☛ https://gateoverflow.in/39722

Consider the two cascade 2 to 1 multiplexers as shown in the figure .

The minimal sum of products form of the output X is

¯¯¯¯ ¯¯¯¯
A. P Q + PQR
¯¯¯¯
B. P Q + QR
¯¯¯¯ ¯¯¯¯
C. PQ + P QR
¯¯¯¯ ¯¯¯¯
D. Q R + PQR

gate2016-cse-set1 digital-logic multiplexer normal

Answer ☟

4.25.9 Multiplexer: GATE CSE 2020 | Question: 19 top☝ ☛ https://gateoverflow.in/333212

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given
point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is
______.

gate2020-cse numerical-answers digital-logic multiplexer

Answer ☟

4.25.10 Multiplexer: GATE CSE 2021 Set 2 | Question: 5 top☝ ☛ https://gateoverflow.in/357535

Which one of the following circuits implements the Boolean function given below?
f(x, y, z) = m0 + m1 + m3 + m4 + m5 + m6 , where mi is the ith minterm.

A.

B.

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 C.

D.

gate2021-cse-set2 digital-logic combinational-circuits multiplexer

Answer ☟

4.25.11 Multiplexer: GATE IT 2005 | Question: 48 top☝ ☛ https://gateoverflow.in/3809

The circuit shown below implements a 2-input NOR gate using two 2 − 4 MUX (control signal 1 selects the upper input).
What are the values of signals x, y and z?

A. 1, 0, B
B. 1, 0, A
C. 0, 1, B
D. 0, 1, A

gate2005-it digital-logic normal multiplexer

Answer ☟

4.25.12 Multiplexer: GATE IT 2007 | Question: 8 top☝ ☛ https://gateoverflow.in/3441

The following circuit implements a two-input AND gate using two 2 − 1 multiplexers.

© Copyright GATE Overflow. Some rights reserved.

 What are the values of X1 , X2 , X3 ?
A. X1 = b, X2 = 0, X3 = a
B. X1 = b, X2 = 1, X3 = b
C. X1 = a, X2 = b, X3 = 1
D. X1 = a, X2 = 0, X3 = b

gate2007-it digital-logic normal multiplexer

Answer ☟

4.25.13 Multiplexer: GATE1992-04-b top☝ ☛ https://gateoverflow.in/17407

A priority encoder accepts three input signals (A, B and C) and produces a two-bit output (X1 , X0 ) corresponding to the
highest priority active input signal. Assume A has the highest priority followed by B and C has the lowest priority. If none of the
inputs are active the output should be 00, design the priority encoder using 4 : 1 multiplexers as the main components.

gate1992 digital-logic combinational-circuits multiplexer descriptive

Answer ☟

Answers: Multiplexer

4.25.1 Multiplexer: GATE CSE 1987 | Question: 1-IV top☝ ☛ https://gateoverflow.in/80193


Answer is B)

A′ B′ C + AB′ C ′ + A′ BC ′ + ABC

= (A + B′ )(A′ + B)C + A′ BC ′ + AB′ C ′

=A ⊕ B ⊕ C
 18 votes -- srestha (85.2k points)

4.25.2 Multiplexer: GATE CSE 1990 | Question: 5-b top☝ ☛ https://gateoverflow.in/85398


AB + BC + CA = AB + A′ BC + AB′ C

 18 votes -- kirti singh (2.6k points)

© Copyright GATE Overflow. Some rights reserved.

 4.25.3 Multiplexer: GATE CSE 1996 | Question: 2.22 top☝ ☛ https://gateoverflow.in/2751


0−C will be selected for A = 0, B = 0 .
1 − C̄ will be selected for A = 0, B = 1.
2 − C̄ will be selected for A = 1, B = 0.
3−C will be selected for A = 1, B = 1.

So, f = ĀB̄C + ĀBC̄ + AB̄C̄ + ABC

= Ā(B̄C + BC̄ ) + A(B̄C̄ + BC)

= Ā(B ⊕ C) + A(B ⊙ C)
¯¯¯¯¯¯¯¯¯¯¯¯¯¯
= Ā(B ⊕ C) + A(B ⊕ C )

= A⊕B⊕C
Correct Answer: C

 25 votes -- Arjun Suresh (332k points)

4.25.4 Multiplexer: GATE CSE 1998 | Question: 1.14 top☝ ☛ https://gateoverflow.in/1651


for n bit data select input

2n : 1

for 4 it is 16 : 1

Correct Answer: C
 27 votes -- Bhagirathi Nayak (11.7k points)

4.25.5 Multiplexer: GATE CSE 2001 | Question: 2.11 top☝ ☛ https://gateoverflow.in/729


g = X1′
So, f = ac′ + bc

= X1′ X2′ + X1 X2

So, (C).
 30 votes -- Arjun Suresh (332k points)

4.25.6 Multiplexer: GATE CSE 2004 | Question: 60 top☝ ☛ https://gateoverflow.in/1055


Answer is option A.
′
Z X + ZY
Put Z = T , X = R, Y = 1 in Z ′ X + ZY
= T ′R + 1 ∗ T

= (T + T ′ )(T + R)
= T +R

 27 votes -- Digvijay (44.9k points)

4.25.7 Multiplexer: GATE CSE 2007 | Question: 34 top☝ ☛ https://gateoverflow.in/1232


2n−1 to 1

We will map (n − 1) variables to select lines and 1 variable to input line

© Copyright GATE Overflow. Some rights reserved.

  44 votes -- Anurag Semwal (6.7k points)

4.25.8 Multiplexer: GATE CSE 2016 Set 1 | Question: 30 top☝ ☛ https://gateoverflow.in/39722


For 2 : 1 MUX, output Y = S ′ Io + SI1
So, output of MUX1 ,f1 = P ′ 0 + PR = PR

Output of MUX2 , f2 = Q′ R′ + Qf1 = Q′ R′ + PQR

which is option D

 43 votes -- Monanshi Jain (7k points)

4.25.9 Multiplexer: GATE CSE 2020 | Question: 19 top☝ ☛ https://gateoverflow.in/333212


If there are ‘m’ select lines for a multiplexor, then it may have up to 2m input lines.

Given that there are 32 input lines. So, there must be ⌈log2 n⌉ = ⌈log2 32⌉ = 5 select lines.
 12 votes -- Shaik Masthan (50.4k points)

4.25.10 Multiplexer: GATE CSE 2021 Set 2 | Question: 5 top☝ ☛ https://gateoverflow.in/357535


f(x, y, z) = m0 + m1 + m3 + m4 + m5 + m6
S1 = y, S0 = z

Draw a small table as following and mark the min-terms in f.

I0 I1 I2 I3
x̄ 0 1 2 3
x 4 5 6 7

I0 = (x̄ + x) = 1 (both rows are marked)

I1 = (x̄ + x) = 1 (both rows are marked)
I2 = x (only row corresponding to x is marked)
I3 = x̄ (only row corresponding to x̄ is marked)
A is correct.

 2 votes -- Nikhil Dhama (2.5k points)

4.25.11 Multiplexer: GATE IT 2005 | Question: 48 top☝ ☛ https://gateoverflow.in/3809


f = Az + Bz̄ (As A will be selected when z is high) .
So, next function will become g = xf + yf¯
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
= x (Az + Bz̄ ) + y(Az + Bz̄ )
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Putting x = 0, y = 1, z = A , we get g = AA + BĀ = A + B (∵ A + BĀ = A + B) and answer will become D

 38 votes -- John Carter (1.4k points)

4.25.12 Multiplexer: GATE IT 2007 | Question: 8 top☝ ☛ https://gateoverflow.in/3441


Answer: A

F = (bX1′ + aX1 )X3 + X2 X3′

© Copyright GATE Overflow. Some rights reserved.

 Put X1 = b, X2 = 0, X3 = a to get F = ab.
 26 votes -- Rajarshi Sarkar (27.9k points)

4.25.13 Multiplexer: GATE1992-04-b top☝ ☛ https://gateoverflow.in/17407


MSB − Most Significant Bit
LSB − Least Significant Bit
TRUTH TABLE
Inputs : A, B, C
Outputs : MSB, LSB
A B C MSB LSB
0 0 0 0 0
0 0 1 0 1
0 1 X 1 0
1 X X 1 1

MSB = A + B
LSB = A + B̄C

It can be implemented using two 4 × 1 Multiplexers.

 34 votes -- Anurag Pandey (10.5k points)

4.26 Number Representation (51) top☝

4.26.1 Number Representation: GATE CSE 1988 | Question: 2-vi top☝ ☛ https://gateoverflow.in/91687

−−−−
Define the value of r in the following: √(41)r = (7)10

gate1988 digital-logic normal number-representation descriptive

Answer ☟

4.26.2 Number Representation: GATE CSE 1990 | Question: 1-viii top☝ ☛ https://gateoverflow.in/87055

The condition for overflow in the addition of two 2′ s complement numbers in terms of the carry generated by the two most
significant bits is ___________.

gate1990 digital-logic number-representation fill-in-the-blanks

© Copyright GATE Overflow. Some rights reserved.

 Answer ☟

4.26.3 Number Representation: GATE CSE 1991 | Question: 01-iii top☝ ☛ https://gateoverflow.in/500

Consider the number given by the decimal expression:

163 ∗ 9 + 162 ∗ 7 + 16 ∗ 5 + 3

The number of 1′ s in the unsigned binary representation of the number is ______

gate1991 digital-logic number-representation normal numerical-answers

Answer ☟

4.26.4 Number Representation: GATE CSE 1991 | Question: 01-v top☝ ☛ https://gateoverflow.in/503

When two 4-bit numbers A = a3 a2 a1 a0 and B = b3 b2 b1 b0 are multiplied, the bit c1 of the product C is given by ________

gate1991 digital-logic normal number-representation fill-in-the-blanks

Answer ☟

4.26.5 Number Representation: GATE CSE 1992 | Question: 4-a top☝ ☛ https://gateoverflow.in/583

Consider addition in two's complement arithmetic. A carry from the most significant bit does not always correspond to an
overflow. Explain what is the condition for overflow in two's complement arithmetic.

gate1992 digital-logic normal number-representation descriptive

Answer ☟

4.26.6 Number Representation: GATE CSE 1993 | Question: 6.5 top☝ ☛ https://gateoverflow.in/2286

Convert the following numbers in the given bases into their equivalents in the desired bases:

A. (110.101)2 = (x)10
B. (1118)10 = (y)H

gate1993 digital-logic number-representation normal descriptive

Answer ☟

4.26.7 Number Representation: GATE CSE 1994 | Question: 2.7 top☝ ☛ https://gateoverflow.in/2474

Consider n-bit (including sign bit) 2′ s complement representation of integer numbers. The range of integer values, N , that can
be represented is ______ ≤ N ≤ ______ .

gate1994 digital-logic number-representation easy fill-in-the-blanks

Answer ☟

4.26.8 Number Representation: GATE CSE 1995 | Question: 18 top☝ ☛ https://gateoverflow.in/2655

The following is an incomplete Pascal function to convert a given decimal integer (in the range −8 to +7 ) into a binary
integer in 2’s complement representation. Determine the expressions A, B, C that complete program.
function TWOSCOMP (N:integer):integer;
var
REM, EXPONENT:integer;
BINARY :integer;
begin
if(N>=-8) and (N<=+7) then
begin
if N<0 then
N:=A;
BINARY:=0;
EXPONENT:=1;
while N<>0 do

© Copyright GATE Overflow. Some rights reserved.

 begin
REM:=N mod 2;
BINARY:=BINARY + B*EXPONENT;
EXPONENT:=EXPONENT*10;
N:=C
end
TWOSCOMP:=BINARY
end
end;

gate1995 digital-logic number-representation normal descriptive

Answer ☟

4.26.9 Number Representation: GATE CSE 1995 | Question: 2.12, ISRO2015-9 top☝ ☛ https://gateoverflow.in/2624

The number of 1's in the binary representation of (3 ∗ 4096 + 15 ∗ 256 + 5 ∗ 16 + 3) are:

A. 8
B. 9
C. 10
D. 12

gate1995 digital-logic number-representation normal isro2015

Answer ☟

4.26.10 Number Representation: GATE CSE 1996 | Question: 1.25 top☝ ☛ https://gateoverflow.in/2729

Consider the following floating-point number representation.

31 24 23 0
Exponent Mantissa

The exponent is in 2′ s complement representation and the mantissa is in the sign-magnitude representation. The range of the
magnitude of the normalized numbers in this representation is
A. 0 to 1
B. 0.5 to 1
C. 2−23 to 0.5
D. 0.5 to (1 − 2−23 )

gate1996 digital-logic number-representation normal

Answer ☟

4.26.11 Number Representation: GATE CSE 1997 | Question: 5.4 top☝ ☛ https://gateoverflow.in/2255

−−−−−
Given √(224)r = (13)r .
The value of the radix r is:
A. 10
B. 8
C. 5
D. 6

gate1997 digital-logic number-representation normal

Answer ☟

4.26.12 Number Representation: GATE CSE 1998 | Question: 1.17 top☝ ☛ https://gateoverflow.in/1654

The octal representation of an integer is (342)8 . If this were to be treated as an eight-bit integer in an 8085 based computer,
its decimal equivalent is
A. 226
B. −98
C. 76
−30

© Copyright GATE Overflow. Some rights reserved.

 D. −30

gate1998 digital-logic number-representation normal 8085

Answer ☟

4.26.13 Number Representation: GATE CSE 1998 | Question: 2.20 top☝ ☛ https://gateoverflow.in/1693

Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage
space of this attribute if it is stored as an integer rather than in character form?

A. 80%
B. 20%
C. 60%
D. 40%

gate1998 digital-logic number-representation normal

Answer ☟

4.26.14 Number Representation: GATE CSE 1999 | Question: 2.17 top☝ ☛ https://gateoverflow.in/1495

Zero has two representations in

A. Sign-magnitude
B. 2′ s complement
C. 1′ s complement
D. None of the above

gate1999 digital-logic number-representation easy multiple-selects

Answer ☟

4.26.15 Number Representation: GATE CSE 2000 | Question: 1.6 top☝ ☛ https://gateoverflow.in/629

The number 43 in 2′ s complement representation is

A. 01010101
B. 11010101
C. 00101011
D. 10101011

gate2000-cse digital-logic number-representation easy

Answer ☟

4.26.16 Number Representation: GATE CSE 2000 | Question: 2.14 top☝ ☛ https://gateoverflow.in/661

Consider the values of A = 2.0 × 1030 , B = −2.0 × 1030 , C = 1.0, and the sequence
X:= A + B Y:= A + C
X:= X + C Y:= Y + B

executed on a computer where floating point numbers are represented with 32 bits. The values for X and Y will be
A. X = 1.0, Y = 1.0
B. X = 1.0, Y = 0.0
C. X = 0.0, Y = 1.0
D. X = 0.0, Y = 0.0

gate2000-cse digital-logic number-representation normal

Answer ☟

4.26.17 Number Representation: GATE CSE 2001 | Question: 2.10 top☝ ☛ https://gateoverflow.in/728

© Copyright GATE Overflow. Some rights reserved.

 The 2′ s complement representation of (-539)10 in hexadecimal is

A. ABE
B. DBC
C. DE5
D. 9E7

gate2001-cse digital-logic number-representation easy

Answer ☟

4.26.18 Number Representation: GATE CSE 2002 | Question: 1.14 top☝ ☛ https://gateoverflow.in/818

The decimal value 0.25

A. is equivalent to the binary value 0.1

B. is equivalent to the binary value 0.01
C. is equivalent to the binary value 0.00111
D. cannot be represented precisely in binary

gate2002-cse digital-logic number-representation easy

Answer ☟

4.26.19 Number Representation: GATE CSE 2002 | Question: 1.15 top☝ ☛ https://gateoverflow.in/819

The 2′ s complement representation of the decimal value −15 is

A. 1111
B. 11111
C. 111111
D. 10001

gate2002-cse digital-logic number-representation easy

Answer ☟

4.26.20 Number Representation: GATE CSE 2002 | Question: 1.16 top☝ ☛ https://gateoverflow.in/821

Sign extension is a step in

A. floating point multiplication
B. signed 16 bit integer addition
C. arithmetic left shift
D. converting a signed integer from one size to another

gate2002-cse digital-logic easy number-representation

Answer ☟

4.26.21 Number Representation: GATE CSE 2002 | Question: 1.21 top☝ ☛ https://gateoverflow.in/826

In 2′ s complement addition, overflow

A. is flagged whenever there is carry from sign bit addition

B. cannot occur when a positive value is added to a negative value
C. is flagged when the carries from sign bit and previous bit match
D. None of the above

gate2002-cse digital-logic number-representation normal

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.26.22 Number Representation: GATE CSE 2002 | Question: 9 top☝ ☛ https://gateoverflow.in/862

Consider the following 32-bit floating-point representation scheme as shown in the format below. A value is specified by 3
fields, a one bit sign field (with 0 for positive and 1 for negative values), a 24 bit fraction field (with the binary point is at the left
end of the fraction bits), and a 7 bit exponent field (in excess-64 signed integer representation, with 16 is the base of
exponentiation). The sign bit is the most significant bit.

A. It is required to represent the decimal value −7.5 as a normalized floating point number in the given format. Derive the values
of the various fields. Express your final answer in the hexadecimal.
B. What is the largest value that can be represented using this format? Express your answer as the nearest power of 10.

gate2002-cse digital-logic number-representation normal descriptive

Answer ☟

4.26.23 Number Representation: GATE CSE 2003 | Question: 9 top☝ ☛ https://gateoverflow.in/900

Assuming all numbers are in 2′ s complement representation, which of the following numbers is divisible by 11111011 ?
A. 11100111
B. 11100100
C. 11010111
D. 11011011

gate2003-cse digital-logic number-representation normal

Answer ☟

4.26.24 Number Representation: GATE CSE 2004 | Question: 19 top☝ ☛ https://gateoverflow.in/1016

If 73x (in base-x number system) is equal to 54y (in base y-number system), the possible values of x and y are

A. 8, 16
B. 10, 12
C. 9, 13
D. 8, 11

gate2004-cse digital-logic number-representation easy

Answer ☟

4.26.25 Number Representation: GATE CSE 2004 | Question: 28 top☝ ☛ https://gateoverflow.in/1025

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding?
(113. + −111.) + 7.51
113. + (−111. + 7.51)
A. 9.51 and 10.0 respectively
B. 10.0 and 9.51 respectively
C. 9.51 and 9.51 respectively
D. 10.0 and 10.0 respectively

gate2004-cse digital-logic number-representation normal

Answer ☟

© Copyright GATE Overflow. Some rights reserved.

 4.26.26 Number Representation: GATE CSE 2004 | Question: 66 top☝ ☛ https://gateoverflow.in/1060

Let A = 11111010 and B = 00001010 be two 8 − bit 2′ s complement numbers. Their product in 2′ s complement is
A. 11000100
B. 10011100
C. 10100101
D. 11010101

gate2004-cse digital-logic number-representation easy

Answer ☟

4.26.27 Number Representation: GATE CSE 2005 | Question: 16, ISRO2009-18, ISRO2015-2 top☝ ☛ https://gateoverflow.in/1352

The range of integers that can be represented by an n bit 2′ s complement number system is:

A. −2n−1 to (2n−1 − 1)

B. −(2n−1 − 1) to (2n−1 − 1)

C. −2n−1 to 2n−1

D. −(2n−1 + 1) to (2n−1 − 1)

gate2005-cse digital-logic number-representation easy isro2009 isro2015

Answer ☟

4.26.28 Number Representation: GATE CSE 2005 | Question: 17 top☝ ☛ https://gateoverflow.in/1353

The hexadecimal representation of (657)8 is:

A. 1AF
B. D78
C. D71
D. 32F

gate2005-cse digital-logic number-representation easy

Answer ☟

4.26.29 Number Representation: GATE CSE 2006 | Question: 39 top☝ ☛ https://gateoverflow.in/1815

We consider the addition of two 2′ s complement numbers bn−1 bn−2 … b0 and an−1 an−2 … a0 . A binary adder for adding
unsigned binary numbers is used to add the two numbers. The sum is denoted by cn−1 cn−2 … c0 and the carry-out by cout . Which
one of the following options correctly identifies the overflow condition?

A. cout (an−1 ⊕ bn−1 )

¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

¯¯¯¯¯¯ + ¯a ¯¯¯¯¯¯¯¯¯
B. an−1 bn−1 ¯c¯¯n−1 ¯¯¯¯¯¯¯¯¯b
n−1 n−1 cn−1
C. cout ⊕ cn−1
D. an−1 ⊕ bn−1 ⊕ cn−1

gate2006-cse digital-logic number-representation normal

Answer ☟

4.26.30 Number Representation: GATE CSE 2008 | Question: 6 top☝ ☛ https://gateoverflow.in/404

−−−−
Let r denote number system radix. The only value(s) of r that satisfy the equation √121r = 11r , is/are

A. decimal 10
B. decimal 11
C. decimal 10 and 11
D. any value > 2

© Copyright GATE Overflow. Some rights reserved.

 gate2008-cse digital-logic number-representation normal

Answer ☟

4.26.31 Number Representation: GATE CSE 2009 | Question: 5, ISRO2017-57 top☝ ☛ https://gateoverflow.in/1297

(1217)8 is equivalent to
A. (1217)16
B. (028F)16
C. (2297)10
D. (0B17)16

gate2009-cse digital-logic number-representation isro2017

Answer ☟

4.26.32 Number Representation: GATE CSE 2010 | Question: 8 top☝ ☛ https://gateoverflow.in/2179

P is a 16-bit signed integer. The 2's complement representation of P is (F87B)16 . The 2's complement representation of
8 × P is
A. (C3D8)16
B. (187B)16
C. (F878)16
D. (987B)16

gate2010-cse digital-logic number-representation normal

Answer ☟

4.26.33 Number Representation: GATE CSE 2013 | Question: 4 top☝ ☛ https://gateoverflow.in/1413

The smallest integer that can be represented by an 8 − bit number in 2′ s complement form is
A. −256
B. −128
C. −127
D. 0

gate2013-cse digital-logic number-representation easy

Answer ☟

4.26.34 Number Representation: GATE CSE 2014 Set 1 | Question: 8 top☝ ☛ https://gateoverflow.in/1766

The base (or radix) of the number system such that the following equation holds is____________.
312
20 = 13.1

gate2014-cse-set1 digital-logic number-representation numerical-answers normal

Answer ☟

4.26.35 Number Representation: GATE CSE 2014 Set 2 | Question: 8 top☝ ☛ https://gateoverflow.in/1961

Consider the equation (123)5 = (x8)y with x and y as unknown. The number of possible solutions is _____ .

gate2014-cse-set2 digital-logic number-representation numerical-answers normal

Answer ☟

4.26.36 Number Representation: GATE CSE 2015 Set 3 | Question: 35 top☝ ☛ https://gateoverflow.in/8494

© Copyright GATE Overflow. Some rights reserved.

 Consider the equation (43)x = (y3)8 where x and y are unknown. The number of possible solutions is _____

gate2015-cse-set3 digital-logic number-representation normal numerical-answers

Answer ☟

4.26.37 Number Representation: GATE CSE 2016 Set 1 | Question: 07 top☝ ☛ https://gateoverflow.in/39649

T h e 16 − bit 2′ s complement representation of an integer is 1111 1111 1111 0101 ; its decimal representation is
______________

gate2016-cse-set1 digital-logic number-representation normal numerical-answers

Answer ☟

4.26.38 Number Representation: GATE CSE 2016 Set 2 | Question: 09 top☝ ☛ https://gateoverflow.in/39546

Let X be the number of distinct 16-bit integers in 2′ s complement representation. Let Y be the number of distinct 16-bit
integers in sign magnitude representation Then X − Y is______.

gate2016-cse-set2 digital-logic number-representation normal numerical-answers

Answer ☟

4.26.39 Number Representation: GATE CSE 2017 Set 1 | Question: 9 top☝ ☛ https://gateoverflow.in/118289

When two 8-bit numbers A7 . . . A0 and B7 . . . B0 in 2's complement representation (with A0 and B0 as the least significant
bits) are added using a ripple-carry adder, the sum bits obtained are S7 . . . S0 and the carry bits are C7 . . . C0 . An overflow is said
to have occurred if

A. the carry bit C7 is 1

B. all the carry bits (C7 , . . . , C0 ) are 1
C. (A7 . B7 . S¯7 + A¯7 . B¯7 . S7 ) is 1
D. (A0 . B0 . S¯0 + A¯0 . B¯0 . S0 ) is 1

gate2017-cse-set1 digital-logic number-representation

Answer ☟

4.26.40 Number Representation: GATE CSE 2017 Set 2 | Question: 1 top☝ ☛ https://gateoverflow.in/118337

The representation of the value of a 16 − bit unsigned integer X in hexadecimal number system is BCA9. The representation
of the value of X in octal number system is
A. 571244
B. 736251
C. 571247
D. 136251

gate2017-cse-set2 digital-logic number-representation

Answer ☟

4.26.41 Number Representation: GATE CSE 2019 | Question: 22 top☝ ☛ https://gateoverflow.in/302826

Two numbers are chosen independently and uniformly at random from the set {1, 2, … , 13}.

The probability (rounded off to 3 decimal places) that their 4 − bit (unsigned) binary representations have the same most significant
bit is _______________.

gate2019-cse numerical-answers digital-logic number-representation probability

Answer ☟

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 4.26.42 Number Representation: GATE CSE 2019 | Question: 4 top☝ ☛ https://gateoverflow.in/302844

In 16-bit 2’s complement representation, the decimal number −28 is:

A. 1111 1111 0001 1100
B. 0000 0000 1110 0100
C. 1111 1111 1110 0100
D. 1000 0000 1110 0100

gate2019-cse digital-logic number-representation

Answer ☟

4.26.43 Number Representation: GATE CSE 2019 | Question: 8 top☝ ☛ https://gateoverflow.in/302840

Consider Z = X − Y where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid
overflow, the representation of Z would require a minimum of:
A. n bits
B. n − 1 bits
C. n + 1 bits
D. n + 2 bits

gate2019-cse digital-logic number-representation

Answer ☟

4.26.44 Number Representation: GATE CSE 2021 Set 1 | Question: 6 top☝ ☛ https://gateoverflow.in/357446

Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?
A. 15
B. 21
C. D2
D. 528

gate2021-cse-set1 digital-logic number-representation normal

Answer ☟

4.26.45 Number Representation: GATE CSE 2021 Set 2 | Question: 18 top☝ ☛ https://gateoverflow.in/357522

If x and y are two decimal digits and (0.1101)2 = (0.8xy5)10 , the decimal value of x + y is ___________

gate2021-cse-set2 numerical-answers digital-logic number-representation

Answer ☟

4.26.46 Number Representation: GATE IT 2004 | Question: 42 top☝ ☛ https://gateoverflow.in/3685

Using a 4 − bit 2′ s complement arithmetic, which of the following additions will result in an overflow?

i. 1100 + 1100
ii. 0011 + 0111
iii. 1111 + 0111

A. i only
B. ii only
C. iii only
D. i and iii only

gate2004-it digital-logic number-representation normal

Answer ☟

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 4.26.47 Number Representation: GATE IT 2004 | Question: 43 top☝ ☛ https://gateoverflow.in/3686

The number (123456)8 is equivalent to

A. (A72E) 16 and (22130232)4

B. (A72E) 16 and (22131122)4
C. (A73E) 16 and (22130232)4
D. (A62E) 16 and (22120232)4

gate2004-it digital-logic number-representation normal

Answer ☟

4.26.48 Number Representation: GATE IT 2005 | Question: 47 top☝ ☛ https://gateoverflow.in/3808

(34.4) 8 × (23.4) 8 evaluates to

A. (1053.6) 8
B. (1053.2) 8
C. (1024.2) 8
D. None of these

gate2005-it digital-logic number-representation normal

Answer ☟

4.26.49 Number Representation: GATE IT 2006 | Question: 7, ISRO2009-41 top☝ ☛ https://gateoverflow.in/3546

The addition of 4 − bit , two's complement, binary numbers 1101 and 0100 results in
A. 0001 and an overflow
B. 1001 and no overflow
C. 0001 and no overflow
D. 1001 and an overflow

gate2006-it digital-logic number-representation normal isro2009

Answer ☟

4.26.50 Number Representation: GATE IT 2007 | Question: 42 top☝ ☛ https://gateoverflow.in/3477

(C012.25)H − (10111001110.101)B =
A. (135103.412)o
B. (564411.412)o
C. (564411.205)o
D. (135103.205)o

gate2007-it digital-logic number-representation normal

Answer ☟

4.26.51 Number Representation: GATE IT 2008 | Question: 15 top☝ ☛ https://gateoverflow.in/3275

A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the
following two 2′ s complement numbers 01001101 and 11101001 . After the execution of this addition operation, the status of the
carry, overflow and sign flags, respectively will be:
A. 1, 1, 0
B. 1, 0, 0
C. 0, 1, 0
D. 1, 0, 1

gate2008-it digital-logic number-representation normal

© Copyright GATE Overflow. Some rights reserved.

 Answer ☟

Answers: Number Representation

4.26.1 Number Representation: GATE CSE 1988 | Question: 2-vi top☝ ☛ https://gateoverflow.in/91687

 −−
−
√41r = 710

Squaring both sides we get

41r = 4910

⟹ 4r + 1 = 10 × 4 + 9

⟹ 4r = 48

⟹ r = 12.
 23 votes -- kunal chalotra (13.6k points)

4.26.2 Number Representation: GATE CSE 1990 | Question: 1-viii top☝ ☛ https://gateoverflow.in/87055


The condition for overflow in the addition of two 2's complement numbers in terms of the carry generated by the two
most significant bits is when carry on MSB but not From MSB, or Carry from MSB but not on MSB. i.e.,

Cout ⊕ Cn−1 = 1.

i.e. For overflow to happen during addition of two numbers in 2's complement form

'
+C
They must have same sign and result is of opposite sign Overflow occurs if 1. (+A) + (+B) = −C 2.(−A) + (−B) =

PS: Overflow is useful for signed numbers and useless for unsigned numbers

 21 votes -- Prashant Singh (47.2k points)

4.26.3 Number Representation: GATE CSE 1991 | Question: 01-iii top☝ ☛ https://gateoverflow.in/500


The hex representation of given no. is (9753)16

Its binary representation is (1001011101010011)2

The no. of 1′ s is 9.
 38 votes -- Keith Kr (4.5k points)

4.26.4 Number Representation: GATE CSE 1991 | Question: 01-v top☝ ☛ https://gateoverflow.in/503


a3 a2 a1 a0
× b3 b2 b1 b0
a3 b0 a2 b0 a1 b0 a0 b0
a3 b1 a2 b1 a1 b1 a0 b1 −
a3 b2 a2 b2 a1 b2 a0 b2 − −
a3 b3 a2 b3 a1 b3 a0 b3 − − −
c7 c6 c5 c4 c3 c2 c1 c0

c1 = b1 a0 ⊕ a1 b0
 55 votes -- Pooja Palod (24.1k points)

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 4.26.5 Number Representation: GATE CSE 1992 | Question: 4-a top☝ ☛ https://gateoverflow.in/583


XOR of Cin with Cout of the MSB position.
 17 votes -- Amar Vashishth (25.2k points)

4.26.6 Number Representation: GATE CSE 1993 | Question: 6.5 top☝ ☛ https://gateoverflow.in/2286


A. 1 ∗ 22 + 1 ∗ 21 + 0 ∗ 20 + 1 ∗ 2 − 1 + 0 ∗ 2 − 2 + 1 ∗ 2 − 3 = 6.625
B. 1118 mod 16 = 14, quotient = 69

69 mod 16 = 5, quotient = 4
4 mod 16 = 4.
Writing the mods in the reverse order (in hex) gives (45E)H .

Both can be done using a calculator also.

 21 votes -- Arjun Suresh (332k points)

4.26.7 Number Representation: GATE CSE 1994 | Question: 2.7 top☝ ☛ https://gateoverflow.in/2474


−2n−1 ≤ N ≤ 2n−1 − 1
Example : Let us have 3 bit binary numbers (unsigned )
000 (010 ) to 111(710 ) total of 8(23 ) numbers.
But when we have one sign bit then we have half the number of negatives −4 to −1, 0 and 1 to 3.
bit pattern: 100 101 110 111 000 001 010 011

1's comp: -3 -2 -1 0 0 1 2 3

2's comp.: -4 -3 -2 -1 0 1 2 3

 26 votes -- Praveen Saini (41.9k points)

4.26.8 Number Representation: GATE CSE 1995 | Question: 18 top☝ ☛ https://gateoverflow.in/2655


A = 16 + N, ( for N = −1, A = 15 which is the largest value, for N = −8, A = 8)

B = REM

C = N /2
 7 votes -- Shaun Patel (6.1k points)

4.26.9 Number Representation: GATE CSE 1995 | Question: 2.12, ISRO2015-9 top☝ ☛ https://gateoverflow.in/2624


I suggest the following approach, here we can clearly see that numbers are getting multiplied by powers of 16. So this is
nothing but Hexadecimal number in disguise.

(3 × 4096 + 15 × 256 + 5 × 16 + 3) = (3F53)16 = (0011111101010011)2 which has total 2 + 4 + 2 + 2 = 10 1′ s

Correct Answer: C.
 77 votes -- Akash Kanase (36k points)

4.26.10 Number Representation: GATE CSE 1996 | Question: 1.25 top☝ ☛ https://gateoverflow.in/2729


Here, we are asked "magnitude" - so we just need to consider the mantissa bits.
Also, we are told "normalized representation"- so most significant bit of mantissa is always 1 (this is different from IEEE 754
normalized representation where this 1 is omitted in representation, but here it seems to be added on the right of decimal point as

© Copyright GATE Overflow. Some rights reserved.

 seen from options).
So, the maximum value of mantissa will be 23 1's where a decimal point is assumed before first 1. So, this value will be
1 − 2−23 .
Due to the 1 in normalized representation, the smallest positive number will be 1 followed by 23 0's which will be 2−1 = 0.5.
So ans d.
References

 46 votes -- Pooja Palod (24.1k points)

4.26.11 Number Representation: GATE CSE 1997 | Question: 5.4 top☝ ☛ https://gateoverflow.in/2255

 −−−−−
√(224)r = (13)r

Converting r base to decimal

−−−−−−−−−−−−−−
√2 × r2 + 2 × r + 4 = 1 × r + 3

Take square on both sides

2r2 + 2r + 4 = r2 + 6r + 9

⟹ r2 − 4r − 5 = 0

⟹ r2 − 5r + r − 5 = 0

⟹ (r − 5)(r + 1) = 0

r being a base, it can not be −1.

So, C. r = 5 is correct answer

 26 votes -- Praveen Saini (41.9k points)

4.26.12 Number Representation: GATE CSE 1998 | Question: 1.17 top☝ ☛ https://gateoverflow.in/1654


(3 4 2)8 = (011 100 010)2 = (11100010)2 .

If we treat this as an 8 bit integer, the first bit becomes sign bit and since it is "1", number is negative. 8085 uses 2's complement
representation for integers and hence the decimal equivalent will be −(00011110)2 = −30.

Correct Answer: D
 39 votes -- Arjun Suresh (332k points)

4.26.13 Number Representation: GATE CSE 1998 | Question: 2.20 top☝ ☛ https://gateoverflow.in/1693


I assume byte addressable memory- nothing smaller than a byte can be used.

We have four digits. So, to represent signed 4 digit numbers we need 5 bytes- 4 for four digits and 1 for the sign (like -7354). So,
required memory = 5 bytes

Now, if we use integer, the largest number needed to represent is 9999 and this requires 2 bytes of memory for signed
representation (one byte can represent only 256 unique integers).

(5−2) 3
So, memory savings while using integer is 5 = 5 = 60%

Correct Answer: C

© Copyright GATE Overflow. Some rights reserved.

  50 votes -- Arjun Suresh (332k points)

4.26.14 Number Representation: GATE CSE 1999 | Question: 2.17 top☝ ☛ https://gateoverflow.in/1495


A and C.
Sign Magnitude

+0 = 0000
−0 = 1000

1's complement

+0 = 0000
−0 = 1111

 26 votes -- neelansh (151 points)

4.26.15 Number Representation: GATE CSE 2000 | Question: 1.6 top☝ ☛ https://gateoverflow.in/629


2′ s complement representation is not same as 2′ s complement of a number. In 2′ s complement representation positive
integers are represented in its normal binary form while negative numbers are represented in its 2′ s complement form. So, (c) is
correct here.

http://www.ele.uri.edu/courses/ele447/proj_pages/divid/twos.html or archive
References

 58 votes -- Arjun Suresh (332k points)

4.26.16 Number Representation: GATE CSE 2000 | Question: 2.14 top☝ ☛ https://gateoverflow.in/661


Given 32 bits representation. So, the maximum precision can be 32 bits (In 32-bit IEEE representation, maximum
precision is 24 bits but we take the best case here). This means approximately 10 digits.
A = 2.0 × 1030 , C = 1.0
So, A + C should make the 31st digit to 1, which is surely outside the precision level of A (it is 31st digit and not 31st bit). So,
this addition will just return the value of A which will be assigned to Y .
So, Y + B will return 0.0 while X + C will return 1.0.
B choice.
Sample program if anyone wants to try:
#include<stdio.h>
int main()
{
float a = 2.0e30;
float b = -2.0e30;
float c = 1.0;
float y = a+c;
printf("a = %0.25f y = %0.25f\n",a, y);
y = y + b;
float x = a + b;
printf("x = %0.25f\n",x);
x = x + c;
printf("x = %0.25f\n",x);
}

 32 votes -- Arjun Suresh (332k points)

4.26.17 Number Representation: GATE CSE 2001 | Question: 2.10 top☝ ☛ https://gateoverflow.in/728

© Copyright GATE Overflow. Some rights reserved.

 
539 = 512 + 16 + 8 + 2 + 1 = 29 + 24 + 23 + 21 + 20
= (1000011011)2

Now all answers have 12 bits, so we add two 0's at beginning = (001000011011)2

To convert to 2's complement invert all bits till the rightmost 1, which will be (110111100101)2

= (110111100101)2
= (DE5)16
Correct Answer: C
 40 votes -- Arjun Suresh (332k points)

4.26.18 Number Representation: GATE CSE 2002 | Question: 1.14 top☝ ☛ https://gateoverflow.in/818


First Multiplication Iteration
Multiply 0.25 by 2
0.25 ∗ 2 = 0.50 (Product) Fractional part = 0.50 Carry = 0 (MSB)
Second Multiplication Iteration
Multiply 0.50 by 2
0.50 ∗ 2 = 1.00 (Product) Fractional part = 1.00 Carry = 1 (LSB)
The fractional part in the 2nd iteration becomes zero and hence we stop the multiplication iteration.
Carry from the 1st multiplication iteration becomes MSB and carry from 2nd iteration becomes LSB.
So the result is 0.01
Correct Answer: B.

 23 votes -- shekhar chauhan (32.8k points)

4.26.19 Number Representation: GATE CSE 2002 | Question: 1.15 top☝ ☛ https://gateoverflow.in/819


D) is the correct ans.In 2's complement representation, positive numbers are represented in simple binary form and
negative numbers are represented in its 2's complement form. So, for -15, we have to complement its binary value - 01111 and
add a 1 to it, which gives 10001. Option D.
 29 votes -- Ujjwal Saini (283 points)

4.26.20 Number Representation: GATE CSE 2002 | Question: 1.16 top☝ ☛ https://gateoverflow.in/821


(D) is the answer. Sign extension (filling the upper bits using the sign bit) is needed while increasing the number of bits
for representing a number. For positive numbers, 0 is extended and for negative numbers 1 is extended.

 28 votes -- gatecse (63.3k points)

4.26.21 Number Representation: GATE CSE 2002 | Question: 1.21 top☝ ☛ https://gateoverflow.in/826


(B) is the answer. When a positive value and negative value are added overflow never happens.
http://sandbox.mc.edu/~bennet/cs110/tc/orules.html
References

 40 votes -- Arjun Suresh (332k points)

© Copyright GATE Overflow. Some rights reserved.

 4.26.22 Number Representation: GATE CSE 2002 | Question: 9 top☝ ☛ https://gateoverflow.in/862


Here, mantissa is represented in normalized representation and exponent in excess-64 (subtract 64 to get actual value).
a. We have to represent −(7.5)10 = −(111.1)2 .
Now we are using base 16 for exponent. So, mantissa will be .01111 and this makes exponent as 1(4 bit positions and no hiding
first 1 as in IEEE 754 as this is not mentioned in question) which in excess-64 will be 64 + 1 = 65. Number being negative
sign bit is 1. So, we get


(1 01111000 … 0 1000001)2 = (BC000041)16
19 zeroes

b. Largest value will be with largest possible mantissa, largest possible exponent and positive sign bit. So, this will be all 1's
except sign bit which will be


0.111 … 1 × 16127−64 = (1 − 224 ) × 1663 = (1 − 2−24 ) × 1663
24 ones

( Again we did not add implicit 1 as in IEEE 754)

2x = 10y ⟹ y = log 2x = x log 2
So, (1 − 2−24 ) × 1663 = (1 − 10−24 log 2 ) × 1063 log 16 ≈ (1 − 10−7 ) × 1076 = 1076
Not directly relevant here, but a useful read: https://jeapostrophe.github.io/courses/2015/fall/305/notes/dist/reading/help-floating-
point.pdf
References

 34 votes -- Arjun Suresh (332k points)

4.26.23 Number Representation: GATE CSE 2003 | Question: 9 top☝ ☛ https://gateoverflow.in/900


MSB of 2's compliment number has a weight of - 2(n−1)
( Trick: (from reversing sign extension) just skip all leading 1's from MSB expect but 1, and then calculate the value as normal
signed binary rep. )
so by calculating, we get the given number is −5 in decimal. and options are

A. −25
B. −28
C. −41
D. −37

Therefore it is clear that −25 is divisible by −5 . so we can say that (A) is correct

 28 votes -- Nitin Sharma (2.2k points)

4.26.24 Number Representation: GATE CSE 2004 | Question: 19 top☝ ☛ https://gateoverflow.in/1016


Answer is D.

x × 7 + 3 = 5 × y + 4 ⟹ 7x = 5y + 1 .

Only option satisfying this is D.

 25 votes -- Aditi Dan (4k points)

4.26.25 Number Representation: GATE CSE 2004 | Question: 28 top☝ ☛ https://gateoverflow.in/1025


(113. + −111.) = 1.13 × 102 + −1.11 × 102 = 0.02 × 102 = 2.0 × 100
2.0 × 0 + 7.51 × 0 = 9.51 × 0

© Copyright GATE Overflow. Some rights reserved.

 2.0 × 100 + 7.51 × 100 = 9.51 × 100
(−111. + 7.51) = −1.11 × 102 + 7.51 × 100 = −1.11 × 102 + 0.08 × 102 = −1.03 × 102
113. + −1.03 × 102 = 1.13 × 102 + −1.03 × 102 = 0.1 × 102 = 10.0
Reference: https://www.doc.ic.ac.uk/~eedwards/compsys/float/
Correct Answer: A
References

 73 votes -- Arjun Suresh (332k points)

4.26.26 Number Representation: GATE CSE 2004 | Question: 66 top☝ ☛ https://gateoverflow.in/1060


A = 1111 1010 = −6
B = 0000 1010 = 10
A × B = −60 = 1100 0100

Correct Answer: A
 30 votes -- Digvijay (44.9k points)

4.26.27 Number Representation: GATE CSE 2005 | Question: 16, ISRO2009-18, ISRO2015-2 top☝ ☛ https://gateoverflow.in/1352


Total number of distinct numbers that can be represented using n bits = 2n .

In case of unsigned numbers these corresponds to numbers from 0 to 2n − 1.

In case of signed numbers in 1′ s complement or sign magnitude representation, these corresponds to numbers from
−(2n−1 − 1) to 2n−1 − 1 with 2 separate representations for 0.

In case of signed numbers in 2′ s complement representation, these corresponds to numbers from −2n−1 to 2n−1 − 1 with a
single representation for 0.
 4 votes -- Arjun Suresh (332k points)

4.26.28 Number Representation: GATE CSE 2005 | Question: 17 top☝ ☛ https://gateoverflow.in/1353

     


(657)8 = ( 110 101 111 )2 = ( 1 1010 1111)2 = (1AF) 16
6 5 7 1 A F

Correct Answer: A.
 17 votes -- Arjun Suresh (332k points)

4.26.29 Number Representation: GATE CSE 2006 | Question: 39 top☝ ☛ https://gateoverflow.in/1815


Number representation in 2's complement representation:

Positive numbers as they are

Negative numbers in 2′ s complement form.

So, the overflow conditions are

1. When we add two positive numbers (sign bit 0) and we get a sign bit 1
2. When we add two negative numbers (sign bit 1) and we get sign bit 0
3. Overflow is relevant only for signed numbers and carry is used for unsigned numbers
4. When the carryout bit and the carryin to the most significant bit differs

PS: When we add one positive and one negative number we won't get a carry. Also points 1 and 2 are leading to point 4.

© Copyright GATE Overflow. Some rights reserved.

 Now the question is a bit tricky. It is actually asking the condition of overflow of signed numbers when we use an adder which is
meant to work for unsigned numbers.
So, if we see the options, B is the correct one here as the first part takes care of case 2 (negative numbers) and the second part
takes care of case 1 (positive numbers) - point 4. We can see counterexamples for other options:
A - Let n = 4 and we do 0111 + 0111 = 1110 . This overflows as in 2′ s complement representation we can store only up to 7.
But the overflow condition in A returns false as cout = 0 .
C - This works for the above example. But fails for 1001 + 0001 = 1010 where there is no actual overflow (−7 + 1 = −6) ,
but the given condition gives an overflow as cout = 0 and cn−1 = 1 .
D - This works for both the above examples, but fails for 1111 + 1111 = 1110 (−1 + −1 = −2) where there is no actual
overflow but the given condition says so.
Reference: http://www.mhhe.com/engcs/electrical/hamacher/5e/graphics/ch02_025-102.pdf
Thanks, @Dilpreet for the link and correction.
References

 61 votes -- Digvijay (44.9k points)

4.26.30 Number Representation: GATE CSE 2008 | Question: 6 top☝ ☛ https://gateoverflow.in/404

 −−−−−
√(121)r = 11r
−−−−−−−−−−−−−−−−−−−−−−−
√(1 × r0 ) + (2 × r1 ) + (1 × r2 ) = (1 × r0 ) + (1 × r1 )
−−−−−−
√(1 + r)2 = 1 + r

1+r = 1+r
So any integer r satisfies this but r must be greater than 2 as we have 2 in 121 and radix must be greater than any of the
digits. (D) is the most appropriate answer

 43 votes -- Keith Kr (4.5k points)

4.26.31 Number Representation: GATE CSE 2009 | Question: 5, ISRO2017-57 top☝ ☛ https://gateoverflow.in/1297


Answer: (b)
Here are two different ways of solving this problem.
Short Method
Given number is in base 8 thus each digit can be represented in three binary bits to get overall binary equivalent.

(1217)8 = (001 010 001 111)2

I have written the equivalent in group of three bits for easy understanding of the conversion. We can rearrange them in group of
four to get equivalent hexadecimal number (in similar manner).

(001010001111)2 = (0010 1000 1111)2 = (28F )16

Long Method
In a nut shell the long method follow the following conversion

OCT → DEC → HEX

This procedure is good in a sense that the given option also have a decimal equivalent, and thereby might save some time (no in
this case, unfortunately).
Here is the the decimal equivalent

(1217)8 = (1 ∗ 83 + 2 ∗ 82 + 1 ∗ 81 + 7 ∗ 80 )10 = (655)10

© Copyright GATE Overflow. Some rights reserved.

 And we see that decimal equivalent is not in option therefore we proceed for hexadecimal conversion using division method.

(655)10 = (28F )16

Which we can find in given options.

HTH
References

 24 votes -- Prateek Dwivedi (3.5k points)

4.26.32 Number Representation: GATE CSE 2010 | Question: 8 top☝ ☛ https://gateoverflow.in/2179


Multiplication can be directly carried in 2's complement form. F87B = 1111 1000 0111 1011 can be left shifted 3 times
to give 8P = 1100 0011 1101 1000 = C3D8.

Or, we can do as follows:

MSB in (F87B) is 1. So, P is a negative number. So, P = -1 * 2's complement of (F87B) = -1 * (0785) = -1 * (0000 0111 1000
0101)

8 * P = -1 * (0011 1100 0010 1000) (P in binary left shifted 3 times)

In 2's complement representation , this equals, 1100 0011 1101 1000 = C3D8

Correct Answer: A
 68 votes -- Arjun Suresh (332k points)

4.26.33 Number Representation: GATE CSE 2013 | Question: 4 top☝ ☛ https://gateoverflow.in/1413


Range of 2's compliment no = > (−2n−1 ) to +(2n−1 − 1)

Here n = No of bits = 8.

So minimum no = −27 = (B) −128

 33 votes -- Akash Kanase (36k points)

4.26.34 Number Representation: GATE CSE 2014 Set 1 | Question: 8 top☝ ☛ https://gateoverflow.in/1766


Let ‘x’ be the base or radix of the number system .
3.x2 + 1.x1 + 2.x0
The equation is : = 1.x1 + 3.x0 + 1.x−1
2.x1 + 0.x0
3.x2 + x + 2
⟹ = x + 3 + 1/x
2.x
3.x2 + x + 2 x2 + 3x + 1
⟹ =
2.x x
⟹ 3.x2 + x + 2 = 2.x2 + 6x + 2
⟹ x2 + −5x = 0
⟹ x(x − 5) = 0
⟹ x = 0 or x = 5
As base or radix of a number system cannot be zero, here x = 5.

 41 votes -- vinodmits (363 points)

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 4.26.35 Number Representation: GATE CSE 2014 Set 2 | Question: 8 top☝ ☛ https://gateoverflow.in/1961


Converting both sides to decimal,

25 + 10 + 3 = x *y + 8

So, xy = 30

Possible pairs are (1, 30), (2, 15), (3, 10) as the minimum base should be greater than 8.
 42 votes -- Tejas Jaiswal (559 points)

4.26.36 Number Representation: GATE CSE 2015 Set 3 | Question: 35 top☝ ☛ https://gateoverflow.in/8494


(43)x = (y3)8

Since a number in base−k can only have digits from 0 to (k − 1) , we can conclude that: x ≥ 5 and y ≤ 7
Now, the original equation, when converted to decimal base gives:

4x1 + 3x0 = y(81 ) + 3(80 )

4x + 3 = 8y + 3

x = 2y

So, we have the following constraints:

x ≥ 5y ≤ 7x = 2yx, y are integers

The set of values of (x, y) that satisfy these constraints are:

(x , y)

(6 , 3)
(8 , 4)
(10, 5)
(12, 6)
(14, 7)

I am counting 5 pairs of values.

 52 votes -- Praveen Saini (41.9k points)

4.26.37 Number Representation: GATE CSE 2016 Set 1 | Question: 07 top☝ ☛ https://gateoverflow.in/39649


1111 1111 1111 0101
′
2 s complement of
1111 1111 1111 0101 =
0000 0000 0000 1011 =
+11
2′ s complement of
−11 =
+11 ,in
2′ s complement representation
2′ s complement of
+11 =
−11 , in
2′ s complement representation
So
−11 it should be

© Copyright GATE Overflow. Some rights reserved.

  34 votes -- Praveen Saini (41.9k points)

4.26.38 Number Representation: GATE CSE 2016 Set 2 | Question: 09 top☝ ☛ https://gateoverflow.in/39546


2's Complement Representation
The range of n − bit 2's Complement Numbers is −(2n−1 ) to +(2n−1 − 1)
For example, if n = 2 , then −2, −1, 0, 1 belong to the range(which are distinct)
In general 2n distinct integers are possible with n − bit 2′ s Complement Number → X
Sign Magnitude Representation
The range of n − bit Sign Magnitude numbers is −(2n−1 − 1) to +(2n−1 − 1)
For example, if n = 2 , then −1, −0, +0, +1 belong to the range in which −0 = +0 and both represent zero.
In general 2n − 1 distinct integers are possible with n − bit Sign magnitude representation → Y
X − Y = 2n − (2n − 1) = 1.

 37 votes -- Uzumaki Naruto (1.6k points)

4.26.39 Number Representation: GATE CSE 2017 Set 1 | Question: 9 top☝ ☛ https://gateoverflow.in/118289


Answer is (C)
Overflow is said to occur in the following cases

C7 C6 Overflow
0 0 NO
0 1 YES
1 0 YES
1 1 NO

The 3rd condition occurs in the following case A7B7S7', now the question arises how?

C7 C6
A7 1
B7 1
S7 0

NOW, A7 = 1 AND B7 = 1S7 = 0 is only possible when C6 = 0 otherwise S7 would become 1.

C7 has to be 1 (1 + 1 + 0 generates carry)
ON similar basis we can prove that C7 = 0 and C6 = 1 is produced by A7′ B7′ S7 . Hence, either of the two conditions cause
overflow. Hence(C).
Why not A? when C7 = 1 and C6 = 1 this doesn't indicate overflow ( 4th row in the table)
Why not B? if all carry bits are 1 then, C7 = 1 and C6 =1 (This also generates 4th row)
Why not D? These combinations are C0 and C1, the lower carrys do not indicate overflow

 36 votes -- (points)

4.26.40 Number Representation: GATE CSE 2017 Set 2 | Question: 1 top☝ ☛ https://gateoverflow.in/118337


Given: ( BCA9)16
1011 1100 1010 1001
For octal number system: grouping of three- three bits from right to left
1 011 110 010 101 001
1 3 6 2 5 1

© Copyright GATE Overflow. Some rights reserved.

 Answer: option D) (1 3 6 2 5 1)8

 22 votes -- Smriti012 (2.8k points)

4.26.41 Number Representation: GATE CSE 2019 | Question: 22 top☝ ☛ https://gateoverflow.in/302826


These are two groups:

1. MSB with 1
2. MSB with 0

nMSB0 = 7, nMSB1 = 6, ntotal = 13

Choose randomly and INDEPENDENTLY two elements out of 13 elements such that MSB is same.
nMSB1 ∗nMSB1 +nMSB0 ∗nMSB0
P= nTotal

7∗7+6∗6 85
P= 13∗13 = 169 = 0.5029

 39 votes -- Digvijay (44.9k points)

4.26.42 Number Representation: GATE CSE 2019 | Question: 4 top☝ ☛ https://gateoverflow.in/302844


(+28)10 = (0000 0000 00011100)2
−28 is nothing but 2s complement of +28 .

So, 2s complement of (0000 0000 0001 1100)2 is (1111 1111 1110 0100)2

(−28)10 = (1111 1111 1110 0100)2 . Answer is (C).

 28 votes -- Digvijay (44.9k points)

4.26.43 Number Representation: GATE CSE 2019 | Question: 8 top☝ ☛ https://gateoverflow.in/302840


Let X and Y represents 31 and −31 respectively in binary sign magnitude form. X and Y will take 6 bits as range of
sign magnitude form is − (2(n−1) − 1) to 2(n−1) − 1 ; where n is the number of bits.

Now in question Z = X − Y ,

Z = 31 − (−31) = 62

To represent 62 in sign magnitude form we need 7 (6 + 1) bits.

Hence, n + 1 bits needed.

Answer is C .
 36 votes -- DIVYANSHU SAXENA (421 points)

4.26.44 Number Representation: GATE CSE 2021 Set 1 | Question: 6 top☝ ☛ https://gateoverflow.in/357446


Firstly convert base 3 into a decimal number system(Base 10):
(210)3 = (x)10 ⟹ 0 ∗ 30 + 1 ∗ 31 + 2 ∗ 32 = (21)10
Now convert (21)10 into a hexadecimal system. dividing by 16 that is:
(21)10 = (z)16

© Copyright GATE Overflow. Some rights reserved.

 ∴ z = (15)16
Option A is correct.

 1 votes -- Hira (14.1k points)

4.26.45 Number Representation: GATE CSE 2021 Set 2 | Question: 18 top☝ ☛ https://gateoverflow.in/357522


Answer: 3
This conversion is just
1 1 1 8+4+1 13
2 + 4
+ 16 = 16 = 16 = 0.8125
On comparison we get x = 1 and y = 2. Hence, x + y = 3.

 3 votes -- witness_07 (145 points)

Answer = 3

A. (0.1)2 = (0.5)10
B. (0.01)2 = (0.25)10
C. (0.001)2 = (0.125)10
D. (0.0001)2 = (0.0625)10

A + B + D ⟹ (0.1101)2 = 0.8125

 7 votes -- JATIN MITTAL (2.1k points)

4.26.46 Number Representation: GATE IT 2004 | Question: 42 top☝ ☛ https://gateoverflow.in/3685


Only (ii) is the answer.
In 2′ s complement arithmetic, overflow happens only when

1. Sign bit of two input numbers is 0, and the result has sign bit 1
2. Sign bit of two input numbers is 1, and the result has sign bit 0.

Overflow is important only for signed arithmetic while carry is important only for unsigned arithmetic.
A carry happens when there is a carry to (or borrow from) the most significant bit. Here, (i) and (iii) cause a carry but only (ii)
causes overflow.
http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt
References

 39 votes -- Arjun Suresh (332k points)

© Copyright GATE Overflow. Some rights reserved.

 4.26.47 Number Representation: GATE IT 2004 | Question: 43 top☝ ☛ https://gateoverflow.in/3686

   


(123456)8 = (001 010 011 100 101 110)2 = (00 1010 0111 0010 1110 )2 = (A72E) 16
A 7 2 E
= (00 10 10 01 11 00 10 11 10)2 = (22130232)4

So, option (A).

 28 votes -- Arjun Suresh (332k points)

4.26.48 Number Representation: GATE IT 2005 | Question: 47 top☝ ☛ https://gateoverflow.in/3808


Simply convert (34.4)8 and (23.4)8 to decimal.

(34.4)8 = 28.5 in decimal and (23.4)8 = 19.5 in decimal.

28.5 × 19.5 = 555.75

Now convert 555.75 back to octal which is (1053.6)8

←
(34. 4⃗)8 to decimal
= 3 × 81 + 4 × 80 + 4 × 8−1
= 24 + 4 + 0.5
= (28.5)10
←
(23. 4⃗)8 to decimal
= 2 × 81 + 3 × 80 + 4 × 8−1
= 16 + 3 + 0.5
= (19.5)10

(28.5)10 × (19.5)10 = (555.75)10

Now,

(555.75)10 = (?)8

To convert the integer part

8 555
8 69 3
8 8 5
8 1 0
8 0 1 ↑

We get 1053.

To convert the decimal, keep multiplying by 8 till decimal part becomes 0.

 
0.75 × 8 → 6 . 00
keep the integral part 0 decimal part

∴ (555.75)10 = (1053.6)8

Correct Answer: A
 44 votes -- Afaque Ahmad (727 points)

© Copyright GATE Overflow. Some rights reserved.

 4.26.49 Number Representation: GATE IT 2006 | Question: 7, ISRO2009-41 top☝ ☛ https://gateoverflow.in/3546


Answer: C.

The addition results in 0001 and no overflow with 1 as carry bit.

In 2's complement addition Overflow happens only when:

Sign bit of two input numbers is 0, and the result has sign bit 1.
Sign bit of two input numbers is 1, and the result has sign bit 0.

 51 votes -- Rajarshi Sarkar (27.9k points)

4.26.50 Number Representation: GATE IT 2007 | Question: 42 top☝ ☛ https://gateoverflow.in/3477


(C012.25)H − (10111001110.101)B

= 1100 0000 0001 0010. 0010 0101

−0000 0101 1100 1110. 1010 0000

= 1011 1010 0100 0011. 1000 0101

= 1 011 101 001 000 011. 100 001 010

= (135103.412)o

Binary subtraction is like decimal subtraction:0 − 0 = 0, 1 − 1 = 0, 1 − 0 = 1, 0 − 1 = 1 with 1 borrow.

Correct Answer: A
 41 votes -- Arjun Suresh (332k points)

4.26.51 Number Representation: GATE IT 2008 | Question: 15 top☝ ☛ https://gateoverflow.in/3275


Answer: B
01001101
+11101001
-----------------
100110110
Carry = 1
Overflow = 0 (In 2′ s complement addition Overflow happens only when: Sign bit of two input numbers is 0, and the result has
sign bit 1 OR Sign bit of two input numbers is 1, and the result has sign bit 0.)
Sign bit = 0.

 39 votes -- Rajarshi Sarkar (27.9k points)

4.27 Pla (1) top☝

4.27.1 Pla: GATE CSE 1990 | Question: 4-i top☝ ☛ https://gateoverflow.in/85387

State whether the following statements are TRUE or FALSE with reason:

RAM is a combinational circuit and PLA is a sequential circuit.

gate1990 true-false digital-logic ram pla

Answer ☟

Answers: Pla

© Copyright GATE Overflow. Some rights reserved.

 4.27.1 Pla: GATE CSE 1990 | Question: 4-i top☝ ☛ https://gateoverflow.in/85387

Both the statements are false.

1. RAM is not a combinational circuit.For RAM, the input is the memory location selector and the operation (read or write)
and another byte (which can be input for write operation, or output for read operation), and the output is either a success
indicator (for write operation) or the byte at the selected location (for read operation). It does depend on past inputs, or
rather, on the past write operations at the selected byte. This is a Sequential logic circuit.​​
2. PLA is a combinational circuit as ROM & PAL. PLA is a programmable logic device with a programmable AND array
and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no
advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as
many unique terms as there are in the functions it will implement.

 11 votes -- vamsi2376 (2.8k points)

4.28 Prime Implicants (2) top☝

4.28.1 Prime Implicants: GATE CSE 1997 | Question: 5.1 top☝ ☛ https://gateoverflow.in/2252

Let f(x, y, z) = x̄ + ȳ x + xz be a switching function. Which one of the following is valid?

A. ȳ x is a prime implicant of f
B. xz is a minterm of f
C. xz is an implicant of f
D. y is a prime implicant of f

gate1997 digital-logic normal prime-implicants

Answer ☟

4.28.2 Prime Implicants: GATE CSE 2004 | Question: 59 top☝ ☛ https://gateoverflow.in/1054

Which are the essential prime implicants of the following Boolean function?
f(a, b, c) = a′ c + ac′ + b′ c
A. a′ c and ac′
B. a′ c and b′ c
C. a′ c only.
D. ac′ and bc′

gate2004-cse digital-logic normal prime-implicants

Answer ☟

Answers: Prime Implicants

4.28.1 Prime Implicants: GATE CSE 1997 | Question: 5.1 top☝ ☛ https://gateoverflow.in/2252


In sum of terms, any term is an implicant because it implies the function. So, xz is an implicant and hence C is the
answer. Still, lets see the other options.
If no minimization is possible for an implicant (by removing any variable) it becomes a prime implicant.
If a prime implicant is present in any possible expression for a function, it is called an essential prime implicant. (For example in
K-map we might be able to choose among several prime implicants but for essential prime implicants there won't be a choice).

© Copyright GATE Overflow. Some rights reserved.

 So, f = x′ + y ′ x + xz
= y ′ + x′ + z (could be also derived using algebraic rules as in http://www.ee.surrey.ac.uk/Projects/Labview/boolalgebra/ )
So, the prime implicants are x′ , y ′ and z. Being single variable ones and with no common variables, all must be essential also.
Now, a choice is false, as y ′ is a prime implicant and hence, y ′ x is just an implicant but not prime.
b choice - xz is not a minterm. A minterm must include all variables. So, xyz is a minterm so, is xy ′ z, but not xz.
d choice - y ′ is a prime implicant not y.

References

 33 votes -- Arjun Suresh (332k points)

4.28.2 Prime Implicants: GATE CSE 2004 | Question: 59 top☝ ☛ https://gateoverflow.in/1054


f(a, b, c) = a′ c + ac′ + b′ c
We can write these product of sum terms into canonical product of sum form.

     

f(a, b, c) = a′ b′ c + a′ bc + ab′ c′ + abc′ + ab′ c + a′ b′ c
001 011 100 110 101 001

f(a, b, c) = ∑(1, 3, 4, 5, 6)
Now, we can draw the k-map for these minterms.

Prime implicant of f is an implicant that is minimal - that is, the removal of any literal from product term results in a non-
implicant for f .
Essential prime implicant is an prime implicant that cover an output of the function that no combination of other prime
implicants is able to cover.

Prime implicants are: a′ c, b′ c, ab′ , ac′

Essential prime implicants are: a′ c, ac′ (green color) .
References:

http://dispert.international-university.eu/Digital_Design_Website_English/digital_2/dig002_5.html
http://web.cecs.pdx.edu/~mcnames/ECE171/Lectures/Lecture10.html

References

© Copyright GATE Overflow. Some rights reserved.

  14 votes -- Lakshman Patel (65.7k points)

4.29 Rom (4) top☝

4.29.1 Rom: GATE CSE 1993 | Question: 6.6 top☝ ☛ https://gateoverflow.in/2285

A ROM is used to store the Truth table for binary multiple units that will multiply two 4-bit numbers. The size of the ROM
(number of words × number of bits) that is required to accommodate the Truth table is M words × N bits . Write the values of M
and N.

gate1993 digital-logic normal rom descriptive

Answer ☟

4.29.2 Rom: GATE CSE 1996 | Question: 1.21 top☝ ☛ https://gateoverflow.in/2725

A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is
A. 256 × 16
B. 64K × 8
C. 4K × 16
D. 64K × 16

gate1996 digital-logic normal rom

Answer ☟

4.29.3 Rom: GATE CSE 2012 | Question: 19 top☝ ☛ https://gateoverflow.in/51

The amount of ROM needed to implement a 4 − bit multiplier is

A. 64 bits
B. 128 bits
C. 1 Kbits
D. 2 Kbits

gate2012-cse digital-logic normal rom

Answer ☟

4.29.4 Rom: GATE IT 2004 | Question: 10 top☝ ☛ https://gateoverflow.in/3651

What is the minimum size of ROM required to store the complete truth table of an 8 − bit × 8 − bit multiplier?
A. 32K × 16 bits
B. 64K × 16 bits
C. 16K × 32 bits
D. 64K × 32 bits

gate2004-it digital-logic normal rom

Answer ☟

Answers: Rom

4.29.1 Rom: GATE CSE 1993 | Question: 6.6 top☝ ☛ https://gateoverflow.in/2285


A is 4 bit binary no A4A3A2A1

© Copyright GATE Overflow. Some rights reserved.

 B is 4 bit binary no B4B3B2B1

M is result of multiplication M8M7M6M5M4M3M2M1 [check biggest no 1111 × 1111 = 11100001 ]

A4 A3 A2 A1 B4 B3 B2 B1 M8 M7 M6 M5 M4 M3 M2 M1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
1 1 1 1 1 1 1 0 1 1 0 1 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1

4 bits of A and 4 bits of B mean input will consist of 8 bits and need address 00000000 to 11111111 = 28 address

The output will be of 8 bits

So memory will be of 28 × 8

M = 256, N = 8
 22 votes -- Praveen Saini (41.9k points)

4.29.2 Rom: GATE CSE 1996 | Question: 1.21 top☝ ☛ https://gateoverflow.in/2725


When we multiply two 8 bit numbers result can go up to 16 bits. So, we need 16 bits for each of the multiplication result.
Number of results possible = 28 × 28 = 216 = 64 K as we need to store all possible results of multiplying two 8 bit numbers.
So, 64 K × 16 is the answer.

Correct Answer: D
 74 votes -- Arjun Suresh (332k points)

4.29.3 Rom: GATE CSE 2012 | Question: 19 top☝ ☛ https://gateoverflow.in/51


A ROM cannot be written. So, to implement a 4-bit multiplier we must store all the possible combinations of 24 × 24
inputs and their corresponding 8 output bits giving a total of 24 × 24 × 8 bits = 2048 bits. So, (D) is the answer.

PS: We are not storing the input bits explicitly -- those are considered in order while accessing the output 8 bits. In this way, by
storing all the possible outputs in order we can avoid storing the input combinations.

 55 votes -- Arjun Suresh (332k points)

4.29.4 Rom: GATE IT 2004 | Question: 10 top☝ ☛ https://gateoverflow.in/3651


Answer - B.

Multiplying 2 8 bit digits will give result in maximum 16 bits

Total number of multiplications possible = 28 × 28

Hence, space required = 64K × 16 bits

 25 votes -- Ankit Rokde (6.9k points)

4.30 Sequential Circuit (6) top☝

4.30.1 Sequential Circuit: GATE CSE 1987 | Question: 1-III top☝ ☛ https://gateoverflow.in/80034

© Copyright GATE Overflow. Some rights reserved.

 The above circuit produces the output sequence:
A. 1111 1111 0000 0000
B. 1111 0000 1111 0000
C. 1111 0001 0011 0101
D. 1010 1010 1010 1010

gate1987 digital-logic sequential-circuit flip-flop digital-counter

Answer ☟

4.30.2 Sequential Circuit: GATE CSE 1990 | Question: 5-c top☝ ☛ https://gateoverflow.in/85400

For the synchronous counter shown in Fig.3, write the truth table of Q0 , Q1 , and Q2 after each pulse, starting from
Q0 = Q1 = Q2 = 0 and determine the counting sequence and also the modulus of the counter.

gate1990 descriptive digital-logic sequential-circuit flip-flop digital-counter

Answer ☟

4.30.3 Sequential Circuit: GATE CSE 1991 | Question: 5-c top☝ ☛ https://gateoverflow.in/26442

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation
delay through each flip flop and each AND gate is 10 ns . Also, assume that the setup time for the JK inputs of the flip flops is
negligible.

© Copyright GATE Overflow. Some rights reserved.

 gate1991 digital-logic sequential-circuit flip-flop digital-counter

Answer ☟

4.30.4 Sequential Circuit: GATE CSE 1994 | Question: 2-1 top☝ ☛ https://gateoverflow.in/2468

The number of flip-flops required to construct a binary modulo N counter is __________

gate1994 digital-logic sequential-circuit flip-flop digital-counter fill-in-the-blanks

Answer ☟

4.30.5 Sequential Circuit: GATE CSE 2021 Set 1 | Question: 28 top☝ ☛ https://gateoverflow.in/357423

Consider a 3-bit counter, designed using T flip-flops, as shown below:

Assuming the initial state of the counter given by PQR as 000, what are the next three states?
A. 011, 101, 000
B. 001, 010, 111
C. 011, 101, 111
D. 001, 010, 000

gate2021-cse-set1 digital-logic sequential-circuit digital-counter

Answer ☟

4.30.6 Sequential Circuit: GATE1992-04-c top☝ ☛ https://gateoverflow.in/17408

Design a 3-bit counter using D-flip flops such that not more than one flip-flop changes state between any two consecutive
states.

gate1992 digital-logic sequential-circuit flip-flop digital-counter normal descriptive

Answer ☟

Answers: Sequential Circuit

4.30.1 Sequential Circuit: GATE CSE 1987 | Question: 1-III top☝ ☛ https://gateoverflow.in/80034


Let us suppose the initial output of all the JK flip flops is 1

So we can draw the below table to get the output Q3

© Copyright GATE Overflow. Some rights reserved.

 Index Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
Q2 Q′2 Q1 Q′1 Q0 Q′0 Q3 ⊕ Q2 J0′
0 1 1 1 1 1 0 1 0 1 0 0 1
1 1 1 1 0 1 0 1 0 0 1 0 1
2 1 1 0 0 1 0 0 1 0 1 0 1
3 1 0 0 0 0 1 0 1 0 1 1 0
4 0 0 0 1 0 1 0 1 1 0 0 1
5 0 0 1 0 0 1 1 0 0 1 0 1
6 0 1 0 0 1 0 0 1 0 1 1 0
7 1 0 0 1 0 1 0 1 1 0 1 0
8 0 0 1 1 0 1 1 0 1 0 0 1
9 0 1 1 0 1 0 1 0 0 1 1 0
10 1 1 0 1 1 0 0 1 1 0 0 1
11 1 0 1 0 0 1 1 0 0 1 1 0
12 0 1 0 1 1 0 0 1 1 0 1 0
13 1 0 1 1 0 1 1 0 1 0 1 0
14 0 1 1 1 1 0 1 0 1 0 1 0
1 1 1 1

From the above table Q3 that is output is 1111 0001 0011 0101

So the answer should be C.

 3 votes -- Digvijaysingh Gautam (6.3k points)

4.30.2 Sequential Circuit: GATE CSE 1990 | Question: 5-c top☝ ☛ https://gateoverflow.in/85400

Q0 Q1 Q2 Q0N Q1N Q2N

0 0 0 0 0 1
0 0 1 1 1 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 0 1 0

Q0N = Q0 ⟹ J0 = Q1 + Q2 , K0 = 1
Q1N = Q1 ⟹ J1 = Q2 , K1 = Q¯0
Q2N = Q2 ⟹ J2 = Q¯1 . Q¯0 , K2 = 1

0−1−6−2−4−0

© Copyright GATE Overflow. Some rights reserved.

 So, MOD 5 counter.

 25 votes -- Akash Dinkar (27.9k points)

4.30.3 Sequential Circuit: GATE CSE 1991 | Question: 5-c top☝ ☛ https://gateoverflow.in/26442


In a JK flip flop the output toggles when both J and K inputs are 1. So, we must ensure that with each clock the output
from the previous stage reaches the current stage.

' Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for
it to be latched correctly

It is given that setup time is negligible - means as soon as data is stable, the next clock can be given.

Time to get output from FF once input (and clock) is given = 10ns. (Propagation Delay)
Time for inputs to reach F F1 = 0. (Zero AND gate)
Time for inputs to reach F F2 = 10. (One AND gate)
Time for inputs to reach F F3 = 20. (Two AND gates)

So, minimum time period needed for clock is 10 + max(0, 10, 20) = 10 + 20 = 30ns which would mean a maximum clock
frequency of 1/30GHz = 33.33MHz

 88 votes -- Arjun Suresh (332k points)

4.30.4 Sequential Circuit: GATE CSE 1994 | Question: 2-1 top☝ ☛ https://gateoverflow.in/2468


Let say we have to design a mod-8 counter i.e 000 to 111. So we need 3 bits to represent i.e 3 FF.

For mod N : 2x = N

⟹ x = ⌈(log2 N)⌉
 27 votes -- Praveen Saini (41.9k points)

4.30.5 Sequential Circuit: GATE CSE 2021 Set 1 | Question: 28 top☝ ☛ https://gateoverflow.in/357423


From the given 3 state counter made from T flipflops, the next input sequence are as follows:

TP = R
¯¯¯¯
TQ = P
¯¯¯¯
TR = Q

Initial State Current input Next State

P Q R TP TQ TR P+ Q+ R+
0 0 0 0 1 1 0 1 1
0 1 1 1 1 0 1 0 1
1 0 1 1 0 1 0 0 0

In T flip flop for low input(0), the next state is Qn (current state) and for high input(1), it toggles/complements the present state
¯¯¯¯¯¯¯
(Qn )
011, 101, 000
Option A is correct.

 4 votes -- Hira (14.1k points)

4.30.6 Sequential Circuit: GATE1992-04-c top☝ ☛ https://gateoverflow.in/17408


State diagram will be as (remember concept of GRAY code)

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 State table and 3-bit synchronous counter with D FFs, will be as

Present State Next State FF Inputs

ABC ĀB̄C̄ DA DB DC
001 011 011
000 001 001
010 110 110
011 010 010
100 000 000
101 100 100
110 111 111

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  29 votes -- Praveen Saini (41.9k points)

4.31 Shift Registers (2) top☝

4.31.1 Shift Registers: GATE CSE 1987 | Question: 13-a top☝ ☛ https://gateoverflow.in/82607

The below figure shows four D-type flip-flops connected as a shift register using a XOR gate. The initial state and three
subsequent states for three clock pulses are also given.

State QA QB QC QD
Initial 1 1 1 1
After the first clock 0 1 1 1
After the second clock 0 0 1 1
After the third clock 0 0 0 1

The state QA QB QC QD after the fourth clock pulse is

A. 0000
1111

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 B. 1111
C. 1001
D. 1000

gate1987 digital-logic circuit-output sequential-circuit digital-counter shift-registers

Answer ☟

4.31.2 Shift Registers: GATE CSE 1991 | Question: 06,a top☝ ☛ https://gateoverflow.in/532

Using D flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input
lines:

i. Clock CLK
ii. Three parallel data inputs A, B, C
iii. Serial input S
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
iv. Control input load/SHIFT .

gate1991 digital-logic difficult sequential-circuit flip-flop shift-registers descriptive

Answer ☟

Answers: Shift Registers

4.31.1 Shift Registers: GATE CSE 1987 | Question: 13-a top☝ ☛ https://gateoverflow.in/82607


Option (D) 1000
QAn = QC ⊕ QD , QBn = QA , QCn = QB and QDn = QC

QA QB QC QD
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
1 0 0 0

 13 votes -- Prajwal Bhat (7.6k points)

4.31.2 Shift Registers: GATE CSE 1991 | Question: 06,a top☝ ☛ https://gateoverflow.in/532

Refer the Logic diagram for the parallel-in/serial-out SHIFT REGISTER, using D flip-flop gates that shifts data from left to
right in this video : https://youtu.be/7LmBcGiiYwk
 0 votes -- Pradip13 (17 points)

4.32 Static Hazard (1) top☝

4.32.1 Static Hazard: GATE CSE 2006 | Question: 38 top☝ ☛ https://gateoverflow.in/1814

Consider a Boolean function f(w, x, y, z) . Suppose that exactly one of its inputs is allowed to change at a time. If the function
happens to be true for two input vectors i1 = ⟨w1 , x1 , y1 , z1 ⟩ and i2 = ⟨w2 , x2 , y2 , z2 ⟩ , we would like the function to remain true
as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position) without becoming false momentarily. Let
f(w, x, y, z) = ∑(5, 7, 11, 12, 13, 15) . Which of the following cube covers of f will ensure that the required property is
satisfied?

A. ¯w
¯¯¯xz, wxȳ
¯¯, xȳ
¯¯z, xyz, wyz
B. wxy, ¯w ¯¯¯xz, wyz
C. wxȳ¯¯z̄¯¯, xz, wx̄¯¯yz
D. wxȳ¯¯, wyz, wxz, ¯w ¯¯¯xz, xȳ
¯¯z, xyz

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 gate2006-cse digital-logic min-sum-of-products-form difficult static-hazard

Answer ☟

Answers: Static Hazard

4.32.1 Static Hazard: GATE CSE 2006 | Question: 38 top☝ ☛ https://gateoverflow.in/1814


The question is indirectly asking for static-1 hazard in the circuit - that is output becoming 0 momentarily when it is
supposed to be 1.
Static 1 Hazard: Output going to 0 when it should remain 1

Happens in a 2 level SOP implementation.

Suppose only one AND gate (minterm) is 1 in an SOP implementation.
A variable in that minterm changes causing the output of that AND gate to become 0 and another AND gate to be 1.
Depending on the propagation delay of the gates, the output can momentarily become 0 before finalizing on 1. For
example, consider f = a′ b′ + ac and initially a = 0, b = 0, c = 1, so that output is 1. Now, if a changes to 1, again
output should be 1 due to ac term. But if a′ b′ turns to 0 before ac turns to 1, output can be momentarily 0 causing a static-
1 hazard.
Can be detected in a K-map if there are any adjacent 1's not covered by an implicant. i.e., to avoid static hazard, all
adjacent 1’s in a K-map must be covered by some implicant. In the below K-map, the implicant shown in green ensures no
static-1 hazard.

Here f(w, x, y, z) = ∑(5, 7, 11, 12, 13, 15)

So, K -map will be

So, its minimized sum of product expression will be xz + wxy ′ + wyz . Since all the minterms are overlapping, there is no
chance of static hazard here.
Now, let's consider the options one by one:
A. ¯w
¯¯¯xz, wxȳ
¯¯, xȳ
¯¯z, xyz, wyz

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 Chance of static hazard.
Here, when y changes from 0 to 1, the gate for wyz should give 1 (from earlier 0, assuming w = z = 1 ) and that of xy ′ z should
give 0 (from earlier 1). But there is a possibility of circuit giving 0 (static 1 hazard) momentarily due to gate delays ( xy ′ z coming
first and wyz coming later). In order to avoid this, we must add a gate with wxz also which ensure that all adjacent blocks in
K -map are overlapped or a single variable change cannot momentarily change the circuit output.
B. wxy, ¯w
¯¯¯xz, wyz

This is not correct as wxy is not a minterm for the given function
C. wxȳ¯¯z̄¯¯, xz, wx̄
¯¯yz

Here, also static- 1 hazard is possible as the middle 4 pairs are separated by 1 bit difference to both wxy ′ z ′ as well as wx′ yz .
Could have been avoided by using wxy ′ instead of wxy ′ z ′ and wyz instead of wx′ yz which will ensure that all neighboring
blocks are overlapped.
D. wxȳ¯¯, wyz, wxz, ¯w
¯¯¯xz, xȳ
¯¯z, xyz

These minterms cover all the minterms of f and also, all the neighboring 1's are overlapped by minterms. So, no chance of
hazard here, and hence is the required answer.
Correct Answer: D.

 56 votes -- minal (13.1k points)

4.33 Synchronous Asynchronous Circuits (4) top☝

4.33.1 Synchronous Asynchronous Circuits: GATE CSE 1991 | Question: 03-ii top☝ ☛ https://gateoverflow.in/516

Advantage of synchronous sequential circuits over asynchronous ones is:

A. faster operation

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 B. ease of avoiding problems due to hazards
C. lower hardware requirement
D. better noise immunity
E. none of the above

gate1991 digital-logic normal sequential-circuit synchronous-asynchronous-circuits multiple-selects

Answer ☟

4.33.2 Synchronous Asynchronous Circuits: GATE CSE 1998 | Question: 16 top☝ ☛ https://gateoverflow.in/1730

Design a synchronous counter to go through the following states:

1, 4, 2, 3, 1, 4, 2, 3, 1, 4 …

gate1998 digital-logic normal descriptive synchronous-asynchronous-circuits

Answer ☟

4.33.3 Synchronous Asynchronous Circuits: GATE CSE 2001 | Question: 2.12 top☝ ☛ https://gateoverflow.in/730

Consider the circuit given below with initial state Q0 = 1, Q1 = Q2 = 0 . The state of the circuit is given by the value
4 Q2 + 2 Q1 + Q0

Which one of the following is correct state sequence of the circuit?

A. 1, 3, 4, 6, 7, 5, 2
B. 1, 2, 5, 3, 7, 6, 4
C. 1, 2, 7, 3, 5, 6, 4
D. 1, 6, 5, 7, 2, 3, 4

gate2001-cse digital-logic normal synchronous-asynchronous-circuits

Answer ☟

4.33.4 Synchronous Asynchronous Circuits: GATE CSE 2003 | Question: 44 top☝ ☛ https://gateoverflow.in/935

A 1-input , 2-output synchronous sequential circuit behaves as follows:

Let zk , nk denote the number of 0′ s and 1′ s respectively in initial k bits of the input
(zk + nk = k) . The circuit outputs 00 until one of the following conditions holds.

zk − nk = 2 . In this case, the output at the k-th and all subsequent clock ticks is 10.
nk − zk = 2 . In this case, the output at the k-th and all subsequent clock ticks is 01.

What is the minimum number of states required in the state transition graph of the above circuit?
A. 5
B. 6
C. 7
D. 8

gate2003-cse digital-logic synchronous-asynchronous-circuits normal

Answer ☟

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 Answers: Synchronous Asynchronous Circuits

4.33.1 Synchronous Asynchronous Circuits: GATE CSE 1991 | Question: 03-ii top☝ ☛ https://gateoverflow.in/516


Synchronization means less chance of hazards but can only increase the delay. So, synchronous circuits cannot have
faster operation than asynchronous one but it is easier to avoid hazards in synchronous circuits. So, (A) is false and (B) is true.

(C) is false if we don't consider how to avoid the hazards in asynchronous circuits.

(D) Is not necessarily true - often asynchronous circuits have better noise immunity. Reasons are given
here: http://www.cs.columbia.edu/~nowick/async-applications-PIEEE-99-berkel-josephs-nowick-published.pdf

https://en.wikipedia.org/wiki/Asynchronous_circuit
References

 25 votes -- Arjun Suresh (332k points)

4.33.2 Synchronous Asynchronous Circuits: GATE CSE 1998 | Question: 16 top☝ ☛ https://gateoverflow.in/1730


Sequence given is as
1, 4, 2, 3, 1 …
From the given sequence of states we can design the state table and Suppose we are using T-FF for sequential circuit of counter.

Present State Next State FF Inputs

A B C A+ B+ C + TA TB TC
0 0 0 x x x x x x
0 0 1 1 0 0 1 0 1
0 1 0 0 1 1 0 0 1
0 1 1 0 0 1 0 1 0
1 0 0 0 1 0 1 1 0
1 0 1 x x x x x x
1 1 0 x x x x x x
1 1 1 x x x x x x

From the above table, we will find the equation of TA , TB and TC

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  22 votes -- Praveen Saini (41.9k points)

4.33.3 Synchronous Asynchronous Circuits: GATE CSE 2001 | Question: 2.12 top☝ ☛ https://gateoverflow.in/730

Q0 = Q1prev ⊕ Q2prev Q1 = Q0prev Q2 = Q1prev

1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
1 0 0

State = 4Q2 + 2Q1 + Q0

So, state sequence = 1, 2, 5, 3, 7, 6, 4

Correct Answer: B
 41 votes -- Arjun Suresh (332k points)

4.33.4 Synchronous Asynchronous Circuits: GATE CSE 2003 | Question: 44 top☝ ☛ https://gateoverflow.in/935


Though the question is from digital logic, the answer is purely from automata. As per the question, we just need to count
the difference of the number of 0′ s and 1′ s in the first k bit of a number. And we just need to count till this count reaches 2 or −2
(negative when the number of 0′ s is less than the number of 1′ s ). So, the possibilities are −2, −1, 0, 1 and 2 which represents
the five states of the state transition diagram.

For state −2 , the output of the circuit will be 01, for state 2, the output will be 10 (both these states not having any outgoing
transitions) and for other 3 states, the output will be 00 as per the given description of the circuit.

Correct Answer: A
 59 votes -- gatecse (63.3k points)

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 The Automaton will look like this. 

 97 votes -- Rajendra Kumar Dangwal (1.2k points)

Answer Keys

4.1.1 N/A 4.1.2 N/A 4.1.3 N/A 4.1.4 B 4.1.5 B

4.1.6 A 4.1.7 B 4.1.8 19.2 4.1.9 B 4.1.10 -1

4.2.1 B 4.2.2 C 4.3.1 C 4.3.2 A 4.4.1 D

4.4.2 C 4.4.3 N/A 4.4.4 N/A 4.4.5 N/A 4.4.6 D

4.4.7 N/A 4.4.8 A 4.4.9 B 4.4.10 D 4.4.11 C

4.4.12 D 4.4.13 C 4.4.14 C 4.4.15 D 4.4.16 D

4.4.17 D 4.4.18 A 4.4.19 A 4.4.20 D 4.4.21 D

4.4.22 B 4.4.23 1 4.4.24 A 4.4.25 C 4.4.26 C

4.4.27 D 4.4.28 B 4.4.29 B;C;D 4.4.30 B 4.4.31 C

4.5.1 N/A 4.5.2 A 4.5.3 B 4.5.4 A 4.5.5 C

4.5.6 B 4.6.1 A 4.6.2 C 4.6.3 A 4.6.4 3

4.6.5 A 4.6.6 3 4.6.7 B 4.7.1 A 4.7.2 B

4.8.1 N/A 4.8.2 C 4.8.3 N/A 4.8.4 N/A 4.8.5 A;C

4.8.6 B 4.8.7 B 4.8.8 B 4.8.9 011 4.8.10 D

4.8.11 N/A 4.8.12 N/A 4.8.13 B 4.8.14 B 4.8.15 A

4.8.16 A 4.8.17 A 4.8.18 D 4.8.19 A 4.8.20 A

4.8.21 D 4.8.22 A 4.8.23 C 4.8.24 C 4.8.25 C

4.8.26 A 4.8.27 A 4.8.28 B 4.8.29 D 4.8.30 B

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 4.8.31 C 4.8.32 C 4.8.33 X 4.8.34 D 4.8.35 C

4.8.36 A 4.8.37 D 4.8.38 B 4.9.1 A 4.10.1 C

4.10.2 1034 4.11.1 B;C 4.11.2 N/A 4.11.3 N/A 4.11.4 D

4.11.5 D 4.11.6 A 4.11.7 C 4.12.1 N/A 4.12.2 N/A

4.12.3 A 4.12.4 C 4.12.5 D 4.12.6 3 4.12.7 4

4.12.8 B 4.12.9 D 4.12.10 D 4.13.1 D 4.14.1 D

4.14.2 C 4.15.1 N/A 4.15.2 C 4.15.3 A 4.15.4 B

4.15.5 2 4.15.6 D 4.16.1 C 4.16.2 N/A 4.16.3 N/A

4.16.4 N/A 4.16.5 N/A 4.16.6 C 4.16.7 D 4.16.8 D

4.16.9 B 4.17.1 N/A 4.17.2 N/A 4.17.3 B;C 4.17.4 A

4.18.1 D 4.18.2 B 4.18.3 A 4.18.4 C 4.18.5 -7.75 : -7.75

4.18.6 C 4.18.7 C 4.19.1 D 4.19.2 N/A 4.19.3 N/A

4.19.4 N/A 4.19.5 N/A 4.19.6 C 4.19.7 C 4.19.8 B

4.19.9 D 4.19.10 A 4.19.11 B 4.19.12 C 4.19.13 A

4.19.14 B 4.19.15 1 4.19.16 A 4.19.17 D 4.19.18 A

4.19.19 C 4.20.1 A;D 4.21.1 C 4.21.2 B 4.21.3 C

4.22.1 N/A 4.22.2 B 4.22.3 B 4.22.4 B 4.23.1 N/A

4.23.2 A 4.24.1 N/A 4.24.2 N/A 4.24.3 9 4.24.4 N/A

4.24.5 A 4.24.6 B 4.24.7 B 4.24.8 A 4.24.9 A

4.24.10 B 4.24.11 3 4.24.12 6:6 4.24.13 A 4.25.1 B

4.25.2 N/A 4.25.3 C 4.25.4 C 4.25.5 C 4.25.6 A

4.25.7 C 4.25.8 D 4.25.9 5 4.25.10 A 4.25.11 D

4.25.12 A 4.25.13 N/A 4.26.1 12 4.26.2 N/A 4.26.3 9

4.26.4 N/A 4.26.5 N/A 4.26.6 N/A 4.26.7 N/A 4.26.8 N/A

4.26.9 C 4.26.10 D 4.26.11 C 4.26.12 D 4.26.13 C

4.26.14 A;C 4.26.15 C 4.26.16 B 4.26.17 C 4.26.18 B

4.26.19 D 4.26.20 D 4.26.21 B 4.26.22 N/A 4.26.23 A

4.26.24 D 4.26.25 A 4.26.26 A 4.26.27 A 4.26.28 A

4.26.29 B 4.26.30 D 4.26.31 B 4.26.32 A 4.26.33 B

4.26.34 5 4.26.35 3 4.26.36 5 4.26.37 -11 4.26.38 1

4.26.39 C 4.26.40 D 4.26.41 0.502 : 0.504 4.26.42 C 4.26.43 C

4.26.44 A 4.26.45 3:3 4.26.46 B 4.26.47 A 4.26.48 A

4.26.49 C 4.26.50 A 4.26.51 B 4.27.1 False 4.28.1 C

4.28.2 A 4.29.1 N/A 4.29.2 D 4.29.3 D 4.29.4 B

4.30.1 C 4.30.2 N/A 4.30.3 33.33 4.30.4 N/A 4.30.5 A

4.30.6 N/A 4.31.1 D 4.31.2 N/A 4.32.1 D 4.33.1 B

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