COUNTERS

INTRODUCTION
‰In this chapter we will look at how FFs and logic
gates can be combined to produce different types
of counters .
‰We will present several practical applications to
illustrate the many ways in which these logic
circuits can be used in digital systems.
‰We will also look at several of the numerous
counters that are available as ICs.
‰An understanding of the material in this chapter is a
good indication that the principles of the preceding
chapters have been mastered.
Asynchronous
Counter
 ASYNCHRONOUS INPUTS PRESET
‰ For the clocked Flip-Flop that we
have been studying, the S, R, J, K Q
and D inputs have been referred to
as control inputs.
‰ These inputs are also called
synchronous inputs, because their
effect on the FF output is Q
synchronized with the CLK input.
‰ As we have seen, the synchronous CLEAR
control input must be used in
conjunction with a clock signal to
trigger the FF. PRESET CLEAR
‰ Most clocked FFs also have one or FF Response
more asynchronous inputs, which 1 1 Clocked
operate independently of the
synchronous inputs and clock operation*
input. 0 1 Q=1
‰ These asynchronous inputs can be
used to set the FF to the 1 state or 1 0 Q=0
clear the FF to the 0 state at O 0 Not used
anytime, regardless of the
conditions at the other inputs. *Q will respond to J,K
and CLK
Internal Circuitry of the Edge-Triggered
J-K Flip-Flop

SET

Q
RESET
Internal Circuitry of the Edge-Triggered J-K
Flip-Flop with ASYNCHRONOUS INPUTS

PRESET

CLEAR
4-bit Asynchronous Counter

A B C D
D C B A Number of
clock pulses
0 0 0 0 0
A B C D
0 0 0 1 1
0 0 1 0 2
The normal output of FF A acts as the
0 0 1 1 3
CLK input for FF B
0 1 0 0 4
0 1 0 1 5 The normal output of FF B acts as the
0 1 1 0 6 CLK input for FF C
0 1 1 1 7
The normal output of FF C acts as the
1 0 0 0 8
CLK input for FF D
1 0 0 1 9
1 0 1 0 10 All FFs toggle at
1 0 1 1 11 the same time
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
0 0 0 0 16 (Recycles)
0 0 0 1 17
 Important point regarding
Asynchronous Counter
2 This type of counter, where each FF output serves as
the CLK input signal for the next FF, is referred to as an
asynchronous counter.
2 This is because all the FFs do not change states in exact
synchronism with the clock pulses;
2 Only flip- flop A responds to the clock pulses.
2 Flip- flop B has to wait for flip-flop A to change states
before it is toggled.
2 Flip-flop C has to wait for flop-flop B; and so on.
2 Thus, there is a delay between the responses of
consecutive FFs.
2 In modern FFs this delay may be very small (typically 10
to 40 ns), but in some cases, it can be troublesome.
2 Because of the manner in which this type of counter
operates, it is also commonly referred to as a ripple
counter.
 MOD Number
‰ The MOD number is always equal to the number of
states which the counter goes through in each complete
cycle before it recycles back to its starting state.
‰ The MOD number can be increased simply by adding
more FFs to the counter.

‰ That is, MOD number = 2N

where N is the number of FFs connected in the
arrangement of preceding figure.
 FRREQUENCY DIVISION
ƒ Each FF divides the frequency of its input by 2
ƒ In general, for any counter the output from the last
FF (i.e., the MSB) divides the input clock frequency
by the MOD number of the counter.
ƒ A MOD –8 counter could also be called a divide-by-8
counter.
ƒ N flip-flops would produce an output frequency from
the last FF which is equal to 1 N of the input
2
frequency
f in
f out =
Mod − N
 * All J & K inputs
are HIGH

Input CLK CLK CLK

clock
signal
A B C

1
T1 =
fin

1
2T1 =
2fin

1
4T1 =
4fin

1
8T1 =
8fin
 COUNTERS WITH MOD NUMBERS < 2N
‰ The basic ripple counter of figure above is limited to
MOD numbers that are equal to 2N, where N is the
number of FFs.
‰ This value is actually the maximum MOD number
that can be obtained using N flip-flops.
‰ The basic counter can be modified to produce MOD
numbers less than 2N by allowing the counter to skip
states that are normally part of the counting
sequence.
‰ Let us see as example Mod-6 asynchronous counter.
‰ Therefore, the counting sequence is,
Mod-6 Asynchronous up-counter

C B A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0 Temporary states to be
cleared
Mod-6 up-counter

A B C

B
C
 Wave forms
Input 1 2 3 4 5 6 7 8 9 10 11 12
pulses

0 1 0 1 0 1 0

0 0 1 1 0 0 0
Attempt to be
HIGH
0 0 0 0 1 1 0

LOW
 Changing the MOD Number
‰ The counter of Figure above is a MOD-6 counter because of the choice of inputs to the
NAND gate.
‰ Any desired MOD number could be obtained by changing these inputs.
‰ For example, using a three input NAND gate with inputs A, B, and C, the counter would
function normally until the 111 condition was reached, at which point it would
immediately reset to the 000 state.
‰ Ignoring the temporary excursion into the 111 state, the counter would go from 000
through 110 and then recycle back to 000, resulting in a MOD-7 counter (seven states).
GENERAL PROCEDURE
‰ To construct a counter that starts counting from all 0s and has a MOD number of X:
‰ Find the smallest number of FFs such that 2N ≥ X and connect them as a counter. If
2N =X, do not do steps 2 and 3.
‰ Connect a NAND gate output to the asynchronous CLEAR inputs of all the FFs.
‰ Determine which FFs will be in the HIGH state at a count = X; then connect the
normal outputs of these FFs to the NAND gate inputs.
 DECADE COUNTERS/ BCD COUNTERS
‰ The MOD –10 counter is also referred to as a decade counter.
‰ In fact, a decade counter is any counter that has 10 distinct states, no matter what
the sequence.
‰ A decade counter such as the one in figure below, which counts in sequence from
0000(zero) through 1001(decimal 9), is also commonly called a BCD counter;
because it uses only the 10 BCD code groups 0000,0001, …, 1000, and 1001.
‰ To reiterate, any MOD-10 counter is a decade counter; and any decade counter that
counts in binary from 0000 to 1001 is a BCD counter.
‰ Decade counters, especially the BCD type, find widespread use in applications
where pulses or events are to be counted and the results displayed on some type
of decimal numerical readout.
‰ A decade counter is also often used for dividing a pulse frequency exactly by 10.
‰ The input pulses are applied to flip-flop D, which has one-tenth the frequency of
the input.
DECADE COUNTERS/ BCD COUNTERS

A B C D

B
D
 ASYNCHRONOUS DOWN COUNTER
‰ All the counters we have looked at thus far have counted
upward from zero; that is, they were up counters.
‰ It is a relatively simple matter to construct asynchronous
(ripple) down counters, which will count downward from a
maximum count to zero.
‰ There are three options how to modify UP counter to DOWN
counter.
‰ Simply, by taking the inverted output of each FF as the output of the
counter.
‰ By connecting INVERTER between the normal output and the CLK
input of the next FF there by changing the CLK signal from NGT to
PGT.
‰ By connecting the inverted output of each FF to the CLK of the next FF
there by changing the CLK signal from NGT to PGT and taking the
output from normal output
 Comparison of
Down Counter Vs UP
DOWN UP
C B A C B A
1 1 1 0 0 0
1 1 0 0 0 1
1 0 1 0 1 0
1 0 0 0 1 1
0 1 1 1 0 0
0 1 0 1 0 1
0 0 1 1 1 0
0 0 0 1 1 1
DOWN Counter is the complement of UP Counter
Asynchronous 3-bit Down Counter

A B C
Asynchronous 3-bit Down Counter
 FOUR-BIT RIPPLE UP/DOWN COUNTER
‰ As the name indicates an up/down counter is a counter
which can count both in upward and downward
directions.
‰ An up/down counter is also called a forward/ backward
counter or a bidirectional counter.
‰ So, a control signal or a mode signal M is required to
choose the direction of count.
‰ When M = 1 for up counting, QA is transmitted to clock of
FF2, QB to FF3 and QC to FF4 and
‰ similarly when M = 0 for down counting, QA, is transmitted
to clock of FF2, QB to FF2, and QC to FF3.
‰ This is achieved by using two AND gates and one OR
gate at each stage of transmissions as shown in Figure
below.
‰ The external clock signal is applied to FF1.
FOUR-BIT RIPPLE UP/DOWN COUNTER

QA QB QC QD

Clock signal to FF2 = (QA ⋅ M ) + ( QA ⋅ M )

Clock signal to FF3 = (Q B ⋅ M ) + ( QB ⋅ M )

Clock signal to FF4 = (QC ⋅ M) + ( QC ⋅ M )

PROPAGATION DELAY IN RIPPLE COUNTERS
‰ Ripple counters are the simplest type of binary counters,
since they require fewest components to produce a given
counting operation.
‰ They do, however, have one major drawback, which is
caused by their basic principle of operation.
‰ Each FF is triggered by the transition at the output of the
preceding FF.
‰ Because of the inherent propagation delay time (tpd) of
each FF,
‰ this means that the second FF will not respond until a time tpd
after the first FF receives an active clock transition;
‰ the third FF will not respond until a time equal to 2 x tpd after
that clock transition; and so on.
‰ In other words, the propagation delays of the FFs
accumulate so that the Nth FF cannot change states until
a time equal to N x tpd after the clock transition occurs.
‰ This is illustrated in Figure 6.8, where the waveforms for
a 3-bit ripple counter shown.
‰ The first set of waveforms in Figure
6.8(a) shows a situation where an
input pulse occurs every 1000 ns (the
clock period T = 1000 ns) and it is
assumed that each FF has a
propagation delay of 50 ns (tpd =50
ns).
‰ Notice that the A Flip-Flop output
toggles 50 ns after the NGT of each
input pulse. Similarly, B toggles 50 ns
after A goes from 1 to 0, and C
toggles 50 ns after B goes from 1 to
0.
‰ As a result, when the fourth input
pulse occurs, the C output goes 6.8(a)
HIGH after a delay of 150 ns.
‰ In this situation the counter does
operate properly in the sense that the
FFs do eventually get to their correct
states, representing the binary count.
‰ However, the situation worsens if
the input pulses are applied at a
much higher frequency.
‰ The waveforms in Figure 3(b) show what
happens if the input pulses occur one every 100
ns.
‰ Again, each FF output responds 50 ns after the
1-to-0 transition at its CLK input (note the
change in the relative time scale).
‰ Of particular interest is the situation after the
falling edge of the fourth input pulse, where the
C output does not go HIGH until 150 ns later,
which is the same time that the A Output goes
HIGH in response to the fifth input pulse.
‰ In other words, the condition C = 1, B =A=0
(count of 100) never appears, because the input
frequency is too high.
‰ This could cause a serious problem if this
condition were supposed to be used to control
some other operation in a digital system.
6.8(b)
‰ Problems such as this can be avoided if the
period between input pulses is made longer Figure 6.8 Waveforms of 3-bit ripple counter
than the total propagation delay of the counter. illustrating effects of FF propagation delays
That is, T ≥ N×t for different input pulse frequencies
clock pd

where N = number of FFs.

‰ Stated in terms of input-clock frequency, the
maximum frequency that can be used is given
by 1
f max =
N × t pd
 SYNCHRONOUS (PARALLEL) COUNTERS
Limitation of asynchronous Counter
‰ The problems encountered with ripple counters are caused by the
accumulated FF propagation delays.
‰ Stated another way, the FFs do not all change states simultaneously in
synchronism with the input pulses.
‰ These limitations can be overcome with the use of synchronous or parallel
counters in which all the FFs are triggered simultaneously (in parallel) by
the clock-input pulses.
‰ Since the input pulses are applied to all the FFs, some means must be used
to control when a FF is to toggle and when it is to remain unaffected by a
clock pulse.
‰ Only flip-flop A, the LSB, has its J and K inputs permanently at the HIGH
level the J, K inputs of the other FFs are driven by some combination of FF
outputs.
 Circuit Operation
‰ The J and K inputs of the FFs are connected so that only those FFs that are
supposed to toggle on a given NGT will have J=K=1 when that occurs.
‰ The counting sequence shows that the A flip-flop has to change states at
each NGT.
‰ For this reason its J and K inputs are permanently HIGH so that it will
toggle on each NGT of the clock input.
‰ Flip-flop B has to change states on each NGT that occurs while A =1.
‰ This operation is accomplished by connecting output A to the J and K inputs
of flip-flop B so that J=K=1 only when A=1.
‰ Flip-flop C has to change states on each NGT that occurs while A=B=1.
‰ This operation is ensured by connecting the signal AB to the J and K inputs
of flip-flop C.
‰ In the like manner; we can see that flip-flop D has to toggle on each NGT
that occurs while A=B=C=1.
‰ This is accomplished by connecting ABC to the J and K inputs of flip-flop D.
Counting sequence of 4-bit synchronous UP counter
Count D C B A
0 0 0 0 0
1 0 0 0 1 When A=1; B is ready to toggle
2 0 0 1 0
3 0 0 1 1 When A=B=1; B and C are ready to toggle
4 0 1 0 0
5 0 1 0 1 When A=1; B is ready to toggle
6 0 1 1 0
7 0 1 1 1 When A=B=C=1; B, C & D are ready to toggle
8 1 0 0 0
9 1 0 0 1 When A=1; B is ready to toggle
10 1 0 1 0
11 1 0 1 1 When A=B=1; B and C are ready to
12 1 1 0 0 toggle
13 1 1 0 1 When A=1; B is ready to toggle
14 1 1 1 0
15 1 1 1 1 When A=B=C=D=1; All FFs are ready to toggle
0 0 0 0 0
4-bit Synchronous UP counter
ABC
AB

A B C D
 Advantage of Synchronous
Counters over Asynchronous
1. In a parallel counter all the FFs will change states
simultaneously; that is, they are all synched to the NGTs of the
input clock pulses. Thus, unlike the asynchronous counters, the
propagation delays of the FFs do not add together to produce
the overall delay.
2. Instead the total response time of a synchronous counter like
the one in figure above is the time it takes one FF to toggle plus
the time for the new logic levels to propagate through a single
AND gate to reach the J, K inputs. That is
Total delay = FF tpd + AND gate tpd
3. This total delay is the same no matter how many FFs are in the
counter; and it will generally be much lower than an
asynchronous counter with the same number of FFs.
4. As such, a synchronous counter can operate at a much higher
input frequency. Of course, the synchronous counter has more
complex circuitry than that of the asynchronous counter.
 CASCADING OF RIPPLE COUNTERS
9 Ripple counters can be connected in cascade to
increase the modulus of the counter.
9 Cascaded means connecting the Q output of one FF to
clock input of the next
9 A Mod-M and a Mod-N counter in cascade give a Mod-MN
counter.
(a) Examples of counters in cascaded
9 While cascading, the most significant stage of the first
counter is connected to the toggling stage of the
second counter. Some examples of counters in cascade
are shown in Figure (a).
9 The order of cascading does not affect the frequency
division, however, the duty cycle of the most
significant output may depend on the order in which QA QB QA QB QC
the counters are cascaded.
9 Mod counters are often constructed by cascading lower
modulus counters because of the availability of certain (b) Logic diagram of cascaded ripple counters
standard modulus counters in IC form.
9 Figure (b) shows the logic diagram of cascaded ripple
counters.