MB91570 Series

32-bit Microcontroller
MB91F575B/F575BS/F575BH/F575BHS/F575C/
F575CS/F575CH/F575CHS
MB91F577B/F577BS/F577BH/F577BHS/F577CS/
F577CH/F577CHS
MB91F578C(M)/F578CS(M)/F578CH(M)/F578CHS(M)
MB91F579C(M)/F579CS(M)/F579CH(M)/F579CHS(M)
Data Sheet (Full Production)

Publication Number MB91F577_DS705-00009 Revision 3.0 Issue Date June 19, 2015

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MB91570 Series
32-bit Microcontroller
MB91F575B/F575BS/F575BH/F575BHS/F575C/
F575CS/F575CH/F575CHS
MB91F577B/F577BS/F577BH/F577BHS/F577CS/
F577CH/F577CHS
MB91F578C(M)/F578CS(M)/F578CH(M)/F578CHS(M)
MB91F579C(M)/F579CS(M)/F579CH(M)/F579CHS(M)
Data Sheet (Full Production)

 DESCRIPTION
This series is Spansion 32-bit microcontroller designed for automotive and industrial control applications. It
contains the FR81S CPU that is compatible with the FR family. The FR81S has a high level performance
among the Spansion FR family by enhancing CPU instruction pipeline and load store processing, and
improving internal bus transfer.
It is best suited for application control for automotive.

Note: FR is a line of products of Spansion Inc.

Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.

http://www.spansion.com/Support/microcontrollers/

Publication Number MB91F577_DS705-00009 Revision 3.0 Issue Date June 19, 2015

This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.

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 FEATURES
 FR81S CPU Core
・ 32-bit RISC, load/store architecture, 5-stage pipeline
・ Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied ( PLL clock
multiplication system ))
・ General-purpose register : 32-bit ×16 sets
・ 16-bit fixed length instructions ( basic instruction ), 1 instruction per cycle
・ Instructions appropriate to embedded applications
・ Memory-to-memory transfer instruction
・ Bit processing instruction
・ Barrel shift instruction etc.
・ High-level language support instructions
・ Function entry/exit instructions
・ Register content multi-load and store instructions
・ Bit search instructions
・ Logical 1 detection, 0 detection, and change-point detection
・ Branch instructions with delay slot
・ Decrease overhead during branch process
・ Register interlock function
・ Easy assembler writing
・ Built-in multiplier and instruction level support
・ Signed 32-bit multiplication : 5 cycles
・ Signed 16-bit multiplication : 3 cycles
・ Interrupt ( PC/PS saving )
・ 6 cycles ( 16 priority levels )
・ The Harvard architecture allows simultaneous execution of program and data access.
・ Instruction compatibility with the FR family
・ Built-in memory protection function ( MPU )
・ Eight protection areas can be specified commonly for instructions and the data.
・ Control access privilege in both privilege mode and user mode.
・ Built-in FPU (floating point arithmetic)
・ IEEE754 compliant
・ Floating-point register 32-bit × 16 sets

 Peripheral Functions
・ Clock generation (equipped with SSCG function)
・ Main oscillation (4MHz)
・ Sub oscillation (32kHz ) or no sub oscillation
・ PLL multiplication rate : 1 to 20 times
・ Built-in Program flash memory capacity
・ MB91F575 : 512 + 64KB
・ MB91F577 : 1024 + 64KB
・ MB91F578 : 1536 + 64KB
・ MB91F579 : 2048 + 64KB
・ Built-in Data flash memory (WorkFlash) capacity 64KB
・ Built-in RAM capacity
・ Main RAM
MB91F575 : 40KB
MB91F577 : 64KB
MB91F578 : 96KB
MB91F579 : 128KB
・ Backup RAM
MB91F575/7 : 8KB
MB91F578/9 : 16KB

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・ General-purpose ports
[LQFP-144]
・ 111 (none sub oscillation ), 109 (with sub oscillation )
・ Included I2C pseudo open drain ports : 4
・ P057 : Input only
[LQFP-208]
・ 159 (none sub oscillation ), 157 (with sub oscillation )
・ Included I2C pseudo open drain ports : 4
・ P057 : Input only
・ External bus interface
・ 22-bit address, 16-bit data
・ 23 pins of 9-bit address, 8-bit data, ASX, CS0X, CS1X, RDX, WR0X, and WR1X can select
5V/3.3V by the VCCE power supply
・ DMA Controller
・ Up to 16 channels can be started simultaneously.
・ 2 transfer factors ( Internal peripheral request and software )
・ A/D converter (successive approximation type)
・ 8/10-bit resolution : 40 channels
・ Conversion time : 3μs
・ D/A converter (R-2R type)
・ 8-bit resolution : 2 channels
・ External interrupt input: 16 channels
・ Level ("H" / "L"), or edge detection ( rising or falling ) enabled
・ LIN-UART
・ 6 channels, ch.2 to ch.7
・ Selectable from UART, synchronous mode or LIN-UART mode
・ LIN protocol Revision 2.1 supported (LIN-UART).
・ SPI( Serial Peripheral Interface ) supported ( synchronous mode )
・ Full-duplex double buffering system
・ LIN synch break detection ( linked to the input capture )
・ Built-in dedicated baud rate generator
・ DMA transfer support
・ Multi-function serial communication (built-in transmission/reception FIFO memory ) : 4 channels
< UART (Asynchronous serial interface) >
・ Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
・ Parity or no parity is selectable.
・ Built-in dedicated baud rate generator
・ The external clock can be used as the transfer clock
・ Parity, frame, and overrun error detect functions provided
・ DMA transfer support
<CSIO (Synchronous serial interface) >
・ Full-duplex double buffering system, 16-byte transmission FIFO, memory, 16-byte reception FIFO
memory
・ SPI supported; master and slave systems supported; 5 to 9-bit data length can be set.
・ Built-in dedicated baud rate generator (Master operation)
・ The external clock can be entered. (Slave operation)
・ Overrun error detection function is provided
・ DMA transfer support
<LIN-UART (Asynchronous Serial Interface for LIN) >
・ Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
・ LIN protocol revision 2.1 supported
・ Master and slave systems supported
・ Framing error and overrun error detection
・ LIN synch break generation and detection; LIN synch delimiter generation
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・ Built-in dedicated baud rate generator

・ The external clock can be adjusted by the reload counter
・ DMA transfer support
< I2C >
・ Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
・ Standard mode ( Max. 100kbps ) / high-speed mode ( Max. 400kbps ) supported
・ DMA transfer supported ( for transmission only )
・ I2C supporting I/O ( for ch.0 and ch.1 only )
・ CAN Controller (C-CAN) : 3 channels
・ Transfer speed : Up to 1Mbps
・ 64-transmission/reception message buffering : 1 channel,
32-transmission/reception message buffering : 2 channels
・ PPG : 16-bit × 24 channels
・ Reload timer : 16-bit × 7 channels(3 channels are for regular timer interrupt generation. )
・ Free-run timer :
32-bit × 6 channels (Can select each channel for input capture, output compare)
・ Input capture :
32-bit × 12 channels (linked to the free-run timer)
・ Output compare : 32-bit × 12 channels (linked to the free-run timer)
・ Sound generator : 5 channels
・ Frequency and amplitude sequencers provided
・ Stepping motor controller : 6 channels
・ 8/10-bit PWM
・ High current output supported (4 lines × 6 channels)
Can refer back electromotive force using pin-shared A/D converter
・ LCD controller
・ Common output : 4 , Segment output : 32
・ Duty drive (SEG0 to SEG31) and static drive (ST0 to ST8) can be switched.
・ Each of COM0 to COM3, SEG0 to SEG31, V0, V1, V2, and V3 pins for duty drive can be switched
to the general-purpose port. (The SEG23 to SEG31 pins can be switched to static driving.)
・ V0, V1, V2 and V3 pin can be used as the general-purpose port. But V3 pin cannot be used as an
output pin.
・ Each of ST0 to ST8 pins for static drive can be switched to the general-purpose port, or it can be
switched to the segment output of duty drive.
・ MB91F575/7: The amplitude of the SEG0 to SEG22 output is determined by the VCC5 power
supply pin or by the V3 pin even if VCCE pin is supplied to 3.3V.
・ MB91F578/9: The voltage VCCE or less can be supplied to V3 pin. It is prohibited that VCC5
being chosen as LCDC reference voltage by software.
・ Up/Down counter: 2 channels
・ 8/16-bit up/down counter
・ Real-time clock (RTC) (for day, hours, minutes, seconds)
・ Main oscillation / sub oscillation frequency can be selected for the operation clock
・ Calibration: A hardware watchdog of the CR oscillation drive and real-time clock (RTC) of the sub clock
drive
・ The CR oscillation frequency can be trimmed
・ The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler
・ Clock Supervisor
・ Monitoring abnormality (damage of crystal etc.) of sub oscillation ( 32kHz ) (dual clock products)
and main oscillation ( 4 MHz )
・ When abnormality is detected, it switches to the CR clock.
・ Base timer : 2 channels
・ 16-bit timer
・ Any of four PWM/PPG/PWC/reload timer functions can be selected and used.
・ As for the functions of PWC and reload timer, 2 channels of cascade mode can be used as 32-bit
timer.
・ CRC generation

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・ HS-SPI
Note: In this series, the HS-SPI function is prohibited
・ E2PROM and the flash device of the Single/Dual/Quad-SPI protocol can be connected.
・ The power supply of 5V/3.3V supplied to the VCCE power supply pin is used.
・ Maximum 16MHz (Maximum 8 MHz at the slave.)
・ Watchdog timer
・ Hardware watchdog
・ Software watchdog
・ NMI
・ Interrupt controller
・ Interrupt request batch read
・ Multiple interrupts from peripherals can be read by a series of registers.
・ I/O relocation
・ Peripheral function pins can be reassigned.
・ Low-power consumption mode
・ Sleep / Stop / Watch / Sub RUN mode
・ Stop (power shutdown) / Watch (power shutdown) mode
・ Power on reset
・ Low-voltage detection reset (external low-voltage detection)
・ Low-voltage detection reset (internal low-voltage detection)
・ Device Package :
・ LQFP-144 for MB91F575/7/8/9
・ LQFP-208 for MB91F578/9
・ CMOS 90nm Technology
・ Power supplies
・ 5V Power supply
・ The internal 1.2V is generated from 5V with the voltage step-down regulator.
・ I/O port uses the power supply of 5V/3.3V supplied to the VCCE power supply pin.
・ LQFP-144: P010 to P017, P020 to P027, and P030 to P036
・ LQFP-208: P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, and
P190 to P197

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 PRODUCT LINEUP

Product
MB91F575B(S)/C(S) MB91F575BH(S)/CH(S)
Item
System Clock On chip PLL Clock multiple method

Minimum instruction execution time Around 12.5ns (80MHz)

Yes(Non-S series)
Sub clock
No(S series)

FLASH Capacity (Program) 512 + 64KB

FLASH Capacity (Work) 64KB

RAM 40KB + 8KB

BI-ROM 4KB

GDC None

Address : 22-bit Data :16-bit

External BUS I/F (Part of the External BUS I/F pins can select the power supply 5V or 3.3V)

DMA Controller 16 channels

Base Timer(16bit) 2 channels

Free-run Timer(32bit) 6 channels

Input capture(32bit) 12 channels

Output Compare(32bit) 12 channels

Reload Timer(16bit) 7 channels

PPG timer(16bit) 24 channels

Up/down Counter 2 channels

Clock Supervisor Yes

D/A converter 2 channels

External Interrupt 16 channels

A/D converter (8bit/10bit) 40 channels

LIN-UART 6 channels

Multi-Function serial communication 4 channels*1

Yes
HS-SPI Up to 16MHz
Note: In this series, the HS-SPI function is prohibited.

LCD Controller 32seg × 4com(Static drive 8seg × 1com)

CAN 64msg × 1 channel / 32msg × 2 channels

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Product
MB91F575B(S)/C(S) MB91F575BH(S)/CH(S)
Item

Stepping Motor Controller 6 channels

Sound Generator 5 channels

Software Watchdog Yes

Hardware Watchdog Yes

Clock supervisor Initial value "ON" Initial value "OFF"

CRC generation Yes

Low-voltage detection reset

Yes
(External low-voltage detection)

Low-voltage detection reset

Yes
(Internal low-voltage detection)

Package LQFP-144

Others Flash Products

On Chip Debug Yes

2
*1: I C only supported by ch.0 and ch.1.

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Product
MB91F577B(S)/C(S) MB91F577BH(S)/CH(S)
Item

System Clock On chip PLL Clock multiple method

Minimum instruction execution time Around 12.5ns (80MHz)

Yes(Non-S series)
Sub clock
No(S series)

FLASH Capacity (Program) 1024 + 64KB

FLASH Capacity (Work) 64KB

RAM 64KB + 8KB

BI-ROM 4KB

GDC None

Address : 22-bit Data :16-bit

External BUS I/F (Part of the External BUS I/F pins can select the power supply 5V or 3.3V)

DMA Controller 16 channels

Base Timer(16bit) 2 channels

Free-run Timer(32bit) 6 channels

Input capture(32bit) 12 channels

Output Compare(32bit) 12 channels

Reload Timer(16bit) 7 channels

PPG timer(16bit) 24 channels

Up/down Counter 2 channels

Clock Supervisor Yes

D/A converter 2 channels

External Interrupt 16 channels

A/D converter (8bit/10bit) 40 channels

LIN-UART 6 channels

Multi-Function serial communication 4 channels*1

Yes
HS-SPI Up to 16MHz
Note: In this series, the HS-SPI function is prohibited.

LCD Controller 32seg × 4com(Static drive 8seg × 1com)

CAN 64msg × 1 channel / 32msg × 2 channels

Stepping Motor Controller 6 channels

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Product
MB91F577B(S)/C(S) MB91F577BH(S)/CH(S)
Item

Sound Generator 5 channels

Software Watchdog Yes

Hardware Watchdog Yes

Clock supervisor Initial value "ON" Initial value "OFF"

CRC generation Yes

Low-voltage detection reset

Yes
(External low-voltage detection)

Low-voltage detection reset

Yes
(Internal low-voltage detection)

Package LQFP-144

Others Flash Products

On Chip Debug Yes

2
*1: I C only supported by ch.0 and ch.1.

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Product MB91F MB91F MB91F MB91F

Item 578C(S)(M) 578CH(S)(M) 579C(S)(M) 579CH(S)(M)

System Clock On chip PLL Clock multiple method

Minimum instruction execution time Around 12.5ns (80MHz)

Yes(Non-S series)
Sub clock
No(S series)

FLASH Capacity (Program) 1536 + 64KB 2048 + 64KB

FLASH Capacity (Work) 64KB

RAM 96KB + 16KB 128KB + 16KB

BI-ROM 4KB

GDC None

Address : 22-bit Data :16-bit

External BUS I/F (Part of the External BUS I/F pins can select the power supply 5V or 3.3V)

DMA Controller 16 channels

Base Timer(16bit) 2 channels

Free-run Timer(32bit) 6 channels

Input capture(32bit) 12 channels

Output Compare(32bit) 12 channels

Reload Timer(16bit) 7 channels

PPG timer(16bit) 24 channels

Up/down Counter 2 channels

Clock Supervisor Yes

D/A converter 2 channels

External Interrupt 16 channels

A/D converter (8bit/10bit) 40 channels

LIN-UART 6 channels

Multi-Function serial communication 4 channels*1

HS-SPI No

LCD Controller 32seg × 4com(Static drive 8seg × 1com)

CAN 64msg × 1 channel / 32msg × 2 channels

Stepping Motor Controller 6 channels

Sound Generator 5 channels

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Product MB91F MB91F MB91F MB91F

Item 578C(S)(M) 578CH(S)(M) 579C(S)(M) 579CH(S)(M)

Software Watchdog Yes

Hardware Watchdog Yes

Initial value Initial value Initial value Initial value

Clock supervisor
"ON" "OFF" "ON" "OFF"

CRC generation Yes

Low-voltage detection reset

Yes
(External low-voltage detection)

Low-voltage detection reset

Yes
(Internal low-voltage detection)

LQFP-144
Package
LQFP-208 (with suffix "M")

Others Flash Products

On Chip Debug Yes

2
*1: I C only supported by ch.0 and ch.1.

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 PIN ASSIGNMENT (LQFP-144)

P005/D21_0/SCK3_1/TOT1_2/PPG5_0/D29_1/INT5_1
P004/D20_0/SOT3_1/TOT0_2/PPG4_0/D28_1/INT4_1

P133/SCK1_0/INT3_0/ICU4_0/TIOB1/PPG11_1/TRG5
P002/D18_0/SCK2_1/TIN2_2/PPG2_0/D26_1/INT2_1
P001/D17_0/SOT2_1/TIN1_2/PPG1_0/D25_1/INT1_1
P003/D19_0/SIN3_1/TIN3_2/PPG3_0/D27_1/INT3_1

P000/D16_0/SIN2_1/TIN0_2/PPG0_0/D24_1/INT0_1
P007/D23_0/TOT3_2/PPG7_0/D31_1/INT7_1
P006/D22_0/TOT2_2/PPG6_0/D30_1/INT6_1

P131/TRG1/SIN1_0/INT4_0/ICU2_0/TIOA1
P130/SCK0_0/INT0_0/ICU1_0/TIOA0
P132/SOT1_0/INT2_0/ICU3_0/TIOB0

P126/TRG0/SIN0_0/INT1_0/OCU4_0
P134/TRG2/INT5_0/ICU5_0/PPG1_3
P014/D28_0/SEG4/D20_1/INT12_1
P013/D27_0/SEG3/D19_1/INT11_1
P012/D26_0/SEG2/D18_1/INT10_1
P011/D25_0/SEG1/D17_1/INT9_1
P010/D24_0/SEG0/D16_1/INT8_1

P125/OCU3_0/ICU0_0/PPG10_2

P124/OCU2_0/ICU5_2/PPG9_2
P127/SOT0_0/OCU5_0

P095/TX0/PPG10_1
P096/RX0/INT9_0

DEBUGIF
VCC5

MD2
MD1
MD0
VSS

VSS
VSS

VSS
X1
X0
C
144
143

138

133
132

127
126

121

116
115

110
109
142
141
140
139

137
136
135
134

131
130
129
128

125
124
123
122

120
119
118
117

114
113
112
111
VCCE 1 108 VCC5
P015/D29_0/SEG5/D21_1/INT13_1 2 107 RSTX
P016/D30_0/SEG6/D22_1/INT14_1 3 106 P113/RX2/INT11_0/PPG4_2
P017/D31_0/SEG7/D23_1/INT15_1 4 105 P112/TX2/PPG3_2
P020/ASX/SEG8/ICU6_0/OCU0_1 5 104 P111/RX1/INT10_0/PPG2_2
P021/CS0X/SEG9/ICU7_0/OCU1_1 6 103 P110/TX1/PPG1_2/FRCK5_0
P022/CS1X/SEG10/ICU8_0/OCU2_1 7 102 P091/SGA0/SIN2_0/INT12_0/TOT2_1/ICU2_1/PPG6_1
P023/RDX/SEG11/ICU9_0/OCU3_1 8 101 P092/SGO0/SCK2_0/INT13_0/TOT3_1/ICU0_1/PPG7_1
P024/WR0X/SEG12/ICU10_0/OCU11_0 9 100 P093/SGA1/SOT2_0/INT14_0/ICU3_1/PPG8_1
P025/WR1X/SEG13/ICU11_0/OCU10_0 10 99 P094/SGO1/SIN3_0/INT15_0/ICU1_1/PPG9_1
P026/A00/SEG14/SPI_CS3/SIN6_1/OCU9_0 11 98 P097/WOT/SOT3_0/INT8_0/TIN0_0/ICU4_1/PPG0_1
P027/A01/SEG15/SPI_CS2/SOT6_1/OCU8_0 12 97 NMIX
P030/A02/SEG16/SPI_CS1/SCK6_1 13 96 P136/(X1A)
P031/A03/SEG17/SPI_CS0/SIN9_0 14 95 P137/(X0A)
P032/A04/SEG18/SPI_SIO3/SOT9_0/OCU7_0
P033/A05/SEG19/SPI_SIO2/SCK9_0/OCU6_0
15
16
TOP VIEW 94
93
VSS
VCC5
P034/A06/SEG20/SPI_SIO1/SIN8_0/OCU5_1 17 92 P114/SCK3_0/TIN1_0/ICU5_1/SGA2/TRG3/AN32
P035/A07/SEG21/SPI_SIO0/SOT8_0/OCU4_1 18 91 P115/SIN4_0/TIN2_0/SGO2/FRCK4_0/AN33
P036/A08/SEG22/PPG11_0/SPI_CLK/SCK8_0
VCCE
19
20 LQFP-144 90
89
P116/SOT4_0/TIN3_0/SGA3/FRCK3_0/AN34
P117/SCK4_0/TOT0_0/SGO3/TRG4/FRCK2_0/AN35
VSS 21 88 P120/FRCK1_0/SIN5_0/INT6_0/TOT1_0/PPG5_2/AN36
P037/A09/SEG23/ST0/PPG12_0/SIN7_0 22 87 P121/FRCK0_0/SOT5_0/INT7_0/TOT2_0/PPG6_2/AN37
P040/A10/SEG24/ST1/PPG13_0/SOT7_0 23 86 P122/OCU0_0/SCK5_0/TOT3_0/PPG7_2/AN38
P041/A11/SEG25/ST2/PPG14_0/SCK7_0 24 85 P123/OCU1_0/PPG8_2/DAO0/AN39
P042/A12/SEG26/ST3/PPG15_0/AIN0_0 25 84 AVCC
P043/A13/SEG27/ST4/BIN0_0/SGA4_0/OCU6_1 26 83 AVRH
P044/A14/SEG28/ST5/ZIN0_0/SGO4_0/OCU7_1 27 82 AVSS/AVRL
P045/A15/SEG29/ST6/AIN1_0/SIN8_2 28 81 P107/AN7/PPG5_1/DAO1/ICU11_2/SGO4_1
P046/A16/SEG30/ST7/BIN1_0/SOT8_2 29 80 P106/AN6/PPG4_1/ICU10_2/SGA4_1
P047/A17/SEG31/ST8/ZIN1_0/SCK8_2 30 79 P105/SCK5_1/AN5/TOT1_1/PPG3_1/ICU9_2
P050/A18/COM0/OCU8_1 31 78 P104/SOT5_1/AN4/TOT0_1/PPG2_1/ICU8_2
P051/A19/COM1/OCU9_1 32 77 P103/SIN5_1/AN3/TIN3_1/PPG1_1/ICU7_2
P052/A20/COM2/OCU10_1 33 76 P102/SCK4_1/AN2/TIN2_1/PPG10_0/ICU6_2
P053/A21/COM3/OCU11_1 34 75 P101/SOT4_1/AN1/TIN1_1/PPG9_0
P054/SYSCLK/V0/FRCK0_1 35 74 P100/SIN4_1/AN0/TIN0_1/PPG8_0
VCC5 36 73 P090/ADTG/PPG0_2
39
40

45
46

51

56
57

62
63

68
37
38

41
42
43
44

47
48
49
50

52
53
54
55

58
59
60
61

64
65
66
67

69
70
71
72
P077/PWM2M3/AN23/PPG15_1/ICU6_1/SCK7_1

P080/PWM1P4/AN24/SIN6_0/PPG16_0/AIN0_2
P063/PWM2M0/AN11/BIN1_1/SCK1_1

P074/PWM1P3/AN20/PPG12_1/ICU9_1/SCK8_1

P082/PWM2P4/AN26/SCK6_0/PPG18_0/ZIN0_2
P073/PWM2M2/AN19/ICU10_1/SOT8_1
P067/PWM2M1/AN15/AIN0_1/SIN9_1

P075/PWM1M3/AN21/PPG13_1/ICU8_1/SIN7_1
P066/PWM2P1/AN14/BIN0_1/SCK0_1

P076/PWM2P3/AN22/PPG14_1/ICU7_1/SOT7_1
P070/PWM1P2/AN16/SOT9_1
P055/CS2X/V1/FRCK1_1
P056/CS3X/V2/FRCK2_1

P072/PWM2P2/AN18/ICU11_1/SIN8_1

P084/PWM1P5/AN28/ICU1_2/PPG20_0

P086/PWM2P5/AN30/ICU3_2/PPG22_0
P057/RDY/V3/FRCK3_1

P081/PWM1M4/AN25/SOT6_0/PPG17_0/BIN0_2
P064/PWM1P1/AN12/AIN1_1/SIN0_1
P062/PWM2P0/AN10/ZIN1_1/SOT1_1

P083/PWM2M4/AN27/ICU0_2/PPG19_0

P085/PWM1M5/AN29/ICU2_2/PPG21_0

P087/PWM2M5/AN31/ICU4_2/PPG23_0
P071/PWM1M2/AN17/SCK9_1
P065/PWM1M1/AN13/ZIN0_1/SOT0_1
P061/PWM1M0/AN9/SIN1_1
P060/PWM1P0/AN8

DVCC
DVCC

DVCC

DVCC
DVSS

DVSS
DVSS

DVSS
VSS

12 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

 PIN ASSIGNMENT (LQFP-208)

P133/SCK1_0/INT3_0/ICU4_0/TIOB1/TRG5/PPG11_1

P131/TRG1/SIN1_0/INT4_0/ICU2_0/TIOA1
P130/SCK0_0/INT0_0/ICU1_0/TIOA0
P132/SOT1_0/INT2_0/ICU3_0/TIOB0

P126/TRG0/SIN0_0/INT1_0/OCU4_0
P134/TRG2/INT5_0/ICU5_0/PPG1_3

P125/OCU3_0/ICU0_0/PPG10_2

P124/OCU2_0/ICU5_2/PPG9_2
P127/SOT0_0/OCU5_0

P095/TX0/PPG10_1
P157/D31_0/D23_1
P156/D30_0/D22_1
P155/D29_0/D21_1
P154/D28_0/D20_1
P153/D27_0/D19_1
P152/D26_0/D18_1
P151/D25_0/D17_1
P150/D24_0/D16_1
P147/D23_0/D31_1
P146/D22_0/D30_1
P145/D21_0/D29_1
P144/D20_0/D28_1
P143/D19_0/D27_1
P142/D18_0/D26_1
P141/D17_0/D25_1
P140/D16_0/D24_1

P096/RX0/INT9_0
Non connection
Non connection
Non connection
Non connection
P165/WR1X
P164/WR0X

P162/CS1X
P161/CS0X
P163/RDX

P160/ASX
P170/A02
P167/A01
P166/A00

DEBUGIF
VCC5

MD2
MD1
MD0
VSS

VSS

VSS

VSS
X1
X0
C
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VCCE 1 156 VCC5
P171/A03 2 ○ 155 RSTX
P172/A04 3 154 P113/RX2/INT11_0/PPG4_2
P173/A05 4 153 P112/TX2/PPG3_2
P174/A06 5 152 P111/RX1/INT10_0/PPG2_2
P175/A07 6 151 P110/TX1/PPG1_2/FRCK5_0
P176/A08 7 150 P091/SGA0/SIN2_0/INT12_0/TOT2_1/ICU2_1/PPG6_1
P177/A09 8 149 P092/SGO0/SCK2_0/INT13_0/TOT3_1/ICU0_1/PPG7_1
P180/A10 9 148 P093/SGA1/SOT2_0/INT14_0/ICU3_1/PPG8_1
P181/A11 10 147 P094/SGO1/SIN3_0/INT15_0/ICU1_1/PPG9_1
P182/A12 11 146 P097/WOT/SOT3_0/INT8_0/TIN0_0/ICU4_1/PPG0_1
P183/A13 12 145 Non connection
P184/A14 13 144 P007/TOT3_2/PPG7_0/INT7_1
P185/A15 14 143 P006/TOT2_2/PPG6_0/INT6_1
P186/A16 15 142 P005/SCK3_1/TOT1_2/PPG5_0/INT5_1
P187/A17 16 141 P004/SOT3_1/TOT0_2/PPG4_0/INT4_1
P190/A18 17 140 NMIX
P191/A19 18 139 P136/(X1A)
P192/A20 19 138 P137/(X0A)
P193/A21 20 137 VSS
VCCE 21 136 VCC5
VSS 22 135 P003/SIN3_1/TIN3_2/PPG3_0/INT3_1
P194/SYSCLK 23 134 P002/SCK2_1/TIN2_2/PPG2_0/INT2_1
P195/CS2X 24 133 P001/SOT2_1/TIN1_2/PPG1_0/INT1_1
P196/CS3X
P197/RDY
VCC5
VSS
25
26
27
28
TOP VIEW 132
131
130
129
P000/SIN2_1/TIN0_2/PPG0_0/INT0_1
P114/SCK3_0/TIN1_0/ICU5_1/SGA2/AN32/TRG3
P115/SIN4_0/TIN2_0/SGO2/FRCK4_0/AN33
P116/SOT4_0/TIN3_0/SGA3/FRCK3_0/AN34
P010/SEG0/INT8_1 29 128 P117/SCK4_0/TOT0_0/SGO3/FRCK2_0/AN35/TRG4
P011/SEG1/INT9_1
P012/SEG2/INT10_1
P013/SEG3/INT11_1
P014/SEG4/INT12_1
30
31
32
33
LQFP-208 127
126
125
124
P120/FRCK1_0/SIN5_0/INT6_0/TOT1_0/PPG5_2/AN36
P121/FRCK0_0/SOT5_0/INT7_0/TOT2_0/PPG6_2/AN37
P122/OCU0_0/SCK5_0/TOT3_0/PPG7_2/AN38
P123/OCU1_0/PPG8_2/DAO0/AN39
P015/SEG5/INT13_1 34 123 Non connection
P016/SEG6/INT14_1 35 122 AVCC
P017/SEG7/INT15_1 36 121 AVRH
P020/SEG8/ICU6_0/OCU0_1 37 120 AVSS/AVRL
P021/SEG9/ICU7_0/OCU1_1 38 119 Non connection
P022/SEG10/ICU8_0/OCU2_1 39 118 P107/AN7/PPG5_1/DAO1/ICU11_2/SGO4_1
P023/SEG11/ICU9_0/OCU3_1 40 117 P106/AN6/PPG4_1/ICU10_2/SGA4_1
P024/SEG12/ICU10_0/OCU11_0 41 116 Non connection
P025/SEG13/ICU11_0/OCU10_0 42 115 P105/SCK5_1/AN5/TOT1_1/PPG3_1/ICU9_2
P026/SEG14/SIN6_1/OCU9_0 43 114 P104/SOT5_1/AN4/TOT0_1/PPG2_1/ICU8_2
P027/SEG15/SOT6_1/OCU8_0 44 113 Non connection
P030/SEG16/SCK6_1 45 112 P103/SIN5_1/AN3/TIN3_1/PPG1_1/ICU7_2
P031/SEG17/SIN9_0 46 111 P102/SCK4_1/AN2/TIN2_1/PPG10_0/ICU6_2
P032/SEG18/SOT9_0/OCU7_0 47 110 Non connection
P033/SEG19/SCK9_0/OCU6_0 48 109 P101/SOT4_1/AN1/TIN1_1/PPG9_0
P034/SEG20/SIN8_0/OCU5_1 49 108 Non connection
P035/SEG21/SOT8_0/OCU4_1 50 107 P100/SIN4_1/AN0/TIN0_1/PPG8_0
P036/SEG22/PPG11_0/SCK8_0 51 106 P090/ADTG/PPG0_2
VCC5 52 105 Non connection
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
P061/PWM1M0/AN9/SIN1_1

P067/PWM2M1/AN15/SIN9_1/AIN0_1
VSS

VSS

DVSS

DVSS

DVSS

DVSS
VCC5

DVCC

DVCC

DVCC

DVCC
P060/PWM1P0/AN8

P071/PWM1M2/AN17/SCK9_1
P063/PWM2M0/AN11/SCK1_1/BIN1_1
P064/PWM1P1/AN12/SIN0_1/AIN1_1
P065/PWM1M1/AN13/SOT0_1/ZIN0_1

P073/PWM2M2/AN19/SOT8_1/ICU10_1

P083/PWM2M4/AN27/ICU0_2/PPG19_0

P085/PWM1M5/AN29/ICU2_2/PPG21_0

P087/PWM2M5/AN31/ICU4_2/PPG23_0
P075/PWM1M3/AN21/SIN7_1/ICU8_1/PPG13_1

P080/PWM1P4/AN24/SIN6_0/PPG16_0/AIN0_2
P081/PWM1M4/AN25/SOT6_0/PPG17_0/BIN0_2
P077/PWM2M3/AN23/SCK7_1/ICU6_1/PPG15_1
P050/COM0/OCU8_1
P051/COM1/OCU9_1

P054/V0/FRCK0_1
P055/V1/FRCK1_1
P056/V2/FRCK2_1
P057/V3/FRCK3_1
P052/COM2/OCU10_1
P053/COM3/OCU11_1

P070/PWM1P2/AN16/SOT9_1
P062/PWM2P0/AN10/SOT1_1/ZIN1_1

P066/PWM2P1/AN14/SCK0_1/BIN0_1

P072/PWM2P2/AN18/SIN8_1/ICU11_1

P084/PWM1P5/AN28/ICU1_2/PPG20_0

P086/PWM2P5/AN30/ICU3_2/PPG22_0
P074/PWM1P3/AN20/SCK8_1/ICU9_1/PPG12_1

P076/PWM2P3/AN22/SOT7_1/ICU7_1/PPG14_1

P082/PWM2P4/AN26/SCK6_0/PPG18_0/ZIN0_2
P042/SEG26/ST3/PPG15_0/AIN0_0

P045/SEG29/ST6/AIN1_0/SIN8_2
P043/SEG27/ST4/BIN0_0/SGA4_0/OCU6_1
P037/SEG23/ST0/PPG12_0/SIN7_0
P040/SEG24/ST1/PPG13_0/SOT7_0
P041/SEG25/ST2/PPG14_0/SCK7_0

P046/SEG30/ST7/BIN1_0/SOT8_2
P047/SEG31/ST8/ZIN1_0/SCK8_2
P044/SEG28/ST5/ZIN0_0/SGO4_0/OCU7_1

June 19, 2015, MB91F577_DS705-00009-3v0-E 13

CONFIDENTIAL
 D a t a S h e e t

 PIN DESCRIPTION (LQFP-144)

Pin I/O Circuit

Pin Name Function Description
Number Type

P015 General-Purpose I/O Port

D29_0 External Bus Data I/O pin
2 SEG5 H/I4*1 LCDC Segment(Duty)Output pin
D21_1 External Bus Data I/O pin
INT13_1 External Interrupt Request Input pin ch.13 relocation 1
P016 General-Purpose I/O Port
D30_0 External Bus Data I/O pin
3 SEG6 H/I4*1 LCDC Segment(Duty)Output pin
D22_1 External Bus Data I/O pin
INT14_1 External Interrupt Request Input pin ch.14 relocation 1
P017 General-Purpose I/O Port
D31_0 External Bus Data I/O pin
4 SEG7 H/I4*1 LCDC Segment(Duty)Output pin
D23_1 External Bus Data I/O pin
INT15_1 External Interrupt Request Input pin ch.15 relocation 1
P020 General-Purpose I/O Port
ASX External Bus Address-Strobe Output pin
5 SEG8 H/I4*1 LCDC Segment(Duty)Output pin
ICU6_0 Input Capture Input pin ch.6 relocation 0
OCU0_1 Output Compare Output pin ch.0 relocation 1
P021 General-Purpose I/O Port
CS0X External Bus Chip-Select 0 Output pin
6 SEG9 H/I4*1 LCDC Segment(Duty)Output pin
ICU7_0 Input Capture Input pin ch.7 relocation 0
OCU1_1 Output Compare Output pin ch.1 relocation 1
P022 General-Purpose I/O Port
CS1X External Bus Chip-Select 1 Output pin
7 SEG10 H/I4*1 LCDC Segment(Duty)Output pin
ICU8_0 Input Capture Input pin ch.8 relocation 0
OCU2_1 Output Compare Output pin ch.2 relocation 1
P023 General-Purpose I/O Port
RDX External Bus Read-Strobe Output pin
8 SEG11 H/I4*1 LCDC Segment(Duty)Output pin
ICU9_0 Input Capture Input pin ch.9 relocation 0
OCU3_1 Output Compare Output pin ch.3 relocation 1
P024 General-Purpose I/O Port
WR0X External Bus Write-Strobe 0 Output pin
9 SEG12 H/I4*1 LCDC Segment(Duty)Output pin
ICU10_0 Input Capture Input pin ch.10 relocation 0
OCU11_0 Output Compare Output pin ch.11 relocation 0
P025 General-Purpose I/O Port
WR1X External Bus Write-Strobe 1 Output pin
10 SEG13 H/I4*1 LCDC Segment(Duty)Output pin
ICU11_0 Input Capture Input pin ch.11 relocation 0
OCU10_0 Output Compare Output pin ch.10 relocation 0
14 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P026 General-Purpose I/O Port

A00 External Bus Address Output pin
SEG14 LCDC Segment(Duty)Output pin
11 H/I4*1
SPI_CS3 HS_SPI SSEL3 Output pin (Not supported)
SIN6_1 LIN_UART Serial Input pin ch.6 relocation 1
OCU9_0 Output Compare Output pin ch.9 relocation 0
P027 General-Purpose I/O Port
A01 External Bus Address Output pin
SEG15 LCDC Segment(Duty)Output pin
12 H/I4*1
SPI_CS2 HS_SPI SSEL2 Output pin (Not supported)
SOT6_1 LIN_UART Serial Output pin ch.6 relocation 1
OCU8_0 Output Compare Output pin ch.8 relocation 0
P030 General-Purpose I/O Port
A02 External Bus Address Output pin
13 SEG16 H/I4*1 LCDC Segment(Duty)Output pin
SPI_CS1 HS_SPI SSEL1 Output pin (Not supported)
SCK6_1 LIN_UART Serial Clock I/O pin ch.6 relocation 1
P031 General-Purpose I/O Port
A03 External Bus Address Output pin
14 SEG17 H/I4*1 LCDC Segment(Duty)Output pin
SPI_CS0 HS_SPI SSEL0 I/O pin (Not supported)
SIN9_0 Multi-function Serial Input pin ch.9 relocation 0
P032 General-Purpose I/O Port
A04 External Bus Address Output pin
SEG18 LCDC Segment(Duty)Output pin
15 H/I4*1
SPI_SIO3 HS_SPI SDATA3 I/O pin (Not supported)
SOT9_0 Multi-function Serial Output pin ch.9 relocation 0
OCU7_0 Output Compare Output pin ch.7 relocation 0
P033 General-Purpose I/O Port
A05 External Bus Address Output pin
SEG19 LCDC Segment(Duty)Output pin
16 H/I4*1
SPI_SIO2 HS_SPI SDATA2 I/O pin (Not supported)
SCK9_0 Multi-function Serial Clock I/O pin ch.9 relocation 0
OCU6_0 Output Compare Output pin ch.6 relocation 0
P034 General-Purpose I/O Port
A06 External Bus Address Output pin
SEG20 LCDC Segment(Duty)Output pin
17 H/I4*1
SPI_SIO1 HS_SPI SDATA1 I/O pin (Not supported)
SIN8_0 Multi-function Serial Input pin ch.8 relocation 0
OCU5_1 Output Compare Output pin ch.5 relocation 1
P035 General-Purpose I/O Port
A07 External Bus Address Output pin
SEG21 LCDC Segment(Duty)Output pin
18 H/I4*1
SPI_SIO0 HS_SPI SDATA0 I/O pin (Not supported)
SOT8_0 Multi-function Serial Output pin ch.8 relocation 0
OCU4_1 Output Compare Output pin ch.4 relocation 1

June 19, 2015, MB91F577_DS705-00009-3v0-E 15

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P036 General-Purpose I/O Port

A08 External Bus Address Output pin
SEG22 LCDC Segment(Duty)Output pin
19 H/I4*1
PPG11_0 PPG Output pin ch.11 relocation 0
SPI_CLK HS_SPI SCLK I/O pin (Not supported)
SCK8_0 Multi-function Serial Clock I/O pin ch.8 relocation 0
P037 General-Purpose I/O Port
A09 External Bus Address Output pin
SEG23 LCDC Segment(Duty)Output pin
22 I
ST0 LCDC Segment(Static)Output pin
PPG12_0 PPG Output pin ch.12 relocation 0
SIN7_0 LIN_UART Serial Input pin ch.7 relocation 0
P040 General-Purpose I/O Port
A10 External Bus Address Output pin
SEG24 LCDC Segment(Duty)Output pin
23 I
ST1 LCDC Segment(Static)Output pin
PPG13_0 PPG Output pin ch.13 relocation 0
SOT7_0 LIN_UART Serial Output pin ch.7 relocation 0
P041 General-Purpose I/O Port
A11 External Bus Address Output pin
SEG25 LCDC Segment(Duty)Output pin
24 I
ST2 LCDC Segment(Static)Output pin
PPG14_0 PPG Output pin ch.14 relocation 0
SCK7_0 LIN_UART Serial Clock I/O pin ch.7 relocation 0
P042 General-Purpose I/O Port
A12 External Bus Address Output pin
SEG26 LCDC Segment(Duty)Output pin
25 I
ST3 LCDC Segment(Static)Output pin
PPG15_0 PPG Output pin ch.15 relocation 0
AIN0_0 Up/down Counter AIN Input pin ch.0 relocation 0
P043 General-Purpose I/O Port
A13 External Bus Address Output pin
SEG27 LCDC Segment(Duty)Output pin
26 ST4 I LCDC Segment(Static)Output pin
BIN0_0 Up/down Counter BIN Input pin ch.0 relocation 0
SGA4_0 Sound Generator SGA Output pin ch.4 relocation 0
OCU6_1 Output Compare Output pin ch.6 relocation 1
P044 General-Purpose I/O Port
A14 External Bus Address Output pin
SEG28 LCDC Segment(Duty)Output pin
27 ST5 I LCDC Segment(Static)Output pin
ZIN0_0 Up/down Counter ZIN Input pin ch.0 relocation 0
SGO4_0 Sound Generator SGO Output pin ch.4 relocation 0
OCU7_1 Output Compare Output pin ch.7 relocation 1

16 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P045 General-Purpose I/O Port

A15 External Bus Address Output pin
SEG29 LCDC Segment(Duty)Output pin
28 I
ST6 LCDC Segment(Static)Output pin
AIN1_0 Up/down Counter AIN Input pin ch.1 relocation 0
SIN8_2 Multi-function Serial Input pin ch.8 relocation 2
P046 General-Purpose I/O Port
A16 External Bus Address Output pin
SEG30 LCDC Segment(Duty)Output pin
29 I
ST7 LCDC Segment(Static)Output pin
BIN1_0 Up/down Counter BIN Input pin ch.1 relocation 0
SOT8_2 Multi-function Serial Output pin ch.8 relocation 2
P047 General-Purpose I/O Port
A17 External Bus Address Output pin
SEG31 LCDC Segment(Duty)Output pin
30 I
ST8 LCDC Segment(Static)Output pin
ZIN1_0 Up/down Counter ZIN Input pin ch.1 relocation 0
SCK8_2 Multi-function Serial Clock I/O pin ch.8 relocation 2
P050 General-Purpose I/O Port
A18 External Bus Address Output pin
31 I
COM0 LCDC Segment(Duty)Common Output pin
OCU8_1 Output Compare Output pin ch.8 relocation 1
P051 General-Purpose I/O Port
A19 External Bus Address Output pin
32 I
COM1 LCDC Segment(Duty)Common Output pin
OCU9_1 Output Compare Output pin ch.9 relocation 1
P052 General-Purpose I/O Port
A20 External Bus Address Output pin
33 I
COM2 LCDC Segment(Duty)Common Output pin
OCU10_1 Output Compare Output pin ch.10 relocation 1
P053 General-Purpose I/O Port
A21 External Bus Address Output pin
34 I
COM3 LCDC Segment(Duty)Common Output pin
OCU11_1 Output Compare Output pin ch.11 relocation 1
P054 General-Purpose I/O Port
SYSCLK External Bus Clock Output pin
35 I2
V0 LCDC Reference Voltage V0 Input pin
FRCK0_1 Free-Run Timer Clock Input pin ch.0 relocation 1
P055 General-Purpose I/O Port
CS2X External Bus Chip-Select 2 Output pin
38 I2
V1 LCDC Reference Voltage V1 Input pin
FRCK1_1 Free-Run Timer Clock Input pin ch.1 relocation 1
P056 General-Purpose I/O Port
CS3X External Bus Chip-Select 3 Output pin
39 I2
V2 LCDC Reference Voltage V2 Input pin
FRCK2_1 Free-Run Timer Clock Input pin ch.2 relocation 1

June 19, 2015, MB91F577_DS705-00009-3v0-E 17

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P057 General-Purpose I/O Port (Input only. No output.)

RDY External Bus RDY Input pin
40 I3
V3 LCDC Reference Voltage V3 Input pin
FRCK3_1 Free-Run Timer Clock Input pin ch.3 relocation 1
P060 General-Purpose I/O Port
43 PWM1P0 K SMC Output pin ch.0
AN8 ADC Analog Input pin ch.8
P061 General-Purpose I/O Port
PWM1M0 SMC Output pin ch.0
44 K
AN9 ADC Analog Input pin ch.9
SIN1_1 Multi-function Serial Input pin ch.1 relocation 1
P062 General-Purpose I/O Port
PWM2P0 SMC Output pin ch.0
45 AN10 K ADC Analog Input pin ch.10
ZIN1_1 Up/down Counter ZIN Input pin ch.1 relocation 1
SOT1_1 Multi-function Serial Output pin ch.1 relocation 1
P063 General-Purpose I/O Port
PWM2M0 SMC Output pin ch.0
46 AN11 K ADC Analog Input pin ch.11
BIN1_1 Up/down Counter BIN Input pin ch.1 relocation 1
SCK1_1 Multi-function Serial Clock I/O pin ch.1 relocation 1
P064 General-Purpose I/O Port
PWM1P1 SMC Output pin ch.1
47 AN12 K ADC Analog Input pin ch.12
AIN1_1 Up/down Counter AIN Input pin ch.1 relocation 1
SIN0_1 Multi-function Serial Input pin ch.0 relocation 1
P065 General-Purpose I/O Port
PWM1M1 SMC Output pin ch.1
48 AN13 K ADC Analog Input pin ch.13
ZIN0_1 Up/down Counter ZIN Input pin ch.0 relocation 1
SOT0_1 Multi-function Serial Output pin ch.0 relocation 1
P066 General-Purpose I/O Port
PWM2P1 SMC Output pin ch.1
49 AN14 K ADC Analog Input pin ch.14
BIN0_1 Up/down Counter BIN Input pin ch.0 relocation 1
SCK0_1 Multi-function Serial Clock I/O pin ch.0 relocation 1
P067 General-Purpose I/O Port
PWM2M1 SMC Output pin ch.1
50 AN15 K ADC Analog Input pin ch.15
AIN0_1 Up/down Counter AIN Input pin ch.0 relocation 1
SIN9_1 Multi-function Serial Input pin ch.9 relocation 1
P070 General-Purpose I/O Port
PWM1P2 SMC Output pin ch.2
53 K
AN16 ADC Analog Input pin ch.16
SOT9_1 Multi-function Serial Output pin ch.9 relocation 1

18 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P071 General-Purpose I/O Port

PWM1M2 SMC Output pin ch.2
54 K
AN17 ADC Analog Input pin ch.17
SCK9_1 Multi-function Serial Clock I/O pin ch.9 relocation 1
P072 General-Purpose I/O Port
PWM2P2 SMC Output pin ch.2
55 AN18 K ADC Analog Input pin ch.18
ICU11_1 Input Capture Input pin ch.11 relocation 1
SIN8_1 Multi-function Serial Input pin ch.8 relocation 1
P073 General-Purpose I/O Port
PWM2M2 SMC Output pin ch.2
56 AN19 K ADC Analog Input pin ch.19
ICU10_1 Input Capture Input pin ch.10 relocation 1
SOT8_1 Multi-function Serial Output pin ch.8 relocation 1
P074 General-Purpose I/O Port
PWM1P3 SMC Output pin ch.3
AN20 ADC Analog Input pin ch.20
57 K
PPG12_1 PPG Output pin ch.12 relocation 1
ICU9_1 Input Capture Input pin ch.9 relocation 1
SCK8_1 Multi-function Serial Clock I/O pin ch.8 relocation 1
P075 General-Purpose I/O Port
PWM1M3 SMC Output pin ch.3
AN21 ADC Analog Input pin ch.21
58 K
PPG13_1 PPG Output pin ch.13 relocation 1
ICU8_1 Input Capture Input pin ch.8 relocation 1
SIN7_1 LIN_UART Serial Input pin ch.7 relocation 1
P076 General-Purpose I/O Port
PWM2P3 SMC Output pin ch.3
AN22 ADC Analog Input pin ch.22
59 K
PPG14_1 PPG Output pin ch.14 relocation 1
ICU7_1 Input Capture Input pin ch.7 relocation 1
SOT7_1 LIN_UART Serial Output pin ch.7 relocation 1
P077 General-Purpose I/O Port
PWM2M3 SMC Output pin ch.3
AN23 ADC Analog Input pin ch.23
60 K
PPG15_1 PPG Output pin ch.15 relocation 1
ICU6_1 Input Capture Input pin ch.6 relocation 1
SCK7_1 LIN_UART Serial Clock I/O pin ch.7 relocation 1
P080 General-Purpose I/O Port
PWM1P4 SMC Output pin ch.4
AN24 ADC Analog Input pin ch.24
63 K
SIN6_0 LIN_UART Serial Input pin ch.6 relocation 0
PPG16_0 PPG Output pin ch.16 relocation 0
AIN0_2 Up/down Counter AIN Input pin ch.0 relocation 2

June 19, 2015, MB91F577_DS705-00009-3v0-E 19

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P081 General-Purpose I/O Port

PWM1M4 SMC Output pin ch.4
AN25 ADC Analog Input pin ch.25
64 K
SOT6_0 LIN_UART Serial Output pin ch.6 relocation 0
PPG17_0 PPG Output pin ch.17 relocation 0
BIN0_2 Up/down Counter BIN Input pin ch.0 relocation 2
P082 General-Purpose I/O Port
PWM2P4 SMC Output pin ch.4
AN26 ADC Analog Input pin ch.26
65 K
SCK6_0 LIN_UART Serial Clock I/O pin ch.6 relocation 0
PPG18_0 PPG Output pin ch.18 relocation 0
ZIN0_2 Up/down Counter ZIN Input pin ch.0 relocation 2
P083 General-Purpose I/O Port
PWM2M4 SMC Output pin ch.4
66 AN27 K ADC Analog Input pin ch.27
ICU0_2 Input Capture Input pin ch.0 relocation 2
PPG19_0 PPG Output pin ch.19 relocation 0
P084 General-Purpose I/O Port
PWM1P5 SMC Output pin ch.5
67 AN28 K ADC Analog Input pin ch.28
ICU1_2 Input Capture Input pin ch.1 relocation 2
PPG20_0 PPG Output pin ch.20 relocation 0
P085 General-Purpose I/O Port
PWM1M5 SMC Output pin ch.5
68 AN29 K ADC Analog Input pin ch.29
ICU2_2 Input Capture Input pin ch.2 relocation 2
PPG21_0 PPG Output pin ch.21 relocation 0
P086 General-Purpose I/O Port
PWM2P5 SMC Output pin ch.5
69 AN30 K ADC Analog Input pin ch.30
ICU3_2 Input Capture Input pin ch.3 relocation 2
PPG22_0 PPG Output pin ch.22 relocation 0
P087 General-Purpose I/O Port
PWM2M5 SMC Output pin ch.5
70 AN31 K ADC Analog Input pin ch.31
ICU4_2 Input Capture Input pin ch.4 relocation 2
PPG23_0 PPG Output pin ch.23 relocation 0
P090 General-Purpose I/O Port
73 ADTG M ADC External Trigger Input pin
PPG0_2 PPG Output pin ch.0 relocation 2
P100 General-Purpose I/O Port
SIN4_1 LIN_UART Serial Input pin ch.4 relocation 1
74 AN0 J ADC Analog Input pin ch.0
TIN0_1 Reload Timer Event Input pin ch.0 relocation 1
PPG8_0 PPG Output pin ch.8 relocation 0

20 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P101 General-Purpose I/O Port

SOT4_1 LIN_UART Serial Output pin ch.4 relocation 1
75 AN1 J ADC Analog Input pin ch.1
TIN1_1 Reload Timer Event Input pin ch.1 relocation 1
PPG9_0 PPG Output pin ch.9 relocation 0
P102 General-Purpose I/O Port
SCK4_1 LIN_UART Serial Clock I/O pin ch.4 relocation 1
AN2 ADC Analog Input pin ch.2
76 J
TIN2_1 Reload Timer Event Input pin ch.2 relocation 1
PPG10_0 PPG Output pin ch.10 relocation 0
ICU6_2 Input Capture Input pin ch.6 relocation 2
P103 General-Purpose I/O Port
SIN5_1 LIN_UART Serial Input pin ch.5 relocation 1
AN3 ADC Analog Input pin ch.3
77 J
TIN3_1 Reload Timer Event Input pin ch.3 relocation 1
PPG1_1 PPG Output pin ch.1 relocation 1
ICU7_2 Input Capture Input pin ch.7 relocation 2
P104 General-Purpose I/O Port
SOT5_1 LIN_UART Serial Output pin ch.5 relocation 1
AN4 ADC Analog Input pin ch.4
78 J
TOT0_1 Reload Timer Output pin ch.0 relocation 1
PPG2_1 PPG Output pin ch.2 relocation 1
ICU8_2 Input Capture Input pin ch.8 relocation 2
P105 General-Purpose I/O Port
SCK5_1 LIN_UART Serial Clock I/O pin ch.5 relocation 1
79 AN5 ADC Analog Input pin ch.5
J
TOT1_1 Reload Timer Output pin ch.1 relocation 1
PPG3_1 PPG Output pin ch.3 relocation 1
ICU9_2 Input Capture Input pin ch.9 relocation 2
P106 General-Purpose I/O Port
AN6 ADC Analog Input pin ch.6
80 PPG4_1 J PPG Output pin ch.4 relocation 1
ICU10_2 Input Capture Input pin ch.10 relocation 2
SGA4_1 Sound Generator SGA Output pin ch.4 relocation 1
P107 General-Purpose I/O Port
AN7 ADC Analog Input pin ch.7
PPG5_1 PPG Output pin ch.5 relocation 1
81 L
DAO1 DAC Output pin ch.1
ICU11_2 Input Capture Input pin ch.11 relocation 2
SGO4_1 Sound Generator SGO Output pin ch.4 relocation 1
P123 General-Purpose I/O Port
OCU1_0 Output Compare Output pin ch.1 relocation 0
85 PPG8_2 L PPG Output pin ch.8 relocation 2
DAO0 DAC Output pin ch.0
AN39 ADC Analog Input pin ch.39

June 19, 2015, MB91F577_DS705-00009-3v0-E 21

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P122 General-Purpose I/O Port

OCU0_0 Output Compare Output pin ch.0 relocation 0
SCK5_0 LIN_UART Serial Clock I/O pin ch.5 relocation 0
86 J
TOT3_0 Reload Timer Output pin ch.3 relocation 0
PPG7_2 PPG Output pin ch.7 relocation 2
AN38 ADC Analog Input pin ch.38
P121 General-Purpose I/O Port
FRCK0_0 Free-Run Timer Clock Input pin ch.0 relocation 0
SOT5_0 LIN_UART Serial Output pin ch.5 relocation 0
87 INT7_0 J External Interrupt Request Input pin ch.7 relocation 0
TOT2_0 Reload Timer Output pin ch.2 relocation 0
PPG6_2 PPG Output pin ch.6 relocation 2
AN37 ADC Analog Input pin ch.37
P120 General-Purpose I/O Port
FRCK1_0 Free-Run Timer Clock Input pin ch.1 relocation 0
SIN5_0 LIN_UART Serial Input pin ch.5 relocation 0
88 INT6_0 J External Interrupt Request Input pin ch.6 relocation 0
TOT1_0 Reload Timer Output pin ch.1 relocation 0
PPG5_2 PPG Output pin ch.5 relocation 2
AN36 ADC Analog Input pin ch.36
P117 General-Purpose I/O Port
SCK4_0 LIN_UART Serial Clock I/O pin ch.4 relocation 0
TOT0_0 Reload Timer Output pin ch.0 relocation 0
J
89 SGO3 Sound Generator SGO Output pin ch.3
TRG4 PPG Trigger Input pin 4 (ch.16-ch.19)
FRCK2_0 Free-Run Timer Clock Input pin ch.2 relocation 0
AN35 ADC Analog Input pin ch.35
P116 General-Purpose I/O Port
SOT4_0 LIN_UART Serial Output pin ch.4 relocation 0
90 TIN3_0 Reload Timer Event Input pin ch.3 relocation 0
J
SGA3 Sound Generator SGA Output pin ch.3
FRCK3_0 Free-Run Timer Clock Input pin ch.3 relocation 0
AN34 ADC Analog Input pin ch.34
P115 General-Purpose I/O Port
SIN4_0 LIN_UART Serial Input pin ch.4 relocation 0
TIN2_0 Reload Timer Event Input pin ch.2 relocation 0
91 J
SGO2 Sound Generator SGO Output pin ch.2
FRCK4_0 Free-Run Timer Clock Input pin ch.4 relocation 0
AN33 ADC Analog Input pin ch.33
P114 General-Purpose I/O Port
SCK3_0 LIN_UART Serial Clock I/O pin ch.3 relocation 0
TIN1_0 Reload Timer Event Input pin ch.1 relocation 0
92 ICU5_1 J Input Capture Input pin ch.5 relocation 1
SGA2 Sound Generator SGA Output pin ch.2
TRG3 PPG Trigger Input pin 3 (ch.12-ch.15)
AN32 ADC Analog Input pin ch.32
22 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P137 General-Purpose I/O Port

95 M (Y)
(X0A) Sub Clock oscillation Input pin (only dual clock product)
P136 General-Purpose I/O Port
96 M (Y)
(X1A) Sub Clock oscillation Output pin (only dual clock product)
97 NMIX R NMI Pin
P097 General-Purpose I/O Port
WOT RTC Overflow Output pin
SOT3_0 LIN_UART Serial Output pin ch.3 relocation 0
98 INT8_0 M External Interrupt Request Input pin ch.8 relocation 0
TIN0_0 Reload Timer Event Input pin ch.0 relocation 0
ICU4_1 Input Capture Input pin ch.4 relocation 1
PPG0_1 PPG Output pin ch.0 relocation 1
P094 General-Purpose I/O Port
SGO1 Sound Generator SGO Output pin ch.1
SIN3_0 LIN_UART Serial Input pin ch.3 relocation 0
99 M
INT15_0 External Interrupt Request Input pin ch.15 relocation 0
ICU1_1 Input Capture Input pin ch.1 relocation 1
PPG9_1 PPG Output pin ch.9 relocation 1
P093 General-Purpose I/O Port
SGA1 Sound Generator SGA Output pin ch.1
SOT2_0 LIN_UART Serial Output pin ch.2 relocation 0
100 M
INT14_0 External Interrupt Request Input pin ch.14 relocation 0
ICU3_1 Input Capture Input pin ch.3 relocation 1
PPG8_1 PPG Output pin ch.8 relocation 1
P092 General-Purpose I/O Port
SGO0 Sound Generator SGO Output pin ch.0
SCK2_0 LIN_UART Serial Clock I/O pin ch.2 relocation 0
101 INT13_0 M External Interrupt Request Input pin ch.13 relocation 0
TOT3_1 Reload Timer Output pin ch.3 relocation 1
ICU0_1 Input Capture Input pin ch.0 relocation 1
PPG7_1 PPG Output pin ch.7 relocation 1
P091 General-Purpose I/O Port
SGA0 Sound Generator SGA Output pin ch.0
SIN2_0 LIN_UART Serial Input pin ch.2 relocation 0
102 INT12_0 M External Interrupt Request Input pin ch.12 relocation 0
TOT2_1 Reload Timer Output pin ch.2 relocation 1
ICU2_1 Input Capture Input pin ch.2 relocation 1
PPG6_1 PPG Output pin ch.6 relocation 1
P110 General-Purpose I/O Port
TX1 CAN TX Data Output pin ch.1
103 M
PPG1_2 PPG Output pin ch.1 relocation 2
FRCK5_0 Free-Run Timer Clock Input pin ch.5 relocation 0
P111 General-Purpose I/O Port
RX1 CAN RX Data Input pin ch.1
104 M
INT10_0 External Interrupt Request Input pin ch.10 relocation 0
PPG2_2 PPG Output pin ch.2 relocation 2

June 19, 2015, MB91F577_DS705-00009-3v0-E 23

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P112 General-Purpose I/O Port

105 TX2 M CAN TX Data Output pin ch.2
PPG3_2 PPG Output pin ch.3 relocation 2
P113 General-Purpose I/O Port
RX2 CAN RX Data Input pin ch.2
106 M
INT11_0 External Interrupt Request Input pin ch.11 relocation 0
PPG4_2 PPG Output pin ch.4 relocation 2
107 RSTX R Reset Pin
110 DEBUGIF B DEBUG I/F pin
P095 General-Purpose I/O Port
111 TX0 M CAN TX Data Output pin ch.0
PPG10_1 PPG Output pin ch.10 relocation 1
P096 General-Purpose I/O Port
112 RX0 M CAN RX Data Input pin ch.0
INT9_0 External Interrupt Request Input pin ch.9 relocation 0
P124 General-Purpose I/O Port
OCU2_0 Output Compare Output pin ch.2 relocation 0
113 M
ICU5_2 Input Capture Input pin ch.5 relocation 2
PPG9_2 PPG Output pin ch.9 relocation 2
114 MD0 A Mode Pin 0
115 MD1 A Mode Pin 1
116 MD2 R2 Mode Pin 2
117 X0 X Main Clock oscillation Input pin
118 X1 X Main Clock oscillation Output pin
P125 General-Purpose I/O Port
OCU3_0 Output Compare Output pin ch.3 relocation 0
120 M
ICU0_0 Input Capture Input pin ch.0 relocation 0
PPG10_2 PPG Output pin ch.10 relocation 2
P126 General-Purpose I/O Port
TRG0 PPG Trigger Input pin 0 (ch.0-ch.3)
121 SIN0_0 M Multi-function Serial Input pin ch.0 relocation 0
INT1_0 External Interrupt Request Input pin ch.1 relocation 0
OCU4_0 Output Compare Output pin ch.4 relocation 0
P127 General-Purpose I/O Port
122 SOT0_0 N Multi-function Serial Output pin ch.0 relocation 0
OCU5_0 Output Compare Output pin ch.5 relocation 0
P130 General-Purpose I/O Port
SCK0_0 Multi-function Serial Clock I/O pin ch.0 relocation 0
123 INT0_0 N External Interrupt Request Input pin ch.0 relocation 0
ICU1_0 Input Capture Input pin ch.1 relocation 0
TIOA0 Base Timer Output pin ch.0

24 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P131 General-Purpose I/O Port

TRG1 PPG Trigger Input pin 1 (ch.4-ch.7)
SIN1_0 Multi-function Serial Input pin ch.1 relocation 0
124 M
INT4_0 External Interrupt Request Input pin ch.4 relocation 0
ICU2_0 Input Capture Input pin ch.2 relocation 0
TIOA1 Base Timer I/O pin ch.1
P132 General-Purpose I/O Port
SOT1_0 Multi-function Serial Output pin ch.1 relocation 0
125 INT2_0 N External Interrupt Request Input pin ch.2 relocation 0
ICU3_0 Input Capture Input pin ch.3 relocation 0
TIOB0 Base Timer Input pin ch.0
P133 General-Purpose I/O Port
SCK1_0 Multi-function Serial Clock I/O pin ch.1 relocation 0
INT3_0 External Interrupt Request Input pin ch.3 relocation 0
126 ICU4_0 N Input Capture Input pin ch.4 relocation 0
TIOB1 Base Timer Input pin ch.1
PPG11_1 PPG Output pin ch.11 relocation 1
TRG5 PPG Trigger Input pin 5 (ch.20-ch.23)
P134 General-Purpose I/O Port
TRG2 PPG Trigger Input pin 2 (ch.8-ch.11)
127 INT5_0 M External Interrupt Request Input pin ch.5 relocation 0
ICU5_0 Input Capture Input pin ch.5 relocation 0
PPG1_3 PPG Output pin ch.1 relocation 3
P000 General-Purpose I/O Port
D16_0 External Bus Data I/O pin
SIN2_1 LIN_UART Serial Input pin ch.2 relocation 1
131 TIN0_2 M Reload Timer Event Input pin ch.0 relocation 2
PPG0_0 PPG Output pin ch.0 relocation 0
D24_1 External Bus Data I/O pin
INT0_1 External Interrupt Request Input pin ch.0 relocation 1
P001 General-Purpose I/O Port
D17_0 External Bus Data I/O pin
SOT2_1 LIN_UART Serial Output pin ch.2 relocation 1
132 TIN1_2 M Reload Timer Event Input pin ch.1 relocation 2
PPG1_0 PPG Output pin ch.1 relocation 0
D25_1 External Bus Data I/O pin
INT1_1 External Interrupt Request Input pin ch.1 relocation 1
P002 General-Purpose I/O Port
D18_0 External Bus Data I/O pin
SCK2_1 LIN_UART Serial Clock I/O pin ch.2 relocation 1
133 TIN2_2 M Reload Timer Event Input pin ch.2 relocation 2
PPG2_0 PPG Output pin ch.2 relocation 0
D26_1 External Bus Data I/O pin
INT2_1 External Interrupt Request Input pin ch.2 relocation 1

June 19, 2015, MB91F577_DS705-00009-3v0-E 25

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P003 General-Purpose I/O Port

D19_0 External Bus Data I/O pin
SIN3_1 LIN_UART Serial Input pin ch.3 relocation 1
134 TIN3_2 M Reload Timer Event Input pin ch.3 relocation 2
PPG3_0 PPG Output pin ch.3 relocation 0
D27_1 External Bus Data I/O pin
INT3_1 External Interrupt Request Input pin ch.3 relocation 1
P004 General-Purpose I/O Port
D20_0 External Bus Data I/O pin
SOT3_1 LIN_UART Serial Output pin ch.3 relocation 1
135 TOT0_2 M Reload Timer Output pin ch.0 relocation 2
PPG4_0 PPG Output pin ch.4 relocation 0
D28_1 External Bus Data I/O pin
INT4_1 External Interrupt Request Input pin ch.4 relocation 1
P005 General-Purpose I/O Port
D21_0 External Bus Data I/O pin
SCK3_1 LIN_UART Serial Clock I/O pin ch.3 relocation 1
136 TOT1_2 M Reload Timer Output pin ch.1 relocation 2
PPG5_0 PPG Output pin ch.5 relocation 0
D29_1 External Bus Data I/O pin
INT5_1 External Interrupt Request Input pin ch.5 relocation 1
P006 General-Purpose I/O Port
D22_0 External Bus Data I/O pin
TOT2_2 Reload Timer Output pin ch.2 relocation 2
137 M
PPG6_0 PPG Output pin ch.6 relocation 0
D30_1 External Bus Data I/O pin
INT6_1 External Interrupt Request Input pin ch.6 relocation 1
P007 General-Purpose I/O Port
D23_0 External Bus Data I/O pin
TOT3_2 Reload Timer Output pin ch.3 relocation 2
138 M
PPG7_0 PPG Output pin ch.7 relocation 0
D31_1 External Bus Data I/O pin
INT7_1 External Interrupt Request Input pin ch.7 relocation 1
P010 General-Purpose I/O Port
D24_0 External Bus Data I/O pin
139 SEG0 H/I4*1 LCDC Segment(Duty)Output pin
D16_1 External Bus Data I/O pin
INT8_1 External Interrupt Request Input pin ch.8 relocation 1
P011 General-Purpose I/O Port
D25_0 External Bus Data I/O pin
140 SEG1 H/I4*1 LCDC Segment(Duty)Output pin
D17_1 External Bus Data I/O pin
INT9_1 External Interrupt Request Input pin ch.9 relocation 1

26 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin I/O Circuit

Pin Name Function Description
Number Type

P012 General-Purpose I/O Port

D26_0 External Bus Data I/O pin
*1
141 SEG2 H/I4 LCDC Segment(Duty)Output pin
D18_1 External Bus Data I/O pin
INT10_1 External Interrupt Request Input pin ch.10 relocation 1
P013 General-Purpose I/O Port
D27_0 External Bus Data I/O pin
142 SEG3 H/I4*1 LCDC Segment(Duty)Output pin
D19_1 External Bus Data I/O pin
INT11_1 External Interrupt Request Input pin ch.11 relocation 1
P014 General-Purpose I/O Port
D28_0 External Bus Data I/O pin
*1
143 SEG4 H/I4 LCDC Segment(Duty)Output pin
D20_1 External Bus Data I/O pin
INT12_1 External Interrupt Request Input pin ch.12 relocation 1
1 VCCE - +3.3v/+5.0v Power Supply pin
20 VCCE - +3.3v/+5.0v Power Supply pin
21 VSS - GND pin
36 VCC5 - +5.0v Power Supply pin
37 VSS - GND pin
41 DVCC - Power Supply pin for SMC high current
42 DVSS - GND pin for SMC high current
51 DVCC - Power Supply pin for SMC high current
52 DVSS - GND pin for SMC high current
61 DVCC - Power Supply pin for SMC high current
62 DVSS - GND pin for SMC high current
71 DVCC - Power Supply pin for SMC high current
72 DVSS - GND pin for SMC high current
82 AVSS/AVRL - ADC, DAC GND pin / Low Reference Voltage pin
83 AVRH - ADC High Reference Voltage pin
84 AVCC - ADC,DAC Analog Power Supply pin
93 VCC5 - +5.0v Power Supply pin
94 VSS - GND pin
108 VCC5 - +5.0v Power Supply pin
109 VSS - GND pin
119 VSS - GND pin
128 VCC5 - +5.0v Power Supply pin
129 VSS - GND pin
130 C - External Capacitance Connection Pin
144 VSS - GND pin
*1: I/O circuit type H is applied to MB91F575/7 and type I4 applied to MB91F578/9.

June 19, 2015, MB91F577_DS705-00009-3v0-E 27

CONFIDENTIAL
 D a t a S h e e t

 PIN DESCRIPTION (LQFP-208)

Pin Number Pin Name I/O Circuit Type Function Description
1 VCCE - +3.3v/+5.0v Power Supply pin
P171 General-Purpose I/O Port
2 M2
A03 External Bus Address Output pin
P172 General-Purpose I/O Port
3 M2
A04 External Bus Address Output pin
P173 General-Purpose I/O Port
4 M2
A05 External Bus Address Output pin
P174 General-Purpose I/O Port
5 M2
A06 External Bus Address Output pin
P175 General-Purpose I/O Port
6 M2
A07 External Bus Address Output pin
P176 General-Purpose I/O Port
7 M2
A08 External Bus Address Output pin
P177 General-Purpose I/O Port
8 M2
A09 External Bus Address Output pin
P180 General-Purpose I/O Port
9 M2
A10 External Bus Address Output pin
P181 General-Purpose I/O Port
10 M2
A11 External Bus Address Output pin
P182 General-Purpose I/O Port
11 M2
A12 External Bus Address Output pin
P183 General-Purpose I/O Port
12 M2
A13 External Bus Address Output pin
P184 General-Purpose I/O Port
13 M2
A14 External Bus Address Output pin
P185 General-Purpose I/O Port
14 M2
A15 External Bus Address Output pin
P186 General-Purpose I/O Port
15 M2
A16 External Bus Address Output pin
P187 General-Purpose I/O Port
16 M2
A17 External Bus Address Output pin
P190 General-Purpose I/O Port
17 M2
A18 External Bus Address Output pin
P191 General-Purpose I/O Port
18 M2
A19 External Bus Address Output pin
P192 General-Purpose I/O Port
19 M2
A20 External Bus Address Output pin
P193 General-Purpose I/O Port
20 M2
A21 External Bus Address Output pin
21 VCCE - +3.3v/+5.0v Power Supply pin
22 VSS - GND pin
P194 General-Purpose I/O Port
23 M2
SYSCLK External Bus Clock Output pin
P195 General-Purpose I/O Port
24 M2
CS2X External Bus Chip-Select 2 Output pin
P196 General-Purpose I/O Port
25 M2
CS3X External Bus Chip-Select 3 Output pin
P197 General-Purpose I/O Port
26 M2
RDY External Bus RDY Input pin
27 VCC5 - +5.0v Power Supply pin
28 VSS - GND pin
P010 General-Purpose I/O Port
29 H
SEG0 LCDC Segment(Duty)Output pin

28 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

29 INT8_1 H External Interrupt Request Input pin ch.8 relocation 1
P011 General-Purpose I/O Port
30 SEG1 I LCDC Segment(Duty)Output pin
INT9_1 External Interrupt Request Input pin ch.9 relocation 1
P012 General-Purpose I/O Port
31 SEG2 I LCDC Segment(Duty)Output pin
INT10_1 External Interrupt Request Input pin ch.10 relocation 1
P013 General-Purpose I/O Port
32 SEG3 I LCDC Segment(Duty)Output pin
INT11_1 External Interrupt Request Input pin ch.11 relocation 1
P014 General-Purpose I/O Port
33 SEG4 I LCDC Segment(Duty)Output pin
INT12_1 External Interrupt Request Input pin ch.12 relocation 1
P015 General-Purpose I/O Port
34 SEG5 I LCDC Segment(Duty)Output pin
INT13_1 External Interrupt Request Input pin ch.13 relocation 1
P016 General-Purpose I/O Port
35 SEG6 I LCDC Segment(Duty)Output pin
INT14_1 External Interrupt Request Input pin ch.14 relocation 1
P017 General-Purpose I/O Port
36 SEG7 I LCDC Segment(Duty)Output pin
INT15_1 External Interrupt Request Input pin ch.15 relocation 1
P020 General-Purpose I/O Port
SEG8 LCDC Segment(Duty)Output pin
37 I
ICU6_0 Input Capture Input pin ch.6 relocation 0
OCU0_1 Output Compare Output pin ch.0 relocation 1
P021 General-Purpose I/O Port
SEG9 LCDC Segment(Duty)Output pin
38 I
ICU7_0 Input Capture Input pin ch.7 relocation 0
OCU1_1 Output Compare Output pin ch.1 relocation 1
P022 General-Purpose I/O Port
SEG10 LCDC Segment(Duty)Output pin
39 I
ICU8_0 Input Capture Input pin ch.8 relocation 0
OCU2_1 Output Compare Output pin ch.2 relocation 1
P023 General-Purpose I/O Port
SEG11 LCDC Segment(Duty)Output pin
40 I
ICU9_0 Input Capture Input pin ch.9 relocation 0
OCU3_1 Output Compare Output pin ch.3 relocation 1
P024 General-Purpose I/O Port
SEG12 LCDC Segment(Duty)Output pin
41 I
ICU10_0 Input Capture Input pin ch.10 relocation 0
OCU11_0 Output Compare Output pin ch.11 relocation 0
P025 General-Purpose I/O Port
SEG13 LCDC Segment(Duty)Output pin
42 I
ICU11_0 Input Capture Input pin ch.11 relocation 0
OCU10_0 Output Compare Output pin ch.10 relocation 0
P026 General-Purpose I/O Port
SEG14 LCDC Segment(Duty)Output pin
43 I
SIN6_1 LIN_UART Serial Input pin ch.6 relocation 1
OCU9_0 Output Compare Output pin ch.9 relocation 0
P027 General-Purpose I/O Port
SEG15 I LCDC Segment(Duty)Output pin
44
SOT6_1 LIN_UART Serial Output pin ch.6 relocation 1
OCU8_0 I Output Compare Output pin ch.8 relocation 8
45 P030 I General-Purpose I/O Port

June 19, 2015, MB91F577_DS705-00009-3v0-E 29

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

SEG16 LCDC Segment(Duty)Output pin
45 I
SCK6_1 LIN_UART Serial Clock I/O pin ch.6 relocation 1
P031 General-Purpose I/O Port
46 SEG17 I LCDC Segment(Duty)Output pin
SIN9_0 Multi-function Serial Input pin ch.9 relocation 0
P032 General-Purpose I/O Port
SEG18 LCDC Segment(Duty)Output pin
47 I
SOT9_0 Multi-function Serial Output pin ch.9 relocation 0
OCU7_0 Output Compare Output pin ch.7 relocation 7
P033 General-Purpose I/O Port
SEG19 LCDC Segment(Duty)Output pin
48 I
SCK9_0 Multi-function Serial Clock I/O pin ch.9 relocation 0
OCU6_0 Output Compare Output pin ch.6 relocation 6
P034 General-Purpose I/O Port
SEG20 LCDC Segment(Duty)Output pin
49 I
SIN8_0 Multi-function Serial Input pin ch.8 relocation 0
OCU5_1 Output Compare Output pin ch.5 relocation 1
P035 General-Purpose I/O Port
SEG21 LCDC Segment(Duty)Output pin
50 I
SOT8_0 Multi-function Serial Output pin ch.8 relocation 0
OCU4_1 Output Compare Output pin ch.4 relocation 1
P036 General-Purpose I/O Port
SEG22 LCDC Segment(Duty)Output pin
51 I
PPG11_0 PPG Output pin ch.11 relocation 0
SCK8_0 Multi-function Serial Clock I/O pin ch.8 relocation 0
52 VCC5 - +5.0v Power Supply pin
53 VSS - GND pin
P037 General-Purpose I/O Port
SEG23 LCDC Segment(Duty)Output pin
54 ST0 I LCDC Segment(Static)Output pin
PPG12_0 PPG Output pin ch.12 relocation 0
SIN7_0 LIN_UART Serial Input pin ch.7 relocation 0
P040 General-Purpose I/O Port
SEG24 LCDC Segment(Duty)Output pin
55 ST1 I LCDC Segment(Static)Output pin
PPG13_0 PPG Output pin ch.13 relocation 0
SOT7_0 LIN_UART Serial Output pin ch.7 relocation 0
P041 General-Purpose I/O Port
SEG25 LCDC Segment(Duty)Output pin
56 ST2 I LCDC Segment(Static)Output pin
PPG14_0 PPG Output pin ch.14 relocation 0
SCK7_0 LIN_UART Serial Clock I/O pin ch.7 relocation 0
57 VCC5 - +5.0v Power Supply pin
58 VSS - GND pin
P042 General-Purpose I/O Port
SEG26 LCDC Segment(Duty)Output pin
59 ST3 I LCDC Segment(Static)Output pin
PPG15_0 PPG Output pin ch.15 relocation 0
AIN0_0 Up/down Counter AIN Input pin ch.0 relocation 0
P043 General-Purpose I/O Port
SEG27 LCDC Segment(Duty)Output pin
ST4 LCDC Segment(Static)Output pin
60 I
BIN0_0 Up/down Counter BIN Input pin ch.0 relocation 0
SGA4_0 Sound Generator SGA Output pin ch.4 relocation 0
OCU6_1 Output Compare Output pin ch.6 relocation 1

30 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

P044 General-Purpose I/O Port
SEG28 LCDC Segment(Duty)Output pin
ST5 LCDC Segment(Static)Output pin
61 I
ZIN0_0 Up/down Counter ZIN Input pin ch.0 relocation 0
SGO4_0 Sound Generator SGO Output pin ch.4 relocation 0
OCU7_1 Output Compare Output pin ch.7 relocation 1
P045 General-Purpose I/O Port
SEG29 LCDC Segment(Duty)Output pin
62 ST6 I LCDC Segment(Static)Output pin
AIN1_0 Up/down Counter AIN Input pin ch.1 relocation 0
SIN8_2 Multi-function Serial Input pin ch.8 relocation 2
P046 General-Purpose I/O Port
SEG30 LCDC Segment(Duty)Output pin
63 ST7 I LCDC Segment(Static)Output pin
BIN1_0 Up/down Counter BIN Input pin ch.1 relocation 0
SOT8_2 Multi-function Serial Output pin ch.8 relocation 2
P047 General-Purpose I/O Port
SEG31 LCDC Segment(Duty)Output pin
64 ST8 I LCDC Segment(Static)Output pin
ZIN1_0 Up/down Counter ZIN Input pin ch.1 relocation 0
SCK8_2 Multi-function Serial Clock I/O pin ch.8 relocation 2
P050 General-Purpose I/O Port
65 COM0 I LCDC Segment(Duty)Common Output pin
OCU8_1 Output Compare Output pin ch.8 relocation 1
P051 General-Purpose I/O Port
66 COM1 I LCDC Segment(Duty)Common Output pin
OCU9_1 Output Compare Output pin ch.9 relocation 1
P052 General-Purpose I/O Port
67 COM2 I LCDC Segment(Duty)Common Output pin
OCU10_1 Output Compare Output pin ch.10 relocation 1
P053 General-Purpose I/O Port
68 COM3 I LCDC Segment(Duty)Common Output pin
OCU11_1 Output Compare Output pin ch.11 relocation 1
P054 General-Purpose I/O Port
69 V0 I2 LCDC Reference Voltage V0 Input pin
FRCK0_1 Free-Run Timer Clock Input pin ch.0 relocation 1
P055 General-Purpose I/O Port
70 V1 I2 LCDC Reference Voltage V1 Input pin
FRCK1_1 Free-Run Timer Clock Input pin ch.1 relocation 1
P056 General-Purpose I/O Port
71 V2 I2 LCDC Reference Voltage V2 Input pin
FRCK2_1 Free-Run Timer Clock Input pin ch.2 relocation 1
P057 General-Purpose I/O Port
72 V3 I3 LCDC Reference Voltage V3 Input pin
FRCK3_1 Free-Run Timer Clock Input pin ch.3 relocation 1
73 DVCC - Power Supply pin for SMC high current
74 DVSS - GND pin for SMC high current
P060 General-Purpose I/O Port
75 PWM1P0 K SMC Output pin ch.0
AN8 ADC Analog Input pin ch.8
P061 General-Purpose I/O Port
PWM1M0 SMC Output pin ch.0
76 K
AN9 ADC Analog Input pin ch.9
SIN1_1 Multi-function Serial Input pin ch.1 relocation 1
77 P062 K General-Purpose I/O Port

June 19, 2015, MB91F577_DS705-00009-3v0-E 31

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

PWM2P0 SMC Output pin ch.0
AN10 ADC Analog Input pin ch.10
77 K
SOT1_1 Multi-function Serial Output pin ch.1 relocation 1
ZIN1_1 Up/down Counter ZIN Input pin ch.1 relocation 1
P063 General-Purpose I/O Port
PWM2M0 SMC Output pin ch.0
78 AN11 K ADC Analog Input pin ch.11
SCK1_1 Multi-function Serial Clock I/O pin ch.1 relocation 1
BIN1_1 Up/down Counter BIN Input pin ch.1 relocation 1
P064 General-Purpose I/O Port
PWM1P1 SMC Output pin ch.1
79 AN12 K ADC Analog Input pin ch.12
SIN0_1 Multi-function Serial Input pin ch.0 relocation 1
AIN1_1 Up/down Counter AIN Input pin ch.1 relocation 1
P065 General-Purpose I/O Port
PWM1M1 SMC Output pin ch.1
80 AN13 K ADC Analog Input pin ch.13
SOT0_1 Multi-function Serial Output pin ch.0 relocation 1
ZIN0_1 Up/down Counter ZIN Input pin ch.0 relocation 1
P066 General-Purpose I/O Port
PWM2P1 SMC Output pin ch.1
81 AN14 K ADC Analog Input pin ch.14
SCK0_1 Multi-function Serial Clock I/O pin ch.0 relocation 1
BIN0_1 Up/down Counter BIN Input pin ch.0 relocation 1
P067 General-Purpose I/O Port
PWM2M1 SMC Output pin ch.1
82 AN15 K ADC Analog Input pin ch.15
SIN9_1 Multi-function Serial Input pin ch.9 relocation 1
AIN0_1 Up/down Counter AIN Input pin ch.0 relocation 1
83 DVCC - Power Supply pin for SMC high current
84 DVSS - GND pin for SMC high current
P070 General-Purpose I/O Port
PWM1P2 SMC Output pin ch.2
85 K
AN16 ADC Analog Input pin ch.16
SOT9_1 Multi-function Serial Output pin ch.9 relocation 1
P071 General-Purpose I/O Port
PWM1M2 SMC Output pin ch.2
86 K
AN17 ADC Analog Input pin ch.17
SCK9_1 Multi-function Serial Clock I/O pin ch.9 relocation 1
P072 General-Purpose I/O Port
PWM2P2 SMC Output pin ch.2
87 AN18 K ADC Analog Input pin ch.18
SIN8_1 Multi-function Serial Input pin ch.8 relocation 1
ICU11_1 Input Capture Input pin ch.11 relocation 1
P073 General-Purpose I/O Port
PWM2M2 SMC Output pin ch.2
88 AN19 K ADC Analog Input pin ch.19
SOT8_1 Multi-function Serial Output pin ch.8 relocation 1
ICU10_1 Input Capture Input pin ch.10 relocation 1
P074 General-Purpose I/O Port
PWM1P3 SMC Output pin ch.3
AN20 ADC Analog Input pin ch.20
89 K
SCK8_1 Multi-function Serial Clock I/O pin ch.8 relocation 1
ICU9_1 Input Capture Input pin ch.9 relocation 1
PPG12_1 PPG Output pin ch.12 relocation 1

32 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

P075 General-Purpose I/O Port
PWM1M3 SMC Output pin ch.3
AN21 ADC Analog Input pin ch.21
90 K
SIN7_1 LIN_UART Serial Input pin ch.7 relocation 1
ICU8_1 Input Capture Input pin ch.8 relocation 1
PPG13_1 PPG Output pin ch.13 relocation 1
P076 General-Purpose I/O Port
PWM2P3 SMC Output pin ch.3
AN22 ADC Analog Input pin ch.22
91 K
SOT7_1 LIN_UART Serial Output pin ch.7 relocation 1
ICU7_1 Input Capture Input pin ch.7 relocation 1
PPG14_1 PPG Output pin ch.14 relocation 1
P077 General-Purpose I/O Port
PWM2M3 SMC Output pin ch.3
AN23 ADC Analog Input pin ch.23
92 K
SCK7_1 LIN_UART Serial Clock I/O pin ch.7 relocation 1
ICU6_1 Input Capture Input pin ch.6 relocation 1
PPG15_1 PPG Output pin ch.15 relocation 1
93 DVCC - Power Supply pin for SMC high current
94 DVSS - GND pin for SMC high current
P080 General-Purpose I/O Port
PWM1P4 SMC Output pin ch.4
AN24 ADC Analog Input pin ch.24
95 K
SIN6_0 LIN_UART Serial Input pin ch.6 relocation 0
PPG16_0 PPG Output pin ch.16 relocation 0
AIN0_2 Up/down Counter AIN Input pin ch.0 relocation 2
P081 General-Purpose I/O Port
PWM1M4 SMC Output pin ch.4
AN25 ADC Analog Input pin ch.25
96 K
SOT6_0 LIN_UART Serial Output pin ch.6 relocation 0
PPG17_0 PPG Output pin ch.17 relocation 0
BIN0_2 Up/down Counter BIN Input pin ch.0 relocation 2
P082 General-Purpose I/O Port
PWM2P4 SMC Output pin ch.4
AN26 ADC Analog Input pin ch.26
97 K
SCK6_0 LIN_UART Serial Clock I/O pin ch.6 relocation 0
PPG18_0 PPG Output pin ch.18 relocation 0
ZIN0_2 Up/down Counter ZIN Input pin ch.0 relocation 2
P083 General-Purpose I/O Port
PWM2M4 SMC Output pin ch.4
98 AN27 K ADC Analog Input pin ch.27
ICU0_2 Input Capture Input pin ch.0 relocation 2
PPG19_0 PPG Output pin ch.19 relocation 0
P084 General-Purpose I/O Port
PWM1P5 SMC Output pin ch.5
99 AN28 K ADC Analog Input pin ch.28
ICU1_2 Input Capture Input pin ch.1 relocation 2
PPG20_0 PPG Output pin ch.20 relocation 0
P085 General-Purpose I/O Port
PWM1M5 SMC Output pin ch.5
100 AN29 K ADC Analog Input pin ch.29
ICU2_2 Input Capture Input pin ch.2 relocation 2
PPG21_0 PPG Output pin ch.21 relocation 0
P086 General-Purpose I/O Port
101 K
PWM2P5 SMC Output pin ch.5

June 19, 2015, MB91F577_DS705-00009-3v0-E 33

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

AN30 ADC Analog Input pin ch.30
101 ICU3_2 K Input Capture Input pin ch.3 relocation 2
PPG22_0 PPG Output pin ch.22 relocation 0
P087 General-Purpose I/O Port
PWM2M5 SMC Output pin ch.5
102 AN31 K ADC Analog Input pin ch.31
ICU4_2 Input Capture Input pin ch.4 relocation 2
PPG23_0 PPG Output pin ch.23 relocation 0
103 DVCC - Power Supply pin for SMC high current
104 DVSS - GND pin for SMC high current
105 Non connection - Non connection
P090 General-Purpose I/O Port
106 ADTG M ADC External Trigger Input pin
PPG0_2 PPG Output pin ch.0 relocation 2
P100 General-Purpose I/O Port
SIN4_1 LIN_UART Serial Input pin ch.4 relocation 1
107 AN0 J ADC Analog Input pin ch.0
TIN0_1 Reload Timer Event Input pin ch.0 relocation 1
PPG8_0 PPG Output pin ch.8 relocation 0
108 Non connection - Non connection
P101 General-Purpose I/O Port
SOT4_1 LIN_UART Serial Output pin ch.4 relocation 1
109 AN1 J ADC Analog Input pin ch.1
TIN1_1 Reload Timer Event Input pin ch.1 relocation 1
PPG9_0 PPG Output pin ch.9 relocation 0
110 Non connection - Non connection
P102 General-Purpose I/O Port
SCK4_1 LIN_UART Serial Clock I/O pin ch.4 relocation 1
AN2 ADC Analog Input pin ch.2
111 J
TIN2_1 Reload Timer Event Input pin ch.2 relocation 1
PPG10_0 PPG Output pin ch.10 relocation 0
ICU6_2 Input Capture Input pin ch.6 relocation 2
P103 General-Purpose I/O Port
SIN5_1 LIN_UART Serial Input pin ch.5 relocation 1
AN3 ADC Analog Input pin ch.3
112 J
TIN3_1 Reload Timer Event Input pin ch.3 relocation 1
PPG1_1 PPG Output pin ch.1 relocation 1
ICU7_2 Input Capture Input pin ch.7 relocation 2
113 Non connection - Non connection
P104 General-Purpose I/O Port
SOT5_1 LIN_UART Serial Output pin ch.5 relocation 1
AN4 ADC Analog Input pin ch.4
114 J
TOT0_1 Reload Timer Output pin ch.0 relocation 0
PPG2_1 PPG Output pin ch.2 relocation 1
ICU8_2 Input Capture Input pin ch.8 relocation 2
P105 General-Purpose I/O Port
SCK5_1 LIN_UART Serial Clock I/O pin ch.5 relocation 1
AN5 ADC Analog Input pin ch.5
115 J
TOT1_1 Reload Timer Output pin ch.1 relocation 1
PPG3_1 PPG Output pin ch.3 relocation 1
ICU9_2 Input Capture Input pin ch.9 relocation 2
116 Non connection - Non connection
P106 General-Purpose I/O Port
117 AN6 J ADC Analog Input pin ch.6
PPG4_1 PPG Output pin ch.4 relocation 1

34 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

ICU10_2 Input Capture Input pin ch.10 relocation 2
117 J
SGA4_1 Sound Generator SGA Output pin ch.4 relocation 1
P107 General-Purpose I/O Port
AN7 ADC Analog Input pin ch.7
PPG5_1 PPG Output pin ch.5 relocation 1
118 L
DAO1 DAC Output pin ch.1
ICU11_2 Input Capture Input pin ch.11 relocation 2
SGO4_1 Sound Generator SGO Output pin ch.4 relocation 1
119 Non connection - Non connection
AVSS ADC, DAC GND pin
120 -
AVRL ADC Low Reference Voltage pin
121 AVRH - ADC High Reference Voltage pin
122 AVCC - ADC,DAC Analog Power Supply pin
123 Non connection - Non connection
P123 General-Purpose I/O Port
OCU1_0 Output Compare Output pin ch.1 relocation 0
124 PPG8_2 L PPG Output pin ch.8 relocation 2
DAO0 DAC Output pin ch.0
AN39 ADC Analog Input pin ch.39
P122 General-Purpose I/O Port
OCU0_0 Output Compare Output pin ch.0 relocation 0
SCK5_0 LIN_UART Serial Clock I/O pin ch.5 relocation 0
125 J
TOT3_0 Reload Timer Output pin ch.3 relocation 0
PPG7_2 PPG Output pin ch.7 relocation 2
AN38 ADC Analog Input pin ch.38
P121 General-Purpose I/O Port
FRCK0_0 Free-Run Timer Clock Input pin ch.0 relocation 0
SOT5_0 LIN_UART Serial Output pin ch.5 relocation 0
126 INT7_0 J External Interrupt Request Input pin ch.7 relocation 0
TOT2_0 Reload Timer Output pin ch.2 relocation 0
PPG6_2 PPG Output pin ch.6 relocation 2
AN37 ADC Analog Input pin ch.37
P120 General-Purpose I/O Port
FRCK1_0 Free-Run Timer Clock Input pin ch.1 relocation 0
SIN5_0 LIN_UART Serial Input pin ch.5 relocation 0
127 INT6_0 J External Interrupt Request Input pin ch.6 relocation 0
TOT1_0 Reload Timer Output pin ch.1 relocation 0
PPG5_2 PPG Output pin ch.5 relocation 2
AN36 ADC Analog Input pin ch.36
P117 General-Purpose I/O Port
SCK4_0 LIN_UART Serial Clock I/O pin ch.4 relocation 0
TOT0_0 Reload Timer Output pin ch.0 relocation 0
128 SGO3 J Sound Generator SGO Output pin ch.3
FRCK2_0 Free-Run Timer Clock Input pin ch.2 relocation 0
AN35 ADC Analog Input pin ch.35
TRG4 PPG Trigger Input pin 4 (ch.16-ch.19)
P116 General-Purpose I/O Port
SOT4_0 LIN_UART Serial Output pin ch.4 relocation 0
TIN3_0 Reload Timer Event Input pin ch.3 relocation 0
129 J
SGA3 Sound Generator SGA Output pin ch.3
FRCK3_0 Free-Run Timer Clock Input pin ch.3 relocation 0
AN34 ADC Analog Input pin ch.34
P115 General-Purpose I/O Port
130 SIN4_0 J LIN_UART Serial Input pin ch.4 relocation 0
TIN2_0 Reload Timer Event Input pin ch.2 relocation 0

June 19, 2015, MB91F577_DS705-00009-3v0-E 35

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

SGO2 Sound Generator SGO Output pin ch.2
130 FRCK4_0 J Free-Run Timer Clock Input pin ch.4 relocation 0
AN33 ADC Analog Input pin ch.33
P114 General-Purpose I/O Port
SCK3_0 LIN_UART Serial Clock I/O pin ch.3 relocation 0
TIN1_0 Reload Timer Event Input pin ch.1 relocation 0
131 ICU5_1 J Input Capture Input pin ch.5 relocation 1
SGA2 Sound Generator SGA Output pin ch.2
AN32 ADC Analog Input pin ch.32
TRG3 PPG Trigger Input pin 3 (ch.12-ch.15)
P000 General-Purpose I/O Port
SIN2_1 LIN_UART Serial Input pin ch.2 relocation 1
132 TIN0_2 M Reload Timer Event Input pin ch.0 relocation 2
PPG0_0 PPG Output pin ch.0 relocation 0
INT0_1 External Interrupt Request Input pin ch.0 relocation 1
P001 General-Purpose I/O Port
SOT2_1 LIN_UART Serial Output pin ch.2 relocation 1
133 TIN1_2 M Reload Timer Event Input pin ch.1 relocation 2
PPG1_0 PPG Output pin ch.1 relocation 0
INT1_1 External Interrupt Request Input pin ch.1 relocation 1
P002 General-Purpose I/O Port
SCK2_1 LIN_UART Serial Clock I/O pin ch.2 relocation 1
134 TIN2_2 M Reload Timer Event Input pin ch.2 relocation 2
PPG2_0 PPG Output pin ch.2 relocation 0
INT2_1 External Interrupt Request Input pin ch.2 relocation 1
P003 General-Purpose I/O Port
SIN3_1 LIN_UART Serial Input pin ch.3 relocation 1
135 TIN3_2 M Reload Timer Event Input pin ch.3 relocation 2
PPG3_0 PPG Output pin ch.3 relocation 0
INT3_1 External Interrupt Request Input pin ch.3 relocation 1
136 VCC5 - +5.0v Power Supply pin
137 VSS - GND pin
P137 General-Purpose I/O Port
138 M(Y)
(X0A) Sub Clock oscillation Input pin (only dual clock product)
P136 General-Purpose I/O Port
139 M(Y)
(X1A) Sub Clock oscillation Output pin (only dual clock product)
140 NMIX R NMI Pin
P004 General-Purpose I/O Port
SOT3_1 LIN_UART Serial Output pin ch.3 relocation 1
141 TOT0_2 M Reload Timer Output pin ch.0 relocation 2
PPG4_0 PPG Output pin ch.4 relocation 0
INT4_1 External Interrupt Request Input pin ch.4 relocation 1
P005 General-Purpose I/O Port
SCK3_1 LIN_UART Serial Clock I/O pin ch.3 relocation 1
142 TOT1_2 M Reload Timer Output pin ch.1 relocation 2
PPG5_0 PPG Output pin ch.5 relocation 0
INT5_1 External Interrupt Request Input pin ch.5 relocation 1
P006 General-Purpose I/O Port
TOT2_2 Reload Timer Output pin ch.2 relocation 2
143 M
PPG6_0 PPG Output pin ch.6 relocation 0
INT6_1 External Interrupt Request Input pin ch.6 relocation 1
P007 General-Purpose I/O Port
TOT3_2 Reload Timer Output pin ch.3 relocation 2
144 M
PPG7_0 PPG Output pin ch.7 relocation 0
INT7_1 External Interrupt Request Input pin ch.7 relocation 1

36 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

145 Non connection - Non connection
P097 General-Purpose I/O Port
WOT RTC Overflow Output pin
SOT3_0 LIN_UART Serial Output pin ch.3 relocation 0
146 INT8_0 M External Interrupt Request Input pin ch.8 relocation 0
TIN0_0 Reload Timer Event Input pin ch.0 relocation 0
ICU4_1 Input Capture Input pin ch.4 relocation 1
PPG0_1 PPG Output pin ch.0 relocation 1
P094 General-Purpose I/O Port
SGO1 Sound Generator SGO Output pin ch.1
SIN3_0 LIN_UART Serial Input pin ch.3 relocation 0
147 M
INT15_0 External Interrupt Request Input pin ch.15 relocation 0
ICU1_1 Input Capture Input pin ch.1 relocation 1
PPG9_1 PPG Output pin ch.9 relocation 1
P093 General-Purpose I/O Port
SGA1 Sound Generator SGA Output pin ch.1
SOT2_0 LIN_UART Serial Output pin ch.2 relocation 0
148 M
INT14_0 External Interrupt Request Input pin ch.14 relocation 0
ICU3_1 Input Capture Input pin ch.3 relocation 1
PPG8_1 PPG Output pin ch.8 relocation 1
P092 General-Purpose I/O Port
SGO0 Sound Generator SGO Output pin ch.0
SCK2_0 LIN_UART Serial Clock I/O pin ch.0 relocation 0
149 INT13_0 M External Interrupt Request Input pin ch.13 relocation 0
TOT3_1 Reload Timer Output pin ch.3 relocation 1
ICU0_1 Input Capture Input pin ch.0 relocation 1
PPG7_1 PPG Output pin ch.7 relocation 1
P091 General-Purpose I/O Port
SGA0 Sound Generator SGA Output pin ch.0
SIN2_0 LIN_UART Serial Input pin ch.2 relocation 0
150 INT12_0 M External Interrupt Request Input pin ch.12 relocation 0
TOT2_1 Reload Timer Output pin ch.2 relocation 1
ICU2_1 Input Capture Input pin ch.2 relocation 1
PPG6_1 PPG Output pin ch.6 relocation 1
P110 General-Purpose I/O Port
TX1 CAN TX Data Output pin ch.1
151 M
PPG1_2 PPG Output pin ch.1 relocation 2
FRCK5_0 Free-Run Timer Clock Input pin ch.5 relocation 0
P111 General-Purpose I/O Port
RX1 CAN RX Data Input pin ch.1
152 M
INT10_0 External Interrupt Request Input pin ch.10 relocation 0
PPG2_2 PPG Output pin ch.2 relocation 2
P112 General-Purpose I/O Port
153 TX2 M CAN TX Data Output pin ch.2
PPG3_2 PPG Output pin ch.3 relocation 2
P113 General-Purpose I/O Port
RX2 CAN RX Data Input pin ch.2
154 M
INT11_0 External Interrupt Request Input pin ch.11 relocation 0
PPG4_2 PPG Output pin ch.4 relocation 2
155 RSTX R Reset Pin
156 VCC5 - +5.0v Power Supply pin
157 VSS - GND pin
158 DEBUGIF B DEBUG I/F pin

June 19, 2015, MB91F577_DS705-00009-3v0-E 37

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

P095 General-Purpose I/O Port
159 TX0 M CAN TX Data Output pin ch.0
PPG10_1 PPG Output pin ch.10 relocation 1
P096 General-Purpose I/O Port
160 RX0 M CAN RX Data Input pin ch.0
INT9_0 External Interrupt Request Input pin ch.9 relocation 0
P124 General-Purpose I/O Port
OCU2_0 Output Compare Output pin ch.2 relocation 0
161 M
ICU5_2 Input Capture Input pin ch.5 relocation 2
PPG9_2 PPG Output pin ch.9 relocation 2
162 Non connection - Non connection
163 Non connection - Non connection
164 Non connection - Non connection
165 Non connection - Non connection
166 MD0 A Mode Pin 0
167 MD1 A Mode Pin 1
168 MD2 R2 Mode Pin 2
169 X0 X Main Clock oscillation Input pin
170 X1 X Main Clock oscillation Output pin
171 VSS - GND pin
P125 General-Purpose I/O Port
OCU3_0 Output Compare Output pin ch.3 relocation 0
172 M
ICU0_0 Input Capture Input pin ch.0 relocation 0
PPG10_2 PPG Output pin ch.10 relocation 2
P126 General-Purpose I/O Port
TRG0 PPG Trigger Input pin 0 (ch.0-ch.3)
173 SIN0_0 M Multi-function Serial Input pin ch.0 relocation 0
INT1_0 External Interrupt Request Input pin ch.1 relocation 0
OCU4_0 Output Compare Output pin ch.4 relocation 0
P127 General-Purpose I/O Port
174 SOT0_0 N Multi-function Serial Output pin ch.0 relocation 0
OCU5_0 Output Compare Output pin ch.5 relocation 0
P130 General-Purpose I/O Port
SCK0_0 Multi-function Serial Clock I/O pin ch.0 relocation 0
175 INT0_0 N External Interrupt Request Input pin ch.0 relocation 0
ICU1_0 Input Capture Input pin ch.1 relocation 0
TIOA0 Base Timer I/O pin ch.0
P131 General-Purpose I/O Port
TRG1 PPG Trigger Input pin 1 (ch.4-ch.7)
SIN1_0 Multi-function Serial Input pin ch.1 relocation 0
176 M
INT4_0 External Interrupt Request Input pin ch.4 relocation 0
ICU2_0 Input Capture Input pin ch.2 relocation 0
TIOA1 Base Timer I/O pin ch.1
P132 General-Purpose I/O Port
SOT1_0 Multi-function Serial Output pin ch.1 relocation 0
177 INT2_0 N External Interrupt Request Input pin ch.2 relocation 0
ICU3_0 Input Capture Input pin ch.3 relocation 0
TIOB0 Base Timer I/O pin ch.0
P133 General-Purpose I/O Port
SCK1_0 Multi-function Serial Clock I/O pin ch.1 relocation 0
INT3_0 External Interrupt Request Input pin ch.3 relocation 0
178 ICU4_0 N Input Capture Input pin ch.4 relocation 0
TIOB1 Base Timer I/O pin ch.1
TRG5 PPG Trigger Input pin 5 (ch.20-ch.23)
PPG11_1 PPG Output pin ch.11 relocation 1

38 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Pin Number Pin Name I/O Circuit Type Function Description

P134 General-Purpose I/O Port
TRG2 PPG Trigger Input pin 2 (ch.8-ch.11)
179 INT5_0 M External Interrupt Request Input pin ch.5 relocation 0
ICU5_0 Input Capture Input pin ch.5 relocation 0
PPG1_3 PPG Output pin ch.1 relocation 3
180 VCC5 - +5.0v Power Supply pin
181 VSS - GND pin
182 C - External Capacitance Connection Pin
P140 General-Purpose I/O Port
183 D16_0 M2 External Bus Data I/O pin
D24_1 External Bus Data I/O pin
P141 General-Purpose I/O Port
184 D17_0 M2 External Bus Data I/O pin
D25_1 External Bus Data I/O pin
P142 General-Purpose I/O Port
185 D18_0 M2 External Bus Data I/O pin
D26_1 External Bus Data I/O pin
P143 General-Purpose I/O Port
186 D19_0 M2 External Bus Data I/O pin
D27_1 External Bus Data I/O pin
P144 General-Purpose I/O Port
187 D20_0 M2 External Bus Data I/O pin
D28_1 External Bus Data I/O pin
P145 General-Purpose I/O Port
188 D21_0 M2 External Bus Data I/O pin
D29_1 External Bus Data I/O pin
P146 General-Purpose I/O Port
189 D22_0 M2 External Bus Data I/O pin
D30_1 External Bus Data I/O pin
P147 General-Purpose I/O Port
190 D23_0 M2 External Bus Data I/O pin
D31_1 External Bus Data I/O pin
P150 General-Purpose I/O Port
191 D24_0 M2 External Bus Data I/O pin
D16_1 External Bus Data I/O pin
P151 General-Purpose I/O Port
192 D25_0 M2 External Bus Data I/O pin
D17_1 External Bus Data I/O pin
P152 General-Purpose I/O Port
193 D26_0 M2 External Bus Data I/O pin
D18_1 External Bus Data I/O pin
P153 General-Purpose I/O Port
194 D27_0 M2 External Bus Data I/O pin
D19_1 External Bus Data I/O pin
P154 General-Purpose I/O Port
195 D28_0 M2 External Bus Data I/O pin
D20_1 External Bus Data I/O pin
P155 General-Purpose I/O Port
196 D29_0 M2 External Bus Data I/O pin
D21_1 External Bus Data I/O pin
P156 General-Purpose I/O Port
197 D30_0 M2 External Bus Data I/O pin
D22_1 External Bus Data I/O pin

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Pin Number Pin Name I/O Circuit Type Function Description

P157 General-Purpose I/O Port
198 D31_0 M2 External Bus Data I/O pin
D23_1 External Bus Data I/O pin
P160 General-Purpose I/O Port
199 M2
ASX External Bus Address-Strobe Output pin
P161 General-Purpose I/O Port
200 M2
CS0X External Bus Chip-Select 0 Output pin
P162 General-Purpose I/O Port
201 M2
CS1X External Bus Chip-Select 1 Output pin
P163 General-Purpose I/O Port
202 M2
RDX External Bus Read-Strobe Output pin
P164 General-Purpose I/O Port
203 M2
WR0X External Bus Write-Strobe 0 Output pin
P165 General-Purpose I/O Port
204 M2
WR1X External Bus Write-Strobe 1 Output pin
P166 General-Purpose I/O Port
205 M2
A00 External Bus Address Output pin
P167 General-Purpose I/O Port
206 M2
A01 External Bus Address Output pin
P170 General-Purpose I/O Port
207 M2
A02 External Bus Address Output pin
208 VSS - GND pin

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 I/O CIRCUIT TYPE

Type Circuit Remarks
H General-purpose I/O port with COM/SEG output and
with against 3V pad power supply (5V tolerant).

IOH = -1/-2mA(@VCCE=5V),
IOH = -0.5/-1/-2mA(@VCCE=3.3V),
IOL = 1/2mA(@VCCE=5V),
IOL = 0.5/1/2mA(@VCCE=3.3V)
Pull-down resistor control
Automotive level input
TTL input
TTL level input
CMOS level hysteresis input
CMOS level input

I General-purpose I/O port with COM/SEG output.

IOH = -1/-2mA, IOL = 1/2mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input

TTL input

I2 General-purpose I/O port with LCDC reference

voltage input

IOH = -1/-2mA, IOL = 1/2mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input
TTL input

LCDC ref. voltage input

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Type Circuit Remarks

I3 General-purpose input port with LCDC V3 input

Pull-up resistor control

Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input

TTL input

I4 General-purpose I/O port with COM/SEG output.

IOH = -1/-2mA(@VCCE=5V),
IOH = -0.5/-1mA(@VCCE=3.3V),
IOL = 1/2mA(@VCCE=5V),
IOL = 0.5/1mA(@VCCE=3.3V)
Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
TTL input
CMOS level hysteresis input
CMOS level input

J General-purpose I/O port with analog input.

IOH = -1/-2mA, IOL = 1/2mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input

TTL input

Analog input

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Type Circuit Remarks

K General-purpose I/O port with analog input and with
high current capable for SMC.

IOH = -1/-2/-30mA, IOL = 1/2/30mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input
TTL input

Analog input

L General-purpose I/O port with analog input and with

DAC output

IOH = -1/-2mA, IOL = 1/2mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input

TTL input

M General-purpose I/O port.

IOH = -1/-2mA, IOL = 1/2mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input

TTL input

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Type Circuit Remarks

M2 General-purpose I/O port.

IOH = -1/-2mA(@VCCE=5V),
IOH = -0.5/-1mA(@VCCE=3.3V),
IOL = 1/2mA(@VCCE=5V),
IOL = 0.5/1mA(@VCCE=3.3V)
Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
TTL input
CMOS level input

N General-purpose I/O port with I2C output

IOH = -1/-2/-3mA, IOL = 1/2/3mA

Pull-up resistor control
Pull-down resistor control
Automotive level input
TTL level input
CMOS level hysteresis input
CMOS level input

TTL input

A Mode pin

B DEBUG I/F pin

Digital output

TTL input

R CMOS level hysteresis input

Pull-up resistor 50 kΩ

Hysteresis input

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Type Circuit Remarks

R2 CMOS level hysteresis input
Hysteresis input

Pull-down resistor 50KΩ

X Main oscillation I/O

Standby control

Y Sub oscillation I/O

Standby control

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 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.

1. Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

 Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.

 Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.

 Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.

1. Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.

2. Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause
large current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.

3. Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.

 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high-voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:

1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include
attention to abnormal noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.

Code: DS00-00004-2Eb

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 Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.

 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.

 Precautions Related to Usage of Devices

Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.

2. Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.

 Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.

 Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.

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 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.

 Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:

1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for
storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.

Condition: 125°C/24 h

 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:

1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for
ion generation may be needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize
shock loads is recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.

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3. Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.

For reliable performance, do the following:

1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.

2. Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.

3. Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.

4. Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.

5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.

Please check the latest handling precautions at the following URL.

http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

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 HANDLING DEVICES
This section explains the latch-up prevention and the treatment of a pin.

 For latch-up prevention

If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding
the ratings is applied between VCC pin and VSS pin, a latch-up may occur in CMOS IC. If the latch-up
occurs, the power supply current increases excessively and device elements may be damaged by heat. Take
care to prevent any voltage from exceeding the maximum ratings in device application.

Also, the analog power supply voltage (AVcc, AVRH), analog input ,and the power supply voltage to
high-current output buffer pins (DVcc), the power supply voltage of external bus interface (VccE) must not
be exceed the digital power supply voltage (Vcc5) when the power supply voltage to the analog system and
high-current output buffer pins the power supply voltage of external bus interface (VccE) is turned on or
off.

In the correct power-on sequence, turn on the digital power supply voltage (Vcc5), analog power supply
voltage (AVcc, AVRH), the power supply voltage of external bus interface (VccE), and the power supply
voltage of high-current output buffer pins (DVcc) simultaneously. Or, turn on the digital power supply
voltage (Vcc5), and then turn on analog power supply voltage (AVcc, AVRH), the power supply voltage of
external bus interface (VccE), and the power supply voltage of high-current output buffer pins (DVcc).

 Treatment of unused pins

If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or
latch-up. Connect a 2kΩ resistor to each of unused pins for pull-up or pull-down connection.

Also, if I/O pins are not used, they must be set to the output state for opening or they must be set to the
input state and treated in the same way as for the input pins.

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 Power supply pins

The device is designed to ensure that if the device contains multiple VCC pin or VSS pin, the pins that
should be at the same potential are interconnected to prevent latch-up or other malfunctions. Further,
connect these pins to an external power source or ground to reduce unwanted radiation, prevent strobe
signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc.
As shown in figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or Vss
systems are connected, the device cannot operate correctly even within the guaranteed operating range.

Figure -1 Power Supply Input Pins

VCC
VSS

VCC VSS
VSS

VCC VCC

VSS
VSS VCC

The power supply pins should be connected to VCC pin and VSS pin of this device at the low impedance
from the power supply source.

In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between the VCC pin and the VSS pin.

 Crystal oscillation circuit

An external noise to the X0 pin or X1 pin may cause a device malfunction. The printed circuit board must
be designed to lay out the X0 pin and the X1 pin, crystal oscillator (or ceramic resonator), and the bypass
capacitor to be grounded to the close position to the device.

The printed circuit board artwork is recommended to surround the X0 pin and X1 pin by ground circuits.

 Mode pins (MD2, MD1, MD0)

Connect the MD2, MD1and MD0 mode pin to the VCC pin or VSS pin directly. To prevent an erroneous
selection of test mode caused by the noise, reduce the pattern length between each mode pin and VCC pin
or VSS pin on the printed circuit board. Also, use the low-impedance pin connection.

 During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to
have 50μs or longer (between 0.2V to 2.7V) during power-on.

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 Notes during PLL clock operation

When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock
may continue to operate at the free running frequency of the self-oscillator circuit built in the PLL clock.
This operation is not guaranteed.

 Treatment of A/D converter power supply pins

Connect the pins to have AVcc=AVRH=Vcc5 and AVss/AVRL=Vss even if the A/D converter is not used.

 Notes on using external clock

An external clock is not supported. None of the external direct clock input can be used for both main clock
and sub clock.

 Power-on sequence of A/D converter analog inputs

Be sure to turn on the digital power supply voltage (Vcc) first, and then turn on the A/D converter power
supply voltage (AVcc, AVRH, AVRL) and analog input voltage (AN0 to AN39). Also, turn off the A/D
converter power supplies and analog inputs first, and then turn off the digital power supply voltage (Vcc5).
When the AVRH pin voltage is turned on or off, it must not exceed AVcc. Even if a common analog input
pin is used as an input port, its input voltage must not exceed AVcc. (However, the analog power supply
voltage and digital power supply voltage can be turned on or off simultaneously.)

 Treatment of power supplies for high current output buffer pins (DVcc,
DVss)
Be sure to turn on the digital power supply voltage (Vcc) first, and then turn on the power supply voltage
for high current output buffer pins (DVcc, DVss). Also, turn off the power supplies for high current output
buffer pins first, and then turn off the digital power supply voltage (Vcc).

Even if the high current output buffer pins are used as general-purpose ports, the power supply voltage of
high current output buffer pins (DVcc, DVss) must be powered. (The power supplies of high current output
buffer pins and the digital power supplies can be turned on or off simultaneously.

 Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to
assure the internal stabilization of the device.

For the standard values, see the "Recommended Operating Conditions" of the latest data sheet.

 Function Switching of a Multiplexed Port

To switch between the port function and the multiplexed pin function, use the PFR (port function register).
However, if a pin is also used for an external bus, its function is switched by the external bus setting. For
details, see "I/O PORTS".

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 Low-power Consumption Mode

To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off),
follow the procedure explained in the "Activating the sleep mode, watch mode, or stop mode" or the
"Activating the watch mode (power-off) or stop mode(power-off)" of "POWER CONSUMPTION
CONTROL" in Hardware Manual.

Take the following notes when using a monitor debugger.

 Do not set a break point for the low-power consumption transition program.
 Do not execute an operation step for the low-power consumption transition program.

 Precautions when writing to registers including the status flag

When writing a function control data in the register that has a status flag (especially, an interrupt request
flag), taking care not to clear its status flag erroneously must be followed.

The program must be written not to clear the flag to the status bit, and then to set the control bits to have the
desired value.

Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) By the Byte, Half-word, or Word access, writing data in the control bits and
status flag simultaneously is done. During this time, take care not to clear other bits (in this case, the bits of
status flag) erroneously.

Note: These points can be ignored because the bit instructions to a register which supports RMW are
already taken the points into consideration. Care must be taken when the bit instruction is used to a register
which does not support RMW.

 No-connected-pin
The product of LQFP-208 has some no-connected-pin which is not connected to any function on die. Pins
are recommended to be pulled-up or pulled-down on the extern circuit.

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 BLOCK DIAGRAM

FR81s CPU Core

Regulator
MPU
Power On Reset Debug Interface
Instruction D ata
CR OSC

XBS
Wild Register XBS Crossbar Switch

RAM Flash
・MainFlash ・WorkFlash 64KB

On-Chip Bus
From Master
On-Chip Bus Layer 2
To Slave

From Master
On-Chip Bus Layer 1
To Slave

Ext-Bus I/F RAM ECC Control (XBS-RAM)

Bus matster
SPI_CS0-3,
HS_SPI (1ch)
SPI_CLK,
DMAC
SPI_SIO0-3 CAN (3ch)
Register
Clock / Bus
Bridge
Peripheral Bridge Bus
Performance
RX0-2, RAM ECC Backup Counter
TX0-2 Control -RAM 16 32

Clock Bridge Mode Registers

(PCLK1⇔PCLK2)
MD 0,MD1,MD2,P 127
32- bit Peripheral B us

Ext-Bus Pins
CAN Prescaler
D16-31,A 00-21,
A SX,CS0X,CS1X , Clock Bridge
RDX,W R0X,WR1X, RTC/WDT1 Calibration (PCLK1⇔PCLK2)
RDY ,SY SCLK

I/O Port Setting Registers CRC

Sound Generator (5ch) SGO0-4,SGA 0-4
SO T2-7,SIN2-7, Lin-UART (6ch)
SCK2-7

SOT 0/1/8/9,SIN 0/1/8/9, M ultifunction Serial Interface (4ch)

SC K0/1/8/9
Port

FRCK0-5 Free Run Timer (6ch)

16- bit Peripheral B us

I/O

Bus Bridge
I/O

ICU0-11 Input Capture (12ch) ( 32-bit ⇔ 16-bit)

Port

INT0-15,
16-bit Peripheral B us

Hi-Z Controls f or

OCU0-11 Output Compare (12ch) External Interrupt Request (16ch)

Standby Mode

Base Timer (2ch) RTC WOT

TIOA 0-1,TIOB0-1

Clock Supervisor V0-3,

A IN0-1,BIN0-1,ZIN0-1
Up Down Counter (2ch) ST0-8, COM0-3,
SEG0-31
LCD Controller
TRG0-5,PPG0-23
PPG(24ch) NMIX
NMI
A DTG,A N0-39 AD Converter
A DC enabled (A DER)
Low Voltage Detection (External Power Supply)
DA O0-1 DA Converter
Low Voltage Detection (Internal Power Supply)

Clock Controls (Configuration

Registers, Main Timer, Sub Timer,
PWM1M0-5, Stepping Motor Controller (6ch) PLL Timer)
PWM1P0-5,
PWM2M0-5,
PWM2P0-5

TIN0-3,TOT0-3 Reload Timer (4ch : ch.0,1,2,3)

Clock Controls (Divide Settings) RS TX
Reload Timer (3ch : ch.4,5,6) Reset Controls
Low Power Control Registers
WatchdogTimer (SW and HW)
Delayed Interrupt
DMA Request and Clear MUX
Interrupt Controller
Interrupt Requests Batch Reading

Note: In this series, the HS-SPI function is prohibited

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 MEMORY MAP
 Memory map

MB91F575
0000 0000H I/O Area
0000 4000H BackUp RAM (8KB)
0000 6000H
I/O Area

0001 0000H
RAM (40KB)

0001 A000H

Reserved

0007 0000H
Flash memory
(512+64)KB

0010 0000H

Reserved

0033 0000H
WorkFlash (64KB)

0034 0000H
Reserved

1000 0000H

HS_SPI MEM Area

2000 0000H HS_SPI CSR area

HSSSWAP register
2000 0404H

Reserved

8000 0000H

External bus Area

FFFF FFFFH

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 Memory map

MB91F577
0000 0000H I/O Area

0000 4000H Backup RAM (8KB)

0000 6000H I/O Area

0001 0000H
RAM (64KB)

0002 0000H

Reserved

0007 0000H

Flash Memory
(1024+64) KB

0018 0000H

Reserved

0033 0000H WorkFlash

(64KB)

0034 0000H
Reserved

1000 0000H HS_SPI MEM Area

2000 0000H HS_SPI CSR Area,

HSSSWAP register
2000 0404H Reserved

8000 0000H
External bus area
FFFF FFFFH

56 MB91F577_DS705-00009-3v0-E, June 19, 2015

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 Memory map

MB91F578
0000 0000H I/O Area

0000 4000H Backup RAM (16KB)

0000 8000H I/O Area

0001 0000H
RAM (96KB)

0002 8000H

Reserved

0007 0000H

Flash Memory
(1536+64) KB

0020 0000H

Reserved

0033 0000H WorkFlash

(64KB)

0034 0000H
Reserved

1000 0000H HS_SPI MEM Area

2000 0000H HS_SPI CSR Area,

HSSSWAP register
2000 0404H Reserved

8000 0000H
External bus area
FFFF FFFFH

June 19, 2015, MB91F577_DS705-00009-3v0-E 57

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 Memory map

MB91F579
0000 0000H I/O Area

0000 4000H Backup RAM (16KB)

0000 8000H I/O Area

0001 0000H
RAM (128KB)

0003 0000H

Reserved

0007 0000H

Flash Memory
(2048+64) KB

0028 0000H

Reserved

0033 0000H WorkFlash

(64KB)

0034 0000H
Reserved

1000 0000H HS_SPI MEM Area

2000 0000H HS_SPI CSR Area,

HSSSWAP register
2000 0404H Reserved

8000 0000H
External bus area
FFFF FFFFH

58 MB91F577_DS705-00009-3v0-E, June 19, 2015

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 I/O MAP

The following I/O map shows the relationship between memory space and registers for peripheral
resources.

 Legend of I/O Map

Read/Write attribute (R: Read W: Write)

Address offset value/ register name

Address Block
+0 +1 +2 +3
BT1TMR[R] H BT1TMCR[R/W]B,H,W
000090 H
0000000000000000 00000000 00000000
BT1STC[R/W] B
000094 H
00000000
Base timer 1
BT1PCSR/BT1PRLL[R /W] H BT1PDU T/BT1PRLH/BT1D TBF[R/W] H
000098 H
0000000000000000 0000000000000000
BTSEL[R /W] B BTSS SR[W] B,H
00009CH
----000 0 -------- ------11
ADERH [R/W]B, H, W ADER L [R/W]B, H, W
0000A0 H
00000000 00000000 00000000 00000000
ADC S1 [R/W] B, H,W ADCS0 [R/W] B, H,W ADCR1 [R] B, H,W ADCR 0 [R] B, H,W
0000A4 H A/D converter
00000000 00000000 ------XX XXXXX XXX
ADCT1 [R/W] B, H,W ADC T0 [R/W] B, H,W ADSCH [R/W] B, H,W ADECH [R/W] B, H,W
0000A8 H
00010000 00101100 ---00000 ---00000

Data access attribute

B: Byte
H: Half-word
W: Word
(Note)
The access by the data access attribute
not described is disabled.

Initial register value after reset

The initial register value after reset indicates as follows:

"1": Initial value "1"

"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting

Note:
It is prohibited to access addresses not described here.

June 19, 2015, MB91F577_DS705-00009-3v0-E 59

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Table: I/O Map

Address offset value / Register name
Address Block
+0 +1 +2 +3
PDR00[R/W] PDR01[R/W] PDR02[R/W] PDR03[R/W]
000000H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDR04[R/W] PDR05[R/W] PDR06[R/W] PDR07[R/W]
000004H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDR08[R/W] PDR09[R/W] PDR10[R/W] PDR11[R/W] Port data register
000008H B,H,W B,H,W B,H,W B,H,W *4:MB91F578/9
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX only
PDR12[R/W] PDR13[R/W] PDR14[R/W] PDR15[R/W]
00000CH B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XX-XXXXX XXXXXXXX*4 XXXXXXXX*4
PDR16[R/W] PDR17[R/W] PDR18[R/W] PDR19[R/W]
000010H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX*4 XXXXXXXX*4 XXXXXXXX*4 XXXXXXXX*4
000014H
to ― ― ― ― Reserved
000038H
WDTCR0[R/W] WDTCPR0[W] WDTCR1[R] WDTCPR1[W]
Watchdog timer
00003CH B,H,W B,H,W B,H,W B,H,W
[S]
-0--0000 00000000 ----0110 00000000

000040H ― ― ― ― Reserved

DICR [R/W] B Delayed

000044H ― ― ―
-------0 interrupt

TMRLRA4 [R/W] H TMR4 [R] H

000048H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 4
TMRLRB4 [R/W] H TMCSR4 [R/W] B, H,W
00004CH
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA5 [R/W] H TMR5 [R] H
000050H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 5
TMRLRB5 [R/W] H TMCSR5 [R/W] B, H,W
000054H
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA6 [R/W] H TMR6 [R] H
000058H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 6
TMRLRB6 [R/W] H TMCSR6 [R/W] B, H,W
00005CH
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA0 [R/W] H TMR0 [R] H
000060H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 0
TMRLRB0 [R/W] H TMCSR0 [R/W] B, H,W
000064H
XXXXXXXX XXXXXXXX 00000000 0-000000
000068H
to ― ― ― ― Reserved
00007CH

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Address offset value / Register name

Address Block
+0 +1 +2 +3
BT0TMR[R] H BT0TMCR[R/W]H
000080H
00000000 00000000 -0000000 00000000
Base timer 0
BT0STC[R/W] B
000084H ― ― ―
0000-000

BT0PDUT/BT0PRLH/BT0DTBF[R/
BT0PCSR/BT0PRLL[R/W] H
000088H W] H Base timer 0
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX

00008CH ― ― ― ― Reserved

BT1TMR[R] H BT1TMCR[R/W]H
000090H
00000000 00000000 -0000000 00000000

BT1STC[R/W] B
000094H ― ― ―
0000-000 Base timer 1

BT1PDUT/BT1PRLH/BT1DTBF[R/
BT1PCSR/BT1PRLL[R/W] H
000098H W] H
00000000 00000000
00000000 00000000
BTSEL01[R/W]
BTSSSR[W] B,H
00009CH B ― Base timer 0,1
-------- ------11
----0000
ADERH [R/W]B, H, W ADERL [R/W]B, H, W
0000A0H
00000000 00000000 00000000 00000000

ADCS1 [R/W] ADCS0 [R/W] ADCR1 [R] B, ADCR0 [R] B,

0000A4H B, H,W B, H,W H,W H,W
0000000- 000----- ------XX XXXXXXXX
A/D converter
ADCT1 [R/W] ADCT0 [R/W] ADSCH [R/W] ADECH [R/W]
0000A8H B, H,W B, H,W B, H,W B, H,W
00010000 00101100 --000000 --000000
EADERLL EADCS [R] B,
0000AC H ― [R/W] B, H,W H,W ―
00000000 --000000
Multi-UART0
SCR0/(IBCR0) SMR0 [R/W] SSR0 [R/W] ESCR0/(IBSR0)
0000B0H [R/W] B,H,W B,H,W B,H,W [R/W] B,H,W
*1: Byte access
0--00000 000-0000 0-000011 -0000000
is permitted only
for access to
RDR0/(TDR0)[R/W] B,H,W *1 BGR0 [R/W] H,W
0000B4H lower
-------0 00000000 00000000 00000000
8 bits
― / (ISMK0) ― / (ISBA0)
0000B8H [R/W] B,H,W [R/W] B,H,W ― ― *2: Reserved
-------- *2 -------- *2 because I2C
FCR10 [R/W] FCR00 [R/W] FBYTE20 [R/W] FBYTE10 [R/W] mode is not set
0000BCH B,H,W B,H,W B,H,W B,H,W immediately
---00100 -0000000 00000000 00000000 after reset.

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Address offset value / Register name

Address Block
+0 +1 +2 +3
SCR1/(IBCR1) SMR1 [R/W] SSR1 [R/W] ESCR1/(IBSR1) Multi-UART1
0000C0H [R/W] B,H,W B,H,W B,H,W [R/W] B,H,W
0--00000 000-0000 0-000011 -0000000 *1: Byte access
is permitted only
RDR1/(TDR1)[R/W] B,H,W *1 BGR1 [R/W] H,W
0000C4H for access to
-------0 00000000 00000000 00000000
lower 8 bits
― / (ISMK1) ― / (ISBA1)
0000C8H [R/W] B,H,W [R/W] B,H,W ― ― *2: Reserved
-------- *2 -------- *2 because I2C
FCR11 [R/W] FCR01 [R/W] FBYTE21 [R/W] FBYTE11 [R/W] mode is not set
0000CCH B,H,W B,H,W B,H,W B,H,W immediately
---00100 -0000000 00000000 00000000 after reset.
SCR2 [R/W] B, SMR2 [R/W] B, SSR2 [R/W] B, RDR2 /TDR2
0000D0H H, W H, W H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART2
ESCR2 [R/W] B, ECCR2 [R/W] B,
BGR2 [R/W] B, H, W
0000D4H H, W H, W
-0000000 00000000
00000X00 -0000-XX
SCR3 [R/W] B, SMR3 [R/W] B, SSR3 [R/W] B, RDR3 /TDR3
0000D8H H, W H, W H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART3
ESCR3 [R/W] B, ECCR3 [R/W] B,
BGR3 [R/W] B, H, W
0000DCH H, W H, W
-0000000 00000000
00000X00 -0000-XX
SCR4 [R/W] B, SMR4 [R/W] B, SSR4 [R/W] B, RDR4 /TDR4
0000E0H H, W H, W H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART4
ESCR4 [R/W] B, ECCR4 [R/W] B,
BGR4 [R/W] B, H, W
0000E4H H, W H, W
-0000000 00000000
00000X00 -0000-XX
SCR5 [R/W] B, SMR5 [R/W] B, SSR5 [R/W] B, RDR5 /TDR5
0000E8H H, W H, W H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART5
ESCR5 [R/W] B, ECCR5 [R/W] B,
BGR5 [R/W] B, H, W
0000ECH H, W H, W
-0000000 00000000
00000X00 -0000-XX
SCR6 [R/W] B, SMR6 [R/W] B, SSR6 [R/W] B, RDR6 /TDR6
0000F0H H, W H, W H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART6
ESCR6 [R/W] B, ECCR6 [R/W] B,
BGR6 [R/W] B, H, W
0000F4H H, W H, W
-0000000 00000000
00000X00 -0000-XX
SCR7 [R/W] B, SMR7 [R/W] B, SSR7 [R/W] B, RDR7 /TDR7
0000F8H H, W H, W H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART7
ESCR7 [R/W] B, ECCR7 [R/W] B,
BGR7 [R/W] B, H, W
0000FCH H, W H, W
-0000000 00000000
00000X00 -0000-XX

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Address offset value / Register name

Address Block
+0 +1 +2 +3
TMRLRA1 [R/W] H TMR1 [R] H
000100H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 1
TMRLRB1 [R/W] H TMCSR1 [R/W] B, H,W
000104H
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA2 [R/W] H TMR2 [R] H
000108H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 2
TMRLRB2 [R/W] H TMCSR2 [R/W] B, H,W
00010CH
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA3 [R/W] H TMR3 [R] H
000110H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 3
TMRLRB3 [R/W] H TMCSR3 [R/W] B, H,W
000114H
XXXXXXXX XXXXXXXX 00000000 0-000000
000118H
to ― ― ― ― Reserved
00011CH
OCCP6 [R/W] W
000120H
00000000 00000000 00000000 00000000
OCCP7 [R/W] W
000124H Output compare
00000000 00000000 00000000 00000000
6,7
OCFS67 [R/W] OCSH67[R/W] OCSL67[R/W]
000128H B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
OCCP8 [R/W] W
00012CH
00000000 00000000 00000000 00000000
OCCP9 [R/W] W
000130H Output compare
00000000 00000000 00000000 00000000
8,9
OCFS89 [R/W] OCSH89[R/W] OCSL89[R/W]
000134H B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
OCCP10 [R/W] W
000138H
00000000 00000000 00000000 00000000
OCCP11 [R/W] W Output compare
00013CH
00000000 00000000 00000000 00000000 10,11
OCFS1011 OCSH1011[R/W] OCSL1011[R/W]
000140H [R/W] B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00

GCN13 [R/W] H GCN23 [R/W] B PPG12, 13, 14,

000144H ―
00110010 00010000 ----0000 15 control

GCN14 [R/W] H GCN24 [R/W] B PPG16, 17, 18,

000148H ―
00110010 00010000 ----0000 19 control

GCN15 [R/W] H GCN25 [R/W] B PPG20, 21, 22,

00014CH ―
00110010 00010000 ----0000 23 control

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Address offset value / Register name

Address Block
+0 +1 +2 +3
PTMR11 [R] H,W PCSR11 [W] H,W
000150H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG11
PDUT11 [W] H,W PCN11 [R/W] B,H,W
000154H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR12 [R] H,W PCSR12 [W] H,W
000158H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG12
PDUT12 [W] H,W PCN12 [R/W] B,H,W
00015CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR13 [R] H,W PCSR13 [W] H,W
000160H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG13
PDUT13 [W] H,W PCN13 [R/W] B,H,W
000164H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR14 [R] H,W PCSR14 [W] H,W
000168H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG14
PDUT14 [W] H,W PCN14 [R/W] B,H,W
00016CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR15 [R] H,W PCSR15 [W] H,W
000170H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG15
PDUT15 [W] H,W PCN15 [R/W] B,H,W
000174H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR16 [R] H,W PCSR16 [W] H,W
000178H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG16
PDUT16 [W] H,W PCN16 [R/W] B,H,W
00017CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR17 [R] H,W PCSR17 [W] H,W
000180H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG17
PDUT17 [W] H,W PCN17 [R/W] B,H,W
000184H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR18 [R] H,W PCSR18 [W] H,W
000188H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG18
PDUT18 [W] H,W PCN18 [R/W] B,H,W
00018CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR19 [R] H,W PCSR19 [W] H,W
000190H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG19
PDUT19 [W] H,W PCN19 [R/W] B,H,W
000194H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR20 [R] H,W PCSR20 [W] H,W
000198H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG20
PDUT20 [W] H,W PCN20 [R/W] B,H,W
00019CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR21 [R] H,W PCSR21 [W] H,W
0001A0H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG21
PDUT21 [W] H,W PCN21 [R/W] B,H,W
0001A4H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR22 [R] H,W PCSR22 [W] H,W
0001A8H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG22
PDUT22 [W] H,W PCN22 [R/W] B,H,W
0001ACH
XXXXXXXX XXXXXXXX 0000000- 000000-0

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Address offset value / Register name

Address Block
+0 +1 +2 +3
PTMR23 [R] H,W PCSR23 [W] H,W
0001B0H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG23
PDUT23 [W] H,W PCN23 [R/W] B,H,W
0001B4H
XXXXXXXX XXXXXXXX 0000000- 000000-0
0001B8H
to ― ― ― ― Reserved
0001FCH
PWC20 [R/W] H,W PWC10 [R/W] H,W
000200H
------XX XXXXXXXX ------XX XXXXXXXX
Stepping motor
PWS20 [R/W] PWS10 [R/W] controller 0
PWC0 [R/W] B
000204H ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC21 [R/W] H,W PWC11 [R/W] H,W
000208H
------XX XXXXXXXX ------XX XXXXXXXX
Stepping motor
PWS21 [R/W] PWS11 [R/W] controller 1
PWC1 [R/W] B
00020CH ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC22 [R/W] H,W PWC12 [R/W] H,W
000210H
------XX XXXXXXXX ------XX XXXXXXXX
Stepping motor
PWS22 [R/W] PWS12 [R/W] controller 2
PWC2 [R/W] B
000214H ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC23 [R/W] H,W PWC13 [R/W] H,W
000218H
------XX XXXXXXXX ------XX XXXXXXXX
Stepping motor
PWS23 [R/W] PWS13 [R/W] controller3
PWC3 [R/W] B
00021CH ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC24 [R/W] H,W PWC14 [R/W] H,W
000220H
------XX XXXXXXXX ------XX XXXXXXXX
Stepping motor
PWS24 [R/W] PWS14 [R/W] controller 4
PWC4 [R/W] B
000224H ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC25 [R/W] H,W PWC15 [R/W] H,W
000228H
------XX XXXXXXXX ------XX XXXXXXXX
Stepping motor
PWS25 [R/W] PWS15 [R/W] controller 5
PWC5 [R/W] B
00022CH ― B,H,W B,H,W
-00000--
-0000000 --000000
000230H
to ― ― ― ― Reserved
000238H
DACR0 [R/W] DADR0 [R/W] DACR1 [R/W] DADR1 [R/W]
00023CH B,H,W B,H,W B,H,W B,H,W DA converter
-------0 XXXXXXXX -------0 XXXXXXXX

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Address offset value / Register name

Address Block
+0 +1 +2 +3
CPCLR0 [R/W] W
000240H
11111111 11111111 11111111 11111111
TCDT0 [R/W] W
000244H
00000000 00000000 00000000 00000000 Free-run timer 0
TCCSH0 TCCSL0
000248H [R/W]B,H,W [R/W]B,H,W ―
0-----00 -1-00000
CPCLR1 [R/W] W
00024CH
11111111 11111111 11111111 11111111
TCDT1 [R/W] W
000250H
00000000 00000000 00000000 00000000 Free-run timer 1
TCCSH1 TCCSL1
000254H [R/W]B,H,W [R/W]B,H,W ―
0-----00 -1-00000

000258H ― ― ― ― Reserved

GCN10 [R/W] H GCN20 [R/W] B PPG0, 1, 2, 3

00025CH ―
00110010 00010000 ----0000 control
GCN11 [R/W] H GCN21 [R/W] B PPG4, 5, 6, 7
000260H ―
00110010 00010000 ----0000 control
GCN12 [R/W] H GCN22 [R/W] B PPG8, 9, 10, 11
000264H ―
00110010 00010000 ----0000 control
PPGDIV [R/W]
000268H ― ― ― B
------00
PTMR0 [R] H,W PCSR0 [W] H,W PPG0
00026CH
11111111 11111111 XXXXXXXX XXXXXXXX
PDUT0 [W] H,W PCN0 [R/W] B, H,W
000270H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR1 [R] H,W PCSR1 [W] H,W
000274H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG1
PDUT1 [W] H,W PCN1 [R/W] B,H,W
000278H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR2 [R] H,W PCSR2 [W] H,W
00027CH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG2
PDUT2 [W] H,W PCN2 [R/W] B,H,W
000280H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR3 [R] H,W PCSR3 [W] H,W
000284H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG3
PDUT3 [W] H,W PCN3 [R/W] B,H,W
000288H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR4 [R] H,W PCSR4 [W] H,W
00028CH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG4
PDUT4 [W] H,W PCN4 [R/W] B,H,W
000290H
XXXXXXXX XXXXXXXX 0000000- 000000-0

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Address offset value / Register name

Address Block
+0 +1 +2 +3
PTMR5 [R] H,W PCSR5 [W] H,W
000294H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG5
PDUT5 [W] H,W PCN5 [R/W] B,H,W
000298H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR6 [R] H,W PCSR6 [W] H,W
00029CH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG6
PDUT6 [W] H,W PCN6 [R/W] B,H,W
0002A0H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR7 [R] H,W PCSR7 [W] H,W
0002A4H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG7
PDUT7 [W] H,W PCN7 [R/W] B,H,W
0002A8H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR8 [R] H,W PCSR8 [W] H,W
0002ACH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG8
PDUT8 [W] H,W PCN8 [R/W] B,H,W
0002B0H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR9 [R] H,W PCSR9 [W] H,W
0002B4H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG9
PDUT9 [W] H,W PCN9 [R/W] B,H,W
0002B8H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR10 [R] H,W PCSR10 [W] H,W
0002BCH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG10
PDUT10 [W] H,W PCN10 [R/W] B,H,W
0002C0H
XXXXXXXX XXXXXXXX 0000000- 000000-0
IPCP0 [R] W
0002C4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP1 [R] W
0002C8H Input capture 0,1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS01 [R/W] LSYNS0 [R/W] ICS01 [R/W] B,
0002CCH B, H, W ― B,H,W H, W
------00 --000000 00000000
IPCP2 [R] W
0002D0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP3 [R] W
0002D4H Input capture 2,3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS23 [R/W] B, ICS23 [R/W] B,
0002D8H H, W ― ― H, W
------00 00000000
IPCP4 [R] W
0002DCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
0002E0H Input capture 4,5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS45 [R/W] B, ICS45 [R/W] B,
0002E4H H, W ― ― H, W
------00 00000000

June 19, 2015, MB91F577_DS705-00009-3v0-E 67

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
OCCP0 [R/W] W
0002E8H
00000000 00000000 00000000 00000000
OCCP1 [R/W] W Output compare
0002ECH
00000000 00000000 00000000 00000000 0,1
OCFS01 [R/W] OCSH01[R/W] OCSL01[R/W]
0002F0H B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
OCCP2 [R/W] W
0002F4H
00000000 00000000 00000000 00000000
OCCP3 [R/W] W
0002F8H Output compare
00000000 00000000 00000000 00000000
2,3
OCFS23 [R/W] OCSH23[R/W] OCSL23[R/W]
0002FCH B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
000300H
to ― ― ― ― Reserved
00030CH

68 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
MPUCR [R/W] H
000310H ― ―
000000-0 ----0100
000314H ― ― ― ―

000318H ―

00031CH ― ― ―

DPVAR [R] W
000320H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR [R/W] H
000324H ― ―
-------- 00000--0

DEAR [R] W
000328H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DESR [R/W] H
00032CH ― ― MPU [S]
-------- 00000--0
(Only the CPU
PABR0 [R/W] W can
000330H access this area)
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0 [R/W] H
000334H ― ―
000000-0 00000--0
PABR1 [R/W] W
000338H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1 [R/W] H
00033CH ― ―
000000-0 00000--0
PABR2 [R/W] W
000340H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2 [R/W] H
000344H ― ―
000000-0 00000--0
PABR3 [R/W] W
000348H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3 [R/W] H
00034CH ― ―
000000-0 00000--0

June 19, 2015, MB91F577_DS705-00009-3v0-E 69

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
PABR4 [R/W] W
000350H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4 [R/W] H
000354H ― ―
000000-0 00000--0
PABR5 [R/W] W
000358H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5 [R/W] H
00035CH ― ― MPU [S]
000000-0 00000--0
(Only the CPU
PABR6 [R/W] W can
000360H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 access this area)
PACR6 [R/W] H
000364H ― ―
000000-0 00000--0
PABR7 [R/W] W
000368H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR7 [R/W] H
00036CH ― ―
000000-0 00000--0
PABR8 [R/W] W
000370H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR8 [R/W] H
000374H ― ―
000000-0 00000--0
PABR9[R/W] W
000378H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR9 [R/W] H
00037CH ― ―
000000-0 00000--0
PABR10 [R/W] W MPU [S] (Only
000380H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 product
PACR10 [R/W] H supporting MPU
000384H ― ― 12 channels or
000000-0 00000--0
16 channels)
PABR11 [R/W] ,W (Only the CPU
000388H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 can
PACR11 [R/W] H access this area)
00038CH ― ―
000000-0 00000--0
PABR12 [R/W] W
000390H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR12 [R/W] H
000394H ― ―
000000-0 00000--0
PABR13 [R/W] W
000398H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR13 [R/W] H
00039CH ― ―
000000-0 00000--0

70 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
PABR14 [R/W]W
0003A0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 MPU [S]
PACR14 [R/W] H (Only product
0003A4H ― ―
000000-0 00000--0 supporting MPU
16 channels)
PABR15 [R/W] W
0003A8H (Only the CPU
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
can
PACR15 [R/W] H access this area)
0003ACH ― ―
000000-0 00000--0
0003B0H
to ― ― ― ― Reserved [S]
0003FCH
ICSEL0[R/W] ICSEL1[R/W] ICSEL2[R/W] ICSEL3[R/W]
000400H B, H, W B, H, W B, H, W B, H, W
-----000 -----000 -------0 -------0
ICSEL4[R/W] ICSEL5[R/W] ICSEL6[R/W] ICSEL7[R/W]
000404H B, H, W B, H, W B, H, W B, H, W
-------0 -------0 -----000 -----000
ICSEL8[R/W] ICSEL9[R/W] ICSEL10 ICSEL11[R/W]
000408H B, H, W B, H, W [R/W]B, H, W B, H, W
------00 ------00 ------00 ------00 Generation and
clear
ICSEL12[R/W] ICSEL13[R/W] ICSEL14 ICSEL15[R/W]
of DMA transfer
00040CH B, H, W B, H, W [R/W]B, H, W B, H, W
request
------00 -------0 -------0 -------0

ICSEL16[R/W] ICSEL17[R/W] ICSEL18 ICSEL19[R/W]

000410H B, H, W B, H, W [R/W]B, H, W B, H, W
-------0 -------0 -------0 -----000

ICSEL20[R/W] ICSEL21[R/W] ICSEL22

000414H B, H, W B, H, W [R/W]B, H, W ―
-----000 ------00 ------00
IRPR0H[R] IRPR0L[R] IRPR1H[R] IRPR1L[R]
000418H B, H, W B, H, W B, H, W B, H, W
00------ 00------ 00------ 00------
IRPR2H[R] IRPR2L[R] IRPR3H[R] IRPR3L[R]
00041CH B, H, W B, H, W B, H, W B, H, W
00------ 00------ 000000-- 000000--
IRPR4H[R] IRPR4L[R] IRPR5H[R] IRPR5L[R]
000420H B, H, W B, H, W B, H, W B, H, W
0000---- 0000---- 0000---- 000-----
IRPR6H[R] IRPR6L[R] IRPR7H[R] IRPR7L[R] Interrupt request
000424H B, H, W B, H, W B, H, W B, H, W batch read
--000--- 00000--- -0000--- ------00 register
IRPR8H[R] IRPR8L[R] IRPR9H[R] IRPR9L[R]
000428H B, H, W B, H, W B, H, W B, H, W
000----- 000----- 00------ 00------
IRPR10H[R] IRPR10L[R] IRPR11H[R] IRPR11L[R]
00042CH B, H, W B, H, W B, H, W B, H, W
00------ 00------ 00------ 00------
IRPR12H[R] IRPR12L[R] IRPR13H[R] IRPR13L[R]
000430H B, H, W B, H, W B, H, W B, H, W
000000-- 000000-- 000----- 00000---

June 19, 2015, MB91F577_DS705-00009-3v0-E 71

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
IRPR14H[R] IRPR14L[R] IRPR15H[R] Interrupt request
000434H B, H, W B, H, W B, H, W ― batch read
00000000 00000000 000----- register
000438H
to ― ― ― ― Reserved
00043CH
ICR00 [R/W] B, ICR01 [R/W] B, ICR02 [R/W] B, ICR03 [R/W] B,
000440H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR04 [R/W] B, ICR05 [R/W] B, ICR06 [R/W] B, ICR07 [R/W] B,
000444H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR08 [R/W] B, ICR09 [R/W] B, ICR10 [R/W] B, ICR11 [R/W] B,
000448H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR12 [R/W] B, ICR13 [R/W] B, ICR14 [R/W] B, ICR15 [R/W] B,
00044CH H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR16 [R/W] B, ICR17 [R/W] B, ICR18 [R/W] B, ICR19 [R/W] B,
000450H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR20 [R/W] B, ICR21 [R/W] B, ICR22 [R/W] B, ICR23 [R/W] B,
000454H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111 Interrupt
ICR24 [R/W] B, ICR25 [R/W] B, ICR26 [R/W] B, ICR27 [R/W] B, controller [S]
000458H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR28 [R/W] B, ICR29 [R/W] B, ICR30 [R/W] B, ICR31 [R/W] B,
00045CH H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR32 [R/W] B, ICR33 [R/W] B, ICR34 [R/W] B, ICR35 [R/W] B,
000460H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR36 [R/W] B, ICR37 [R/W] B, ICR38 [R/W] B, ICR39 [R/W] B,
000464H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR40 [R/W] B, ICR41 [R/W] B, ICR42 [R/W] B, ICR43 [R/W] B,
000468H H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
ICR44 [R/W] B, ICR45 [R/W] B, ICR46 [R/W] B, ICR47 [R/W] B,
00046CH H, W H, W H, W H, W
---11111 ---11111 ---11111 ---11111
000470H
to ― ― ― ― Reserved [S]
00047CH

72 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
Reset control [S]
Power
consumption
RSTRR [R] RSTCR [R/W] STBCR [R/W] control [S]
000480H B,H,W B,H,W B,H,W * ―
XXXX--XX 111----0 000---11 *: Writing to
STBCR by
DMA is not
permitted
000484H ― ― ― ― Reserved [S]
DIVR0 [R/W] DIVR1 [R/W] DIVR2 [R/W]
Clock control
000488H B,H,W B,H,W B,H,W ―
[S]
000----- 0001---- 0011----
00048CH ― ― ― ― Reserved [S]
IORR0[R/W] IORR1[R/W] IORR2[R/W] IORR3[R/W]
000490H B, H, W B, H, W B, H, W B, H, W
-0000000 -0000000 -0000000 -0000000
IORR4[R/W] IORR5[R/W] IORR6[R/W] IORR7[R/W]
000494H B, H, W B, H, W B, H, W B, H, W
-0000000 -0000000 -0000000 -0000000 DMA transfer
request from a
IORR8[R/W] IORR9[R/W] IORR10[R/W] IORR11[R/W]
peripheral [S]
000498H B, H, W B, H, W B, H, W B, H, W
-0000000 -0000000 -0000000 -0000000
IORR12[R/W] IORR13[R/W] IORR14[R/W] IORR15[R/W]
00049CH B, H, W B, H, W B, H, W B, H, W
-0000000 -0000000 -0000000 -0000000

0004A0H ― ― ― ― Reserved
CANPRE [R/W]
0004A4H B,H,W ― ― ― CAN prescaler
----0000
0004A8H
to ― ― ― ― Reserved
0004B4H
CUCR0 [R/W] B,H,W CUTD0 [R/W] B,H,W
0004B8H
-------- ---0--00 10000000 00000000

CUTR0 [R] B,H,W

0004BCH
-------- 00000000 00000000 00000000

0004C0H ― ― ― ―
RTC/WDT1
calibration
CUCR1 [R/W] B,H,W CUTD1[R/W] B,H,W
0004C4H (Calibration)
-------- ---0--00 11000011 01010000
CUTR1 [R] B,H,W
0004C8H
-------- 00000000 00000000 00000000
CRTR [R/W]
0004CCH B,H,W ― ― ―
01111111
0004D0H
to ― ― ― ― Reserved
0004DCH

June 19, 2015, MB91F577_DS705-00009-3v0-E 73

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
SCR8/(IBCR8) SMR8 [R/W] SSR8 [R/W] ESCR8/(IBSR8)
0004E0H [R/W] B,H,W B,H,W B,H,W [R/W] B,H,W
0--00000 000-0000 0-000011 -0000000
Multi-UART8
RDR8/(TDR8)[R/W] B,H,W *1 BGR8 [R/W] H,W
0004E4H
-------0 00000000 00000000 00000000
*1: Byte access
is permitted only
0004E8H ― ― ― ― for access to
lower 8 bits
FCR18 [R/W] FCR08 [R/W] FBYTE28 [R/W] FBYTE18 [R/W]
0004ECH B,H,W B,H,W B,H,W B,H,W
---00100 -0000000 00000000 00000000
SCR9/(IBCR9) SMR9 [R/W] SSR9 [R/W] ESCR9/(IBSR9)
0004F0H [R/W] B,H,W B,H,W B,H,W [R/W] B,H,W
0--00000 000-0000 0-000011 -0000000
Multi-UART9
RDR9/(TDR9)[R/W] B,H,W *1 BGR9 [R/W] H,W
0004F4H
-------0 00000000 00000000 00000000 *1: Byte access
is permitted only
0004F8H ― ― ― ― for access to
lower
8 bits
FCR19 [R/W] FCR09 [R/W] FBYTE29 [R/W] FBYTE19 [R/W]
0004FCH B,H,W B,H,W B,H,W B,H,W
---00100 -0000000 00000000 00000000
000500H
to ― ― ― ― Reserved
00050CH
CSELR [R/W] CMONR [R] MTMCR [R/W] STMCR [R/W]
000510H B,H,W B,H,W B,H,W B,H,W
001---00 001---00 00001111 0000-111 Clock control
CSTBR [R/W] PTMCR [R/W] [S]
PLLCR [R/W] B,H,W
000514H B,H,W B,H,W
-------- 11110000
-0000000 00------
CPUAR [R/W]
000518H ― ― B,H,W ― Reset [S]
0----XXX
00051CH ― ― ― ― Reserved [S]
CCPSSELR CCPSDIVR
000520H [R/W] B,H,W ― ― [R/W] B,H,W
-------0 -000-000
CCPLLFBR CCSSFBR0 CCSSFBR1
000524H ― [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W
-0000000 --000000 ---00000
Clock control 2
CCSSCCR0
CCSSCCR1[R/W]H,W
000528H ― [R/W] B,H,W
000----- --------
----0000
CCCGRCR0 CCCGRCR1 CCCGRCR2
00052CH ― [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W
00----00 00000000 00000000

74 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
CCRTSELR CCPMUCR0 CCPMUCR1
000530H [R/W] B,H,W ― [R/W] B,H,W [R/W] B,H,W
0------0 0-----00 0--00000
000534H ― ― ― ― Clock control 2
000538H ― ― ― ―
00053CH ― ― ― ―
000540H
to ― ― ― ― Reserved
00054CH
EIRR0[R/W] ENIR0[R/W] External
ELVR0[R/W] B,H,W
000550H B,H,W B,H,W interrupt
00000000 00000000
XXXXXXXX 00000000 (INT0 to INT7)
EIRR1[R/W] ENIR1[R/W] External
ELVR1[R/W] B,H,W
000554H B,H,W B,H,W interrupt
00000000 00000000
XXXXXXXX 00000000 (INT8 to INT15)

000558H ― ― ― ― Reserved

WTDR[R/W] H
00055CH ― ―
00000000 00000000
WTCRH [R/W] WTCRM [R/W] WTCRL [R/W]
000560H ― B B,H B,H
------00 00000000 ----00-0
WTBRH [R/W] WTBRM [R/W] WTBRL [R/W] Real-time clock
000564H ― B B B
--XXXXXX XXXXXXXX XXXXXXXX
WTHR [R/W] WTMR [R/W]
WTSR [R/W] B
000568H B,H B,H ―
--000000
---00000 --000000
CSVCR[R/W]B
00056CH ― -001110- ― ― Clock supervisor
-001010-*3
000570H
to ― ― ― ― Reserved
00057CH
REGSEL [R/W]
Regulator
000580H B,H,W ― ― ―
control
0110011-
LVD5R [R/W] LVD5F [R/W] LVD [R/W]
Low-voltage
000584H B,H,W B,H,W B,H,W ―
detection
-------1 0-100--1 01000--0
000588H
to ― ― ― ― Reserved
00058CH

June 19, 2015, MB91F577_DS705-00009-3v0-E 75

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
PMUSTR [R/W] PMUCTLR PWRTMCTL
000590H B,H,W [R/W] B,H,W [R/W] B,H,W ―
0-----1X 0-00---- -----011

PMUINTF0 PMUINTF1 PMUINTF2

000594H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W ― PMU
00000000 00000000 0000----

000598H ― ― ― ―

00059CH
to ― ― ― ― Reserved
0005A4H
LCDCMR [R/W] LCRS [R/W] LCR0 [R/W] LCR1 [R/W]
0005A8H B,H,W B,H,W B,H,W B,H,W
0------- 00000000 00010000 --------
VRAM0[R/W] VRAM1[R/W] VRAM2[R/W] VRAM3[R/W]
0005ACH B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
VRAM4[R/W] VRAM5[R/W] VRAM6[R/W] VRAM7[R/W]
0005B0H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
VRAM8[R/W] VRAM9[R/W] VRAM10[R/W] VRAM11[R/W] LCD controller
0005B4H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
VRAM12[R/W] VRAM13[R/W] VRAM14[R/W] VRAM15[R/W]
0005B8H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
LDR0[R/W] LDR1[R/W]
0005BCH B,H,W B,H,W ― ―
-------0 00000000
0005C0H
to ― ― ― ― Reserved
0005FCH
ASR0 [R/W] W
000600H
00000000 00000000 -------- 1111-001
ASR1 [R/W] W
000604H
XXXXXXXX XXXXXXXX -------- XXXX-XX0
External bus
ASR2 [R/W] W Interface [S]
000608H
XXXXXXXX XXXXXXXX -------- XXXX-XX0

ASR3 [R/W] W
00060CH
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000610H
to ― ― ― ― Reserved [S]
00063CH

76 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
ACR0 [R/W] W
000640H
-------- -------- -------- 01--00--
ACR1 [R/W] W
000644H
-------- -------- -------- XX--XX-- External bus
ACR2 [R/W] W Interface [S]
000648H
-------- -------- -------- XX--XX--
ACR3 [R/W] W
00064CH
-------- -------- -------- XX--XX--
000650H
to ― ― ― ― Reserved [S]
00067CH
AWR0 [R/W] W
000680H
----1111 00000000 11110000 00000-0-
AWR1 [R/W] W
000684H
----XXXX XXXXXXXX XXXXXXXX XXXXX-X- External bus
AWR2 [R/W] W Interface [S]
000688H
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
AWR3 [R/W] W
00068CH
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000690H
Reserved
to ― ― ― ―
(to 0006FFH[S])
00070CH
BPCCRA[R/W] BPCCRB[R/W] BPCCRC[R/W]
000710H B B B ―
00000000 00000000 00000000
BPCTRA [R/W] W Bus performance
000714H
00000000 00000000 00000000 00000000 counter
BPCTRB [R/W] W
000718H
00000000 00000000 00000000 00000000
BPCTRC [R/W] W
00071CH
00000000 00000000 00000000 00000000
000720H
to ― ― ― ― Reserved
0007F8H
BMODR[R] B,
0007FCH H, W ― ― ― Operation mode
XXXXXXXX
000800H
to ― ― ― ― Reserved [S]
00083CH
FCTLR[R/W] H FSTR[R/W] B Flash memory
000840H ―
-0--1000 0--0---- -----001 register [S]
000844H ― ― ― ― Reserved [S]
000848H ― ― ― ―
00084CH ― ― ― ―
Reserved [S]
000850H ― ― ― ―
000854H ― ― ― ―
000858H ― ― WREN[R/W] H 00000000 00000000 Wild register [S]

June 19, 2015, MB91F577_DS705-00009-3v0-E 77

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
00085CH ― ― ― ―
000860H ― ― ― ―
000864H ― ― ― ―
000868H ― ― ― ―
Reserved [S]
00086CH ― ― ― ―
000870H ― ― ― ―
000874H ― ― ― ―
000878H ― ― ― ―
00087CH ― ― ― ― Reserved [S]
WRAR00 [R/W] W
000880H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR00 [R/W] W
000884H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01 [R/W] W
000888H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR01 [R/W] W
00088CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02 [R/W] W
000890H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR02 [R/W] W
000894H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03 [R/W] W
000898H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR03 [R/W] W
00089CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04 [R/W] W
0008A0H
-------- --XXXXXX XXXXXXXX XXXXXX-- Wild register [S]
WRDR04 [R/W] W
0008A4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05 [R/W] W
0008A8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR05 [R/W] W
0008ACH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06 [R/W] W
0008B0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR06 [R/W] W
0008B4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07 [R/W] W
0008B8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR07 [R/W] W
0008BCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08 [R/W] W
0008C0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR08 [R/W] W
0008C4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

78 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
WRAR09 [R/W] W
0008C8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR09 [R/W] W
0008CCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10 [R/W] W
0008D0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR10 [R/W] W
0008D4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11 [R/W] W
0008D8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR11 [R/W] W
0008DCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12 [R/W] W
0008E0H
-------- --XXXXXX XXXXXXXX XXXXXX-- Wild register [S]
WRDR12 [R/W] W
0008E4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13 [R/W] W
0008E8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR13 [R/W] W
0008ECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14 [R/W] W
0008F0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR14 [R/W] W
0008F4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15 [R/W] W
0008F8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR15 [R/W] W
0008FCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900H
to ― ― ― ― Reserved
000BF8H
UER [W] B,H,W
000BFCH ― ― OCDU
-------- -------X
DCCR0[R/W] W
000C00H
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H DTCR0[R/W] H
000C04H
0------- -----000 00000000 00000000
DSAR0[R/W] W
000C08H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0 [R/W] W
000C0CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMA controller
DCCR1 [R/W] W [S]
000C10H
0----000 --00--00 00000000 0-000000
DCSR1 [R/W] H DTCR1 [R/W] H
000C14H
0------- -----000 00000000 00000000
DSAR1 [R/W] W
000C18H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1 [R/W] W
000C1CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

June 19, 2015, MB91F577_DS705-00009-3v0-E 79

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
DCCR2 [R/W] W
000C20H
0----000 --00--00 00000000 0-000000
DCSR2 [R/W] H DTCR2 [R/W] H
000C24H
0------- -----000 00000000 00000000
DSAR2 [R/W] W
000C28H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2 [R/W] W
000C2CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
000C30H
0----000 --00--00 00000000 0-000000
DCSR3 [R/W] H DTCR3 [R/W] H
000C34H
0------- -----000 00000000 00000000
DSAR3 [R/W] W
000C38H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3 [R/W] W
000C3CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4 [R/W] W
000C40H
0----000 --00--00 00000000 0-000000
DCSR4 [R/W] H DTCR4 [R/W] H
000C44H DMA controller
0------- -----000 00000000 00000000
[S]
DSAR4[R/W] W
000C48H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4[R/W] W
000C4CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5 [R/W] W
000C50H
0----000 --00--00 00000000 0-000000
DCSR5 [R/W] H DTCR5 [R/W] H
000C54H
0------- -----000 00000000 00000000
DSAR5 [R/W] W
000C58H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5 [R/W] W
000C5CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6 [R/W] W
000C60H
0----000 --00--00 00000000 0-000000
DCSR6 [R/W] H DTCR6 [R/W] H
000C64H
0------- -----000 00000000 00000000
DSAR6 [R/W] W
000C68H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6 [R/W] W
000C6CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

80 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
DCCR7 [R/W] W
000C70H
0----000 --00--00 00000000 0-000000
DCSR7 [R/W] H DTCR7 [R/W] H
000C74H
0------- -----000 00000000 00000000
DSAR7 [R/W] W
000C78H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDAR7 [R/W] W
000C7CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DCCR8 [R/W] W
000C80H
0----000 --00--00 00000000 0-000000
DCSR8 [R/W] H DTCR8 [R/W] H
000C84H
0------- -----000 00000000 00000000
DSAR8 [R/W] W
000C88H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDAR8 [R/W] W
000C8CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DCCR9 [R/W] W
000C90H
0----000 --00--00 00000000 0-000000
DCSR9 [R/W] H DTCR9 [R/W] H DMA controller
000C94H [S]
0------- -----000 00000000 00000000
DSAR9 [R/W] W
000C98H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR9 [R/W] W
000C9CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR10 [R/W] W
000CA0H
0----000 --00--00 00000000 0-000000
DCSR10[R/W] H DTCR10[R/W] H
000CA4H
0------- -----000 00000000 00000000
DSAR10 [R/W] W
000CA8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR10 [R/W] W
000CACH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR11[R/W] W
000CB0H
0----000 --00--00 00000000 0-000000
DCSR11 [R/W] H DTCR11 [R/W] H
000CB4H
0------- -----000 00000000 00000000
DSAR11 [R/W] W
000CB8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR11 [R/W] W
000CBCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

June 19, 2015, MB91F577_DS705-00009-3v0-E 81

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
DCCR12 [R/W] W
000CC0H
0----000 --00--00 00000000 0-000000
DCSR12 [R/W] H DTCR12 [R/W] H
000CC4H
0------- -----000 00000000 00000000

DSAR12 [R/W] W
000CC8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDAR12 [R/W] W
000CCCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR13 [R/W] W
000CD0H
0----000 --00--00 00000000 0-000000
DCSR13[R/W] H DTCR13[R/W] H
000CD4H
0------- -----000 00000000 00000000
DSAR13[R/W] W
000CD8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR13[R/W] W
000CDCH DMA controller
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]
DCCR14[R/W] W
000CE0H
0----000 --00--00 00000000 0-000000
DCSR14[R/W] H DTCR14[R/W] H
000CE4H
0------- -----000 00000000 00000000
DSAR14[R/W] W
000CE8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR14[R/W] W
000CECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR15[R/W] W
000CF0H
0----000 --00--00 00000000 0-000000
DCSR15[R/W] H DTCR15[R/W] H
000CF4H
0------- -----000 00000000 00000000
DSAR15[R/W] W
000CF8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR15[R/W] W
000CFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000D00H
to ― ― ― ― Reserved [S]
000DF0H
DNMIR[R/W] B DILVR[R/W] B
000DF4H ― ―
0------0 ---11111
DMA controller
[S]
DMACR[R/W] W
000DF8H
0------- -------- 0------- --------

000DFCH ― ― ― ― Reserved [S]

82 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
DDR00[R/W] DDR01[R/W] DDR02[R/W] DDR03[R/W]
000E00H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
DDR04[R/W] DDR05[R/W] DDR06[R/W] DDR07[R/W]
000E04H B,H,W B,H,W B,H,W B,H,W
00000000 -0000000 00000000 00000000
Data direction
DDR08[R/W] DDR09[R/W] DDR10[R/W] DDR11[R/W]
Register
000E08H B,H,W B,H,W B,H,W B,H,W
*4:MB91F578/9
00000000 00000000 00000000 00000000
only
DDR12[R/W] DDR13[R/W] DDR14[R/W] DDR15[R/W]
000E0CH B,H,W B,H,W B,H,W B,H,W
00000000 00-00000 00000000*4 00000000*4
DDR16[R/W] DDR17[R/W] DDR18[R/W] DDR19[R/W]
000E10H B,H,W B,H,W B,H,W B,H,W
00000000*4 00000000*4 00000000*4 00000000*4
000E14H
to ― ― ― ― Reserved
000E1CH
PFR00[R/W] PFR01[R/W] PFR02[R/W] PFR03[R/W]
000E20H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 10000000
PFR04[R/W] PFR05[R/W] PFR06[R/W] PFR07[R/W]
000E24H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 00000000 00000000
Port function
PFR08[R/W] PFR09[R/W] PFR10[R/W] PFR11[R/W]
register
000E28H B,H,W B,H,W B,H,W B,H,W
*4:MB91F578/9
00000000 0-000000 00000000 00000000
only
PFR12[R/W] PFR13[R/W] PFR14[R/W] PFR15[R/W]
000E2CH B,H,W B,H,W B,H,W B,H,W
00000000 00-00000 00000000*4 00000000*4
PFR16[R/W] PFR17[R/W] PFR18[R/W] PFR19[R/W]
000E30H B,H,W B,H,W B,H,W B,H,W
00000000*4 00000000*4 00000000*4 00000000*4
000E34H
to ― ― ― ― Reserved
000E3CH
PDDR00[R] PDDR01[R] PDDR02[R] PDDR03[R]
000E40H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDDR04[R] PDDR05[R] PDDR06[R] PDDR07[R]
000E44H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input data
PDDR08[R] PDDR09[R] PDDR10[R] PDDR11[R] direct read
000E48H B,H,W B,H,W B,H,W B,H,W register
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX *4:MB91F578/9
PDDR12[R] PDDR13[R] PDDR14[R] PDDR15[R] only
000E4CH B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XX-XXXXX XXXXXXXX*4 XXXXXXXX*4
PDDR16[R] PDDR17[R] PDDR18[R] PDDR19[R]
000E50H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX*4 XXXXXXXX*4 XXXXXXXX*4 XXXXXXXX*4
000E54H
to ― ― ― ― Reserved
000E5CH
June 19, 2015, MB91F577_DS705-00009-3v0-E 83

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
EPFR00[R/W] EPFR01[R/W] EPFR02[R/W] EPFR03[R/W]
000E60H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 ---00000 ---00000
EPFR04[R/W] EPFR05[R/W] EPFR06[R/W] EPFR07[R/W]
000E64H B,H,W B,H,W B,H,W B,H,W
---00000 ---00000 ---00000 ---00000
EPFR08[R/W] EPFR09[R/W] EPFR10[R/W] EPFR11[R/W]
000E68H B,H,W B,H,W B,H,W B,H,W
---00000 ---00000 -0000000 --000000
EPFR12[R/W] EPFR13[R/W] EPFR14[R/W] EPFR15[R/W]
000E6CH B,H,W B,H,W B,H,W B,H,W
--000000 --000000 --000000 -0000000
EPFR16[R/W] EPFR17[R/W] EPFR18[R/W] EPFR19[R/W]
000E70H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 10000000 11111111
EPFR20[R/W] EPFR21[R/W] EPFR22[R/W] EPFR23[R/W]
000E74H B,H,W B,H,W B,H,W B,H,W
11111111 00000000 00000000 00000000
EPFR24[R/W] EPFR25[R/W] EPFR26[R/W] EPFR27[R/W] Extended port
000E78H B,H,W B,H,W B,H,W B,H,W function register
-----000 -----000 ----0000 ---00000
EPFR28[R/W] EPFR29[R/W] EPFR30[R/W] EPFR31[R/W]
000E7CH B,H,W B,H,W B,H,W B,H,W
----0000 00000000 00000000 00000000
EPFR32[R/W] EPFR33[R/W] EPFR34[R/W] EPFR35[R/W]
000E80H B,H,W B,H,W B,H,W B,H,W
00000000 ---00000 ---00000 ---00000
EPFR36[R/W] EPFR37[R/W] EPFR38[R/W] EPFR39[R/W]
000E84H B,H,W B,H,W B,H,W B,H,W
---00000 00000000 ---00000 00000000
EPFR40[R/W] EPFR41[R/W] EPFR42[R/W] EPFR43[R/W]
000E88H B,H,W B,H,W B,H,W B,H,W
--000000 -----000 ------00 00000000
EPFR44[R/W] EPFR45[R/W] EPFR46[R/W] EPFR47[R/W]
000E8CH B,H,W B,H,W B,H,W B,H,W
00000000 00000000 --000000 -------0
000E90H ― ― ― ―
EPFR52[R/W] EPFR53[R/W] EPFR54[R/W]
Extended port
000E94H B,H,W B,H,W B,H,W ―
function register
-------0 ---00000 ----0000
000E98H
to ― ― ― ― Reserved
000E9CH

84 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
PPCR00[R/W] PPCR01[R/W] PPCR02[R/W] PPCR03[R/W]
000EA0H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
PPCR04[R/W] PPCR05[R/W] PPCR06[R/W] PPCR07[R/W]
000EA4H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111 Port
PPCR08[R/W] PPCR09[R/W] PPCR10[R/W] PPCR11[R/W] pull-up/down
000EA8H B,H,W B,H,W B,H,W B,H,W control register
11111111 11111111 11111111 11111111 *4:MB91F578/9
PPCR12[R/W] PPCR13[R/W] PPCR14[R/W] PPCR15[R/W] only
000EACH B,H,W B,H,W B,H,W B,H,W
11111111 11-11111 11111111*4 11-11111*4
PPCR16[R/W] PPCR17[R/W] PPCR18[R/W] PPCR19[R/W]
000EB0H B,H,W B,H,W B,H,W B,H,W
11111111*4 11111111*4 11111111*4 11-11111*4
000EBCH ― ― ― ― Reserved
PPER00[R/W] PPER01[R/W] PPER02[R/W] PPER03[R/W]
000EC0H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
PPER04[R/W] PPER05[R/W] PPER06[R/W] PPER07[R/W]
000EC4H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000 Port
PPER08[R/W] PPER09[R/W] PPER10[R/W] PPER11[R/W] pull-up/down
000EC8H B,H,W B,H,W B,H,W B,H,W enable register
00000000 00000000 00000000 00000000 *4:MB91F578/9
PPER12[R/W] PPER13[R/W] PPER14[R/W] PPER15[R/W] only
000ECCH B,H,W B,H,W B,H,W B,H,W
00000000 00-00000 00000000*4 00000000*4
PPER16[R/W] PPER17[R/W] PPER18[R/W] PPER19[R/W]
000ED0H B,H,W B,H,W B,H,W B,H,W
00000000*4 00000000*4 00000000*4 00000000*4
000EDCH ― ― ― ― Reserved
PILR00[R/W] PILR01[R/W] PILR02[R/W] PILR03[R/W]
000EE0H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
PILR04[R/W] PILR05[R/W] PILR06[R/W] PILR07[R/W]
000EE4H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
Port input level
PILR08[R/W] PILR09[R/W] PILR10[R/W] PILR11[R/W] selection register
000EE8H B,H,W B,H,W B,H,W B,H,W *4:MB91F578/9
11111111 11111111 11111111 11111111 only
PILR12[R/W] PILR13[R/W] PILR14[R/W] PILR15[R/W]
000EECH B,H,W B,H,W B,H,W B,H,W
11111111 11-11111 11111111*4 11111111*4
PILR16[R/W] PILR17[R/W] PILR18[R/W] PILR19[R/W]
000EF0H B,H,W B,H,W B,H,W B,H,W
11111111*4 11111111*4 11111111*4 11111111*4
000EFCH ― ― ― ― Reserved

June 19, 2015, MB91F577_DS705-00009-3v0-E 85

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
EPILR00[R/W] EPILR01[R/W] EPILR02[R/W] EPILR03[R/W]
000F00H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
EPILR04[R/W] EPILR05[R/W] EPILR06[R/W] EPILR07[R/W]
000F04H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000 Extended Port
EPILR08[R/W] EPILR09[R/W] EPILR10[R/W] EPILR11[R/W] input level
000F08H B,H,W B,H,W B,H,W B,H,W selection register
00000000 00000000 00000000 00000000 *4:MB91F578/9
EPILR12[R/W] EPILR13[R/W] EPILR14[R/W] EPILR15[R/W] only
000F0CH B,H,W B,H,W B,H,W B,H,W
00000000 00-00000 00000000*4 00000000*4
EPILR16[R/W] EPILR17[R/W] EPILR18[R/W] EPILR19[R/W]
000F10H B,H,W B,H,W B,H,W B,H,W
00000000*4 00000000*4 00000000*4 00000000*4
000F1CH ― ― ― ― Reserved
PODR00[R/W] PODR01[R/W] PODR02[R/W] PODR03[R/W]
000F20H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
PODR04[R/W] PODR05[R/W] PODR06[R/W] PODR07[R/W]
000F24H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
Port output drive
PODR08[R/W] PODR09[R/W] PODR10[R/W] PODR11[R/W] register
000F28H B,H,W B,H,W B,H,W B,H,W *4:MB91F578/9
00000000 00000000 00000000 00000000 only
PODR12[R/W] PODR13[R/W] PODR14[R/W] PODR15[R/W]
000F2CH B,H,W B,H,W B,H,W B,H,W
00000000 00-00000 00000000*4 00000000*4
PODR16[R/W] PODR17[R/W] PODR18[R/W] PODR19[R/W]
000F30H B,H,W B,H,W B,H,W B,H,W
00000000*4 00000000*4 00000000*4 00000000*4
EPODR01 [R/W] EPODR02 [R/W] EPODR03 [R/W]
000F34H ― B,H,W B,H,W B,H,W
Extended Port
00000000 00000000 -0000000
output drive
EPODR06 [R/W] EPODR07 [R/W] EPODR08 [R/W]
register
000F38H B,H,W B,H,W B,H,W ―
00000000 00000000 00000000
000F3CH ― ― ― ― Reserved

PORTEN [R/W]
Port input enable
000F40H B,H,W ― ― ―
register
-------0
000F44H
to ― ― ― ― Reserved
000F6CH
RCRL0[W] UDCRH0[R] UDCRL0[R]
RCRH0[W] H,W
000F70H B,H,W H,W B,H,W
XXXXXXXX Up/down
XXXXXXXX 00000000 00000000
counter 0
CCR0[R/W] B,H CSR0[R/W] B
000F74H ―
00000000 -0001000 00000000
000F78H
to ― ― ― ― Reserved
000F7CH

86 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
RCRL1[W] UDCRH1 [R] UDCRL1[R]
RCRH1[W] H,W
000F80H B,H,W H,W B,H,W
XXXXXXXX
XXXXXXXX 00000000 00000000 Up/down
counter 1
CCR1[R/W] B,H CSR1[R/W] B
000F84H ―
00000000 -0001000 00000000
000F88H
to ― ― ― ― Reserved
000F8CH
OCCP4 [R/W] W
000F90H
00000000 00000000 00000000 00000000

OCCP5 [R/W] W Output compare

000F94H
00000000 00000000 00000000 00000000 4,5
OCFS45 [R/W] OCSH45 [R/W] OCSL45[R/W]
000F98H B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
000F9CH ― ― ― ― Reserved
CPCLR2 [R/W] W
000FA0H
11111111 11111111 11111111 11111111
TCDT2 [R/W] W
000FA4H
00000000 00000000 00000000 00000000 Free-run timer 2
TCCSH2 [R/W] TCCSL2 [R/W]
000FA8H B,H,W B,H,W ―
0-----00 -1-00000
CPCLR3 [R/W] W
000FACH
11111111 11111111 11111111 11111111
TCDT3 [R/W] W
000FB0H
00000000 00000000 00000000 00000000 Free-run timer 3
TCCSH3 [R/W] TCCSL3 [R/W]
000FB4H B,H,W B,H,W ―
0-----00 -1-00000
CPCLR4 [R/W] W
000FB8H
11111111 11111111 11111111 11111111
TCDT4 [R/W] W
000FBCH
00000000 00000000 00000000 00000000 Free-run timer 4
TCCSH4 [R/W] TCCSL4 [R/W]
000FC0H B,H,W B,H,W ―
0-----00 -1-00000
CPCLR5 [R/W] W
000FC4H
11111111 11111111 11111111 11111111
TCDT5 [R/W] W
000FC8H
00000000 00000000 00000000 00000000 Free-run timer 5
TCCSH5 TCCSL5
000FCCH [R/W]B,H,W [R/W]B,H,W ―
0-----00 -1-00000

June 19, 2015, MB91F577_DS705-00009-3v0-E 87

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 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
IPCP6 [R] W
000FD0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
000FD4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input capture 6,7
ICFS67 [R/W] LSYNS1 [R/W] ICS67 [R/W]
000FD8H B, H, W ― B,H,W B, H, W
------00 ----0000 00000000
IPCP8 [R] W
000FDCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP9 [R] W
000FE0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input capture 8,9
ICFS89 [R/W] ICS89 [R/W]
000FE4H B, H, W ― ― B, H, W
------00 00000000
IPCP10 [R] W
000FE8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP11 [R] W
000FECH Input capture
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
10,11
ICFS1011 [R/W] ICS1011 [R/W]
000FF0H B, H, W ― ― B, H, W
------00 00000000
000FF4H
to ― ― ― ― Reserved
000FFCH
SACR [R/W] PICD [R/W]
001000H B,H,W B,H,W ― ― Clock control
-------0 ----0011
001004H
to ― ― ― ― Reserved
00103CH
SGDER0 [R/W]
SGCR0[R/W] B,H,W
001040H ― B,H,W
-0000-0- 000--000
00000000
SGFR0[R/W] SGNR0[R/W]
SGAR0[R/W] B,H,W
001044H B,H,W B,H,W
00000000 00000000 Sound generator
00000000 00000000
0
SGTCR0[R/W] SGIDR0[R/W]
SGPCR0[R/W] B,H,W
001048H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR0[W] B,H,W
00104CH
00000000 00000000 00000000 00000000
001050H
to ― ― ― ― Reserved
00105CH

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CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
SGDER1[R/W]
SGCR1[R/W] B,H,W
001060H ― B,H,W
-0000-0- 000--000
00000000
SGFR1[R/W] SGNR1[R/W]
SGAR1[R/W] B,H,W
001064H B,H,W B,H,W
00000000 00000000 Sound generator
00000000 00000000
SGTCR1[R/W] SGIDR1[R/W] 1
SGPCR1[R/W] B,H,W
001068H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR1[W] B,H,W
00106CH
00000000 00000000 00000000 00000000
001070H
to ― ― ― ― Reserved
00107CH
SGDER2[R/W]
SGCR2[R/W] B,H,W
001080H ― B,H,W
-0000-0- 000--000
00000000
SGFR2[R/W] SGNR2[R/W]
SGAR2[R/W] B,H,W
001084H B,H,W B,H,W
00000000 00000000
00000000 00000000 Sound generator
2
SGTCR2[R/W] SGIDR2[R/W]
SGPCR2[R/W] B,H,W
001088H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR2[W] B,H,W
00108CH
00000000 00000000 00000000 00000000
001090H
to ― ― ― ― Reserved
00109CH
SGDER3[R/W]
SGCR3[R/W] B,H,W
0010A0H ― B,H,W
-0000-0- 000--000
00000000
SGFR3[R/W] SGNR3[R/W]
SGAR3[R/W] B,H,W
0010A4H B,H,W B,H,W
00000000 00000000 Sound generator
00000000 00000000
3
SGTCR3[R/W] SGIDR3[R/W]
SGPCR3[R/W] 00000000
0010A8H B,H,W B,H,W
B,H,W 11111111
00000000 00000000
SGDMAR3[W] B,H,W
0010ACH
00000000 00000000 00000000 00000000
0010B0H
to ― ― ― ― Reserved
0010BCH

June 19, 2015, MB91F577_DS705-00009-3v0-E 89

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 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
SGDER4[R/W]
SGCR4[R/W] B,H,W
0010C0H ― B,H,W
-0000-0- 000--000
00000000
SGFR4[R/W] SGNR4[R/W]
SGAR4[R/W] B,H,W
0010C4H B,H,W B,H,W
00000000 00000000 Sound generator
00000000 00000000
SGTCR4[R/W] SGIDR4[R/W] 4
SGPCR4[R/W] B,H,W
0010C8H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR4[W] B,H,W
0010CCH
00000000 00000000 00000000 00000000
0010D0H
to ― ― ― ― Reserved
00112CH
CRCCR[R/W]
001130H ― ― ― B,H,W
-0000000
CRCINIT[R/W] B,H,W
001134H CRC operation
1111111 1111111 1111111 1111111
CRCIN[R/W] B,H,W
001138H
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
00113CH
1111111 1111111 1111111 1111111
001140H
to ― ― ― ― Reserved
001FFCH

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 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
CTRLR0 [R/W] B,H,W STATR0[R/W] B,H,W
002000H
--------000-0001 -------- 00000000
ERRCNT0
BTR0[R/W] B,H,W
002004H [R] B,H,W
-0100011 00000001
00000000 00000000
INTR0
TESTR0[R/W] B,H,W
002008H [R] B,H,W
-------- X00000--
00000000 00000000
BRPER0
00200CH [R/W] B,H,W ―
-------- ----0000
IF1CREQ0 IF1CMSK0
002010H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
IF1MSK20 IF1MSK10
002014H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF1ARB20 IF1ARB10
002018H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1MCTR0
00201CH [R/W] B,H,W ―
00000000 0---0000
IF1DTA10
IF1DTA20[R/W] B,H,W CAN0
002020H [R/W] B,H,W
00000000 00000000 (64msb)
00000000 00000000
IF1DTB10 IF1DTB20
002024H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002028H,
Reserved
00202CH
002030H,
Reserved (IF1 data mirror)
002034H
002038H,
Reserved
00203CH
IF2CREQ0 IF2CMSK0
002040H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
IF2MSK20 IF2MSK10
002044H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF2ARB20 IF2ARB10
002048H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2MCTR0
00204CH [R/W] B,H,W ―
00000000 0---0000

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 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
IF2DTA10 IF2DTA20
002050H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2DTB10 IF2DTB20
002054H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002058H,
Reserved
00205CH
002060H,
Reserved (IF2 data mirror)
002064H
002068H
to Reserved
00207CH
TREQR20 TREQR10
002080H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
TREQR40 TREQR30
002084H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
002088H ― ―
00208CH ― ―
NEWDT20 NEWDT10
002090H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000 CAN0
NEWDT40 NEWDT30 (64msb)
002094H [R] B,H,W [R]B,H,W
00000000 00000000 00000000 00000000
002098H ― ―
00209CH ― ―
INTPND20 INTPND10
0020A0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
INTPND40 INTPND30
0020A4H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
0020A8H ― ―
0020ACH ― ―
MSGVAL20 MSGVAL10
0020B0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
MSGVAL40 MSGVAL30
0020B4H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
0020B8H ― ―
0020BCH ― ―
0020C0H
to Reserved
0020FCH

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CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
CTRLR1
STATR1[R/W] B,H,W
002100H [R/W] B,H,W
-------- 00000000
--------000-0001
ERRCNT1
BTR1[R/W] B,H,W
002104H [R] B,H,W
-0100011 00000001
00000000 00000000
INTR1
TESTR1[R/W] B,H,W
002108H [R] B,H,W
-------- X00000--
00000000 00000000
BRPER1
00210CH [R/W] B,H,W ―
-------- ----0000
IF1CREQ1 IF1CMSK1
002110H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
IF1MSK21 IF1MSK11
002114H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF1ARB21 IF1ARB11
002118H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1MCTR1
00211CH [R/W] B,H,W ―
00000000 0---0000 CAN1
IF1DTA11 IF1DTA21 (32msb)
002120H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1DTB11 IF1DTB21
002124H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002128H,
Reserved
00212CH
002130H,
Reserved (IF1 data mirror)
002134H
002138H,
Reserved
00213CH
IF2CREQ1 IF2CMSK1
002140H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
IF2MSK21 IF2MSK11
002144H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF2ARB21 IF2ARB11
002148H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2MCTR1
00214CH [R/W] B,H,W ―
00000000 0---0000

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 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
IF2DTA11 IF2DTA21
002150H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2DTB11 IF2DTB21
002154H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002158H,
Reserved
00215CH
002160H,
Reserved (IF2 data mirror)
002164H
002168H
to Reserved
00217CH
TREQR21 TREQR11
002180H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
002184H ― ―
002188H ― ―
00218CH ― ―
NEWDT21 NEWDT11 CAN1
002190H [R] B,H,W [R] B,H,W (32msb)
00000000 00000000 00000000 00000000
002194H ― ―
002198H ― ―
00219CH ― ―
INTPND21 INTPND11
0021A0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
0021A4H ― ―
0021A8H ― ―
0021ACH ― ―
MSGVAL21 MSGVAL11
0021B0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
0021B4H ― ―
0021B8H ― ―
0021BCH ― ―
0021C0H
to Reserved
0021FCH

94 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
CTRLR2
STATR2[R/W] B,H,W
002200H [R/W] B,H,W
-------- 00000000
-------- 000-0001
ERRCNT2[R] B,H,W BTR2[R/W] B,H,W
002204H
00000000 00000000 -0100011 00000001
INTR2[R] B,H,W TESTR2[R/W] B,H,W
002208H
00000000 00000000 -------- X00000--

BRPER2
00220CH [R/W] B,H,W ―
-------- ----0000
IF1CREQ2[R/W] B,H,W IF1CMSK2[R/W] B,H,W
002210H
0------- 00000001 -------- 00000000
IF1MSK22 IF1MSK12[R/W]
002214H [R/W] B,H,W B,H,W
11-11111 11111111 11111111 11111111
IF1ARB22 IF1ARB12[R/W]
002218H [R/W] B,H,W B,H,W
00000000 00000000 00000000 00000000
IF1MCTR2[R/W] B,H,W
00221CH ―
00000000 0---0000
IF1DTA12 IF1DTA22[R/W]
002220H [R/W] B,H,W B,H,W
00000000 00000000 00000000 00000000 CAN2
(32msb)
IF1DTB12 IF1DTB22[R/W]
002224H [R/W] B,H,W B,H,W
00000000 00000000 00000000 00000000
002228H,
Reserved
00222CH
002230H,
Reserved (IF1 data mirror)
002234H
002238H,
Reserved
00223CH
IF2CREQ2[R/W] B,H,W IF2CMSK2[R/W] B,H,W
002240H
0------- 00000001 -------- 00000000
IF2MSK22 IF2MSK12[R/W]
002244H [R/W] B,H,W B,H,W
11-11111 11111111 11111111 11111111
IF2ARB22[R/W] B,H,W IF2ARB12[R/W] B,H,W
002248H
00000000 00000000 00000000 00000000
IF2MCTR2[R/W] B,H,W
00224CH ―
00000000 0---0000
IF2DTA12[R/W] B,H,W IF2DTA22[R/W] B,H,W
002250H
00000000 00000000 00000000 00000000
IF2DTB12[R/W] B,H,W IF2DTB22[R/W] B,H,W
002254H
00000000 00000000 00000000 00000000

June 19, 2015, MB91F577_DS705-00009-3v0-E 95

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 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
002258H,
Reserved
00225CH
002260H,
Reserved (IF2 data mirror)
002264H
002268H
to Reserved
00227CH
TREQR22[R] B,H,W TREQR12[R] B,H,W
002280H
00000000 00000000 00000000 00000000
002284H ― ―
002288H ― ―
00228CH ― ―
NEWDT22[R] B,H,W NEWDT12[R] B,H,W
002290H
00000000 00000000 00000000 00000000 CAN2
002294H ― ― (32msb)
002298H ― ―
00229CH ― ―
INTPND22[R] B,H,W INTPND12[R] B,H,W
0022A0H
00000000 00000000 00000000 00000000
0022A4H ― ―
0022A8H ― ―
0022ACH ― ―
MSGVAL22[R] B,H,W MSGVAL12[R] B,H,W
0022B0H
00000000 00000000 00000000 00000000
0022B4H ― ―
0022B8H ― ―
0022BCH ― ―
0022C0H
to ― ― ― ― Reserved
0022FCH
DFCTLR[R/W] DFSTR[R/W]
002300H B,H,W ― B,H,W
-0------ -------- -----001 WorkFlash
002304H ― ― ― ―
FLIFCTLR FLIFFER1 FLIFFER2
Flash/
002308H [R/W] B,H,W ― [R/W] B,H,W [R/W] B,H,W
WorkFlash
---0--00 -------- --------
00230CH
to ― ― ― ― Reserved
0023FCH
SEEARX[R] B,H,W DEEARX[R] B,H,W
002400H --000000 00000000 --000000 00000000
-0000000 00000000*4 -0000000 00000000*4 XBS RAM
EFEARX [R/W] ECC control
EECSRX[R/W]
B,H,W register
002404H B,H,W ―
--000000 00000000 *4: MB91F578/9
----0000
-0000000 00000000*4 only
EFECRX [R/W] B,H,W
002408H ―
-------0 00000000 00000000
96 MB91F577_DS705-00009-3v0-E, June 19, 2015

CONFIDENTIAL
 D a t a S h e e t

Address offset value / Register name

Address Block
+0 +1 +2 +3
00240CH
to ― ― ― ― Reserved
002FFCH
SEEARA[R] B,H,W DEEARA[R] B,H,W
003000H -----000 00000000 -----000 00000000
----0000 00000000*4 ----0000 00000000*4 Backup RAM
EFEARA[R/W] ECC control
EECSRA[R/W]
B,H,W register
003004H B,H,W ―
-----000 00000000 *4: MB91F578/9
----0000
----0000 00000000*4 only
EFECRA [R/W] B,H,W
003008H ―
-------0 00000000 00000000
00300CH
to ― ― ― ― Reserved
003FFCH
004000H
Backup RAM
to Backup-RAM*5
area
007FFCH

008000H
Reserved
to ― ― ― ―
(00F000H to[S])
00FEFCH
DSUCR [R/W] B,H,W
00FF00H ― ― OCDU [S]
-------- -------0
00FF04H
to ― ― ― ― Reserved [S]
00FF0CH
PCSR [R/W] B,H,W
00FF10H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
PSSR [R/W] B,H,W
00FF14H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
to ― ― ― ― Reserved [S]
00FFF4H
EDIR1 [R] B,H,W
00FFF8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
EDIR0 [R] B,H,W
00FFFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S] : It is a system register. The illegal instruction exception (data access error) is generated when read/write is
performed on these registers in the user mode.
*3: The initial value is different by part number. For details, refer to the CSVCR register in chapter “Clock Supervisor”

*4: MB91F578/9 only

*5: See the maximum size of series on the memory map

June 19, 2015, MB91F577_DS705-00009-3v0-E 97

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 D a t a S h e e t

 INTERRUPT VECTOR TABLE

This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.

 Interrupt Vector
Interrupt
Default
number Interrupt RN
Interrupt factor Offset address for
Deci Hexa- level
TBR *1
mal decimal
Reset 0 00 - 3FCH 000FFFFCH -
System reserved 1 01 - 3F8H 000FFFF8H -
System reserved 2 02 - 3F4H 000FFFF4H -
System reserved 3 03 - 3F0H 000FFFF0H -
System reserved 4 04 - 3ECH 000FFFECH -
FPU exception 5 05 - 3E8H 000FFFE8H -
Exception of instruction access protection
6 06 - 3E4H 000FFFE4H -
violation
Exception of data access protection violation 7 07 - 3E0H 000FFFE0H -
Data access error interrupt 8 08 - 3DCH 000FFFDCH -
INTE instruction 9 09 - 3D8H 000FFFD8H -
Instruction break 10 0A - 3D4H 000FFFD4H -
System Reserved 11 0B - 3D0H 000FFFD0H -
System Reserved 12 0C - 3CCH 000FFFCCH -
System Reserved 13 0D - 3C8H 000FFFC8H -
Exception of illegal instruction 14 0E - 3C4H 000FFFC4H -
NMI request/
15 (FH)
XBS RAM double-bit error detection/ 15 0F 3C0H 000FFFC0H -
Fixed
Backup RAM double-bit error detection
External interrupt 0-7 16 10 ICR00 3BCH 000FFFBCH 0
External interrupt 8-15 17 11 ICR01 3B8H 000FFFB8H 1
Reload timer 0/1/4/5 18 12 ICR02 3B4H 000FFFB4H 2(*2)
Reload timer 2/3/6 19 13 ICR03 3B0H 000FFFB0H 3(*2)

Multi-function serial interface ch.0 (reception

completed)/ 20 14 ICR04 3ACH 000FFFACH 4 (*3)
Multi-function serial interface ch.0 (status)

Multi-function serial interface ch.0

21 15 ICR05 3A8H 000FFFA8H 5
(transmission completed)

Multi-function serial interface ch.1 (reception

completed)/ 22 16 ICR06 3A4H 000FFFA4H 6 (*3)
Multi-function serial interface ch.1 (status)
Multi-function serial interface ch.1
23 17 ICR07 3A0H 000FFFA0H 7
(transmission completed)
LIN-UART2 (reception completed) 24 18 ICR08 39C H 000FFF9CH 8
LIN-UART2 (transmission completed) 25 19 ICR09 398H 000FFF98H 9
LIN-UART3 (reception completed) 26 1A ICR10 394H 000FFF94H 10
LIN-UART3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11
LIN-UART4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12

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 D a t a S h e e t

Interrupt
number Default RN
Interrupt
Interrupt factor Offset address for
Deci Hexa- level
TBR *1
mal decimal
LIN-UART4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13
LIN-UART5 (reception completed) 30 1E ICR14 384H 000FFF84H 14
LIN-UART5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15
LIN-UART6 (reception completed) 32 20 ICR16 37CH 000FFF7CH 16
LIN-UART6 (transmission completed) 33 21 ICR17 378H 000FFF78H 17
CAN0 34 22 ICR18 374H 000FFF74H -
CAN1 35 23 ICR19 370H 000FFF70H -
CAN2/
Up/down counter 0/ 36 24 ICR20 36CH 000FFF6CH -
Up/down counter 1
Real time clock 37 25 ICR21 368H 000FFF68H -
Sound generator 0 /
38 26 ICR22 364H 000FFF64H 22
LIN-UART7 (reception completed)
Sound generator 1 /
39 27 ICR23 360H 000FFF60H 23
LIN-UART7 (transmission completed)
PPG0/1/10/11/20/21 40 28 ICR24 35CH 000FFF5CH 24
PPG2/3/12/13/22/23 41 29 ICR25 358H 000FFF58H 25
PPG4/5/14/15 42 2A ICR26 354H 000FFF54H 26
PPG6/7/16/17 43 2B ICR27 350H 000FFF50H 27
PPG8/9/18/19 44 2C ICR28 34CH 000FFF4CH 28
Multi-function serial interface ch.8 (reception
completed)/ 29
45 2D ICR29 348H 000FFF48H
Multi-function serial interface ch.8 (status) / (*4)
HS_SPI reception interrupt request
Main timer/Sub timer/PLL timer /
Multi-function serial interface 30
46 2E ICR30 344H 000FFF44H
ch.8(transmission completed)/ (*4)
HS_SPI transmission interrupt request
Clock calibration unit (Sub oscillation) /
Sound generator 4/
31
Multi-function serial interface ch.9 (reception 47 2F ICR31 340H 000FFF40H
(*5)
completed) /
Multi-function serial interface ch.9 (status)
A/D converter 48 30 ICR32 33CH 000FFF3CH 32
Clock calibration Unit (CR oscillation) /
33
Multi-function serial interface ch.9 49 31 ICR33 338H 000FFF38H
(*5)
(transmission completed)
Free-run timer 0/2/4 50 32 ICR34 334H 000FFF34H -
Free-run timer 1/3/5 51 33 ICR35 330H 000FFF30H -
ICU0/6 (fetching) 52 34 ICR36 32CH 000FFF2CH 36
ICU1/7 (fetching) 53 35 ICR37 328H 000FFF28H 37
ICU2/8 (fetching) 54 36 ICR38 324H 000FFF24H 38
ICU3/9 (fetching) 55 37 ICR39 320H 000FFF20H 39
ICU4/10 (fetching) 56 38 ICR40 31CH 000FFF1CH 40

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Interrupt
number Default RN
Interrupt
Interrupt factor Offset address for
Deci Hexa- level
TBR *1
mal decimal
ICU5/11 (fetching) 57 39 ICR41 318H 000FFF18H 41
OCU0/1/6/7/10/11 (match) 58 3A ICR42 314H 000FFF14H 42
OCU2/3/4/5/8/9 (match) 59 3B ICR43 310H 000FFF10H 43
Base timer 0 IRQ0 /
Base timer 0 IRQ1 / 60 3C ICR44 30CH 000FFF0CH 44
Sound generator 2
Base timer 1 IRQ0 /
Base timer 1 IRQ1 /
45
Sound generator 3 / 61 3D ICR45 308H 000FFF08H
(*6)
XBS RAM single bit error generation /
Backup RAM single bit error generation
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3E ICR46 304H 000FFF04H -
Delayed interrupt 63 3F ICR47 300H 000FFF00H -
System reserved
64 40 - 2FCH 000FFEFCH -
(Used for REALOSTM*7.)
System reserved
65 41 - 2F8H 000FFEF8H -
(Used for REALOS.)
66 42 2F4H 000FFEF4H
Used with the INT instruction. | | - | | -
255 FF 000H 000FFC00H
*1: It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN
(Resource Number) is assigned.
*2: Reload timer ch.4 to ch.6 does not support the DMA transfer by the interrupt.
*3: The status of the multi-function serial interface does not support the DMA transfer by I 2C reception.
*4: HS_SPI does not support the DMA transfer by the interrupt.
*5: The clock calibration unit does not support the DMA transfer by the interrupt.
*6: It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
*7: REALOS is the trademark of Spansion LLC.

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 ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter Symbol Unit Remarks
Min Max
VCC5 VSS-0.3 VSS+6.0 V
Power supply voltage*1,*2 DVCC VSS-0.3 VSS+6.0 V DVCC ≤ VCC5
VCCE VSS-0.3 VSS+6.0 V VCCE ≤ VCC5
AVRH ≤ AVCC ≤
Analog power supply voltage*1,*2 AVCC VSS-0.3 VSS+6.0 V
VCC5
1
Analog reference voltage* AVRH VSS-0.3 VSS+6.0 V AVRH ≤ AVCC
VI1 VSS-0.3 VCC5+0.3 V
Input voltage*1 VI2 VSS-0.3 VCC5+0.3 V SMC shared pin
VIE VSS-0.3 VCC5+0.3 V
Analog pin input voltage*1 VIA5 VSS-0.3 VCC5+0.3 V
VO1 VSS-0.3 VCC5+0.3 V
Output voltage*1 VO2 VSS-0.3 VCC5+0.3 V SMC shared pin
VOE VSS-0.3 VCC5+0.3 V
Maximum clamp current ICLAMP -4 4 mA *8
Total maximum clamp current Σ|ICLAMP | – 20 mA *8
I OL1 – 7 mA 2mA is selected*6
"L" level maximum output current *3
IOL2 – 40 mA 30mA is selected *7
IOLAV1 – 2 mA 2mA is selected *6
"L" level average output current *4
IOLAV2 – 30 mA 30mA is selected *7
ΣIOL1 – 50 mA *6
"L" level total output current*5
ΣIOL2 – 250 mA *7
IOH1 * 3
– -7 mA 2mA is selected*6
"H" level maximum output current*3
IOH2 * 3
– -40 mA 30mA is selected *7
IOHAV1 * 4
– -2 mA 2mA is selected *6
"H" level average output current*4
IOHAV2 *4 – -30 mA 30mA is selected *7
ΣIOH1 – -50 mA *6
"H" level total output current*5
ΣIOH2 – -250 mA *7
Power consumption PD – 710 mW
Operating temperature TA -40 +105 °C
Storage temperature Tstg -55 +150 °C
*1: This parameter is based on VSS=AVSS=DVSS=0.0V.
*2: Caution must be taken that AVCC, DVCC, and VCCE do not exceed VCC5 upon power-on and under other
circumstances.
*3: Maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: Average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Outputs other than P60-P87 pins
*7: Output of P60-P87 pins

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*8: • Corresponding pins: all general-purpose ports. (Except P010 to P017, P020 to P027, P030 to P037, P040
to P047, P050 to P053, P90/ADTG/PPG0_2)
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
• Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+ B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
• Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
• Do not leave + B input pins open.

Sample recommended circuit

MB91570 series

Protective diode
Limiting resistor current

+Binput (12 to 16V)

<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

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2. Recommended operating conditions

(VSS=DVSS=AVSS=0.0V)
Value
Parameter Symbol Unit Remarks
Min Max
VCC5 4.5 5.5 V
DVCC 4.5 5.5 V
Recommended operation guarantee range
AVCC5 4.5 5.5 V
Power supply VCCE 3.0 5.5 V
voltage VCC5 3.5 5.5 V
DVCC 3.5 5.5 V
Operation guarantee range
AVCC5 3.5 5.5 V
VCCE 2.7 5.5 V
Use a ceramic capacitor or a capacitor that has
4.7
Smoothing the similar frequency characteristics. Use a
CS (tolerance μF
capacitor * capacitor with a capacitance greater than CS as
within±50%)
the smoothing capacitor on the VCC pin.
Operating
TA -40 +105 °C
temperature
*: Refer to the following diagram for details on the connection of smoothing capacitor CS.

 C Pin Connection Diagram

CS VSS DVSS AVSS

<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under
any conditions other than these conditions may adversely affect reliability of device and could result in
device failure. No warranty is made with respect to any use, operating conditions or combinations not
represented on this data sheet. If you are considering application under any conditions other than listed
herein, please contact sales representatives beforehand.

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3. DC characteristics
(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=DVSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
CMOS
VCC5
VIH1 input level 0.7×VCCE – V *
+0.3
is selected
CMOS
hysteresis VCC5
VIH2
input level
0.7×VCCE – +0.3
V *
P010 to P017,
P020 to P027, is selected
P030 to P036 Automotive
VCC5
VIH3 input level 0.8×VCCE – +0.3
V *
is selected
TTL input
VCC5
VIH4 level is 2.0 – +0.3
V *
selected
P000 to P007, CMOS
VCC5
VIH5 P037, input level 0.7×VCC5 – +0.3
V
P040 to P047, is selected
P050 to P057, CMOS
P060 to P067, hysteresis VCC5
“H” level input VIH6
P070 to P077, input level
0.7×VCC5 – +0.3
V
voltage
P080 to P087, is selected
P090 to P097, Automotive
VCC5
VIH7 P100 to P107, input level 0.8×VCC5 – +0.3
V
P110 to P117, is selected
P120 to P127,
P130 to P137,
P140 to P147,
TTL input
P150 to P157, VCC5
VIH8
P160 to P167,
level is 2.0 – +0.3
V
selected
P170 to P177,
P180 to P187,
P190 to P197*1
VCC5
VIH9 RSTX, NMIX, MD2 – 0.7×VCC5 – +0.3
V
VCC5
VIH10 MD0, MD1 – 0.7×VCC5 – V
+0.3
VCC5
VIH11 DEBUGIF – 2.0 – +0.3
V

* : VCCE=5.0V±10%, or VCCE=3.0 to 3.6V

*1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to
P197.

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(TA: Recommended operating conditions, VCC5=5.0 V±10%, VCCE=5.0 V±10%, VSS=DVSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
CMOS
VSS
VIL1 input level – 0.3×VCCE V *
-0.3
is selected
CMOS
hysteresis VSS
VIL2
input level -0.3
– 0.3×VCCE V *
P010 to P017,
P020 to P027, is selected
P030 to P036 Automotive
VSS
VIL3 input level
-0.3
– 0.5×VCCE V *
is selected
TTL input
VSS
VIL4 level is
-0.3
– 0.8 V *
selected
P000 to P007, CMOS
VSS
VIL5 P037, input level
-0.3
– 0.3×VCC5 V
P040 to P047, is selected
P050 to P057, CMOS
P060 to P067, hysteresis VSS
“L” level VIL6
P070 to P077,
– 0.3×VCC5 V
input level -0.3
input voltage
P080 to P087, is selected
P090 to P097, Automotive
VSS
VIL7 P100 to P107, input level – 0.5×VCC5 V
-0.3
P110 to P117, is selected
P120 to P127,
P130 to P137,
P140 to P147,
TTL input
P150 to P157, VSS
VIL8
P160 to P167,
level is
-0.3
– 0.8 V
selected
P170 to P177,
P180 to P187,
P190 to P197*1
VSS
VIL9 RSTX, NMIX, MD2 – -0.3
– 0.3×VCC5 V
VSS
VIL10 MD0, MD1 – -0.3
– 0.3×VCC5 V
VSS
VIL11 DEBUGIF – -0.3
– 0.8 V

*: VCCE=5.0V±10%, or VCCE=3.0 to 3.6V

*1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to
P197.

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(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=DVSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max

VCCE = 3.0V VCCE

VOH1
IOH = -0.5mA -0.5
– VCCE V *
P010 to P017,
P020 to P027, VCCE = 3.0V VCCE
VOH2 P030 to P036 IOH = -1.0mA -0.5
– VCCE V *
VCCE = 3.0V VCCE
VOH3
IOH = -2.0mA -0.5
– VCCE V *
P000 to P007,
VCC5 = 4.5V VCC5
VOH4 P037,
I = -1.0mA -0.5
– VCC5 V
P040 to P047, OH

P050 to P056,
P060 to P067,
“H” level P070 to P077,
output P080 to P087,
voltage P090 to P097,
P100 to P107,
P110 to P117,
VCC5 = 4.5V VCC5
VOH5 P120 to P127,
I = -2.0mA -0.5
– VCC5 V
P130 to P137, OH

P140 to P147,
P150 to P157,
P160 to P167,
P170 to P177,
P180 to P187,
P190 to P197*1
P060 to P067,
DVCC = 4.5V DVCC SMC
VOH6 P070 to P077,
IOH = -30.0mA -0.5
– DVCC V
shared pin
P080 to P087
* : VCCE=5.0V±10%, or VCCE=3.0 to 3.6V
*1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to
P197.

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(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=DVSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Condition Unit Remarks
Min Typ Max
VCCE = 3.0V
VOL1 0 – 0.4 V *
IOL = 0.5mA
P010 to P017,
VCCE = 3.0V
VOL2 P020 to P027,
IOL = 1.0mA
0 – 0.4 V *
P030 to P036
VCCE = 3.0V
VOL3
IOL = 2.0mA
0 – 0.4 V *
P000 to P007, VCC5 = 4.5V
VOL4
P037, IOL = 1.0mA
0 – 0.4 V
P040 to P047,
P050 to P056,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
“L” level P110 to P117, VCC5 = 4.5V
output
VOL5
P120 to P127,
0 – 0.4 V
IOL = 2.0mA
voltage P130 to P137,
P140 to P147,
P150 to P157,
P160 to P167,
P170 to P177,
P180 to P187,
P190 to P197*1
P060 to P067,
DVCC = 4.5V SMC
VOL6 P070 to P077,
IOL = 30.0mA
0 – 0.55 V
shared pin
P080 to P087
I2C shared
P127, P130, VCC5 = 4.5V pin
VOL7
P132, P133 IOL = 3.0mA
0 – 0.4 V
(I2C is
selected)
VCC5 = 2.7V
VOL8 DEBUGIF
IOL = 25.0mA
0 – 0.25 V
* : VCCE=5.0V±10%, or VCCE=3.0 to 3.6V
*1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to
P197.

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(TA: Recommended operating conditions, VCC5=5.0V±10%,VCCE=5.0V±10%,VSS=DVSS=AVSS=0.0V)

Value Re
Parameter Symbol Pin name Condition Unit mar
Min Typ Max ks
Port input pins
VCC5=VCCE=
IIL1 other than -5 – +5 μA
Input leak DVCC=AVCC=
P107,123
current 5.5V
P107,P123
IIL2
(DA shared pin)
VSS<VI<VCC -10 – +10 μA
RUP1 RSTX, NMIX – 25 – 100 kΩ
Pull-up
Pull-up resistance
resistance RUP2 All port input pins
is selected
25 – 100 kΩ
RDOWN1 MD2 – 25 – 100 kΩ
Pull-down Pull-down
resistance RDOWN2 All port input pins resistance is 25 – 100 kΩ
selected
Other than VCCE,
VCC5, VSS,
DVCC, DVSS,
CIN1 AVCC, AVSS, C, – – 5 15 pF
Input P060 to P067,
capacitance P070 to P077,
P080 to P087
P060 to P067,
CIN2 P070 to P077, When using SMC – 15 45 pF
P080 to P087

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(TA: Recommended operating conditions, VCC5=5.0V±10%,VCCE=5.0V±10%,VSS=DVSS=AVSS=0.0V)

Pin Value
Parameter Symbol Condition Unit Remarks
name Min Typ Max
At normal operation 100 *4
Operating frequency
– 60 mA
FCP=80MHz,
Fcpp=40MHz 125 *5

FLASH write 115 *3, *4

Operating frequency
ICC5 – 75 mA
FCP=80MHz,
Fcpp=40MHz 140 *3, *5

At FLASH erase 115 *3, *4

Operating frequency
– 75 mA
FCP=80MHz,
Fcpp=40MHz 140 *3, *5

At sleep mode 60 *4
Operating frequency
ICCS5
FCP=80MHz,
– 20 mA
Fcpp=40MHz 75 *5
Power
supply VCC5 At bus sleep mode 55 *4
current Operating frequency
ICCBS5 – 15 mA
FCP=80MHz,
Fcpp=40MHz 70 *5

When using
At RTC mode – 750 1400 μA external clock*1,
ICCT5 4MHz source TA=25˚C
oscillation When using
– 900 1550 μA
crystal, TA=25˚C
When using
At RTC mode – 170 330 μA external clock*1,
shutdown TA=25˚C
ICCTS5
4MHz source
When using
oscillation – 320 480 μA
crystal, TA=25˚C

ICCH5 At stop mode – 400 1200 μA TA=25˚C

At stop mode
ICCHS5
shutdown
– 120 240 μA TA=25˚C

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(TA: Recommended operating conditions, VCC5=5.0V±10%,VCCE=5.0V±10%,VSS=DVSS=AVSS=0.0V)

Value Rem
Parameter Symbol Pin name Condition Unit
Min Typ Max arks

High current PWM1Pn,

DVCC =4.5V
output drive PWM1Mn,
IOH=-30.0mA
capacity ΔVOH6 PWM2Pn,
Maximum
– – 90 mV *2
Phase-to-phase PWM2Mn
deviation of VOH6
deviation1 (n=0 to 5)
High current PWM1Pn,
DVCC =4.5V
output drive PWM1Mn,
IOL=30.0mA
capacity ΔVOL6 PWM2Pn,
Maximum
– – 90 mV *2
Phase-to-phase PWM2Mn
deviation of VOL6
deviation2 (n=0 to 5)
V0 to V1,
LCD divider
RLCD V1 to V2, – 6.25 12.5 25 kΩ
resistor
V2 to V3
COM0 to COM3 COMm
output impedance
RVCOM
(m=0 to 3)
– – – 4.5 kΩ
SEG00 to SEG31 SEGn
output impedance
RVSEG
(n=00 to 31)
– – – 17 kΩ
V0 to V3,
COMm
LCDC leak
current
ILCDC (m=0 to 3), TA=+25˚C -0.5 – +0.5 μA
SEGn
(n=00 to 31)
*1: The power supply current value when the external clock is supplied from the X1 pin. Note that the power
supply current value when using the external clock is different from that using the oscillator.
*2: If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of
VOH6 / VOL6 for each pin is defined. Same for other channels.
*3: This product contains both program flash and WorkFlash. This parameter is defined when only one of them
is in the write/erase state.
*4: MB91F575/7
*5: MB91F578/9

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4. AC Characteristics
(1) Main Clock Timing
(TA: Recommended operating conditions, VCC5 =5.0V±10%, VSS=DVSS=AVSS=0.0V)
Pin Condi Value
Parameter Symbol Unit Remarks
name tions Min Typ Max
Source oscillation clock
FC X0,X1 – – 4 – MHz
frequency
Source oscillation clock
tCYL X0,X1 – – 250 – ns
cycle time
FCP – – 2 – 80 MHz CPU clock
Internal operating clock
FCPP – – 2 – 40 MHz Peripheral bus clock
cycle time*
FCPT – – 2 – 40 MHz External bus clock
tCP – – 12.5 – 500 ns CPU clock
Internal operating clock
tCPP – – 25 – 500 ns Peripheral bus clock
cycle time*
tCPT – – 25 – 500 ns External bus clock
CAN PLL jitter FCP=80MHz
tPJ – – -10 – +10 ns
(when lock) (4MHz×Multiplied by 20)
Built-in CR oscillation
frequency
FCCR – – 50 100 200 kHz
*: The maximum / minimum value is defined when using the main clock and PLL clock.

 X0,X1 clock timing

tCYL

X0

 CAN PLL jitter

Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.

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(1-2) Sub clock timing (products without s-suffix)

(TA: Recommended operating conditions, VCC=5.0V±10%,VSS=DVSS=AVSS=0.0V)

Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
Source oscillation clock
FCL X0A,X1A – 32.768 – kHz
frequency
–
Source oscillation clock
cycle time
tLCYL X0A,X1A – 30.52 – µs

 X0A,X1A clock timing

tLCYL

X0A

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 Guaranteed operation range

Internal operation clock frequency vs. Power supply voltage

Note: The CPU will be reset at the power supply voltage 4V±0.3V or less.

Oscillation clock frequency vs. Internal operation clock frequency

Internal operation clock frequency
PLL clock
Main Multipli Multipli
Multipli Multipli Multipli Multipli
Clock ... ed by ed by
ed by 1 ed by 2 ed by 3 ed by 4
19 20
Oscillation
clock 4MHz 2MHz 4MHz 8MHz 12MHz 16MHz ... 76MHz 80MHz
frequency

 Example of oscillation circuit

X0 X1

0
R=0
4MHz

C1=10pF C2=10pF

Note: As to the product with its clock supervisor’s initial value is ”ON”, when the oscillator is unable
to start within 20ms from the stop state the clock supervisor will detect the oscillation stop. As
a result, the CPU moves to the fail safe operation.
Design your printed circuit board so that the oscillator can start oscillation within 20ms.

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AC characteristics are specified by the following measurement reference voltage values.

 Input Signal Waveform  Output Signal Waveform

Hysteresis Input Pin (Automotive) Output Pin
0.8Vcc 2.4V
0.5Vcc 0.8V

Hysteresis Input Pin (CMOS Normal)

0.7Vcc
0.3Vcc

Hysteresis Input Pin (CMOS Hysteresis)

0.7Vcc
0.3Vcc

TTL Input Pin

2.0V
0.8V

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(2) Reset Input

(TA: Recommended operating conditions, VCC5 =5.0V±10%, VSS=AVSS=0.0V)
Con Value
Sym Pin
Parameter ditio Unit Remarks
bol name Min Max
ns
Under normal
10 – µs
operation
Reset input time Oscillation time of oscillator*
– ms In Stop mode
tRSTL RSTX – +100µs
100µs – µs In RTC mode
Width for reset
input removal
1µs – µs
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%.
For crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms, and for an external clock, the time is 0 ms.

t
RSTL,

RSTX
0.2Vcc5 0.2Vcc5

 In Stop mode
tRSTL

RSTX
0.2 VCC5 0.2 VCC5

90% of
amplitude
X0

Internal operation
clock 100 μs
Oscillation time Oscillation stabilization
of oscillator waiting time

Instruction
Internal reset execution

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(3) Power-on Conditions

(TA: Recommended operating conditions, VSS=0.0V)
Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
When turning on
Level detection
– VCC5 – 2.1 2.3 2.5 V power for
voltage
microcontroller
Level detection During voltage
– VCC5 – – – 125 mV
hysteresis width drop
Level detection time – – – – – 30 us *1
VCC5 = at level
Slope detection
– VCC5 detection release – – 4 mV/µs *2
undetected standard
level time
Power off time tOFF VCC5 – 50 – – ms *3
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope
detection. This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss

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(4) Multi-function Serial

(4-1) UART timing

Bit setting: SMR:MD2=0,SMR:MD1=1,SMR:MD0=0,SMR:SCINV=0,SCR:SPI=0

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK0, SCK1,
Serial clock cycle time tSCYC 4tCPP – ns
SCK8, SCK9
SCK0, SCK1,
SCK ↓→ SCK8, SCK9, Internal shift clock mode:
tSLOVI -30 +30 ns CL=50pF(When drive
SOT delay time SOT0, SOT1,
SOT8, SOT9 – capability is 2mA or more.)
CL=20pF(When drive
Valid SIN→
tIVSHI SCK0, SCK1, 34 – ns capability is 1mA)
SCK ↑ setup time SCK8, SCK9,
SCK ↑→ SIN0, SIN1,
tSHIXI SIN8, SIN9 0 – ns
Valid SIN hold time
Serial clock "H" pulse
width
tSHSL tCPP+10 – ns
SCK0, SCK1,
SCK8, SCK9
Serial clock "L" pulse width tSLSH 2tCPP-10 – ns

SCK0, SCK1,
SCK ↓→ SCK8, SCK9,
tSLOVE
SOT0, SOT1,
– 33 ns
SOT delay time External shift clock mode:
SOT8, SOT9 CL=50pF(When drive
Valid SIN→ – capability is 2mA or more.)
tIVSHE SCK0, SCK1, 10 – ns CL=20pF(When drive
SCK ↑setup time SCK8, SCK9,
capability is 1mA)
SCK ↑→ SIN0, SIN1,
tSHIXE SIN8, SIN9 20 – ns
Valid SIN hold time
SCK0, SCK1,
SCK fall time tF
SCK8, SCK9
– 5 ns

SCK0, SCK1,
SCK rise time tR
SCK8, SCK9
– 5 ns

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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• Internal shift clock mode

tSCYC
2.4V
SCKx
0.8V 0.8V
tSLOVI

2.4V
SOTx
0.8V
tIVSHI tSHIXI
VIH VIH
SINx VIL VIL

• External shift clock mode

tSLSH tSHSL

VIH VIH VIH

SCKx
VIL VIL VIL

tF tSLOVE tR
2.4V
SOTx
0.8V

tIVSHE tSHIXE
VIH VIH
SINx VIL VIL

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Bit setting: SMR:MD2=0,SMR:MD1=1,SMR:MD0=0,SMR:SCINV=1,SCR:SPI=0

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK0, SCK1,
Serial clock cycle time tSCYC 4tCPP – ns
SCK8, SCK9
SCK0, SCK1,
SCK ↑ → SCK8, SCK9, Internal shift clock mode:
tSHOVI -30 +30 ns CL=50pF(When drive
SOT delay time SOT0, SOT1,
SOT8, SOT9 – capability is 2mA or more.)
CL=20pF(When drive
Valid SIN→
tIVSLI SCK0, SCK1, 34 – ns capability is 1mA)
SCK ↓setup time SCK8, SCK9,
SCK ↓ → SIN0, SIN1,
tSLIXI SIN8, SIN9 0 – ns
Valid SIN hold time
Serial clock "H" pulse
width
tSHSL tCPP+10 – ns
SCK0, SCK1,
SCK8, SCK9
Serial clock "L"pulse width tSLSH 2tCPP-10 – ns

SCK0, SCK1,
SCK ↑ → SCK8, SCK9,
tSHOVE
SOT0, SOT1,
– 33 ns
SOT delay time External shift clock mode:
SOT8, SOT9 CL=50pF(When drive
Valid SIN→ – capability is 2mA or more.)
tIVSLE SCK0, SCK1, 10 – ns CL=20pF(When drive
SCK ↓setup time SCK8, SCK9,
capability is 1mA)
SCK ↓ → SIN0, SIN1,
tSLIXE SIN8, SIN9 20 – ns
Valid SIN hold time
SCK0, SCK1,
SCK fall time tF
SCK8, SCK9
– 5 ns

SCK0, SCK1,
SCK rise time tR
SCK8, SCK9
– 5 ns

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V 2.4V
SCKx
0.8V

t SHOVI
2.4V
SOTx
0.8V
t IVSLI t SLIXI
V IH VIH
SINx V IL
V IL

 External shift clock mode

tS H S L tS LS H

VIH VIH VIH

SCKx
VIL VIL VIL

tR tS HO V E tF
2 .4 V
SOTx
0 .8 V

tIV SLE tS LIX E

VIH VIH
S IN x VIL VIL

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Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit
Min Min
SCK0, SCK1,
Serial clock cycle time tSCYC 4tCPP – ns
SCK8, SCK9
SCK0, SCK1,
SCK↑→SOT SCK8, SCK9,
tSHOVI -30 +30 ns
delay time SOT0, SOT1,
SOT8, SOT9 Internal shift clock mode
CL=50pF(When drive capability is
Valid SIN→SCK↓ SCK0, SCK1, 2mA or more.)
tIVSLI 34 – ns
setup time SCK8, SCK9, CL=20pF(When drive capability is
SCK↓→ SIN0, SIN1, 1mA)
tSLIXI SIN8, SIN9 0 – ns
Valid SIN hold time
SCK0, SCK1,
SOT→SCK↓ SCK8, SCK9,
tSOVLI 2tCPP-30 – ns
delay time SOT0, SOT1,
SOT8, SOT9
Serial clock "H" pulse
tSHSL tCPP+10 – ns
width SCK0, SCK1,
Serial clock "L" pulse SCK8, SCK9
tSLSH 2tCPP-10 – ns
width
SCK0, SCK1,
SCK↑→SOT SCK8, SCK9,
tSHOVE – 33 ns
delay time SOT0, SOT1, External shift clock mode
SOT8, SOT9 CL=50pF(When drive capability is
Valid SIN→SCK↓ SCK0, SCK1,
2mA or more.)
tIVSLE C =20pF(When drive capability is 10 – ns
setup time SCK8, SCK9, L
1mA)
SCK↓→ SIN0, SIN1,
tSLIXE SIN8, SIN9 20 – ns
Valid SIN hold time
SCK0, SCK1,
SCK fall time tF – 5 ns
SCK8, SCK9
SCK0, SCK1,
SCK rise time tR – 5 ns
SCK8, SCK9

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum baud rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V
SCKx
0.8V tSHOVI 0.8V
tSOVLI

2.4V 2.4V
SOTx
0.8V 0.8V
tIVSLI tSLIXI

VIH VIH
SINx VIL VIL

 External shift clock mode

tSLSH tSHSL

VIH VIH VIH

SCKx
VIL VIL VIL

* tF tR tSHOVE
2.4V 2.4V
SOTx
0.8V 0.8V
tIVSLE tSLIXE

VIH VIH
SINx VIL VIL

*: Changes when writing to TDR register

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Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit
Min Min
SCK0, SCK1,
Serial clock cycle time tSCYC 4tCPP – ns
SCK8, SCK9
SCK0, SCK1,
SCK↓→SOT SCK8, SCK9,
tSLOVI -30 +30 ns
delay time SOT0, SOT1,
SOT8, SOT9 Internal shift clock mode
CL=50pF (When drive capability
Valid SIN→SCK↑ SCK0, SCK1, is 2mA or more.)
tIVSHI 34 – ns
setup time SCK8, SCK9, CL=20pF (When drive capability
SCK↑→ SIN0, SIN1, is 1mA)
tSHIXI SIN8, SIN9 0 – ns
Valid SIN hold time
SCK0, SCK1,
SOT→SCK↑ SCK8, SCK9,
tSOVHI 2tCPP-30 – ns
delay time SOT0, SOT1,
SOT8, SOT9
Serial clock "H"pulse
tSHSL tCPP+10 – ns
width SCK0, SCK1,
Serial clock "L" pulse SCK8, SCK9
tSLSH 2tCPP-10 – ns
width
SCK0, SCK1,
SCK↓→SOT SCK8, SCK9,
tSLOVE – 33 ns
delay time SOT0, SOT1, External shift clock mode
SOT8, SOT9 CL=50pF (When drive capability
Valid SIN→SCK↑ SCK0, SCK1,
is 2mA or more.)
tIVSHE C =20pF (When drive capability 10 – ns
setup time SCK8, SCK9, L
is 1mA)
SCK↑→ SIN0, SIN1,
tSHIXE SIN8, SIN9 20 – ns
Valid SIN hold time
SCK0, SCK1,
SCK fall time tF – 5 ns
SCK8, SCK9
SCK0, SCK1,
SCK rise time tR – 5 ns
SCK8, SCK9

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum baud rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V 2.4V
SCKx
0.8V
tSOVHI
tSLOVI

2.4V 2.4V
SOTx
0.8V 0.8V
tIVSHI tSHIXI

VIH VIH
SINx VIL VIL

 External shift clock mode

tSHSL tSLSH
tR tF
VIH VIH VIH
SCKx
VIL VIL VIL

tSLOVE
*
2.4V 2.4V
SOTx
0.8V 0.8V
tIVSHE tSHIXE

VIH VIH
SINx VIL VIL

*: Changes when writing to TDR register

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(4-2)External clock (EXT = 1): asynchronous only

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Conditions Unit
Min Max

Serial clock "H" pulse width tSHSL CL=50pF tCPP+10 - ns

(When drive capability is
Serial clock "L" pulse width tSLSH SCK0, SCK1, 2mA or more.) tCPP+10 - ns
SCK fall time tF SCK8, SCK9 CL=20pF - 5 ns
(When drive capability is
SCK rise time tR 1mA) - 5 ns

tR tF
tSHSL tSLSH
SCK VIH VIH VIH
VIL VIL VIL

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2
(4-3) I C timing
(TA: Recommended operating conditions, VCC5=5.0V±10%, VSS=AVSS=0.0V)
Standard High-speed
Sym mode mode Uni Rema
Parameter Pin name Conditions
bol t rks
Min Max Min Max
SCK0_0,
SCL clock frequency fSCL 0 100 0 400 kHz
SCK1_0
SOT0_0,
SOT1_0
Repeat "start" condition
(SDA)
hold time tHDSTA
SCK0_0,SC
4.0 – 0.6 – µs
SDA ↓→ SCL ↓
K1_0
(SCL)
SCK0_0,
Width of "L" for SCL
clock
tLOW SCK1_0 4.7 – 1.3 – µs
(SCL)
SCK0_0,
Width of "H" for SCL
clock
tHIGH SCK1_0 4.0 – 0.6 – µs
(SCL) CL = 50 pF
Repeat "start" condition SCK0_0, (When drive
setup time tSUSTA SCK1_0 capability is 4.7 – 0.6 – µs
SCL ↑→ SDA ↓ (SCL) 2mA or
SOT0_0, more.)
SOT1_0 CL=20pF
Data hold time (SDA) (When drive
tHDDAT 0 3.45*2 0 0.9 µs
SCL ↓→ SDA ↓↑ SCK0_0, capability is
SCK1_0 1mA)
(SCL) R = (VP/IOL)
SOT0_0, *1
SOT1_0
Data setup time (SDA)
tSUDAT 250*3 – 100 – ns
SDA ↓↑→ SCL ↑ SCK0_0,
SCK1_0
(SCL)
SOT0_0,
SOT1_0
"Stop" condition setup
(SDA)
time tSUSTO
SCK0_0,
4.0 – 0.6 – µs
SCL ↑ →SDA ↑
SCK1_0
(SCL)
Bus-free time between
"stop" condition and tBUF – 4.7 – 1.3 – µs
"start" condition

Noise filter tSP – – 2tCPP*4 – 2tCPP*4 – ns

*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
VP shows the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width(tLOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the peripheral bus clock to 8MHz or more when use I2C.

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SDA

tSUDAT tSUSTA
tLOW tBUF

SCL

tHDSTA tHDDAT tHIGH tHDSTA tSP tSUSTO

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(5)LIN-UART timing
 Bit setting: ESCR:SCES=0,ECCR:SCDE=0
(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%,VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↓ → SCK6,SCK7,
tSLOVI -50 +50 ns
SOT delay time SOT2,SOT3, Internal shift clock
SOT4,SOT5, – mode:
SOT6,SOT7 CL=80pF+1  TTL
Valid SIN→ SCK2,SCK3,
tIVSHI SCK4,SCK5, tCPP+80 – ns
SCK ↑ setup time
SCK6,SCK7,
SCK ↑ → SIN2,SIN3,
tSHIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
Serial clock "L" pulse
width
tSLSH SCK2,SCK3, 3tCPP-tR – ns
SCK4,SCK5,
Serial clock "H" pulse
tSHSL SCK6,SCK7 tCPP+10 – ns
width
SCK2,SCK3,
SCK4,SCK5,
SCK ↓→ SCK6,SCK7,
tSLOVE
SOT2,SOT3,
– 2tCPP+60 ns
SOT delay time
SOT4,SOT5,
External shift clock
SOT6,SOT7
– mode:
Valid SIN→ SCK2,SCK3,
CL=80pF+1  TTL
tIVSHE SCK4,SCK5, 30 – ns
SCK ↑ setup time
SCK6,SCK7,
SCK ↑ → SIN2,SIN3,
tSHIXE SIN4,SIN5, tCPP+30 – ns
Valid SIN hold time
SIN6,SIN7

SCK fall time tF SCK2,SCK3, – 10 ns

SCK4,SCK5,
SCK rise time tR SCK6,SCK7 – 40 ns

Notes:  CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

t SCYC
2.4V
SCKx
0.8V

t SLOVI
2.4V
SOTx
0.8V
t IVSHI t SHIXI
V IH V IH
SINx V IL V IL

 External shift clock mode

tSLSH tSHSL
VIH VIH VIH
SCKx
VIL
VIL
tR
tF tSLOVE
2.4V
SOTx
0.8V
tIVSHE tSHIXE
VIH VIH
SINx VIL VIL

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 Bit setting: ESCR: SCES=1, ECCR: SCDE=0

(TA: Recommended operating conditions,VCC5=5.0V±10%, VCCE=5.0V±10%,VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↑→ SCK6,SCK7,
tSHOVI -50 +50 ns
SOT delay time SOT2,SOT3,
Internal shift clock mode:
SOT4,SOT5, –
CL=80pF+1  TTL
SOT6,SOT7
Valid SIN→ SCK2,SCK3,
tIVSLI SCK4,SCK5, tCPP+80 – ns
SCK ↓setup time
SCK6,SCK7,
SCK ↓→ SIN2,SIN3,
tSLIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
Serial clock "H" pulse
tSHSL SCK2,SCK3, 3tCPP-tR – ns
width
SCK4,SCK5,
Serial clock "L" pulse
tSLSH SCK6,SCK7 tCPP+10 – ns
width
SCK2,SCK3,
SCK4,SCK5,
SCK ↑→ SCK6,SCK7,
tSHOVE
SOT2,SOT3,
– 2tCPP+60 ns
SOT delay time
SOT4,SOT5,
External shift clock
SOT6,SOT7
– mode:
Valid SIN → SCK2,SCK3,
CL=80pF+1  TTL
tIVSLE SCK4,SCK5, 30 – ns
SCK ↓setup time
SCK6,SCK7,
SCK ↓→ SIN2,SIN3,
tSLIXE SIN4,SIN5, tCPP+30 – ns
Valid SIN hold time
SIN6,SIN7

SCK fall time tF SCK2,SCK3, – 10 ns

SCK4,SCK5,
SCK rise time tR SCK6,SCK7 – 40 ns

Notes:  CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

t SCYC
2.4V
SCKx
0.8V

t SHOVI
2.4V
SOTx
0.8V
t IVSLI t SLIXI
VIH VIH
SINx VIL V IL

 External shift clock mode

tS H S L tS LS H

VIH VIH VIH

SCKx
VIL VIL VIL

tR tS HO V E tF
2 .4 V
SOTx
0 .8 V

tIV SLE tS LIX E

VIH VIH
S IN x VIL VIL

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 Bit setting: ESCR:SCES=0, ECCR:SCDE=1

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↑→ SCK6,SCK7,
tSHOVI -50 +50 ns
SOT delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Valid SIN → SCK2,SCK3, Internal shift clock
tIVSLI SCK4,SCK5, – tCPP+80 – ns mode:
SCK ↓setup time
SCK6,SCK7, CL=80pF+1  TTL
SCK ↓→ SIN2,SIN3,
tSLIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SOT → SCK6,SCK7,
tSOVLI 3tCPP-70 – ns
SCK ↓ delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7

Notes:  CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.

 Internal shift clock mode

t SCYC
2.4V
SCKx
0.8V t SHOVI 0.8V

t SOVLI

2.4V 2.4V
SOTx
0.8V 0.8V
t IVSLI t SLIXI
VIH V IH
SINx VIL VIL

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 Bit setting: ESCR: SCES=1, ECCR: SCDE=1

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)

Sym Conditi Value

Parameter Pin name Unit Remarks
bol ons Min Max
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↓→ SCK6,SCK7,
tSLOVI -50 +50 ns
SOT delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Valid SIN→ SCK2,SCK3, Internal shift clock
tIVSHI SCK4,SCK5, – tCPP+80 – ns Mode:
SCK ↑ setup time
SCK6,SCK7, CL=80pF+1  TTL
SCK ↑→ SIN2,SIN3,
tSHIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SOT → SCK6,SCK7,
tSOVHI 3tCPP-70 – ns
SCK ↑ delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7

Notes:  CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.

 Internal shift clock mode

t SCYC
2.4V 2.4V
SCKx
0.8V

t SOVHI t SLOVI

2.4V 2.4V
SOTx
0.8V 0.8V
t IVSHI t SHIXI

VIH VIH
SINx VIL V IL

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(6) Timer input timing

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit
Min Max
TIN0, TIN1,
TIN2, TIN3,
ICU0 to ICU11,
tTIWH,
Input pulse width FRCK0 to FRCK5, – 4tCPP – ns
tTIWL
TIOA, TIOB,
AIN0, BIN0, ZIN0 ,
AIN1, BIN1, ZIN1

 Timer input timing

TINx
t TIWH t TIWL
ICUx
FRCKx
VIH VIH
TIOA,TIOB
AINx,BINx,ZINx VIL VIL

(7) Trigger input timing

(TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Max
INT0 to
tTRGH,
INT15, 5tCPP – ns
Input pulse width
tTRGL
ADTG, –
RX0 to
RX2
1 – µs In stop mode

 Trigger input timing

t TRGH t TRGL

INTx V IH VIH
ADTG
RXx VIL VIL

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(8) NMI input timing

(TA: Recommended operating conditions, VCC5 =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit
Min Max
Input pulse width tNMIL NMIX – 4tCPP – ns

 NMIX input timing

t NMIL

NMIX VIH VIH

VIL VIL

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(9) Low voltage detection (External low-voltage detection)

(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
Power supply voltage
VCC5 VCC5 – – – 5.5 V
range
When
power-supply
Detection voltage VDL VCC5 *1 3.9 4.1 4.3 V voltage falls and
detection level is
set initially
When
Hysteresis width VHYS VCC5 – – – 125 mV power-supply
voltage rises
Low voltage detection
Td – – – – 30 μs
time
Power supply voltage
– VCC5 – -2 – 2 V/ms *2
fluctuation rate
*1: If the power supply voltage fluctuates within the time less than the low-voltage detection time (Td), there is a
possibility that the low-voltage detection will occur or stop after the power supply voltage passes the
detection range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation
of the power supply voltage within the limits of the power supply voltage fluctuation rate.

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(10) Low voltage detection (Internal low-voltage detection)

(TA:Recommended operating conditions, VSS=AVSS=0.0V)
Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
Power supply voltage
VRDP5 – – – 1.3 V
range
When
Detection voltage VRDL * 0.8 0.9 1.0 V power-supply
VCC
voltage falls
When
Hysteresis width VRHYS – – – 50 mV power-supply
voltage rises
Low voltage detection
Td – – – – 30 µs
time
*: If the fluctuation of the power supply is faster than the low voltage detection time (Td), there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.

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(11) High current output slew rate

(TA: Recommended operating conditions, DVCC5=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Typ Max
P060 to P067,
Output rise /fall tR2, load capacitance
P070 to P077, – 15 – 100 ns
time tF2 85pF
P080 to P087

 Slew rate output timing

VH VH
VL VL
VH=VOL2+0.9 × (VOH2-VOL2)
VL=VOL2+0.1 × (VOH2-VOL2)

t R2 t F2

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(12) Clock output timing

(TA: Recommended operating conditions, VCC5=VCCE=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Sym Conditi Value Remark
Parameter Pin name Unit
bol ons Min Max s

Cycle time tCYC SYSCLK tCPT – ns

SYSCLK ↑→ SYSCLK ↓ tCHCL SYSCLK – (1/2 tCYC) - 7 (1/2 tCYC) + 7 ns

SYSCLK ↓→ SYSCLK ↑ tCLCH SYSCLK (1/2 tCYC) - 7 (1/2 tCYC) + 7 ns

tCYC

tCHCL tCLCH

VOH=VCC/2
SYSCLK VOH
VOL=VCC/2

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(13) External bus I/F (synchronous mode) timing

(TA: Recommended operating conditions, VCC5=VCCE =AVCC=5.0V±10%, VSS=AVSS=0.0V)
(External load capacitance 50pF)
Value
Parameter Symbol Pin name Unit Remarks
Min Max
Cycle time tCYC SYSCLK 25 – ns
tCHASL, SYSCLK,
ASX delay time 0.5 18 ns
tCHASH ASX
SYSCLK,
CS0X to CS3X delay tCHCSL,
CS0X to 0.5 18 ns
time tCHCSH
CS3X
tCHAV, SYSCLK,
A00 to A21 delay time 0.5 18 ns
tCHAX A00 to A21
tCHRL, SYSCLK,
RDX delay time 0.5 18 ns
tCHRH RDX
tCYC× RWT=1, set RWT to 1 or more.
RDX minimum pulse tRLRH RDX – ns
2 - 20 *
Data setup → RDX ↑ 18 + RWT=1, set RWT to 1 or more.
tDSRH RDX,
tCYC
– ns
*
time
D16 to D31
RDX ↑→ data hold tRHDH 0 – ns
SYSCLK,
tCHWL,
WRnX delay time WR0X, 0.5 18 ns
tCHWH
WR1X
WRnX minimum pulse WR0X,
width
tWLWH
WR1X
tCYC - 10 – ns WWT=0 *
SYSCLK ↑→
tCHDV 0.5 18 ns
data output time SYSCLK,
SYSCLK ↑→ data D16 to D31
tCHDX – 18 ns Set WRCS to 1 or more.
hold time
SYSCLK ↑→ address
tCHMAV 0.5 18 ns
output time
 In multiplex mode, set as
follows:
Set CSWR and CSRD to 2 or
more.
 ASCY must satisfy the
following conditions because
SYSCLK,
of setting ADCY>ASCY and
SYSCLK ↑→ address D16 to D31
tCHMAX – 18 ns protocol violation
hold time
prevention.
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
Refer to Hardware Manual for
details.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.

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External bus I/F (synchronous mode, read operation, and multiplex mode) timing
t1 t2 t3 t4

tCYC

SYSCLK

tCHASL tCHASL
ASCY=0
ASX

tCHASL tCHCSH
ACS=0 RDCS=0
CS0X to CS3X

tCHRL
RWT=1
tCHRH
RDX
tRLRH
CSRD=2

ADCY=1
tCHMAV tCHMAX
D16 to D31 Valid Address Read Data

tDSRH tRHDH

External bus I/F (synchronous mode, read operation, and split mode) timing
t1 t2 t3 t4

tCYC

SYSCLK

tCHASL tCHASH
ASCY=0
ASX

tCHCSL tCHCSH
CS0X to CS3X ACS=0 RDCS=0

tCHRL tCHRH
RWT=1
RDX CSRD=0 tRLRH

tCHAV tCHAX
A00 to A21 Valid Address

D16 to D31 Read Data

tDSRH tRHDH

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External bus I/F (synchronous mode, write operation, and multiplex mode) timing
t1 t2 t3 t4

tCYC

SYSCLK

tCHASL tCHASH
ASCY=0
ASX

tCHCSL tCHCSH
CS0X to CS3X WRCS=1
ACS=0

tCHWL tCHWH
WR0X to WR1X
tWLWH
CSWR=2
WWT=0

ADCY=1
tCHMAV tCHDV tCHDX
D16 to D31 Valid Address Write Data

External bus I/F (synchronous mode, write operation, and split mode) timing
t1 t2 t3 t4

tCYC

SYSCLK

tCHASL tCHASH
ASCY=0
ASX

tCHCSL tCHCSH
WRCS=1
CS0X to CS3X ACS=0

tCHWL tCHWH
WR0X to WR1X CSWR=0
tWLWH
WWT=0

tCHAV tCHAX
A00 to A21 Valid Address
tCHDV tCHDX
D16 to D31 Write Data

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(14) External bus I/F (Asynchronous mode) timing

(TA: Recommended operating conditions, VCC5=VCCE=AVCC=5.0V±10%, VSS=AVSS=0.0V)
(External load capacitance 50pF)
Value
Parameter Symbol Pin name Unit Remarks
Min Max
Cycle time tCYC SYSCLK 25 – ns
Address setup 2 ×tCYC – 2 ×tCYC + RWT=1,
tASRH ns
→ RDX↑time RDX, 12 12 Set RWT to “1” or more. *
RDX ↑→ A00 to A21
tRHAH tCYC – 12 tCYC + 12 ns Set RDCS to “1” or more.
Address hold
Data setup → 18 + RWT=1,
tDSRH – ns
RDX↑time RDX, tCYC Set RWT to “1” or more.
D16 to D31
RDX ↑ → Data hold tRHDH 0 – ns
Address setup
tASWH WR0X to tCYC – 12 tCYC + 12 ns WWT=0 *
→ WRnX↑time
WR1X,
WRnX ↑→
tWHAH A00 to A21 tCYC – 12 tCYC + 12 ns Set WRCS to “1” or more.
Address hold
Data setup →
tDSWH WR0X to tCYC – 16 tCYC + 16 ns WWT=0 *
WRnX ↑ time
WR1X,
WRnX ↑→ Data hold tWHDH D16 to D31 tCYC – 16 tCYC + 16 ns Set WRCS to “1” or more.
Address setup
tMASASH tCYC – 16 tCYC + 16 ns ASCY=0
→ ASX↑time
In multiplex mode, set as
follows:
 Set CSWR and CSRD to
2 or more.
 ASCY must satisfy the
following conditions because
ASX,
of setting ADCY>ASCY and
ASX ↑→ D16 to D31
tMASHAH tCYC – 16 tCYC + 16 ns protocol violation
Address hold
prevention.
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
Refer to Hardware Manual for
details.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.

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External bus I/F (asynchronous mode, read operation, and multiplex mode) timing
t1 t2 t3 t4 t5

tCYC

SYSCLK

ASCY=0
ASX

RDCS=1
CS0X to CS3X ACS=0

RWT=1
RDX CSRD=2

ADCY=1

D16 to D31 Valid Address Read Data

tRHDH
tMASASH tMASHAH tDSRH

External bus I/F (asynchronous mode, read operation, and split mode) Timing
t1 t2 t3 t4 t5

tCYC

SYSCLK

ASCY=0
ASX

RDCS=1
CS0X to CS3X ACS=0

RWT=1
RDX CSRD=0

A00 to A21 Valid Address

tASRH tRHAH
D16 to D31 Read Data

tDSRH tRHDH

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External bus I/F (asynchronous mode, write operation, and multiplex mode) timing
t1 t2 t3 t4

tCYC

SYSCLK

ASCY=0
ASX

WRCS=1
CS0X to CS3X ACS=0

WR0X, WR1X CSWR=2

WWT=0

ADCY=1

D16 to D31 Valid Address Write Data

tMASASH tMASHAH tDSWH tWHDH

External bus I/F (Asynchronous mode, write operation, and split mode) timing
t1 t2 t3 t4

tCYC

SYSCLK

ASCY=0
ASX

WRCS=1
CS0X to CS3X ACS=0

WR0X, WR1X CSWR=0

WWT=0

A00 to A21 Valid Address

tASWH tWHAH
D16 to D31 Write Data

tDSWH tWHDH

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(15) External bus I/F (ready) timing

(TA: Recommended operating conditions, VCC5= VCCE =AVCC=5.0V±10%, VSS=AVSS=0.0V)
(External load capacitance 50pF)
Value
Parameter Symbol Pin name Unit Remarks
Min Max
If using RDY, set SYSCLK to
Cycle time tCYC SYSCLK 50 – ns
20 MHz or less.
RDY setup time→ SYSCLK,
SYSCLK ↑
tRDYS
RDY
28 – ns
SYSCLK ↑→ SYSCLK,
tRDYH 0 – ns
RDY hold time RDY

External bus I/F (ready) timing

t1 t2 t3 t4 t5 t6

tCYC

SYSCLK

ASX
ASCY=2

CS0X to CS3X

ACS=2 RDCS=2

RDX
RWT=2
CSRD=2 Auto wait cycle
tRDYS tRDYH
RDY

Added cycle by RDY

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(16) HS-SPI timing

(TA: Recommended operating conditions, VCC5= VCCE =AVCC=5.0V±10%, VSS=AVSS=0.0V)
(External load capacitance 20pF)

Condi Value Remark

Parameter Symbol Pin name Unit
tions Min Max s

Master 62.5 – ns
Serial clock cycle
tSCYCM SPI_CLK
time
Slave 100 – ns

Valid CS → CLK
start time tOSLSK02 1.5×tSCYCM – 15 – ns
(mode0/mode2)
Valid CS → CLK
SPI_CLK,
start time tOSLSK13 tSCYCM – 15 – ns
SPI_CS0,
(mode1/mode3)
SPI_CS1, –
CLK end → Invalid
SPI_CS2,
CS time tOSKSL02
SPI_CS3
tSCYCM -10 – ns
*1
(mode0/mode2)
*2
CLK end → Invalid
CS time tOSKSL13 1.5×tSCYCM -10 – ns
(mode1/mode3)
SPI_CLK,
SPI_SIO0, Master -10 15 ns
SIO data output time tOSDAT SPI_SIO1,
SPI_SIO2, Slave – 28 ns
SPI_SIO3
SPI_CLK,
SIO setup tDSSET SPI_SIO0, 22 – ns
SPI_SIO1, –
SIO hold tSDHOLD SPI_SIO2, 0.5×tSCYCM – ns
SPI_SIO3
*1: VCCE=5.0V±10%, or VCCE=3.0 to 3.6V
*2: In the voltage range shown in *1, this parameter is defined when IOH is -2mA and IOL is 2mA.

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SPI_CS0,
SPI_CS1, t SCYCM
SPI_CS2,
SPI_CS3

mode0

mode2
t OSLSK02 t OSKSL02
SPI_CLK

mode1

mode3
t OSLSK13 t OSKSL13

input
SPI_SIO0,
SPI_SIO1,
SPI_SIO2, t DSSET t SDHOLD
SPI_SIO3 UP

output

t OSDAT

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5. A/D Converter
(1) Electrical Characteristics
(TA: Recommended operating conditions, VCC5=5.0V±10%, AVCC=5.0V±10%, VSS=AVSS=0.0V)
Sym Value
Parameter Pin name Unit Remarks
bol Min Typ Max
Resolution – – – – 10 bit
Total error – – – – ±3.0 LSB
Non linearity error – – – – ±2.5 LSB
Differential linearity error – – – – ±1.9 LSB
AN0 to AVSS AVSS
Zero transition voltage VOT – V 1LSB=
AN39 -1.5LSB +2.5LSB
(AVCC-AVSS)
AN0 to AVCC AVCC
Full-scale transition voltage VFST
AN39 -3.5LSB
– +0.5LSB
V /1024

Sampling time tSMP – 1.2 – – µs *1

Compare time tCMP – 1.8 – – µs *1
A/D conversion time tCNV – 3.0 – – µs *1
AN0 to VAVSS ≤ VAIN ≤
Analog port input current IAIN
AN39
-5 – +5 µA
VAVCC
AN0 to
Analog input voltage VAIN AVSS – AVRH V
AN39
AVRH AVRH 4.5 – 5.5 V AVCC ≥ AVRH
Reference voltage
AVRL AVSS – 0.0 – V
IA – – 4.0 mA
AVCC
IAH – – 6.0 µA *2
Power supply current
IR – 600 900 µA
AVRH
IRH – – 5 µA *2
AN0 to
Variation between channels – – – 4 LSB
AN39
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is
stopped.

Note: Be sure to use the clock with a frequency between 8MHz and 17MHz for the ADC compare clock in order
to ensure its accuracy.

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(2) Definition of A/D Converter Terms

Resolution : Analog variation that is recognized by an A/D converter.

Linearity error : Deviation of the actual conversion characteristics from a straight line that
connects the zero transition point ("00 0000 0000"←→"00 0000 0001") to the
full-scale transition point ("11 1111 1110"← →"11 1111 1111").

Differential linearity : Deviation of the input voltage from the ideal value that is required to change the
error output code by 1LSB.

Total error : Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error, and linearity error.

Total error

3FF

1.5 LSB
3FE
Actual conversion
characteristics
3FD
Digital output

{1 LSB × (N - 1) + 0.5 LSB}

004

VNT
003
(Actually-measured value)
Actual conversion
002 characteristics
Ideal characteristics
001

0.5 LSB
AVSS AVRH
(AVRL) Analog input

VNT - {1LSB × (N - 1) + 0.5LSB}

Total error of digital output N = [LSB]
1LSB
AVRH - AVSS
1LSB (Ideal value) = [V]
1024

VOT (Ideal value) = AVSS + 0.5 LSB[V]

VFST (Ideal value) = AVRH - 1.5 LSB[V]
VNT: Voltage at which the digital output changes from (N - 1) to N.

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VNT - {1LSB × (N - 1) + VOT}

Linearity error of digital output N = [LSB]
1LSB

V(N + 1) T - VNT
Differential linearity error of digital output N = - 1 LSB [LSB]
1LSB

VFST - VOT
1LSB = [V]
1022

VOT: Voltage at which the digital output changes from “000H” to “001 H”.
VFST: Voltage at which the digital output changes from “3FE H” to “3FF H”.

(3) Notes on Using A/D Converter

<About the output impedance of the analog input of external circuit>

 External impedance values of the external input of 4.2 kΩ or lower (sampling time = 1.2 μs@ machine
clock of 16 MHz) are recommended. When the external impedance is too high, the sampling time for
analog voltages may not be sufficient. In this case, it is recommended to connect the capacitor
(approx. 0.1 μF) to the analog input pin.

 Analog input circuit model

Comparator

Analog input R
C
During sampling: ON

R C
MB91570series 4.0kΩ(Max) 16.5pF(Max) *
*: except DA shared pin
Note: Listed values must be considered as reference values.

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6. D/A converter
(TA: Recommended operating conditions, VCC5=AVCC=5.0V±10%,VSS=AVSS=0.0V)
Pin Value
Parameter Symbol Unit Remarks
name Min Typ Max
Resolution – – – – 8 bit
Differential linearity error – – – – ±3.0 LSB
Load capacitance:
– – – 0.58 0.69 µs
20 pF
Conversion time
Load capacitance:
– – – 2.90 3.43 µs
100 pF
Per 1ch
Reference voltage supply
IDVR AVCC – 475 580 µA
*
current Per 1ch in power
IDVRS AVCC – – 7.5 µA
down mode
Analog output impedance – – – 3.8 4.5 kΩ
*: Reference voltage supply current (VCC = AVCC = 5.0 V) is specified.

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7. Flash memory

(1) Electrical characteristics

Value
Parameter Unit Remarks
Min Typ Max
8 Kbyte sector*1,
– 200 800 ms excluding internal
preprogramming time
8 Kbyte sector*1,
– 300 1100 ms including internal
preprogramming time
Sector erase time
64 Kbyte sector*1,
– 400 2000 ms excluding internal
preprogramming time
64 Kbyte sector*1,
– 700 3700 ms including internal
preprogramming time
Exclusive of overhead time at
8-bit writing time – 9 288 µs
system level*1
Exclusive of overhead time at
16-bit writing time – 12 384 µs
system level*1
Exclusive of overhead time at
ECC writing time – 9 288 µs
system level*1
1,000 cycles/
20 years,
Erase cycle*2/ 10,000 cycles/
– – – Average TA=+85°C*3
Data retain time 10 years,
100,000 cycles/
5 years
*1: The guaranteed value for erasure up to 100,000 cycles.
*2: Number of erase cycles for each sector.
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).

(2) Notes
While the Flash memory is written or erased, shutdown of the external power (VCC5) is prohibited.
In the application system where VCC5 might be shut down while writing or erased, be sure to turn the power
off by using an external low-voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection voltage (V DL*1), hold
VCC5 at 2.7V or more within the duration calculated by the following expression:

Td*1[µs] + (period of PCLK [µs] × 257) + 50 [µs]

*1: See "4. AC characteristics (9) Low voltage detection (External low-voltage detection) "

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 ORDERING INFORMATION
Part number Package*
MB91F575BPMC
MB91F575BSPMC
MB91F575BHPMC
MB91F575BHSPMC
MB91F575CPMC
MB91F575CSPMC
MB91F575CHPMC
MB91F575CHSPMC
MB91F577BPMC
MB91F577BSPMC
MB91F577BHPMC
MB91F577BHSPMC LQFP-144 pin, Plastic
MB91F577CPMC (FPT-144P-M08)
MB91F577CSPMC
MB91F577CHPMC
MB91F577CHSPMC
MB91F578CPMC
MB91F578CSPMC
MB91F578CHPMC
MB91F578CHSPMC
MB91F579CPMC
MB91F579CSPMC
MB91F579CHPMC
MB91F579CHSPMC
MB91F575BSPMC1
MB91F575BHSPMC1
MB91F577BSPMC1
MB91F577BHSPMC1
MB91F578CPMC1
MB91F578CSPMC1 LQFP-144 pin, Plastic
MB91F578CHPMC1 (FPT-144P-M12)
MB91F578CHSPMC1
MB91F579CPMC1
MB91F579CSPMC1
MB91F579CHPMC1
MB91F579CHSPMC1

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Part number Package*

MB91F578CMPMC
MB91F578CSMPMC
MB91F578CHMPMC
MB91F578CHSMPMC LQFP-208-pin, Plastic
MB91F579CMPMC (FPT-208P-M06)
MB91F579CSMPMC
MB91F579CHMPMC
MB91F579CHSMPMC
*: For details of the package, see " PACKAGE DIMENSIONS ".

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 PACKAGE DIMENSIONS

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 Major Changes
Page Section Change Results
Revision 2.0
- - Initial release
Revision 2.1
- - Company name and layout design change
Revision 2.2
- P104-P108 Revised text position

See Supplementary Information as described in Document Definition.

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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.

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