4, 4) Write! the VHDL code for following Swe diagtun-of a Moore 6 | ae Ke b) Design end implements decade'coumter using J-K flip-flops and’ 6 write VHDL cote. 5. a) Write the VHDL code for following cyclic shift register with Sas 6 delay = | t aaa — papary by Design and implement an 8-t0-3 Priority Encoder f VHDL code using if else statement, nsGovernment College of Engineering, Amravati (An Autonomous Institute of Government of Maharashtra) Fourth Semester B. Tech. (Electronics and Telecommunication Engineering) Summer — 2022 Course Code: ETU425 @ Tix se Name: Digital System Design 2 Hrs, 30 Min. Max. Marks: 60 Instructions to Candi assumptions made 1. Solve any TWO 2) Explain different IEEE stan b) 6 c) «©. What are different data objects used in 6 2 Solve any TWO a between PROM, PLA & PAL 6 by i D-flip 6 °) Design4:1 MUX and write the VHDL program in behavioral 6 modeling. 3, Solve any TWO a) Write a VHDL Program for 2:4 Decoders using Behavioral 6 Modeling. b) Explain in short, the operation of'a complex programmable logic device (CPLD) and a field-programmable gate array A c) What is metastability? What are the eas occurs? How to avoid: metastGovernment Calle 7 (Aw Autonmony: ttre at aekineering, A Went'et Fay ag Maharanirn) powrtty Semester B. Tech. (Electronics and Telecotmmun Sumamer- 2029 e ‘Course Name: Digital System Design Time: 2 Hes. 30 Min, Coarse Code: ETU 428 Max, Marks) oi instructions to Candidate 1) All questions: are compulsory. 2 ) Assume suitable data wherever necessary and clearly state the assumptions made 5) Diagrams ’sketches should be given Wherever necessary. 4) Use of logarithmic table, drawing instruments and non-programmable ealculutoes i permitted, 5) Figures to the right indicate full miarks L a) Explain. various data objets in VHDL. Cie nevessary mM examples? 5) Explain various Data Types with example in VIDE? 4 *) 4 4 Solve any three a) Writea VIDE cade for inplementaion of 8 103 encoder? 4 by Write a short note on PLA? 4 ©) Waite a VADL code for Implementation of 4 bit up cotintes? 4 @) State the concept of nace free stare assignment? - x Solve any three a} Write a short note on FPGA? Elaborate elements ot design units: Design and implernenti3-bit!5.) Explain the working of Inverting Amplifier in detail 6 * GOVERNMENT COLLEGE OF ENGINEERING. AMRAY TL (An Ainonomous Insti of Govt, of Maharashtra) Electronics Engineering Department - st Duration: 1.20 Hr Sub: HTU425 Digit! System Design Date: 2007-22 rks: 50. Note: Solve any 5; Euch question carries Gmark 0 Enlist predefined attributes and explain each with suitable example o Minimize the following logie funetion using Quine-MeCluskey, method: and tealize using NAND gates FOAB.C De Lan( 1,5/0,12, 13,14) 402.4) oO What are the different data types used in VAL, Explain each with example o4 Multiplexer 8:1 has A,B, connected to selection inputs 52.51 and 30 respectively. The Jata inputs DO: through D7 are as, follows:021=12"170,03"D5=1,00=D4=D and Dé=Dbar. Determine Hoolean expres Q Implement the following multiple output funetion using 3:8 decader and external gates SF EUAB.C > SmC145,7) F200 )=Min(2,36.7 Q \huit are the differen types of operators in VUIDL? Esiplain it in detail with mpl a Ss 2 c) Whatare different data objects used in VHDL? Explain in bri 6 2. Solve any TWO ) Compare between PROM, PLA & PAL 6 b) Design and implement positive edge triggered 1D-flip-flop using, 6 HDI o Design4:] MUX a modeling. 1 write the VHDL program in behavioral 6 Solve any TWO Write a VHDL Program for 2:4 Decoders: Modleling. plain in short, the operation oft device (CPID) and a fields ‘oceurs? Hiei ita