Ali Mansoor

2018 1
Chapter4: Operators and Attributes

• Introducing Operators and Attributes in VHDL

• Sparsely used operators

• A few illustrative (not actual) design examples

• Still a ‘‘foundation’’ chapter

• start dealing with actual designs in next 2 chapters (5, 6)

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Operators

• Assignment operators

• Logical operators

• Arithmetic operators

• Relational operators

• Shift operators

• Concatenation operators

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Assignment Operators
<=
Signal <= value
:=
VARIABLE := value
CONSTANT:= value
GENERIC := value
=>
To assign values to individual vector elements or with OTHERS
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
w <= "10000000“
w <= (0 =>'1', OTHERS =>'0') -- LSB is '1', the others are '0'

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Logical Operators

Valid Data Types:

BIT , BIT_VECTOR
STD_LOGIC, STD_LOGIC_VECTOR
STD_ULOGIC, STD_ULOGIC_VECTOR

• NOT (has precedence over the others)

• AND
• OR
• NAND
• NOR
• XOR
• XNOR
Example:
y <= NOT a AND b; -- (a'.b)
y <= NOT (a AND b); -- (a.b)'
y <= a NAND b; -- (a.b)' VARIABLE := value;

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Arithmetic Operators
Valid Data Types:
• INTEGER,
• SIGNED,
• UNSIGNED
• REAL (not synthesizable)
• std_logic_signed
• std_logic_unsigned
• STD_LOGIC_VECTOR (addition, subtraction)

+ Addition (Synthesizable)
- Subtraction (Synthesizable)
* Multiplication (Synthesizable)
/ Division only power of two dividers (shift operation) are allowed!
** Exponentiation
MOD Modulus --the remainder of y/x with the signal of x
REM Remainder --the remainder of y/x with the signal of y
ABS Absolute value

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Comparison Operators
Valid Data Types:
• Any data type!
= Equal to
/= Not Equal to
< Less than
> Greater than
<= Less than or Equal
>= Greater than or Equal

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Shift Operators
<left operand> shift operation <right operand>
Valid Data Types:
< BIT_VECTOR > shift operation < INTEGER >

sll Shift left logic --filling right positions with ‘0’s

srl Shift right logic -- filling left positions with ‘0’s

What is the arithmetic meaning of sll?

What is the arithmetic meaning of srl?
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Data Attributes
Considering a data d, then:
Pre-defined, synthesizable data attributes:

d’LOW: Returns lower array index

d’HIGH: Returns upper array index
d’LEFT: Returns leftmost array index
d’RIGHT: Returns rightmost array index
d’LENGTH: Returns vector size
d’RANGE: Returns vector range
d’REVERSE_RANGE: Returns vector range in reverse order

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Data Attributes
Pre-defined, synthesizable data attributes:
d’LOW: Returns lower array index
d’HIGH: Returns upper array index
d’LEFT: Returns leftmost array index
d’RIGHT: Returns rightmost array index
d’LENGTH: Returns vector size
d’RANGE: Returns vector range
d’REVERSE_RANGE: Returns vector range in reverse order

• Example
SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);

d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0, d'LENGTH=8,

d'RANGE=(7 downto 0), d'REVERSE_RANGE=(0 to 7)

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Data Attributes Example
• Example: four equivalent LOOP statements for the signal x:
SIGNAL x: STD_LOGIC_VECTOR (0 TO 7);

• FOR i IN RANGE (0 TO 7) LOOP ...

• FOR i IN x'RANGE LOOP ...

• FOR i IN RANGE (x'LOW TO x'HIGH) LOOP ...

• FOR i IN RANGE (0 TO x'LENGTH-1) LOOP ...

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Data Attributes…
• For enumerated data types:

• d’VAL(pos): Returns value in the position specified

• d’POS(value): Returns position of the value specified

• d’LEFTOF(value): Returns value in the position to the left of the value

specified

• d’VAL(row, column): Returns value in the position specified; etc.

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Signal Attributes
Considering a signal s, then:

s’EVENT: Returns true when an event occurs on s (synthesizable)

s’STABLE: Returns true if no event has occurred on s
s’ACTIVE: Returns true if s =‘1’
s’QUIET <time>: Returns true if no event has occurred during the time specified
s’LAST_EVENT: Returns the time elapsed since last event
s’LAST_ACTIVE: Returns the time elapsed since last s= ‘1’
s’LAST_VALUE: Returns the value of s before the last event; etc.

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Signal Attributes Example
• Example: four equivalent assignments. They return TRUE when a
rising event (a change) occurs on clk.

IF (clk'EVENT AND clk='1')... -- EVENT attribute used with IF

IF (NOT clk'STABLE AND clk='1')... -- STABLE attribute used with IF

WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT attribute used with WAIT

IF RISING_EDGE(clk)... -- call to a function

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User-Defined Attributes
• User-defined attribute
• must be declared
• must be specified
• Attribute Declaration

• Attribute Specification

• attribute_type: any data type (BIT, INTEGER, STD_LOGIC_VECTOR, etc.)

• class: TYPE, SIGNAL, FUNCTION, etc.
• value: ‘0’, 27, ‘‘00 11 10 01’’, etc.

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User-Defined Attribute example…
• Example:

ATTRIBUTE number_of_inputs: INTEGER; -- declaration

ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3; -- specification
...
inputs <= nand3'number_of_pins; -- attribute call, returns 3

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User-Defined Attribute Example:
• Enumerated Encoding:
• enum_encoding attribute

TYPE color IS (red, green, blue, white);

default encoding is sequential, i.e.:
red = ‘‘00’’, green =‘‘01’’, blue = ‘‘10’’, white =‘‘11’’
Enum_encoding allows changing the default encoding (sequential).
ATTRIBUTE enum_encoding OF color: TYPE IS "11 00 10 01";

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Operator Overlaping:
• User-defined Operators
• Consider pre-defined arithmetic operators (+, -, *, /, etc.)
• Operating on certain data types (e.g. INTEGER)
• Not operating on BIT
• Specifying a new kind of addition (+) on type BIT_VECTORT
• Named as Operator Overloading
Example: Adding an integer to a binary 1-bit number
--Using the defined + operator
--Defining a new + operator
------------------------------
FUNCTION "+" (a: INTEGER, b: BIT) RETURN
SIGNAL inp1, outp: INTEGER RANGE 0 TO 15;
INTEGER IS
SIGNAL inp2: BIT;
BEGIN
(...)
IF (b='1') THEN RETURN a+1;
ELSE RETURN a; outp <= 3 + inp1 + inp2;
END IF; (...)
END "+"; ------------------------------

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GENERIC:
• a way of specifying a generic parameter

• generic parameter:
• static
• modifiable
• adaptable to different applications
• more flexibility
• more reusability
• declaring GENERIC statement in the ENTITY
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GENERIC Example:
• Example: ENTITY my_entity IS
• A generic parameter, INTEGER n=8 GENERIC (n : INTEGER := 8);
• When finding in the: PORT (...);
• ENTITY END my_entity;
• or the following ARCHITECTURES ARCHITECTURE my_architecture OF my_entity IS
• its value will be 8 ...
END my_architecture:

• Specifying more than one GENERIC parameter in an ENTITY

example:
GENERIC (n: INTEGER := 8; vector: BIT_VECTOR := "00001111");

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Examples…
• Providing some examples to illustrate use of:
• Operators
• Attributes
• GENERIC
• Still for establishing basic foundations of VHDL
• Some parts may be confusing
• After studying next chapters, return and read examples again

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Example: generic m-by-n decoder
---------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------
ENTITY decoder IS
PORT ( ena : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); IF (ena='1') THEN
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); FOR i IN sel'RANGE LOOP -- sel range is 2 downto 0
END decoder; IF (sel(i)='1') THEN -- Bin-to-Integer conversion
--------------------------------------------- temp2:=2*temp2+1;
ARCHITECTURE generic_decoder OF decoder IS ELSE
BEGIN temp2 := 2*temp2;
PROCESS (ena, sel) END IF;
END LOOP;
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); temp1(temp2):='0';
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH; END IF;
BEGIN x <= temp1;
temp1 := (OTHERS => '1'); END PROCESS;
temp2 := 0; END generic_decoder;

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Generic decoder simulation results
• In the example: m =3 and n =8
• the use of GENERIC would have made it clearer
• that m and n are indeed generic parameters.

• When ena = ‘0’ x = ‘‘11111111’’ (255)

• When sel =‘‘000’’ (0) x =‘‘11111110’’ (254)
• When sel =‘‘001’’ (1) x =‘‘11111101’’ (253)
• When sel =‘‘010’’ (2) x =‘‘11111011’’ (251)

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Example: Generic Parity Detector
1 --------------------------------------------
2 ENTITY parity_det IS --Assign a value rather than n=7, then the code will work for
3 GENERIC (n : INTEGER := 7); --any other vector size!
4 PORT ( input: IN BIT_VECTOR (n DOWNTO 0);
5 output: OUT BIT);
6 END parity_det;
7 --------------------------------------------
8 ARCHITECTURE parity OF parity_det IS
9 BEGIN
10 PROCESS (input) Question:This Circuits is based on……
11 VARIABLE temp: BIT;
Even Parity /Odd Parity
12 BEGIN
13 temp := '0';
14 FOR i IN input'RANGE LOOP
15 temp := temp XOR input(i);
16 END LOOP;
17 output <= temp;
18 END PROCESS;
19 END parity;
20 -------------------------------------------- 24
Example 4.3: Generic Parity Generator
1 -----------------------------------------------
2 ENTITY parity_gen IS
3 GENERIC (n : INTEGER := 7);
4 PORT ( input: IN BIT_VECTOR (n-1 DOWNTO 0);
5 output: OUT BIT_VECTOR (n DOWNTO 0));
6 END parity_gen;
7 -----------------------------------------------
8 ARCHITECTURE parity OF parity_gen IS
9 BEGIN
10 PROCESS (input)
11 VARIABLE temp1: BIT;
12 VARIABLE temp2: BIT_VECTOR (output'RANGE); Question:This Circuits is based on……
13 BEGIN Even Parity /Odd Parity
14 temp1 := '0';
15 FOR i IN input'RANGE LOOP
16 temp1 := temp1 XOR input(i);
17 temp2(i) := input(i);
18 END LOOP;
19 temp2(output'HIGH) := temp1;
20 output <= temp2;
21 END PROCESS;
22 END parity;
23 ----------------------------------------------- 25
Summary: Operators

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Summary: Attributes

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Problems:
Considering the following declarations:
SIGNAL a : BIT := '1';
SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";
SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";
SIGNAL d : BIT_VECTOR (7 DOWNTO 0);
SIGNAL e : INTEGER RANGE 0 TO 255;
SIGNAL f : INTEGER RANGE -128 TO 127;

1) Operators (Fill in the blanks):

x1 <= a & c; -> x1 <= ________
x2 <= c & b; -> x2 <= ________
x3 <= b XOR c; -> x3 <= ________
x4 <= a NOR b(3); -> x4 <= ________
x5 <= b sll 2; -> x5 <= ________
x6 <= b sla 2; -> x6 <= ________
x7 <= b rol 2; -> x7 <= ________
x8 <= a AND NOT b(0) AND NOT c(1); -> x8 <= ________
d <= (5=>'0', OTHERS=>'1'); -> d<= ________ 28
Problems:
Considering the following declarations:
SIGNAL a : BIT := '1';
SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";
SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";
SIGNAL d : BIT_VECTOR (7 DOWNTO 0);
SIGNAL e : INTEGER RANGE 0 TO 255;
SIGNAL f : INTEGER RANGE -128 TO 127;

2) Attributes(Fill in the blanks).

c'LOW -> ______
d'HIGH -> ______
c'LEFT -> ______
d'RIGHT -> ______
c'RANGE -> ______
d'LENGTH -> ______
c'REVERSE_RANGE -> ______

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Problems:
3) Verify whether operations are legal/illegal. Briefly justify your answers. Considering the following declarations:
b(0) AND a -> legal/illegal why?________ SIGNAL a : BIT := '1';
a + d(7) -> legal/illegal why?________ SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";
NOT b XNOR c -> legal/illegal why?________ SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";
c+d -> legal/illegal why?________ SIGNAL d : BIT_VECTOR (7 DOWNTO 0);
e–f -> legal/illegal why?________ SIGNAL e : INTEGER RANGE 0 TO 255;
IF (b<c) ... -> legal/illegal why?________ SIGNAL f : INTEGER RANGE -128 TO 127;
IF (b>=a) ... -> legal/illegal why?________
IF (f/=e) ... -> legal/illegal why?________
IF (e>d) ... -> legal/illegal why?________
b sra 1 -> legal/illegal why?________
c srl -2 -> legal/illegal why?________
f ror 3 -> legal/illegal why?________
e*3 -> legal/illegal why?________
5**5 -> legal/illegal why?________
f/4 -> legal/illegal why?________
e/3 -> legal/illegal why?________
d <= c -> legal/illegal why?________
d(6 DOWNTO 3) := b -> legal/illegal why?________
e <= d -> legal/illegal why?________
f := 100 -> legal/illegal why?________
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Problems:
4) Rewrite m-by-n decoder example code to make it truly generic.
Guides:
• Two values must be changed:
• the range of sel (line 7)
• the range of x (line 8)
• 4.a) Replace upper range limits of sel and x by an attribute which is a
function of n
• 4.b) Modify binary-to-integer conversion code to still work here!
• assuming that sel had been declared as an INTEGER
• Guide: the range of sel must be specified in terms of n

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