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Exp6 122 DSD

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18 views1 page

Exp6 122 DSD

Uploaded by

sejalrayakwar147
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Experiment No.

6
Roll No. : 117
Aim : Study of Full adder using case statement.
Objective : Designing Full adder using case statement.
Program : module fa(sum,carry,a,b,cin);
Full output reg sum,carry; Truth Table :
Adder input wire a,b,cin;
always @(a,b,cin) Input Output
begin A B Cin Sum Carry
case({a,b,cin}) 0 0 0 0 0
3'b000:begin sum=0;carry=0;end 0 0 1 1 0
3'b001:begin sum=1;carry=0;end 0 1 0 1 0
0 1 1 0 1
3'b010:begin sum=1;carry=0;end
1 0 0 1 0
3'b011:begin sum=0;carry=1;end 1 0 1 0 1
3'b100:begin sum=1;carry=0;end 1 1 0 0 1
3'b101:begin sum=0;carry=1;end 1 1 1 1 1
3'b110:begin sum=0;carry=1;end
3'b111:begin sum=1;carry=1;end
endcase
end
endmodule

Simulation Full Adder :


Result :

Full Adder
RTL View : Decoder0

a
b IN[2..0] OUT[7..0] WideOr1
cin
carry

DECODER

WideOr0
sum

Result / We performed the “ Designing Full adder using case statement.”


Conclusion :
Roll No. : 117 Marks Signature :
VII- out of
Sem/Br : 10
EE-B

Name of Lecturer : Mrs.M.N.Kalbande

Department of Electronics Engineering, YCCE, Nagpur


10/20/2023 7:52:38 PM Page 1 of 1

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