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Numarator

The document describes a VHDL entity for a numarator that uses a clock, reset and enable signals to increment a 4-bit counter and output the value. It contains the entity declaration, architecture, signal declaration and process to increment the counter when enabled.

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6 views1 page

Numarator

The document describes a VHDL entity for a numarator that uses a clock, reset and enable signals to increment a 4-bit counter and output the value. It contains the entity declaration, architecture, signal declaration and process to increment the counter when enabled.

Uploaded by

webexi6286
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity numarator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (0 to 3));
end numarator;

architecture Behavioral of numarator is


component MPG
port ( btn : in STD_LOGIC;
clk : in STD_LOGIC;
en : out STD_LOGIC);
end component;
signal count : STD_LOGIC_VECTOR(0 to 3) := "0000";
begin
process(clk, rst)
begin
if rst = '1' then
count <= "0000";
elsif (clk = '1') and (clk'event) then
if enable = '1' then
count <= count + "0001";
end if;
end if;
end process;
q <= count;
end Behavioral;

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