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Concept of Pipelining 3.1.3

The document discusses the concept of pipelining in computer architecture. It explains how instructions are processed through different phases in an instruction pipeline, allowing multiple instructions to be executed simultaneously. This increases processor speed compared to sequential execution. The document also describes different types of pipeline processors including arithmetic, instruction, and processor pipelines.

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23 views6 pages

Concept of Pipelining 3.1.3

The document discusses the concept of pipelining in computer architecture. It explains how instructions are processed through different phases in an instruction pipeline, allowing multiple instructions to be executed simultaneously. This increases processor speed compared to sequential execution. The document also describes different types of pipeline processors including arithmetic, instruction, and processor pipelines.

Uploaded by

fovov27364
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Lecture 3.1.

3 (Concept of pipelining)
Pipelining
To grasp the concept of pipelining, let us look at the root
level of how the program is executed. Instruction is the
smallest execution packet of a program. Each instruction
contains one or more operations. Simple scalar
processors execute one or more instruction per clock
cycle, with each instruction containing only one
operation. Instructions are executed in a sequence of
phases to produce the expected results. This sequence is
given below:

 IF: Fetches the instruction into the instruction


register.
 ID: Instruction Decode, decodes the instruction for
the opcode.
 AG: Address Generator, generates the address.
 DF: Data Fetch, fetches the operands into the data
register.
 EX: Execution executes the specified operation.
 WB: W
 rite back, writes back the result to the register.
Not all instructions require all the above steps, but most
do. These steps use different hardware functions. In
pipelining, these different phases are performed
concurrently. In pipelining, these phases are considered
independent between different operations and can be
overlapped. Thus, multiple operations can be performed
simultaneously, with each operation having its own
independent phase.
Instruction Pipelining
Let us look at the way instructions are processed in
pipelining. This can be easily understood by the
diagram below:
\

Assume that the instructions are independent. In a simple


pipelining processor, at any given time, there is only one
operation in each phase. The initial phase is the IF phase.
As a result, one operation is fetched on the first clock
cycle. When the next clock pulse arrives, the first
operation goes into the ID phase, leaving the IF phase
empty. Now, this empty phase is allocated to the next
operation. So, during the second clock pulse, the first
operation is in the ID phase, and the second operation is
in the IF phase.
For the third cycle, the first operation will be in the AG
phase, the second operation will be in the ID phase, and
the third operation will be in the IF phase. In this way,
instructions are executed concurrently, and after six
cycles, the processor will output a completely executed
instruction per clock cycle.
Has this instruction executed sequentially, initially the
first instruction has to go through all the phases then the
next instruction is fetched? So, for execution of each
instruction, the processor would require six clock cycles.
But in a pipelined processor, as the execution of
instructions takes place concurrently, only the initial
instruction requires six cycles, and all the remaining
instructions are executed as one per cycle, thereby
reducing the time of execution and increasing the speed
of the processor.
Pipelining Architecture
Parallelism can be achieved with hardware, compilers,
and software techniques. To exploit the concept of
pipelining in computer architecture, many processor
units are interconnected and are functioned concurrently.
In the pipelined processor architecture, there are separate
processing units provided for integers and floating-point
instructions. Whereas in sequential architecture, a single
functional unit is provided.

Pipelined Processor Unit [Elprocus.com]

In static pipelining, the processor should pass the


instruction through all phases of the pipeline, regardless
of the requirement of the instruction. In a dynamic
pipeline processor, an instruction can bypass the phases
depending on its requirement but has to move in
sequential order. In a complex dynamic pipeline
processor, the instruction can bypass the phases as well
as choose the phases out of order.
Classification of pipeline processor
Pipeline processors are classified as:
1. Arithmetic pipeline
2. Instruction pipeline
3. Processor pipeline
Arithmetic pipeline
An arithmetic pipeline generally breaks an arithmetic
operation into multiple arithmetic steps.
So, in an arithmetic pipeline, an arithmetic operation
like multiplication, addition, etc. can be divided into a
series of steps that can be executed one by one in stages
in an Arithmetic Logic Unit (ALU).
Example of Arithmetic pipeline
Listed below are examples of arithmetic pipeline
processors:
 8 stage pipeline used in TI-ASC
 4 stage pipeline used in Star-100
Processor pipeline
In a processor pipeline, processing of the same data
stream is done by a cascade of processors.
In this, each cascade of processor is assigned and process
a specific task.
There is no practical example found for processor
pipelines.
Instruction pipeline
In an instruction pipeline processor, the execution of a
stream of instructions can be pipelined by overlapping
the execution of the current instruction with the fetch,
decode, and operand fetch of subsequent instructions.
Example of an Instruction Pipeline
 All high-performance computers nowadays are
equipped with an instruction-pipeline processor.
OTHER REFRENCES
 https://www.studytonight.com/computer-
architecture/pipelining
 https://www.tutorialspoint.com/what-is-pipelining
 https://www.elprocus.com/pipelining-architecture-
hazards-advantages-disadvantages/
SUGGESTED BOOK REFERENCES
 J.P. Hayes, "Computer Architecture and
Organization", Third Edition.
 Mano, M., "Computer System Architecture", Third
Edition, Prentice Hall.
 Stallings, W., "Computer Organization and
Architecture", Eighth Edition.

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