THE HISTORY OF THE COMPUTER

0th Generation - Mechanical computers 1642-1944.

1642 Blaise Pascal - Perfects a mechanical machine that can +/-, using gears and was hand cranked.
- 1st automatic calculating machine.

1672 Gottfried Leibniz - Same a Pascal's but can also multiply and divide.

1822 Charles Babbage - Difference Engine - can only + and -.

- 1st use of output devices
- output punched onto a copper plate

1832 - Analytical Engine - 1st General purpose computer (was unfinished)

- had a memory / computation unit./ input card reader / output section.
- can be programmed to solve a variety of logical / arithmetic problems

1890 Herman Hollerith - 1st computer using electricity.

- Used punched cards to process data for American census.

1st Generation 1944 -1958 : Vacuum tubes

I/O media : Punched cards & magnetic tape.
Memory : Vacuum Tubes
Characteristics - Large, Slow, Vacuum tubes used too much power, made plenty heat.
- Ran one program at a time
e.g. ENIAC: Electronic Numerical Integrator And Computer. - programmed by setting up thousands of switches & jumper cables.
EDSAC - 1st computer to use stored programs and binary numbers.

John Von Neumann - Concept of binary states

- Von Neumann machine:- Accumulator/ Memory/ ALU / Control unit (Basis of modern day computers)

2nd Generation 1959-1963: Transistors

-Transistors & magnetic cores replaced large Vacuum tubes, being smaller, faster, using less power, high reliability
- Stacks of removable magnetic disks (platter of disks- manchester disks).

3rd Generation : 1964-1970 : Integrated Circuit.

- Complete electronic circuit on a silicon chip replaces transistorized circuits. Size decreased, speed increased
- Computers can process > 1 program at same time (multiprogramming)
- Computers can be used > 1 person at same time (time sharing)
- Operating system replaced human intervention to automatically run and maintain computers. (More reliable/efficient)

4th Generation : 1971 - Now : Large Scale Integration

- LSI circuits used. => thousands of ICs on a silicon chip => microprocessor.
- Computers can access more memory & do more functions.

5th Generation : Now- Future

- Microprocessors speeds increase via further shrinking / simplifying electrical paths (Moore’s Law 18mnths = double processor
power).
- Breaking of linear Moore’s Law :- geometric increase due to new found method of Cu/Si blending.
- New materials to decrease component size and power use. (GaAs instead of Si | Cu/Si vs Al/Si)
- Superconductors : Able to transport a current with no resistance and no leakage.
- Optical circuitry: Light used in circuits rather than slower electricity.
- Artificial Intelligence: Programs which gives computers the ability to learn tasks.
- Thousands of processors in a computer working at the same time : parallel processing:- Load sharing / Clustering
- Estimated 10GHz chip @ 2011.
 WHAT IS A COMPUTER ?

- An electronic device that processes input (data) via following a series of instructions (program) to give an output (information).
- Each instruction tells the computer to perform one task.

input Processing Output

data program information.

LIMITATIONS :
- It can only do what it is told (instructed / programmed) to do, in a language (code) it can use.

Language: Way in which an instruction is written and the laws governing it's use.

SPECIAL PURPOSE vs. GENERAL PURPOSE COMPUTERS.

Special Purpose Computers
If the instructions cannot be changed, the instructions are said to be fixed. Such computers running only those unchangeable instructions
are said to be Special Purpose. i.e. built for a specific task and can't do any other. This computer is not Programmable. i.e. the instructions
cannot be modified and are fixed (hardwired) at the time it was built.

General Purpose Computers.

If the instructions can be changed, a computer would be able to perform different tasks depending on what instructions are given by the
user. It can do varying tasks depending on the program it follows, being thus programmable.

WHY USE A COMPUTER ?

Useful:- - Follows instructions given to it.
- Cheap - Fast
- Accurate - Reliable (Less mechanical failures  solid state)
- General Purpose - Large storage & fast access to it

HOW IS DATA REPRESENTED ?

- The computer is an electronic device => electricity used, therefore represented by electricity.
- Electricity can either flow or not flow ,electric switches. => switch on/off 2 states .
- Each state is represented by a digit. 2 states => 2 digits :- binary :- 0 for off, 1 for on.
- Each binary digit 0 /1 is called a bit which is the fundamental representation of data.
- Combining these bits in a specific way and giving meaning (a code) to the combinations, we can represent input.
e.g. 00 = N, 01 = S , 10 = E, 11 = W.

Computer processes data only by these switches (millions), hence work with only binary values.
Can have 2 bit , 4 bit, 8 bit ,16 bit , 32 bit, 64 bit.. units of data being a measure of the amount of data that can be used at a time by a
computer.

We have ~ 200 chars.

How can we code 200 chars ? i.e. how many bits ? = 8 bits = 256 combinations sufficient to represent all 200 and more. Thus the standard
size of representing useable info/data. = 8 bits = a character = byte.
This is done by using a code to give these combinations meaning.
Common codes = ASCII (American national Standard Code for Information Interchange) i.e. ASCII 'A' = 01000001
EBCDIC (Extended Binary Coded Decimal Interchange Code) i.e . EBCDIC ‘A’ = 11000001.

Units of storage

The unit by which storage is represented = byte = character.

Multiples of bytes are as follows:

Unit Value
Kilobyte (Kb) ~1000 Bytes = 210 bytes
Megabyte (Mb) ~1000 Kb = 220 bytes
Gigabyte (Gb) ~1000 Mb = 230 bytes
Terabyte (Tb) ~ 1000 Gb = 240 bytes
An arbitrary Computer System

This is based on devices that are members of the three major components of a computer system
- Input , Processing, Output. Clock
Processor
Thus a system consists of :- Input Devices, Processing unit,
Output Devices, Memory and
Control
Secondary Storage Devices.
Unit

Input Device Arithmetic Output Device

Logic Unit

TERMINOLOGIES Memory Units

Auxiliary /
ROM RAM Secondary Storage
Data:- Raw user input for processing by the computer.
Primary/Main Storage
Information:- Processed data possessing a certain usefulness.

Instruction :- A command to the computer when followed performs 1 task. It has a specific structure (format).

Program:- A series of instructions written in a specific format (language).

Language: Coded scheme by which programs are written, having their own set of instructions/ keywords, together with the laws
governing the use of these instructions.

Bit:- A binary digit representing the 2 electrical states 1=on /0=off

Byte: Combination of 8 bits = 1 character = unit of data/info/instruction representation.

Word:- Collection of bytes (2). The typical size of an instruction.

Hardware:- The tangible elements of a computer system. It’s physical attributes.

Software:- The intangible elements of a computer system (data, instructions & information).
Firmware :- A cross between hardware & software in which hardware possesses embedded software.

Buffer :- A temporary storage area in memory used to equalize or balance different operating speeds. It can be used between a
slow input device such as a terminal keyboard and the main computer which operates at a very high speed.
- Data being transferred between the communicating devices is placed in a buffer until either device requests it at once.
- This is more efficient than having the devices continuously requesting or waiting on the other for data which would complicate
their interaction within the computer system.

MIPS:- Millions of instructions / second. Asuming a fixed instruction size,it better compares two unrelated processors’ speedss.

MHz :- million clock cycles per second.

Byte Address Word address
Main Memory :- Temporary storage area holding data, instructions and information
0 STO 0
(RAM) utilized by the processor. It consists of a series of cells, each capable
1 2
of holding a byte and referenced by a unique address.
2 1
3 45
In this example a word = 2 bytes = instruction = 16 bit size.
Hence this computer can utilize instructions in 16 bit units.
Such a machine is called a 16 bit machine. 48 ADD 24
49 31
ROM :- Holds pre-installed instructions / data (manufacturer) for the computer to work properly. These cannot be modified but read-
only.

Secondary Storage :- Holds modifiable data/instructions for extended periods with a storage space much larger than RAM.

Clocks

Clocks, are used to keep time. There is a real-time clock inside a PC that is responsible for keeping track of the date and time, but there
are
many other clocks inside, which divide time into MUCH smaller increments. These clocks are used to synchronize the work being
performed by the PC's many different components. Each is responsible for sending out extremely rapid pulses of electricity, which are
then
sent through "logic gates", which process each pulse, sometimes stopping them, other times letting them go through. These pulses, or
"clock
cycles" are the backbone of binary logic processing. "Clock speeds" are measured in megahertz, (MHz) which means "millions of cycles
per
second".
The microprocessor (CPU) has an internal clock that determines how fast an operation will take in the internal processing circuitry. The
clock speed is a base indicator of how quickly the processor can execute an instruction. Some processors are "speed doubled". This means
that processor like a 486 DX2/50 is actually a 25 MHz chip with a double speed processor. The chip communicates with the other devices
on the bus at 25 MHz, but performs all of its internal functions at 50Mhz. This is one way to get more speed out of your PC, but the chip
will not perform as well as a chip that is designed to use the bus at 50 MHz (as well as internally function at that speed). The CPU is also
sometimes rated in "MIPs", which means how many Millions of Instructions Per Second it can process.
 The speed of the PC is determined by other things as well as the clock speed. The type and amount of RAM on the SIMMs, the "width" of
the bus, and the amount of cache RAM are very important as well. If you compare two PCs, one with slower clock speed, and the other
with
a less powerful microprocessor, the overall speed of the PC with the more powerful microprocessor will usually be faster.

The rest of the PC is almost always running at a slower speed than the CPU, and for this reason there are many different clocks within the
PC. Plug-in devices like video cards often have their own clocks, allowing them to run their internal processing duties at their own speeds.

Clock:- A circuit that emits regular pulses via a crystal oscillator, to control the operation and timing of the computer. (A regular
pulse refers to a constant pulse width and separation between consecutive pulses)
- This is required in digital circuits because the order in which events happen is critical. At times one event must precede
another or more than one simultaneously. Thus used to provide synchronization and the required timing relations.

Clock Rate:- Rate at which the clock circuit generates pulses. Measured by MHz (Millions of cycles (pulses) per second). ~1-100MHz
- Best way to compare the processing speeds between processors within the same family.

Clock cycle time:- The time between 2 consecutive pulses or time to generate a pulse ~1000-10nsec.

In a computer many events may happen during a clock cycle. If they are to be done in order, the clock cycle must be divided into
smaller
HIGH cycles,
1 done by (phase) shifting the clock pulses. (Delay circuits are used on the main clock)
TheseVoltage
events are micro-operations that define an instruction which need to be synchronized for orderly execution..
LOW 0

t1 t2 Time Clock Cycle Time = Time for 1 pulse (t2 - t1)

Clock Rate = How many pulses are generated in a second .

THE PROCESSOR

FUNCTIONAL PROCESSOR COMPONENTS

These consist of the Control Unit , the Arithmetic logic Unit and Registers.

Control Unit (CU) :- Controls / coordinates processor's operation and signals various parts for orderly working.
Responsible for the orderly fetching of instructions from main memory & determines their types for execution.

Arithmetic Logic Unit (ALU) :- Performs the corresponding logical / arithmetic operations on the data via the CU's prompting.

Registers - High speed memory devices used for temporary storage of small amounts of data or intermittent results during processing, each
one of a set having a special purpose. It’s size depends on the size of a typical instruction:- word.
e.g. PC : Program counter = the memory address of the next instruction to be fetched.
IR : Instruction Register = holds the instruction being currently processed.
MAR : Memory address register = the memory address/location of an instruction/data to be fetched
MDR : Memory data register = holds the contents of a memory access.
ACC : Accumulator.

Bus :- The electrical paths connecting various components together to allow control signals, addresses and data to be transferred
between them. The amount of signals transferable depends on the bus width (size).
 THE FETCH-EXECUTE (MACHINE) CYCLE FOR VON NEUMANN MACHINES

A cycle of operations performed by the processor in which an instruction is obtained, decoded and run. This includes the fetch cycle
(instruction cycle) performed by the CU and the Execute cycle performed by the ALU. This process is repeated normally until all
instructions in a program have been carried out.

FETCH (INSTRUCTION) CYCLE :- The Control Unit

- Fetches the instruction from RAM in order.
- Decodes the instruction. (fetches operands, if necessary, when decoded)
- Sets off(signals) the respective circuitry in the ALU for that instruction

EXECUTE CYCLE:- The ALU.

- Circuitry executes instruction :- Arithmetic/logic operations.

Result obtained (sent to RAM if needed.:- done by CU).

The both cycles :- Fetch-Execute Cycle is referred to as a MACHINE CYCLE.

IN DETAIL: An arbitrary example of a Machine Cycle.

Points to consider: 1. Word size of a machine.

2. Instruction formats & size.
3. Addressing values in memory.

1. The unit by which data will be processed in this machine will be a wordsize of 2 bytes. (1 word = 2 bytes)
2. An instruction must follow the wordsize (1 instruction = 1 word).
It has 2 parts:- opcode (operation) and an operand (value/value's address) i.e. 1st byte = opcode, 2nd byte = operand.
3. Addresses are the memory locations of an instruction. (Address value = instruction’s /data’s starting byte).
Consider two instructions:-
ADD [X] : add to accumulator contents the value stored in word address X, storing the results in the accumulator

Main Memory [M] Central Processing Unit

0 LDV [3] MAR PC Control

R +1 Unit
1 ADD [4]

2 IR
3 20 Arithmetic
58 Logic Unit
4
MDR ACC

LDV [Y] : load into accumulator the contents of memory at word address Y

PC = 0 (Address of 1st instruction) (1 word = 2 bytes)

CU:
1. Examines the PC register for the RAM address of the next instruction.
2. PC --> MAR ; read signal.
3. M[MAR] --> MDR i.e. reads memory at location MAR into MDR
4. PC = PC + 1 (incremented by 1 instruction/word).
5. MDR --> IR;
6. Decodes IR contents to determine instruction type ,causing respective control signals to be sent to do either :-
i) completing the AL instruction (fetching the Or (ii) performing the NON-AL instruction and skipping ALU use.
operand(s)) IR (address) in IR --> MAR if indirect addr.
 operand (address) in IR --> MAR  M[MAR] --> MDR --> ACC
 M[MAR] --> MDR --> ACC Signals respective circuit in ALU
 Signals respective circuit in ALU
ALU:
7. Processes instruction via respective Arithmetic/logic circuits with predefined registers (e.g. ACC)
8. Stores result into register (ACC)

9. If not end of program go to step 1 (CU).

NOTE
- Fetching (Retrieving) is considered only when a new instruction is to be processed.
- An instruction is interpreted as a hardware microprogram which contains many smaller hardware operations (microinstructions).
- The time taken for a single fetch-execute (machine) cycle is not necessarily a clock cycle.
- A hardware operation (microinstruction) is performed in a clock pulse/cycle. If more needs to be done, shifted clock pulses are used.

ADDRESSING MODES
The above program showed an example of indirect addressing. The two simplest methods of referring to data stored in memory are:-
1. Direct Addressing :- operand = actual value.
2. Indirect Addressing :- operand = memory location of the value. MAR is utilized fully here. I.e. IR(address) MAR
PIPELINING

Method of speeding up the Fetch-Execute cycle by fetching not just the next instruction but the next few that follow it in main
memory. Hence increasing the effective speed (throughput) at which instructions are executed by a processor.
It is the normal way to run a program by executing each instruction one after the other in sequence where each instruction is
processed one at a time by the processor. This is typical serial processing.
However with pipelining you have more than one instruction being processed at the same time, each at a different stage of the
fetch-execute cycle such that maximum use of the processor is made with very little wastage of processing time.
i.e. Let Ix be the Instruction x.

FETCH I1 I2 I3
DECODE I1 I2
EXECUTE I1

increasing time t1 t2 t3

This means while I1 is being executed, I2 is being decoded and I3 is being fetched all at the same time instance t3.
Hence 3 instructions can be processed in one machine cycle for this example machine.

The instructions are placed into a queue of registers feeding into the IR.

When are these pre-fetches made?

- These pre-fetches are carried out if during the execution part, the memory is not accessed.
- If pipelining is in use, the previously pre-fetched queue of instructions will need to be discarded each time such a break in
instruction sequence occurs.

There is a variety of processing techniques:- Based on the amount of instructions to be processed at the same time.
Serial Processing: - operations / instructions completed one after the other in order

Concurrent processing:- instructions overlap during intervals such that more than one instruction are processed simultaneously
at different stages , with some serial order.
The above two has a common trait in that the instructions are still done serially. This happens if the processor has one data
path, and has to be utilized among the instructions being processed .

Parallel processing :- Instructions are processed at the same time with no emphasis on order. This is mainly so if many data
paths exist in the processor so each instruction stream is processed independently.

Fetch I1 I2 I1 I2 I3 I1 I3 I2 I4
Decode I1 I2 I1 I2 I3 I1 I2
Execute I1 I2 I1 I2 I1 I2

time 1 2 3 4 5 6 1 2 3 4 1 2 3 1 2 3

SERIAL CONCURRENT PARALLEL

Processor classification according to pipelining .

SISD - Single instruction Single data :- one instruction for one data path.
MISD - Multiple instruction Single data :- > 1 instruction sharing same data path.
MIMD- Multiple instruction Multiple data :- >1 instruction processed in >1 data path

This data path is the path which the instruction takes through the processor to be run.
If there are many data paths this means that different instructions can be processed at the same time.
 THE ROLE OF THE O.S. IN BRIDGING THE HARDWARE APPLICATION GAP.
OPERATING SYSTEM
What? - System software that manages the use of a computer system's hardware resources for efficient operation, controlling
(limiting) direct hardware utilization by the application software or the user.
Why? - Performs 2 functions:- Acts as an extended machine & a resource manager.

Extended Machine (top-down context)

- Provides a simple interface for the user to operate the computer without needing to know details of how the hardware works to
use it.
Resource Manager (bottom-up context)
- Bottom-up context: Manages the complex operating issues of the hardware/software resources (memory, processor, aux.storage..)
so that they work together efficiently and in order. (such that the computer’s value > sum total of it’s parts)

User

Application Program

Operating System

Hardware

If there is no O.S., working with a computer will become tedious as well as dangerous, since:
- the user will have to know how the hardware works rather than spending more time on running the application.
- errors will be very hard to locate for debugging purposes.
- Unlimited access to critical hardware areas: simple errors may cause a critical system failure (or physical injury)

Thus the O.S. needs to limit the direct manipulation of hardware and make it easy to interface with.
It does this by setting up :
- user mode : environment for running user applications
- supervisor mode : environment holding critical system procedures away from direct user access

- The code comprising the main features of the O.S. loaded into memory is called the kernel. It holds the most referenced
functions / procedures for system operation :- internal commands.
- Extra code not frequently needed is stored on auxiliary storage :- external commands

Booting

This is the process that occurs when the computer is switched on.
Critical instructions are automatically fetched and executed from ROM to perform the tasks of self-testing as power is turned on (POST),
and routines (BIOS) to determine if devices/ peripherals are properly attached to the system for their eventual usage. If no problem is met,
the Operating system residing in secondary storage is read into memory and run, eventually managing and maintaining the system.

ROM Secondary Storage

RAM Data lines

Control lines
Processor
 FIRMWARE : MICROPROGRAMMING / MICROCODE / MACHINE LANGUAGE
Microprogramming:-
- Used to implement machine language instruction sets.
- Introduces a layer of programming below a computer's machine language, thus defining machine language set of instructions.

Microprograms :-
Made up of many microinstructions. These are more elementary and sparser in function than conventional machine language
instructions.

If on a machine the machine language instruction set is implemented via microprogramming, each machine language instruction = set of
microinstructions = microprogram.

e.g. ADD , STO, SUB ,LDV .. = machine language set = instruction set = set of microprograms.

Consider a single instruction :

ADD = set of microinstructions = microprogram
(in a machine cycle) (run in a clock cycle/shifted pulses)
These are either in : software : - Slower, as they need to be fetched from slower storage.
: firmware :- Faster (on chip). This is mostly used, most microcode is implemented here

ARCHITECTURAL HIERARCHY

compiler translation assembler translation

Application programming lang. level 4 software - programming requests hardware commands via use of O.S.

O.S. level 3 software-programming bridge between applications & hardware

Conventional Machine lang. level 2 firmware-programming machine instruction set on chip / processor

Microprogramming level 1 firmware programming Simplest instructions defining an L2 instruction.

Hardware Level level 0 electrical signals No concept of programming at this level.

Interpreter :- Examines / executes L2 instructions directly into L1 instructions ( Machine instruction to microprogram)
Architecture :- Set of data types., operations & features of each level. It deals with these aspects that are visible to the user of that level.

DATA TRANSMISSION & THE CPU

SEMICONDUCTOR TERMINOLOGY
IC - Integrated Circuit
Square piece of silicon (few mm square) on which logic gates have been deposited by photochemical processes, a logic gate
being interconnected circuit elements (resistors, capacitors..) They are mounted in rectangular plastic/ceramic packages

IC types based on their electronic densities Limits:-

- Smaller the circuit, higher resistance /heat builds up
SSI - Small scale integration : 1-10 gates - Physical limitations of machinery down to .3 microns,
MSI - Medium scale integration : 10-100 gates >> 7 million elements per chip
LSI - Large scale integration : 100-100,000 gates
VLSI - Very large scale integration : > 100,000 gates Extensions
- Build chip circuitry layer upon layer
- Maximize logic gate code simplification.

5-15/20-50 mm wide/long. Metal pins are connected to the chip internally which protrude from the package along it's edges to
provide a bridge for the microcircuit.
CPU TYPES:- RISC vs CISC

Basically CISC chips have a complex structure resulting from a complex instruction set to allow backward compatibility. As a result
these instructions need to be broken down (decoded) for execution, which delays execution time.
However RISC chip design is based on keeping the data path during processing extremely simple so that the instruction can be
executed by hardware in the shortest possible time via not having any decoder. This is only possible by having very simple
instructions which need not be decoded. Efficient choice of relevant microcode is selected for simplicity and effectiveness.

CISC RISC
- Complex Instruction Set Computing Reduced Instruction Set Computing
- Complex instructions taking many cycles Simple instructions taking a cycle
- Instruction can do many tasks (General) Instruction does specifically 1 task
- Less or not pipelined (serial processing dominant) Highly pipelined ( parallel processing prevalent, can have unordered execution)
- Instructions are done by microprogram interpreting Instructions are done directly by hardware (= microinstruction)
- Instructions have different formats Fixed format instructions
- Many instructions & modes Few instructions & modes
- Complexity in microprogram (hardware) Complexity in compiler (software)
- One register set (few registers) Many register sets
- More firmware = larger size = larger power use Less firmware = smaller size = low power use
- Less processing per machine cycle done (more More processing per machine cycle (little/no decoding)
decoding)
Note:- Instruction set depends on microcode / programs used to do individual micro-operations.

Extended comparisons
more complex instructions need more processing time = decoding simple instructions require less time as they are executed directly
by hardware = no /little decoding
microinstructions are run by hardware paced by the clock pulses few microinstructions.
longer machine cycle @ clock-speed x => shorter machine cycle @ clock-speed x
- Both process the same instruction but the processing method each does is different.
- At the same clock-speed RISC >= CISC.
- MIPS (processing throughput) is better used to compare different chip architectures capabilities of processing.
- As we see, clock speed is a poor indicator in comparing the capabilities of the two chips.

MIPS vs MHz in processor comparisons across various families.

Mov A Mov A Mov A

X MHz
x MHz

Mov A 2X MHz
Mov Mov
A A
x MHz

Comparing different processor families Comparing same processor families

Same instruction implemented differently for different Instruction is implemented similarly for same
families i.e. in 2 pulses in top example and 4 pulses below. families i.e. in 2 pulses for both.
Clock rates are identical Clock rates are different
Different families
The instruction ,due to the different chip design, will be implemented differently even though the same task (MOV) gets done. It is done in
a different number of pulses, even at the same clock rate. Hence clock rate is inappropriate to compare differing processor families.
However, the number of instructions done in the same time differs for the different chips. i.e. MIPS should be used as the unit to measure
speed between families.
The disadvantage of MIPs exists due to the use of an average instruction size for a processor’s speed. i.e. a 100 MIPs processor means it
can do 10 million average instructions per second when the processor actually has many types of instructions. It is an inaccurate measure.
Same families
The instruction is implemented the same way in the same family because the family has the same architectural design. However the clock
having the higher pulses per unit time (frequency) causes more instructions to be performed in the same time frame.
i.e. MHz is appropriate to measure speeds within the same family.

RISC (O.S.) system: One designed to minimize the # of different microprocessor hardware operations in order to optimize the execution
speed. The software itself is complex, to handle the decoding if required for any complex instruction.

Arguments / Issues behind RISC's development.

 Most operations to be performed in a program are simple  use simple instructions

 no decoder
 very fast / short machine cycle.

 If a complex operation should be encountered / utilized , these can be represented /decoded as many simpler RISC instructions
 if decoder needed, it should be made very simple & hardware based or complex and software based.
 processing speed at it's worst rarely = the speed of CISC.

 Large instruction set allows redundancies & complexities in formats.(inefficient) Not all instructions will be encountered. (20% of
instructions used 80% of time)
 Reduced set of instructions selected to make the most efficient set  efficient, optimal execution.
Common processor families
Manufacturer Family Type Date Notes
Intel 80x86 CISC 1976-199?
i960 RISC
Motorola 680xx CISC 1978-1993 Utilized by Apple computers
88000 RISC
AMD Kx RISC
29000 CISC
Cyrix xX86 CISC
Hewlett-Packard HP-PA RISC
Acorn ARM RISC Archimedes = 1st RISC PC
Digital Alpha RISC
Sun ULTRASPARC RISC
IBM RT/PC (IBM 801) RISC First IBM RISC Machine
SP/2 RISC
RS/6000 RISC
MIPS Rx000 RISC R2000/3000/4000 | R2010 coprocessor

INTEL CHIP FAMILY : series of CISC processors

Year Chip Features Notes

1971 4004 - 1st microprocessor
- 4 bit register/ data bus
- 1 Kb addressable
1972 8008 - 1st 8 bit microprocessor
- 8 bit register / data bus
- 16 Kb addressable
1974 8080 - 1st General Purpose CPU 2 MHz / 0.64 MIPS
- 8 bit register / data bus
- 64 Kb addressable
1978 8086 - 1st 16 bit CPU 5 MHz / 0.33 MIPS (x86 series starts)
- 16 bit register / data bus
- 1 Mb addressable
1979 8088 - Used in original IBM PC (XT) 5 MHz/1.2 MIPS (29,000 transistors)
- 16 bit register/ data bus
- 1 Mb addressable
1984 80286 - Used in IBM PC (AT) 8MHz/ 1.2 MIPS (135,000 transistors)
- 16 bit register / data bus
- 16 Mb addressable. - other speeds 6,12,18 MHz
- 2 operating modes
- Real : works like 8086
- Protected : many environments for > 1 task,
each running separately
1985 80386 - 1st 32 bit CPU (286 & 287 coprocessor on one chip) 16MHz / 6 MIPS (275,000 transistors)
- 32 bit register / data bus
- 4 Gb addressable -other speeds :- 20 ,25, 33 MHz for DX chip
- Better memory management :- 16, 20 MHz for SX chip

1989 80486 - (386 & 387 co-processor on one chip) - other speeds : 25,33,50 MHz for DX chip
- 32 bit register / data bus : 16, 25 MHz for SX chip.
- 4 Gb addressable : 50, 66 MHz for DX2 chip
- memory cache on chip : 75,100 MHz for DX4 chip
- SL chip variants (low power consumption)
1993 Pentium (P5) - 64 bit CPU
- Internal 64 bit register / external 32 bit data bus 60,66,75,90, 100,120, 133,150,180,200 MHz
- Not efficient in changing between 16 & 32 bit modes
1995 Pentium Pro - 64 bit CPU
(P6) - Pentium:- internal cache (16-32K) at processor speed
- internal 64 bit register / external 32 bit data bus - speeds : 180,200 MHz.
- Optimized for 32 bit instructions.
- Symmetric multiprocessing (SMP) (2 / 4 processors).
1996 Pentium - 64 bit CPU
MMX - internal 64 bit register / external 32 bit data bus Speeds : 166, 200,233 MHz.
(P6) - Pentium Pro internal cache removed & replaced with
a multimedia instruction set.
1997 Pentium II - Combined Pentium Pro with MMX instruction set - Speeds : 233, 266, 300, 333, 350, 400, 450 MHz
(P6) - Increased internal cache by 16K at slower speeds.
- Can effectively run 16/32 bit instructions
- SMP supported (2 - 6 processors)
- uses a SEC slot (Single Edge Cartridge)
Co-processor:- A separate processor specifically built to perform complex mathematical tasks (in CAD) :- FPU (Floating Point Unit).
DX:- An INTEL processor having an enabled internal co-processor / FPU.
SX:- An INTEL processor whose internal FPU is disabled permanently and usually has an external bus smaller than it’s internal bus.
MEMORY DEVICES
Memory ( Main/ Primary storage):-
Part of the processing unit of the computer used for storing data and instructions to be used by the processor.
It consists of a large number of storage spaces (cells) each capable of holding a byte, located by a unique address. (binary)
Data can be fetched from (or stored to) any cell very rapidly.

Bit cell (on/off = 1/0)

Power Addresses = row value = 20 bits

Address range = 0 to 220-1
Read = 1Mb addressable
Address
Write
00000000000000000010
Data

A memory bit cell with it’s various buses .

0 1 0 0 1 0 1 0
Memory is considered to be of two major types being RAM & ROM Data = Column value = 8 bits = byte
Can read from / write to an addressed row.
Data transferred onto these data lines (bus).

Memory architecture depicting 1 Mb memory.

RAM ROM
Random Access Memory Read Only Memory
Can read data from and write data to it. Can only read contents.

Used for primary storage to temporarily hold Used to store important control instructions required always by the system
data / instructions for use by the processor. which must never be changed.
e.g. POST & BIOS system ROM instructions/data

Contents vary depending on the user’s task. Contents cannot change, permanently embedded during manufacturing time.

Volatile storage. Requires power supply, otherwise Not volatile. Contents remain unchanged in the absence / presence of power.
it’s contents are lost when power is turned off.

Periodic recharging is needed to retain contents, as the Requires little or no power to function.
cells tend to lose their charge after a short time.
i.e. memory is refreshed or ‘topped-off’ regularly.

Fast access time. 60 to 200 ns Fast access time.

Various packaging types

DIP - Dual inline package
SIP - Single Inline Package
ZIP - Zigzag Inline Package
SIMM - Single inline memory module
DIP ZIP SIP

Various Manufacturing Techniques

MOS - Metal Oxide Semiconductor
CMOS- Composite MOS

SIMM
Types of RAM/ROM chips

RAM chips. ROM chips.

SRAM - Static RAM PROM - Programmable ROM
- cells retain charges longer without the constant - Consist of many fusible wires each representing
refreshing as DRAM, though requiring a constant power a bit location. An applied voltage pattern melts
supply. specific wires representing the pattern input.
- Volatile storage. - Where a melted wire exists = 0. Where good
- Faster access times (10-30 ns) wire exists = 1.
- Expensive. - Contents are permanent / cannot be changed.
- Used for caching purposes.
DRAM - Dynamic RAM EEPROM- Electrically EPROM
- cells periodically need recharging as they leak power. - Like EPROM except:-
- Volatile storage. - Applying voltage erases contents of chip for reuse.
- Fast access times (60-200 ns)
- Cheap
- Used mostly for main memory (primary storage)
VRAM- Video RAM EPROM - Erasable PROM
- For video cards (adapter cards) - Input as electrical signals are stored on the chip.
- Allows 2 devices to access an address simultaneously - Contents cannot be modified.
without the other waiting for the next to finish. - Contents are involatile, as they remain unchanged in
- It is dual ported:- 2 access points for devices. the absence of electricity.
-Expensive - Exposing chip to Ultra-Violet light erases it’s
Processor VRAM CRT controller
contents causing chip to be reused.
Manipulates contents Converts contents to
pixel information.

WRAM - Windows RAM

- Same as VRAM (specifically for video cards)
- Added logic functions to speed up video functions.
- faster than VRAM.
- Very expensive
EDORAM - Extended Data Out RAM
- 10% faster than DRAM
- As cheap as DRAM
- Logic on chip used. Assumes next memory access will
be a neighboring address. Places data out before
processor fetch to present it faster to processor if needed.

EDRAM- Enhanced DRAM

- Combination of DRAM & SRAM
- Small amount of SRAM placed on DRAM chip.
 DRAM has a cache on it.

Memory wait states & caching.

Memory access time:- Time allowed for a memory device to produce a dependable output signal after it receives an input signal requesting
it’s contents at an address. These values range from 60 to 200 ns.
Problem:-
For the memory to be in a ready state for processor usage, i.e. a state for it’s data to be allowed access to, it requires time to prepare
itself
for such usage periodically,. Time is required for recharging it’s contents during which absolutely no access is allowed.
The processor being operationally much faster than memory (~5 ns), therefore should wait on memory to use it.

Solution:- Two methods can be used to cater for this speed difference.

1. Accept the wait period by using a memory wait state.

Wait states or pauses are used by the processor to allow it to wait a few cycles to access a ready memory.
This gives the memory synchronised time to prepare itself for use.

2. Introduce caching (high speed buffer).

Use a memory cache. :- Bank of high speed memory comparable to the processor’s speed which will hold the most frequently or
most recently used data from memory to avoid waiting on slower RAM. (DRAM)
SRAM chips due to it’s fast access speeds would be used.
 CACHING
It is the process of using a cache.
Cache:-
What ? - A fast, small buffer, placed between 2 devices of differing speeds, holding frequently accessed data originating from the slower
device, to be provided to the faster device.

Why ? - To speed up data access between the two devices to equalize their speeds such that the faster obtains data quicker.

How ? - Two devices operating at widely differing speeds causes the faster to unavoidably wait on the slower for it’s data.
This waiting wastes time.
A cache running faster than the slower device will provide the requested data quicker to the faster device, reducing waiting.
The faster device no longer needs to contend with the slower device for it’s data, increasing data transfer efficiency.

When? - Needed wherever a bottleneck arises i.e. wherever two devices exchanging data differ in speeds greatly.

What kind of data should be held in a cache ?

- It should hold the most frequently requested data from the slower device. This avoids time consuming repetitive accesses for the same
data in the slower.

Disk >9 ms
How can this data be chosen ?
- A caching controller can be used. It intelligently determines what data
the faster component requires next, gets it before from the slower Disk/cache controller Falling access times
RAM
device and has it ready in the cache when the faster requires it.
Disk cache
- It does this by following a set of built-in algorithms and track what data
is being used over time with it to determine the most likely data to be Video ROM
used for caching. BIOS ROM Shadow RAM 60 – 200 ns
- It’s success is determined by the algorithms used to maximize cache
‘hits’ and the cache’s size. RAM cache controller
- It can be implemented as firmware/ software. RAM cache 10 – 30 ns

Processor < 10 ns

There are basically two major types of caching implemented in a computer system, where a fast , efficient data flow must be maintained:-

Disk cache & Memory cache

Disk cache Memory cache

Buffers data between secondary storage (disk) and the processor. Buffers data between RAM and the processor.

Utilizes a region of RAM which stores the requested contents from disk. Utilizes SRAM chips external to the processor.

Can store large quantities of disk contents in the cache It has a very small size.

Slower than a memory cache Faster than a disk cache.

Vast speed improvement (ms  ns ) (factor of 1,000,000) Marginal speed improvement (ns ns) (factor of 3)

Cache “hit” :- when data requested is found in the cache.

Cache “miss”:- Requested data is not found in he cache, being accessed from the slower device.
Cache size :- Depends on how much data access is required. It is normally kept small or accessing cache will slow down transfer times.

The processor possesses an internal cache also called L1 (Level 1) cache or primary cache, which caches data & instructions separately.
An L2 cache is also implemented which is external to the processor and is slower. It is also called secondary cache.

Write Through Cache :- Preempts (interrupts) the processor to put data on secondary storage in case of power outage.
Deferred writes :- Wait for system to be free of activities before writing to secondary storage.

Disk
Disk cache Memory cache processor

RAM
 DMA's importance for I/O devices.
DMA - Direct Memory Access.
- A method whereby I/O devices access main memory directly without the active intervention of the processor by the assistance
of respective firmware control logic.

Problem - I/O devices send /receive data streams that cannot be interrupted or data will be lost. The processor slows down this process
to access memory thus increasing the possibility of data loss.

Solution:-
Another processor is used to specifically assist the I/O devices access to main memory. (DMA Controller Chip)
This relieves (frees) the CPU from the burden of accessing memory for the I/O devices, allowing it to do other processing while
the DMA chip assumes the responsibility of memory access simultaneously.

- The DMAC is given priority over the CPU for memory access at all times otherwise the data stream may become affected.
- Data transfer requires lots of signals to acquire the memory bus for memory access as well as to other devices for notification.
This is a lengthy process taking up many memory cycles. The CPU can thus process it's instructions during such periods.

What if the CPU requests memory via bus access while the DMAC is using memory ?
- the CPU will be allowed to wait until the DMAC is finished with memory.

What if the CPU & DMAC requests bus access to memory at the same time ?
- the DMAC is given first choice. Thus bus cycles access to memory (time period to get the bus) that the CPU would have used are
given to the DMAC to access memory. The DMAC is said to have stolen cycles from the CPU to gain memory access.
- Access to memory will be returned to the CPU after usage.

Memory
Data

Memory access Control

Read /Write Data transfer
Address

Initialize DMAC
DMAC DMA granted Peripheral
Processor Bus granted
DMA requested
Bus requested

DMA channel :- DMA pathway to let data be transferred.

Usually > 1 I/O devices would request use of memory. They are allowed access to memory in parallel, each using a
separate DMA channel.
This speeds up the flow of data in the system by allowing > 1 device to work together.
 BUSES
What? - Collection of // electrical conductors (lines) to which components may be connected for the transmission of signals between
them.
- Connections are made at points along the bus' length via connectors with many electrical contacts.
Why? - Facilitates communication between main storage, I/O, processor and other external components.

2 types of buses (in context of location):-

INTERNAL : within the processor, necessary to integrate each part of the CPU. e.g. CU & ALU
EXTERNAL : outside the processor to connect separate hardware components. e.g. CPU & main memory, CPU & I/O devices.

3 types of buses (in context of function):-

Data bus : Transfers signals, representing data, between storage and devices.

Address bus: Transfers signals, representing storage locations or device i.d.’s, of data/instructions or devices respectively for their
location.

Control bus : Transfers signals, representing control values, to devices for their co-ordination / control with the system.

Bus width The # of lines a bus has, where each line transports a bit signal. This one of the factors which determines the speed of
processing. It is also called bandwidth

The data bus width ~ register wordsize.

The address bus width = the power to which 2 is raised giving the amount of memory locations (memory space) that are addressable.

Comparative sizes :- Data bus ~ Address Bus > > Control Bus

- Signals can be sent in any of the following three ways:

- In one direction only : Simplex
- In two directions but not at the same time : Half Duplex
- In two directions at the same time : Duplex

- Computers usually have separate dedicated buses to avoid overloading the path between components and to allow components to
interact with others at their common speeds most efficiently. e.g. processor & memory : very fast (needs a dedicated bus to avoid
delays in communication)

Computer system with a dedicated bus Computer system with a shared bus

Auxiliary Input Output

Storage Devices Devices

CPU

Memory

Auxiliary Input
CPU Memory Storage Devices

Controller Controller
 Expansion Buses
An expansion bus is an extension of the PC's data and address buses. It is the electric pathway used by your PC to connect the computer's
motherboard and peripheral devices. This bus connects to such things as memory boards, video adapter boards, on-board modems, bus
mouse boards, disk controllers and serial I/O boards. It includes a number of slots for these "plug-in" devices.

How Expansion Buses Work

The way data expansion buses work is: the processor or some other component sends signals along several parallel circuit lines. The
number of these lines vary, depending upon the type of bus you have. This example uses the lowest, or 8-bit bus. The 8-bit bus uses sixty-
two lines to connect to adapter cards. Any signal that is sent is received by all of the adapter cards. Next, eight lines send electrical power
to the adapter cards, although different lines have varying voltages. Whether the data is going to memory chips, display adapters or a disk
controller, eight to thirty-two lines are used to transmit it.
This bus allows peripheral devices to be added to the computer system simply by plugging the device’s adapter card into the expansion
bus’ socket.

There are several types of expansion buses:- 8/16 bit :- ISA (AT ).
32 bit :- EISA , MCA , LOCAL BUS (PCI & VL-BUS)
ISA:- - Industry Standard Architecture
- 8 bit IBM AT bus (8086s) .
- Increased to 16 bit bandwidth .(used in PC/AT) (286-486)
- most common bus type / cheap
- speed of 8 MHz for both 8 / 16 bit buses. Transmission rate = 8Mb/\sec

MCA :- - Micro Channel Architecture

- 1st 32 bit bus (IBM in PS/2) to improve 32 bit processing power.
- Bus mastering introduced.(DMA)
- Easy setup. :- Able to resolve conflicts of different components wanting to use same resources (auto-configuration).
- Incompatible with older computers (ISA).
- not widely used / expensive.
With an MCA (Micro Channel Architecture) bus, data is transmitted along 32 lines. This bus will transmit only to adapter cards that are
specifically designed to work with MCA. They cannot accept 8 or 16 ISA, or 32 bit EISA adapter cards. It was not popular because of it’s
incompatibility with older systems and IBM restricted other companies from utilizing it’s designs making it harder to become common.

EISA:- - Extended ISA

- 32 bit bus option to MCA
- Bus mastering.
- Easy setup (auto-configuration.)
- Socket is compatible with older ISA cards.
- Complex circuitry => expensive.
With an EISA, (Extended Industry Standard Architecture) bus, data is transmitted along 32 lines. This bus was designed to compete
with IBM's proprietary MCA bus. However, the EISA bus will work "down" from its 32- bit status; it will also work with 8 and 16
bit ISA adapter cards and disk drives.

Local bus :- VL-BUS & PCI .

It’s design makes it much faster than the other bus designs. The first bus was designed to run at 8 MHz, or about twice as fast as the
processor. When processor speeds increased, up to 50 MHz and faster, the speed of the expansion bus stayed at 8 MHz. The new local
bus can transmit 32 bits of information at the same speed as the PC's processor. However, a PC with a local bus usually only has one or
two slots. These are used where the speed is most important; things like display adapters and disk controllers. The regular, slower
expansion slots are used for devices where speed is not as important, such as keyboards, and serial and parallel ports.
Computers can use a mixture of ISA & VL-BUS or ISA & PCI, not PCI & VL-BUS together both being incompatible with each
other.
- Utilizes the high-speed bus connected locally to the processor
- Very fast speeds (processor speeds)

VL-BUS - VESA LOCAL BUS

- cheap method of boosting old ISA motherboards. (386/486 machines)
- For graphics utilized by video cards and fast data transfers by disks.
- speed of the processor’s local bus (max of 50 Mhz). Transmission speed = 107Mb/sec

PCI - Personal Computer Interconnect (INTEL)

- Utilized on high end machines (introduced on Pentium machines)
- 10 % faster than VL-BUS (>= 55 Mhz) Transmission speed = 132 Mb/sec

PCMCIA / PC-Cards

These slots are very small and compact in size, allowing the insertion of an adapter card the size and shape of a credit card, to which a
peripheral device will be attached to.
- It requires very little power due to the use of compact micro-circuitry.
- Rugged :- as the components are solid state, with very little/ no moving parts.
- Convenient :- very portable (small size).
- Various types:- PCMCIA type I , II, III
- Somewhat expensive / not commonly used on desktop systems/ more used for notebook computers.
- Ports are fast:- integrated electronics reduce the distance to send data - lines are very short)
- Versatile:- can have multiple devices accessing a slot /some cards have multiple functions.
Comparison of Expansion Bus Standards

Name Date Bus width Clock speed Addressing

PC bus 1981 8 bits 4.77 MHz. 1MB
ISA 1984 16 bits 8 MHz 16MB
Micro Channel 1987 32 bits 10 MHz 16MB
EISA 1988 32 bits 8 MHz 4GB
VL Bus 1992 32/64 bits 50 MHz 4GB
PCI 1992 32/64 bits 33 MHz 4GB
PC Card 1990 16 bits 8 MHz 64MB
CardBus 1994 32 bits 33 MHz 4GB

Layout of expansion buses

 PORTS

These are external points of connection (plug or socket interfaces) allowing the connection of peripheral devices onto a PC system.

- A special piece of circuitry is used to provide a compatibility connection between the port and the computer
- the circuitry sits between the computer and the "port" :- adapter card.

- Ports are either serial or parallel.

PARALLEL SERIAL
A parallel interface sends the set of bits comprising a character A serial interface sends or receives the bits comprising each
code all at the same time. character code one at a time in sequence in a continuous
0 stream.

0 1 1 1 1 0 1 1
1 1
=> more wires: A bit signal is transmitted by 1
it’s individual wire. 1 => less wires:- One wire being shared among bit signals.
1
0
Industry standard:- Centronics port. 1
1 Industry standard:- RS232 port:- 9 & 25 pin connectors
Faster / Shorter per byte transmission 1
Slower / Longer per byte transmission.
The multiple wiring for multiple data paths creates crosstalk.
i.e. voltages in wires create feedback onto neighboring wires No such crosstalk as each bit is sent at differing times to the
during data transmission causing interference of the data signals. other, hence they do not affect one another.

Voltages weaken the longer the cable due to signal leakage.

Thus these cables are short. (Maximum 10 ft long) No such length limitation.

Used for devices which utilize a large quantity of data & faster.
(printers, external secondary storage) Devices utilize small data quantities and are fairly slow.
(modems, mice) (2400 – 115,000 bps)
Universal Serial Bus
 Three drawbacks head any list of the most aggravating aspects of serial ports: low speed, complex cabling, and the limited number of
ports. The Universal Serial Bus breaks through all three, combining a signaling rate of 12 Mbits/sec with a mistake proof wiring system
and almost unlimited number of connections. The standard also supports lower speed devices sharing the same wiring system along
with high speed devices. The low speed signaling rate is 1.5 Mbits/sec.
First introduced in 1996, the USB is more than a successor to the RS-232C serial port. It provides the basic mechanism for connecting
most, if not all, peripherals to your PC. Everything from your keyboard to cash register drawer can connect simply and quickly with a USB
plug.

Background
Designed for those who would rather compute than worry about hardware, the premise underlying USB is the substitution of software
intelligence for cabling confusion. USB handles all the issues involved in linking multiple devices with different capabilities and data rates
with a layer cake of software. Along the way, it introduces its own new technology and terminology.
USB divides serial hardware into two classes, hubs and functions. A USB hub provides jacks into which you can plug functions. A USB
function is a device that actually does something. USB's designers imagined that a function may be anything that you can connect to your
computer including keyboards, mice, modems, printers, plotters, scanners, or whatever.
Rather than a simple point to point port, the USB acts as an actual bus that allows you to connect multiple peripherals to one jack on your
PC with all of the linked devices sharing exactly the same signals. Information passes across the bus in the form of packets, and all
functions receive all packets. Your PC accesses individual functions by adding a specific address to the packets, and only the function with
the correct address acts on the packets addressed to it.
The physical manifestation of USB is a port, a jack that's part of a hub. Each physical USB port connects to a single device, and a hub
offers multiple jacks to let you plug in several devices. You can plug one hub into another to provide several additional jacks and ports to
connect more devices. The USB design envisions a hierarchical system with hubs connected to hubs connected to hubs. In that each hub
allows multiple connections, the reach of the USB system branches out like a tree—or a tree's roots. Figure 21.16 gives a conceptual view
of the USB wiring system.
Figure 21.16 USB hierarchical interconnection scheme.
Your PC acts as the base hub for a USB system and is termed the host. The circuitry in your PC that controls this integral hub and the rest
of the USB system is called the bus controller. Each USB system has one and only one bus controller.
The USB system doesn't care which device you plug into which hub or how many levels down the hub hierarchy you put a particular
device. All the system requires is that you properly plug everything together following its simple rule—each device must plug into a hub—
and the USB software sorts everything out. This software, making up the USB protocol, is the most complex part of the design. In
comparison, the actual hardware is simple—but the hardware won't work without the protocol.
The wiring hardware imposes no limit on the number of devices and functions that you can connect in a USB system. You can plug hubs
into hubs into hubs fanning out into as many ports as you like. You do face limits, however. The protocol limits the number of functions on
one bus to 127 because of addressing limits. Seven bits are allowed for encoding function addresses, and one of the potential 128 is
reserved.
In addition, the wiring limits the distance at which you can place functions from hubs. The maximum length of a USB cable is five meters.
Because hubs can regenerate signals, however, your USB system can stretch out for greater distances by making multiple hops through
hubs.
As part of the Plug-and-Play process, the USB controller goes on a device hunt when you start your PC. It interrogates each device to find
out what it is. It then builds a map that locates each device by hub and port number. These become part of the packet address. When the
USB driver sends data out the port, it routes it to the proper device by this hub and port address.
Wiring with USB is, by design, trouble free. Because all devices receive all signals, you face no issues of routing. Because each port has a
single jack that accepts one and only one connector—and a connector of a specific matching type—you don't have to worry about adapters,
crossover cables or the other minutiae required to make old style serial connections work.
On the other hand, USB requires specific software support. Any device with a USB connector has the necessary firmware to handle USB
built in. But your PC also requires software to make the USB system work. Your PC's operating system must know how to send the
appropriate signals to its USB ports. In addition, each function must have a matching software driver. The function driver creates the
commands or packages the data for its associated device. An overall USB driver acts as the delivery service, providing the channel—called,
in USB terminology, a pipe—for routing the data to the various functions. Consequently, each USB you add to your PC requires software
installation along with plugging in the hardware.

Connectors
The USB system involves four different styles of connectors, two chassis-mounted jacks and two plugs at the ends of cables. Each jack and
plug comes in two varieties, A and B.
Hubs have A jacks. These are the primary outward manifestation of the USB port. The matching A plug attaches to the cable that leads to
the USB device. In the purest form of USB, this cable is permanently affixed to the device, and you need worry about no other plugs or
jacks.
The USB standard allows for a second, different style of plug and jack meant only to be used for inputs to USB devices. If a USB device
(other than a hub) requires a connector so that, as a convenience, you can remove the cable, it uses a USB "B" jack. The mating plug is a
"B" plug.
The motivation behind this multiplicity of connectors is to prevent rather than cause confusion. All USB cables have an A plug at one end
and a B plug at the other. One end must attach to a hub and the other to a device. You cannot inadvertently plug things together incorrectly.
Because all A jacks are outputs and all B jacks are inputs, only one form of detachable USB cable exists—one with an A plug at one end
and a B plug at the other. No crossover cables or adapters are needed for any USB wiring scheme.

Cable
The physical USB wiring uses a special four-wire cable. Two conductors in the cable transfer the data as a differential digital signal. That
is, the voltage on the two conductors is of equal magnitude and opposite polarity so that when subtracted from one another (finding the
difference) the result cancels out any noise that ordinarily would add equally to the signal on each line. In addition, the USB cable includes
a power signal, nominally five volts DC, and a ground return. The power signal allows you to supply power for external serial devices
through the USB cable.
The two data wires are twisted together as a pair. The power cables may or may not be.
To achieve its high data rate, the USB specification requires that certain physical characteristics of the cable be carefully controlled. Even
so, the maximum length permitted any USB cable is five meters.
One limit on cable length is the inevitable voltage drop suffered by the power signal. All wires offer some resistance to electrical flow,
and the resistance is proportional to the wire gauge. Hence, lower wire gauges (thicker wires) have lower resistance. Longer cables require
lower wire gauges. At maximum length, the USB specification requires 20-gauge wire, which is one step (two gauge numbers) thinner than
ordinary lamp cord.
 TRANSMISSION CODING
What? - The way in which human input is represented to a computer in a form that it can use.

- The computer uses electrical signals = on/off states represented by binary digits 1/0 denoting these two states respectively.
- We can combine these signals/bits into a pattern to represent something meaningful.
- To represent meaning we use a code. Thus the code will be meaningful electrical bit patterns.
- How many bits?:- ~200 char used. As multiple of 2, 256 is enough=8 bits e.g. 'A' may be represented as the bit pattern 10000001.

There exists several coding methods to represent data in a computer system. Each one is standardized to allow compatibility.

Standardization exists to allow different systems to be compatible via following a fixed set of rules to ensure data is
represented always in the same format, otherwise data exchange will be complicated and limited between differing systems.

- BAUDOT
- 1850's used in telegraph machines.
- 5 bit code = character
- Only uppercase characters & figures used.
- Implemented a key = LTRS which was used to notify sent letters, FIGS used to notify figures sent.
- 32 characters. :- 2 keys FIGS, LTRS doubled range :- 32 for FIGS, 32 for LTRS.
- no order in the coding scheme. => 'A' = 11000 'B'= 10011

- ASCII : American national Standard Code for Information Interchange : To represent integers
- 1st introduced in 1966
- 7 bit code = a character
- code had a numerical order in the bit patterns. This made it easy to represent electronically.
- 128 characters represented (0-127) :- A-Z,a-z,0-9,punctuation ,control chars( LF,CR,BS)
96 printable 31 control chars

- EBCDIC: Extended Binary Coded Decimal Interchange Code : To represent characters

When IBM developed its 360-series of mainframe computers, it developed its own eight-bit data code to encompass the alphabet. Building
on the foundation of BCD, IBM extended the code by adding four more bits and created what it called the Extended Binary Coded Decimal
Interchange Code or EBCDIC.
In the EBCDIC system as developed by IBM, characters were not assigned to all of the potential code values, leaving many of them
undefined

- 8 bit code = a character

- code had partial order in the bit patterns for successive alphabetical characters. Harder to represent
(since some un-ordering was present) 'A' = 11000001 'B'=11000010
- 256 characters (0-255):- 63 control characters

- BCD : Binary Coded Decimal : Designed to represent integers.

When electronic calculators first appeared, the code was obvious: assign a binary code to each of the ten numerals commonly used in our
favored decimal system. The shortest code that works is four bits, sufficient to encode 16 symbols. The leftover six can be used for
mathematical operators or whatever you like.

- This is a way by which integers can be represented.

- The # to be stored is treated as a set of digits & the binary equivalent of each digit is stored,
- How much bits per # ?
4 bits sufficient to represent all 10 decimal digits. i.e. 0 = 0000, 1 = 0001, 2 = 0010... 9 = 1001
- Leftover bit combinations represent '+' & '-' i.e. '+' = 1010 '-' = 1011

e.g. to store 378 = '3' '7' '8' -40 = - 4 0

0011 0111 1000 1011 0100 0000

- in a byte we have 2 4-bit combinations.

A byte can store +/- & digit => range +9 to -9 (if '+' not understood)
digit & digit => range 99 to -9 (if '+' understood)

- Disadvantage = Wasted a bit combination in that zero can have values 1010 0000 (+0) 1011 0000 (-0) when
we need only one combination to represent this number.
 TRANSMISSION ERRORS :- PARITY CHECK CODES
Why? - to detect errors in data/information transmitted between two communicating devices where bits may be erroneously changed
in the course of transmission due to an electrical or mechanical failure.

How? - parity check system used :- two schemes :- Even Parity & Odd Parity
& two variants :- Longitudinal Parity & Cyclic Redundancy Check

Parity systems require an extra bit (parity bit) being transmitted / associated with a byte, whose sum value with the byte’s bits are used to
detect errors in the transmitted byte.

Even Parity :- All bit values in a byte and a parity bit add up to an even number means no errors are present.
- If byte bits added = odd, uses parity bit = 1 for even result.
- If byte bits added = even uses parity bit = 0 for even result.

e.g. 10111011 is transmitted. What should the parity bit be ?

- Sum all bits = 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 = 6

- Is the sum even or odd ? ==> Even = 6.

- Sum + parity bit = Even. => parity bit = 0.

Modified bits with parity bit = 010111011

Odd Parity :- All bit values in a byte and parity bit add up to an odd number means no errors are present.
- If byte bits added = odd, uses parity bit = 0 for odd result.
- If byte bits added = even uses parity bit = 1 for odd result.

e.g. 10111011 is transmitted. What should the parity bit be ?

Sum all bits = 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 = 6

Is the sum even or odd ? ==> Even = 6.

Sum + parity bit = odd. => parity bit = 1.

Modified bits with parity bit = 110111011

Disadvantage:- Even or odd parity systems requires that the byte & parity bit sum value is either even or odd respectively.
However if an even number of bits have errors, these errors will not be detected by this system.

Longitudinal Parity (alias Horizontal Redundancy check):

- either even or odd parity schemes used as above, but is done for a tapes length.
- All characters on a track are tallied along the tape's length, the result stored at the end of the track with a parity bit to maintain
odd/ even parity

Cyclic Redundancy Check

- along the disk track the characters are tallied and used with a formula with an error check value , the result being stored.
If this result doesn't match what was read a CRC error has been detected.