Practice Questions
Practice Questions
Q1. Design a logical circuit using JK, D and T flip-flop that will detect the sequence 1111 in overlapping
mode.
Q2. Design the Mealy model state diagram that will produce an output 1 after receiving the pattern ‘aab’
from the input bit stream of a’s and b’s, otherwise it will produce the output as 0. Draw the state table also
of the Mealy model. Find its equivalent Moore model state diagram and state table.
Q3. Write the Verilog HDL code for the circuit diagram in Gate level and Data flow level for the circuit
as shown in the fig.
Q4. Design a MOD 12 Ripple up and down counter by applying asynchronous inputs using T flip flop.
Q5. The logic operations of two combinational circuits in Figure-I and Figure-II are same or are entirely
different
Q7. Given F = ∑ (1, 5, 6, 7, 11, 12, 13, 15), find number of implicants, PI, EPI.
Q9. Which one of the following circuits is NOT equivalent to a 2-input X-NOR gate.
Q10. What is the minimum number of gates required to implement the Boolean function (AB+C), if we
have to use only 2-input NOR gates?
Q11. In the Karnaugh map shown below, X denotes a don't care term. What is the minimal form of the
function represented by the Karnaugh map?
Q12. Convert the octal number 0.4051 into its equivalent decimal number, and convert the Hexadecimal
equivalent of 01111100110111100011 is
1.
2.
From the table given draw the Karnaugh map with don’t cares. Use don’t care to simplify the function.
Implement the simplified function for the output Y:
Q17. A truth table has LOW outputs for inputs of 0000 to 0110, a HIGH output for 0111, LOW outputs for
1000 to 1001, and don’t-cares for 1010 to 1111. Show the simplest logic circuit for this truth table.
Q18. Design a 4 bit ripple up and down counter using the J-K flip flop.
Q19 Design a 3 bit ripple up and down counter using the D flip flop.
Q22. From the truth table as shown below, determine the standard SOP expression and the equivalent
standard POS expression.
Q23. Show the truth table and the Logic circuit diagram for a decimal to BCD encoder.
Q24. Implement the logic function as specified in table below using the 8: 1input data selector/multiplexer.
Q25. Implement a full adder and a full subtractor circuit using a 4:1 mux.