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CS302 - Lab Manual - Week No

The document describes designing and implementing different types of shift registers including serial in serial out, serial in parallel out, parallel in serial out, and parallel in parallel out. It provides the required components, theory, pin diagrams, logic diagrams, and truth tables for each type of shift register.

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Rooha Kooki
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16 views6 pages

CS302 - Lab Manual - Week No

The document describes designing and implementing different types of shift registers including serial in serial out, serial in parallel out, parallel in serial out, and parallel in parallel out. It provides the required components, theory, pin diagrams, logic diagrams, and truth tables for each type of shift register.

Uploaded by

Rooha Kooki
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab Experiment # 16

Design and Implementation of Shift Register

AIM
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out
Apparatus Required

S No. COMPONENT SPECIFICATION QTY.


1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

Theory
A register can shift its binary information in one or both directions is
known as shift register. The logical configuration of shift register consists of a
D-Flip flop cascaded with output of one flip flop connected to input of next flip
flop. All flip flops receive common clock pulses which causes the shift in the
output of the flip flop. The simplest possible shift register is one that uses only
flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one-bit
position to right.

Pin Diagram
Logic Diagram
Serial in Serial Out

Truth Table

Serial in Serial out


CLK

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
Logic Diagram
Serial in Parallel Out

Truth Table

OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
Logic Diagram: Parallel in Serial Out

Truth Table

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

Logic Diagram
Parallel in Parallel Out

Truth Table

DATA INPUT OUTPUT


CLK
DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

Procedure

(i) Connections are given as per circuit diagram.


(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

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