Difficulty

Level -
Question Statement - mandatory (statement delivered mandator Choice 1 - Choice 2 -
S.No. An output
to the program resides in memory starting from
candidate) y mandatory mandatory
address 2300. It is executed after the computer recognizes
an interrupt when FGO becomes 1 (while IEN=1). What
1 instruction must be placed at address 1?​ Hard BUN 2300 ION 2300
What are the total numbers of memory reference
2 An output program
instructions in basicresides in memory
computer starting from
architecture? Hard 8 7
address 2300. It is executed after the computer recognizes
an interrupt when FGO becomes 1 (while IEN=1) What BUN 2300, ION
3 must be the last two instructions of the output program?​ Hard 2300 ION, BUN 0
When IEN is cleared to zero with ____ instruction, the CPU
6 cannot be interrupted. Hard IOF ION
When IEN is set to 1, with ___ instruction, the computer
7 can be interrupted. Hard IOF ION
In memory reference instructions, what is the value of
9 operation decoder for ADD & AND symbol? Hard D0, D1 D1, D0

Which instruction is being executed below:- AC <- AC /\

16 DR Hard AND ADD

Which instruction has maximum number of Time Cycles,

17 out of given options? Hard ISZ ADD

What is value in AC after execution of AC <- AC /\ DR

19 operation? Initially both AC and DR are 1. Hard 0 1

An instruction at address 002 in the basic computer has I =

0, an operation code of the AND instruction, and an
address part equal to 008 (all numbers are in
hexadecimal). The memory word at address 008 contains
the operand
B8F2 and the content of AC is A937. Determine the value
20 of AC after execution of instruction. Hard A937 B8F2

21 In basic computer architecture, AC typically communicates Medium serial, serial parallel, serial

22 In basic computer architecture, communication interface ty Medium serial, serial parallel, serial

25 SKI will skip the instruction if _____ value is ___. Medium FGI, 1 FGO, 1

26 SKO will skip the instruction if _____ value is ___. Medium FGI, 1 FGO, 1

Which bit pattern in the leftmost 4 bits (15-12) identifies the

29 Input output instructions in basic computer architecture? Hard 1111 1000
_________instruction is used to perform binary operations
on string of bits stored in registers to complement selected
30 bits using ________bit. Medium AND, 0 OR, 1
register to horizontal
register microprogrammin
31 Which of the following is a common design principle inHard operations g
 Which of the following is True regarding CISC architecture? A. Focus on hardware B. Variable sized instructio
38 Medium A and B A and C
In CISC architecture how many instruction/s are required to
41 add two 8 bit numbers. Hard 1 2
RISC, instruction
Following architecture reduces the cycles per instruction at RISC, numbers per
43 the cost of ________. Hard instruction type program
RISC, number CISC, number of
Following architecture reduces the instruction numbers per of cycles per cycles per
44 In RISC architecture,
program at the cost ofif________.
an instruction set contains 50 Hard instruction instruction
instructions, and the average CPI (Cycles Per Instruction)
is 1.5, what is the total number of clock cycles required to
46 execute 1000 instructions? Hard 750 50

The hexadecimal representation of the control word for the

51 microoperation "R1<-R2-R3" in a CPU is ________. Hard 1325 1235

The hexadecimal representation of the control word for the

52 microoperation "R1<-R2+R3" in a CPU is ________. Hard 1223 1322

The hexadecimal representation of the control word for the

53 microoperation "Output <- R2" in a CPU is ________. Hard 1000 1235

The hexadecimal representation of the control word for the

54 microoperation "Output <- Input" in a CPU is ________. Hard 1000 0

The size of OPR and SELD (in bits) in the control word for
55 a CPU is ______ and ______ respectively. Medium 5,3 3,5
Suppose the initial value of SP is 3998 and the stack grows
with decreasing addresses. What is the value of SP after 2
57 Given SP = 00000000 in the 256-word stack, how many
POP operations? Medium 3998 4002
items are there in the stack if FULL = 1 and EMPTY = 0?

58 Given SP = 00000000 in the 256-word stack, how many Hard 256 0

items are there in the stack if FULL = 0 and EMPTY = 1?

59 Hard 256 0

The result of the postfix expression given inside the

62 bracket, (34 * 56 * + ) is ___. Hard 40 90

63 In a stack-organized computer, instructions that typicallyHard ADD MUL

What are the values of C, S, V, and Z when an 8-bit ALU
completes the following subtraction operation: 11110000 -
64 11101100? Hard 1,1,0,0 1,0,1,0
Evaluate the effective address if the addressing mode of
the instruction is Direct, given that the instruction is stored
at location 300, its address field is located at location 301
with a value of 400, and processor register R1 contains the
65 number 200. Hard 400 200
Evaluate the effective address if the addressing mode of
the instruction is Immediate, given that the instruction is
stored at location 300, its address field is located at
location 301 with a value of 400, and processor register R1
66 contains the number 200. Hard 301 200
 Evaluate the effective address if the addressing mode of
the instruction is Relative, given that the instruction is
stored at location 300, its address field is located at
location 301 with a value of 400, and processor register R1
67 contains the number 200. Hard 702 200
What are the values of the status bits C, S, Z, and V after
the instruction "Add immediate operand C6 to register R"
for an 8-bit computer, given that the initial value of register C = 1 ,S = 0, Z
68 In anhexadecimal
R is 8-bit computer
72?with a register R, determine the values Hard = 0, V = 0 C = 1 ,S = 1, Z = 0, V
of the status bits C, S, Z, and V after the instruction
"Subtract immediate operand 9A from R", given that the
69 What are the
initial value ofvalues
registerofRthe status bits C, 72.
is hexadecimal S, Z, and V after Hard C = 1 ,S = 0, Z = 0, C = 0 ,S = 1, Z = 0, V
the instruction "AND immediate operand 8D to register R"
for an 8-bit computer, given that the initial value of register
70 R is hexadecimal 72? Hard C = 1 ,S = 0, Z = 0, C = 0 ,S = 1, Z = 0, V

Data Transfer Instructions move data from one place transfer

71 in computer to another _________the data content. Medium between
with changing transfer between
without changing
memory and processor
Which of the following describes the most common processor registers and
72 data transfer instructions in a computer system? Medium registers input/output
Data
Which instructions within the system performs It designates
Data transfera It designates a
Manipulation
73 decision-making capabilities? Medium transfer from
Instructions transfer from
Instruction
processor input/output
Which of the following accurately describes the use of registers to devices to
74 the load instruction in computer programming? Medium Move
A
memory datafrom
transfer A transfer from
memory
from
memoryoneto place input/output
What does the store instruction typically designate in in computer to
processor Change the path
devices to
75 computer programming? Medium another
registers taken
memory by the
without program when
How do program control instructions serve in changing the executed in
76 enhancing the efficiency of different activities? Hard data content computer
Data
Which category does suitable for LD and ST Data transfer Manipulation
77 isntructions? Medium Instructions Instruction
The instructions transfer data among processor
78 registers and input or output terminals are_____. Hard RORC:
MOV and IN XCH and OUT
An 8-bit register contains the value 0 1 1 1 1 0 1 1 and the 11110111,
carry bit is equal to 1. What are the outputs after RORC ROLC: RORC: 10111100,
79 and ROLC operations ? Medium 10111101 ROLC: 11110110
Which memory addressing concept does the '@' Relative
80 character symbolize in computer programming? Hard address Direct address
The # character precedes the operand in an Immediate
81 An instruction is stored at location 200 with its address field Hard
__________instruction. Address Direct Address
at location 201. The address filed has the value 500. A
processor register R1 contain the number 400. What is the
effective address if the addressing mode of the instruction
82 is auto increment? Hard 400 401
An instruction is stored at location 200 with its address field
at location 201. The address filed has the value 500. A
processor register R1 contain the number 400. What is the
effective address if the addressing mode of the instruction
83 is auto decrement? Hard 499 498

If the output of ALU is not 0, then the zero status bit is set
84 to ___. Medium 0 1
 Assembly language convention of Index addressing
85 is___. Medium LD ADR(X) LD R1
Assembly language convention of Register indirect
86 Mode is___. Medium LD ADR(X) LD R1

87 Register Transfer of Direct address Mode is_____. Medium AC<-M[ADR] AC<-M[M[ADR]]

88 Register Transfer of Indirect address Mode is_____. Medium AC<-M[ADR] AC<-M[M[ADR]]

If the end carry
89 What conditions cause the Bit C (carry) to be set to 0? Hard C8 is 0 If the carry is 0
Identify the addressing mode represented by the Direct Relative
90 register transfer operation: AC<-M[ADR+XR]. Medium Addressing Addressing
Data
Which instruction type is associated with the Data transfer Manipulation
91 mnemonic ADDC? Medium Instructions Instruction
Data
Which instruction type is associated with the Data transfer Manipulation
92 mnemonic MOV and XCH? Hard Instructions Instruction
Logical and bit
Which type of data manipulation is represented by the Arithmetic manipulation
93 instruction with the mnemonic NEG? Medium instructions instructions
Logical and bit
Which type of data manipulation is represented by the Arithmetic manipulation
94 instruction with the mnemonic CLRC? Medium instructions instructions
Logical and bit
What kind of data manipulation does the instruction Arithmetic manipulation
95 mnemonic ROR represent? Medium instructions instructions
Logical and bit
What kind of data manipulation does the instruction Arithmetic manipulation
96 mnemonic RORC represent? Medium instructions instructions
There are ___bit manipulation operations possible in
97 Logical and Bit manipulation instructions. Medium set a bit2or a 3
selected group selectively
The AND instruction of Logical and Bit manipulation of bits of an complement bits
98 instruction is used to ____________. Medium operand of an operand
Which instruction of Logical and Bit manipulation is
used to set a bit or a selected group of bits of an
99 operand. Medium OR AND
Branch and jump instructions of Program control may needs an needs an address
100 be Medium address field
conditional field and
unconditional
and therefore it therefore it is
is zero address one address
101 The skip instruction of Program control___________ Medium instruction Control
It proceeds
skips the
instruction next
It always skips to the instruction
instruction if a
the next specified by the
102 What does a conditional skip instruction do? Medium Control
instruction programmer
condition is metin
proceeds to the an unconditional
What happens if the condition specified in a next instruction branch
103 conditional branch instruction is not met? Medium in sequence instruction
Which instructions of Program control are used in JUMP and CALL and
104 conjunction with subroutines? Medium LOOP RETURN
Which instructions of Program control do not directly
105 change the program sequence? Hard Jump and Skip Move and Load
 It performs
logical AND
between two It performs a
operands and subtraction
updates certain between two
status
It addsbits
two operands, and
What does the compare instruction of Program control without
operands the result is
106 do? Medium retaining
together the retained
result or It updates all bits
Which of the following statements is true about the changing the in the register to
107 test instruction of program control? Medium operands 1
Which symbols represent the four status bits typically
108 found in a processor's status register? Hard C, S, Z, R C, S, Z, V
If the end carry
109 What conditions cause the Bit C (carry) to be set to 1? Hard C8 is 0 If the carry is 0
When does the bit S (sign) get set to 1 within the status If the highest- If the highest-
110 register of a processor? Hard order bit F is 1 order bit F is 0
The Status bit Z (zero) is set to 1 if the output of the ALU
111 contains_______. Hard all 1's at least one 1
Bit V (overflow) is set to 1 if the exclusive-OR of the
112 last two carries is equal to Medium 1 0
The status bits can be checked after an ALU
operation to determine certain relationships that exist
113 between the values of ___________. Medium V and Z A and B

114 Conditional branch instructions are_________. Medium BZ, BC, BP BZ, BM, BV
What does the mnemonic BLOE conditional branch Branch if Lower Branch if Load or
115 instruction stand for? Medium or Equal Equal
Which conditional branch instructions are typically
116 used under unsigned compare conditions (A - B)? Hard BHE and BLO BGT and BGE
Which conditional branch instructions are typically
117 used under signed compare conditions (A - B)? Medium SP
BHE<-and
SP -BLO
1, SP
BGT<-and
SP +BGE
1,
M[SP] <- PC, PC M[SP] <- PC, PC
A subroutine call can be implemented using the <- effective <- effective
118 following micro-operations. Hard address address
The instruction that return from the last subroutine is
implemented by ____________ one of the micro-
119 operation. Hard only with
PC <-M the
[SP-1] only with
PC <-M the
[SP+1]
The state of the CPU at the end of the execute cycle, content of the content of all
particularly when an interrupt is recognized, is program processor
120 primarily determined from: Medium counter registers
What term is used to refer to the collection of all Program Processor Status
121 status bit conditions in the CPU? Medium Counter word word
When the CPU is executing a program that is part of User or kernel Supervisor or
122 the operating system, the mode of CPU is called? Medium mode system mode
In the context of program interrupt handling, CPU
operates in _________ mode while executing user Supervisor
123 programs. Medium mode Kernel mode
from special
The mode that the CPU is operating at any given time status bits in through the
124 is determined ____________________. Medium input-output
the PSW program counter
(l/0) devices a circuit
and a timing monitoring the
125 Where do external interrupts typically originate from? Medium device power supply
I/O device I/O device
Which of the following are examples of external requesting finished transfer
126 interrupts? Medium transfer of data of data
 When an When the CPU
instruction temperature
Under what circumstances a timeout interrupt may encounters a exceeds a certain
127 occur? Medium Restarting the
syntax error threshold
system from Shutting down
the last known the system
128 What action might a power failure interrupt trigger? Medium Input/output
state Illegal or
gracefully
(I/O) devices erroneous use of
requesting an instruction or
129 What typically causes internal interrupts? Medium attention data
Incorrect input Hardware
What is a common cause of error conditions in the provided by the malfunctions
130 context of internal interrupts? Medium user within the CPU
Internal Internal
What characteristic distinguishes internal interrupts interrupts are interrupts are
131 from external interrupts in terms of timing? Medium asynchronous periodic
What term best describes the timing behavior of
132 external interrupts? Medium Synchronous randomly
Periodic
External
throughout the
If the program is rerun, the internal interrupts will External
in the same interrupts
program occur
133 occur _______________. Medium interrupts
place eachare
time randomly
execution
triggered by throughout
What characteristic distinguishes external interrupts errors in the program
134 from internal interrupts? Medium register
program code an invalid
execution
overflow and operation code
Which of the following are examples of interrupts attempt to and stack
135 caused by internal error conditions? Medium divide by zero overflow
Which type of interrupt is commonly utilized with a Hardware External
136 supervisor call instruction? Medium interrupt interrupt
What condition is tested by the Conditional Branch
138 Instruction BNZ? Medium Z=1 Z=0
What condition is tested by the Conditional Branch
139 Instruction BNC? Medium C=0 C=1
In the context of Conditional Branch Instructions,
which branch condition respresents the Test Branch if
140 condition, V=0)? Medium overflow Branch if carry
What is the value of the postfix expression 6 3 2 4 +
162 – *? Medium 1 40
Identify the memory reference instruction having operation
202 decoder D3 and symbolic representation is M[AR]←AC. Medium STA LDA
What is the purpose of the memory reference instruction AND memory Add memory
with operation decoder D3 and symbolic representation word to AC word to AC
203 M[AR]←AC? Medium
AND memory Add memory
What is the purpose of memory reference instruction word to AC word to AC
having operation decoder D2 and symbolic representation
is AC←M[AR]?
206 Medium

Let the PC contains the number 201. The address part of

the instruction contains the number 500. The instruction at
location 201 is read from memory during the fetch phase
and the program counter is then incremented by one to
202. What is the effective address for the relative address
208 mode? Medium 701 702
 The carry bit can be used with rotate instruction to check
whether or not the bit is shifted from the ____ position of a
216 register into the____ position. Medium end, carry carry, end

Sign (S) is set to __, If the highest order bit F7 of 8 bit ALU
227 output (F7-F0) is __. Very Easy 1 & 0 0&1
____ call is called by the user through instructions,
whereas_______ is called by the hardware or any external Interrupt & Subroutine &
240 signal. Hard Subroutine Interrupt

________ interrupts are synchronous with the program Internal & External & power
246 while ______interrupts are asynchronous. Medium power failure failure
If the program is rerun, the _________ will appear in the
same place each time. _______ depend on conditions Interrupts & Subroutine &
247 What assembly
independent instruction
of the programshould
being be used toatimplement
executed the time. a Hard Subroutine Interrupts
conditional branch based on the contents of registers R3
and R4, specifically branching if R3 holds a negative value BLT R3, #0 and BLT R3, #0 and
279 and R4 holds a positive value? Medium BPL R4, #0 BGT R4, #0
Which conditional branch instruction is the most efficient
choice for terminating a loop iteration after the final
280 execution, considering the loop iterates 10 times? Medium BGE R2, #10 BLT R2, #10
 Correct
choice -
mandat
Choice 3 Choice 4 ory

JM 2300 BUN 0 1

6 4 2

ION 0, BUN 0 BUN 0, ION 2

Either IOF or None of the
ION mentioned 1
Either IOF or None of the
ION mentioned 2

D0, D7 D7, D1 2

LDA STA 1

LDA STA 1
None of the
2 mentioned 2

A832 H832 3

serial, parallel parallel, parallel 4

serial, parallel parallel, parallel 1

FGI, 0 FGO, 0 1

FGI, 0 FGO, 0 2
None of the
1001 mentioned 1

XOR, 1 OR, 0 3
vertical
microprogrammi None of the
ng mentioned 1
B and C all of the mention 1

3 5 1
CISC, instruction CISC, instruction
type numbers 2
CISC, instruction CISC, instruction
type numbers 2

1500 3000 3

1125 1135 1

2132 A231 2

1005 1230 1

1235 A231 2

3,3 4,4 1

4000 3996 3

1 255 1

1 255 2
None of the
18 mentioned 4
all of the
DIV mentioned 4

1,1,1,1 1,1,0,1 1

600 301 1

600 400 1
 400 301 1

C = 1 ,S = 0, Z = 1, VC = 1 ,S = 0, Z = 0, V = 1

C = 1 ,S = 0, Z = 1, VC = 1 ,S = 0, Z = 0, V = 2

C = 0 ,S = 0, Z = 1, VC = 1 ,S = 0, Z = 0, V = 3
transfer
with None of the
between the
incrementing mentioned 2
processor
registers all of the
themselves mentioned 4
It designates a
transfer
Programfrom
control It designates
Decision a
making
memory to
Instructions transfer between
instructions 3
processor processor registers
registers, usually A transfer
and input/output
A
antransfer from between
accumulator devices 3
a processor processor registers
register into and input/output
Perform
memory devices 3
arithmetic, logic
and shift all of the
operation. mentioned 2
Program control all of the
Instructions mentioned 1

IN and XCH IN and OUT 4

RORC:
10111101, RORC: 01111011,
ROLC: 11110111 ROLC: 11101111 3

Relative Address Indirect address 4

Indirect Address Relative Address 1

500 501 1

399 398 3
None of the
0 or 1 mentioned 1
LD (R1) LD (R1)+ 1

LD (R1) LD (R1)+ 3

AC<-M[PC+ADR] AC<-NBR 1

AC<-M[PC+ADR] AC<-NBR 2
If the end carry
C8 is 1 If the carry is 1 1
Immediate
Operand Index Addressing 4
Program control None of the
Instructions mentioned 2
Program control None of the
Instructions mentioned 1
all of the
Shift instructions mentioned 1
all of the
Shift instructions mentioned 2
all of the
Shift instructions mentioned 3
None of the
Shift instructions mentioned 3

clear a bit
4 or a 5 2
selected group
of bits of an None of the
operand mentioned 3
all of the
XOR mentioned 1
does not need does not
None need an
of the
an address
Both field address field and
mentioned 3
and therefore it It replacesitthe
therefore is one
It
is executes the
zero address next instruction
address
next instruction
instruction with a NOP (no-
instruction 3
only if a operation) if a
specified The instruction
specified condition
condition is met following
is met the 2
The program conditional branch
terminates instruction is
abruptly skipped 1

PUSH and POP LOAD and STORE 2

Compare and
Test Add and Subtract 3
 It performs a
subtraction
between two
operands, but the
result of the
It multiplies two operation is not
It performs
operands It updates certain
retained 4
logical OR status bits without
between two performing any
operands logical operation 1

C, S, B, V C, P, Z, V 2
If the end carry
C8 is 1 If the carry is 1 3
If the lowest- If the lowest-order
order bit F is 1 bit F is 0 1

all 0's at least one 0 3

None of the
1 and 0 mentioned 1

S and C S and V 2
all of the
BZ, BE, BGE mentioned 4
Branch if Logical
Operator None of the
Executes mentioned 1
None of the
BZ and BC mentioned 1
SP <- SP - 1, None of the
M[SP]
BZ and<-BC SP <- SP + 1, M[SP]
mentioned 2
effective <- effective
address, PC <- address, PC <- PC -
PC + 1 1 1
None of the
only with
PC <-M the
[SP] mentioned 3
content of
certain status all of the
conditions mentioned 4
Program Status
Word Interrupt Vector 3
Kernel or None of the
protected mode mentioned 2

User mode Protected mode 3

by examining by analyzing the
input-output
specific registers interrupt vector 1
(l/0) devices and
any other all of the
external source mentioned 4
elapsed time of
an event or all of the
power failure mentioned 4
When a
program enters
an infinite loop When a system
Transferring
and exceeds the
its clock drifts out of
complete state
time allocation synchronization 3
of the CPU into
nondestructive Triggering a
memory system reboot 3
Timing events
such as clock Power failures or
Premature
ticks system crashes 2
termination of External
Internal
instruction disturbances such
interrupts
execution are as power outages 3
synchronous
with the Internal interrupts
program are random 3
External
interrupts
Asynchronous Sequential 3
depend on only in multi-
external
by external threaded
conditions
events External
programsinterrupts 1
independent of are synchronous
the current with the program
register
program execution 3
overflow and
protection all of the
violation mentioned 4
Software
interrupt Internal interrupt 3

C=0 S=0 2

V=0 C=0 and C=1 1

Branch if no
overflow Branch if no carry 3

74 -18 4

BUN BSA 1
Store content of
AC in memory
None of the
mentioned 3
Load memory Store content of
word to AC AC in memory

201 500 2
 None of the
LSB,MSB mentioned 1
None of the
1&1 mentioned 3
instructions & None of the
operations mentioned 2
timeout and
software Internal & external 4
Internal &
external timeout and power
interrupts failure interrupts 3
BLE R3, #0 and None of the
BPL R4, #0 mentioned 2

BNE R2, #10 BEQ R2, #10 4