Reg 2 Reg

Reg 2 Reg
Introduction: In a reg-to-reg path, both start point and endpoint are

sequential elements; i.e., either an edge-triggered element or a level
sensitive element. Edge-triggered elements are mostly flip-flops,
memories or edge-triggered arcs of sub-partitions of the design.
Flop-to-flop paths: Both start point and endpoint are edge-triggered

(flops). See Setup and hold checks for flop-to-flop paths.
Synthesis: Synthesis transforms the simple RTL design into a gate-

level netlist with all the constraints as specified by the designer. In
simple language, Synthesis is a process that converts the abstract form
of design to a properly implemented chip in terms of logic gates.
Synthesis takes place in multiple steps:
• Converting RTL into simple logic gates.

• Mapping those gates to actual technology-dependent logic gates
available in the technology libraries.
• Optimizing the mapped netlist keeping the constraints set by the
designer intact.
There are various tools which can be used to synthesize a design

provided by various vendors including Synopsys, Cadence and Mentor
Graphics.
Synthesis Flow:
Synthesis is a very important process for the designers as it enables

them to see how the design will actually look like after fabrication. All
parameters including area, timing, power can be reported and checked
by the designer beforehand only. He/she can make the necessary
changes (if required) before the actual fabrication process, thus saving
both time and cost.
Synthesis in VLSI is the process of converting your code (program)

into a circuit. In terms of logic gates, synthesis is the process of
translating an abstract design into a properly implemented chip.
Synthesis Inputs:
• Register Transfer Level (RTL)

• Technology Library (.LIB)
• Standard/Synopsys Design Constraint (SDC)
Register Transfer Level (RTL): In digital circuit design, register-

transfer level (RTL) is a design abstraction which models a
synchronous digital circuit in terms of the flow of digital signals (data)
between hardware registers, and the logical operations performed on
those signals.
Technology Library (.lib): Technology libraries are distributed

and maintained by semiconductor vendors (i.e., fabrication houses).
Ø Logic cells of varied number of inputs.
Ø Inverters and buffers with equal rise and fall delay.
Ø special cells: clock gating, Isolation, AOB etc.
Synopsys Design Constraints: SDC is a format used to specify

the design intent, including the timing, power and area constraints for
a design. SDC is tcl based. Tool used this format: - DC (Design
compiler, ICC (IC compiler), Prime Time (PT).
SDC is a widely used format that allows designers to utilize the same
sets of constraints to drive synthesis, timing analysis, and place-and-
route.
.log file: A log file in VLSI refers to the report or the output file
generated after the compilation and the simulation of the design.
The log file is very useful for Debugging any RTL file and also
any Testbench related failure as it provides the requisite information
for the failures.
Commands used in Reg2Reg:

Set link_library: Link libraries contain the descriptions of library
cells and sub designs in a mapped netlist and can also contain design
files
Setlink_library “ * < .lib path >”
Set target_library: Target libraries contain the cells used to

generate the netlist and definitions for the design’s operating
conditions.
Set target_library “ < .lib path >”
Analyze: Analyzes the specified HDL source files and stores the
resulting templates into the specified library in a format ready to
specialize and elaborate to form linkable cells of a full design.
SYNTAX
Analyze
[ -format Verilog
[-autoread
[ -recursive
Elaborate: It builds a design from the intermediate format of a
Verilog module, a VHDL entity and architecture, or a VHDL
Configuration.
SYNTAX
elaborate <design_name>
Start_gui: It starts the application of the GUI.

SYNTAX
String start_gui
Compile: It performs logic-level and gate-level synthesis and

optimization on the current design.
SYNTAX
Compile
[-no_map]
[-gate_clock]
Create_clock: Creates a clock object and defines its waveforms in
the current design.
SYNTAX
create_clock
[-name clock_name
[-period period_value
get_ports: creates a collection of ports from the current design that

match the specified criteria.
set_input_delay: sets input delay on pins or inputs ports relative to
a clock signal.
set_output_delay: sets output delay on pins or output ports relative

to a clock signal.
all_inputs: Collection of input or input ports in a current design.

all_outputs: Collection of output or inout ports in a current design.
check_timing: This command checks the timing attributes placed on
the current design and issues warning messages as needed. The warning
messages provide information that identifies and corrects potential
errors. The warning messages do not necessarily indicate design
problems.
Report_timing: The report timing command provides a report of

timing information for the current design. By default, the report_timing
command reports the single worst setup path in each clock group.
The slack value shown at the end of the report is the data required time
minus the data arrival time.
This represents the amount of time by which the timing constraint is
Met.

Reg 2 Reg

Uploaded by

Copyright:

Available Formats

Reg 2 Reg

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Reg 2 Reg

Uploaded by

Copyright:

Available Formats

Reg 2 Reg

Introduction: In a reg-to-reg path, both start point and endpoint are

Flop-to-flop paths: Both start point and endpoint are edge-triggered

Synthesis: Synthesis transforms the simple RTL design into a gate-

Synthesis takes place in multiple steps:

• Converting RTL into simple logic gates.

There are various tools which can be used to synthesize a design

Synthesis is a very important process for the designers as it enables

Synthesis in VLSI is the process of converting your code (program)

• Register Transfer Level (RTL)

Register Transfer Level (RTL): In digital circuit design, register-

Technology Library (.lib): Technology libraries are distributed

Synopsys Design Constraints: SDC is a format used to specify

Commands used in Reg2Reg:

Set target_library: Target libraries contain the cells used to

Start_gui: It starts the application of the GUI.

Compile: It performs logic-level and gate-level synthesis and

get_ports: creates a collection of ports from the current design that

set_output_delay: sets output delay on pins or output ports relative

all_inputs: Collection of input or input ports in a current design.

Report_timing: The report timing command provides a report of

You might also like