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Lecture 30

This document discusses strategies for reducing power dissipation in VLSI circuits, including dynamic voltage frequency scaling, power gating, clock gating, and resizing. It explains how these techniques can reduce supply voltage, clock frequency, signal activity, and load capacitance to lower power consumption.

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19 views10 pages

Lecture 30

This document discusses strategies for reducing power dissipation in VLSI circuits, including dynamic voltage frequency scaling, power gating, clock gating, and resizing. It explains how these techniques can reduce supply voltage, clock frequency, signal activity, and load capacitance to lower power consumption.

Uploaded by

inboxherozero
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI DESIGN FLOW: RTL TO

GDS

Lecture 30
Power Optimizations
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan

Overview of power-driven optimizations

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Strategies for Reducing Power Dissipation
2
𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘 Power saving strategies:
where, ▪ Reduce supply voltage
▪ 𝑉𝐷𝐷 = supply voltage ▪ Reduce clock frequency
▪ 𝐶𝐿 = load capacitance ▪ Reduce activity of the signal
▪ 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit ▪ Reduce load capacitance
▪ 𝛼 = activity of the signal

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Dynamic Voltage Frequency Scaling (DVFS)
▪ Utilizes the strategy of reducing supply voltage and clock frequency

▪ Popular technique employed in processors:


➢ Exploit variations in workload to save energy
➢ Full speed of a processor is utilized by only a few tasks or for a small time duration.
➢ For the remaining period, the deadlines can be met at low speed and consuming
significantly less energy

Illustration:
▪ Consider a processor that can perform a task in 10 ms at 1.2 GHz and 1.2 V.
▪ Let us reduce the clock frequency and the supply voltage to half (600 MHz, 0.6 V),
➢ Task will now complete in double the original time, i.e., 20 ms.
➢ Will reduce the switching power dissipation by 1/8 (𝑃𝑡𝑜𝑡 ∝ 𝑉𝐷𝐷2
𝑓𝑐𝑙𝑘 )
➢ Will reduce the energy consumption by 1/4

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Power Gating

▪ Utilizes the strategy of eliminating supply voltage

Power Gating:
▪ Switch off the power supply for a block
▪ Effective technique to tackle both static and dynamic components of power dissipation.
▪ Requires a careful circuit design and inserting specially designed circuit elements.

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Power Gating: Circuit Elements

Circuit Elements
▪ Switch Cell
▪ Retention Cell
▪ Isolation Cell

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Clock Gating
▪ Utilizes the strategy of reducing activity

Assume that there is a set of 𝑁 flip-flops that


captures new data conditionally
▪ Shut off the clock when that condition is
false
▪ Save power in charging/discharging
capacitors in the clock network, including
flip-flops
▪ Find enabling condition of clocking

▪ Simple AND of EN and CLK will lead to glitch

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Clock Gating: Integrated Clock Gater
Integrated Clock Gater (ICG)

▪ Logic gate with an enable


signal so that clock is
propagated when the 𝐸𝑁 = 1

▪ Latch (negative sensitive)


allows EN to propagate only
when CLK is low

▪ When CLK is high, Latch (LT)


output is stable and glitch
cannot propagate

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


Resizing
▪ Resize cells to reduce power dissipation
➢ For example, we can use smaller cells in the noncritical path of a circuit
➢ Reduce the power dissipation due to the reduced load capacitances

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.

soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

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