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Problem Set-1

This document contains practice problems related to CMOS digital design. It includes problems about plotting ID vs VGS curves for NMOS transistors, determining technology parameters from simulations, analyzing transistor behavior for different widths, plotting output voltages for circuits with NMOS and PMOS switches, and calculating propagation delays for an inverter circuit with varying capacitive loads and transistor widths.

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Girija M Hegde
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29 views2 pages

Problem Set-1

This document contains practice problems related to CMOS digital design. It includes problems about plotting ID vs VGS curves for NMOS transistors, determining technology parameters from simulations, analyzing transistor behavior for different widths, plotting output voltages for circuits with NMOS and PMOS switches, and calculating propagation delays for an inverter circuit with varying capacitive loads and transistor widths.

Uploaded by

Girija M Hegde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CMOS Digital Design

Practice Problems
Tutorial Sessions on 17th and 24th May
TAs: Adithya Sunil Edakkadan and Ishan Acharyya
Instructor: Prof. Abhishek Srivastava

1.8µ
1. Plot ID vs VGS for 0.18µ
NMOS transistor and estimate its VT from the graph for the following
cases :

(a) VDS = 50 mV and VGS is swept from 0 to 1.8 V in a step of 0.1 V


(b) VDS = 1.8 V and VGS is swept from 0 to 1.8 V in a step of 0.1 V
(c) Do you observe any difference in VT values in case (a) and (b) ? If yes, explain why.

2. From the simple MOS models discussed in class, find out the technology parameter µCox and
VT for NMOS and PMOS devices with the help of simulations for i) Body to source voltage
(VBS ) of 0V , ii) VBS = 900mV and ii) VBS = −900mV . Do you observe any difference in VT
for the three cases? Explain.

3. Plot ID − VDS for the two cases shown in figures 1(a) and (b). Explain why a W/2L transistor
does not behave in exactly the same way as a series combination of two W/L transistors for
small values of L.

+ V ID + V ID
− DS2 − DS
M2 W/L
= 1.8u/0.18u M1
W/2L
M3 = 1.8u/0.36u
+ VGS2 + VGS
− = 1.8V W/L − = 1.8V
= 1.8u/0.18u
(a) (b)

Figure 1

4. Consider the circuits shown in figures 2(a) and (b). Find the peak ION and average IOF F for
W= 1.8µm, W= 3.6µm, W= 18µm, W= 36µm. (Give plot snapshots and a table of ION and
IOF F for different W.) Do ION and IOF F scale linearly with respect to W, comment.

Figure 2
Figure 3

5. Consider the schematic shown in figure 3. Switch ‘SW’ is closed at time t=0.
1.8µ
(a) Replace the switch ‘SW’ by an NMOS (W/L = 0.18µ ) and plot v(out), when i) vc (0− ) = 0V
and v(in) = 1.8V, ii) vc (0− ) = 1.8V and v(in) = 0V. Do you get exact same voltage at
output as at input in steady state for both the cases. Comment for both the cases with
reasons for difference (if any).
1.8µ
(b) Replace the switch ‘SW’ by an PMOS (W/L = 0.18µ ) and plot v(out), when i) vc (0− ) = 0V
and v(in) = 1.8V, ii) vc (0− ) = 1.8V and v(in) = 0V. Do you get exact same voltage at
output as at input in steady state for both the cases. Comment for both the cases with
reasons for difference (if any).

(Hint : use .ic v(node-name)=value to set initial condition at a node before .control in your
netlist)

6. Write a netlist for the circuit shown in figure 4. Remember to specify the AS, AD and PS, PD
parameters for the transistors. Plot Vout with respect to time and calculate the propagation delay

Figure 4

between input and output (tpd ) and tabulate them for the following cases:
Given: Vin (vin a 0 pulse 0 1.8 0ns 100ps 100ps 9.9ns 20ns)

(a) CL =100 fF, Wn = 1.8µm Wp = 2.5 × Wn


(b) CL =500 fF Wn = 1.8µm Wp = 2.5 × Wn
(c) CL =500 fF Wn = 9µm Wp = 2.5 × Wn .
(d) From the delay table, comment how the scaling up of transistor widths affects the propa-
gation delays.

Note: Delay = (rise-time + fall-time)/2, where rise-time is defined as the delay between rising
output and corresponding falling input when both are at their 50% values. Similarly fall-time
is defined as the delay between falling output and corresponding rising input when both are at
their 50% values.

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