Module 2

Introduction to the ARM Instruction

Set

CHAITHRA.S/AP,CSE/SVCE 1
Topics

Ø Data Processing Instructions

Ø Programme Instructions

Ø Software Interrupt Instructions

Ø Program Status Register Instructions

Ø Coprocessor Instructions

Ø Loading Constants

CHAITHRA.S/AP,CSE/SVCE 2
 Introduction

§ Processor operations is illustrated using examples with pre- and post-

conditions, describing registers and memory before and after the
instruction or instructions are executed.

§ The examples follow this format:

PRE

POST

CHAITHRA.S/AP,CSE/SVCE 3
§ In the pre- and post-conditions, memory is denoted as

– mem

This refers to bits of memory starting at the given byte

§ For example,

mem32 is the 32-bit value starting at address 1 KB.

CHAITHRA.S/AP,CSE/SVCE 4
§ ARM instructions process data held in registers and only access
memory with load and store instructions.

§ ARM instructions commonly take two or three operands.

§ For instance the ADD instruction below adds the two values stored in
registers r1 and r2 (the source registers).

§ It writes the result to register r3 (the destination register).

Instruction Destination Source Source

Syntax register (Rd) register 1 (Rn) register 2 (Rm)

ADD r3, r1, r2 r3 r1 r2

CHAITHRA.S/AP,CSE/SVCE 5
 3.1 DATA PROCESSING INSTRUCTIONS

§ Manipulates data within registers

- move instructions

- arithmetic instructions

- logical instructions

- comparison instructions

- multiply instructions

§ Most data processing instructions can process one of their operands

using the barrel shifter.

CHAITHRA.S/AP,CSE/SVCE 6
§ If you use the S suffix on a data processing instruction, then it updates
the flags in the cpsr.

§ Move and logical operations update the carry flag C, negative flag N,
and zero flag Z.

§ The carry flag is set from the result of the barrel shift as the last bit
shifted out.

§ The N flag is set to bit 31 of the result.

§ The Z flag is set if the result is zero.

CHAITHRA.S/AP,CSE/SVCE 7
3.1.1 MOVE INSTRUCTIONS

§ Simplest ARM instruction

§ Copies N into a destination register Rd, where

N is a register or immediate value

§ Useful for setting initial values and transferring data between registers

§ Syntax:

<instruction> {<cond>} {S} Rd, N

MOV Move a 32-bit value into a register Rd = N

Move the NOT of the 32-bit value into a

MVN Rd = ∼ N
Register
CHAITHRA.S/AP,CSE/SVCE 8
§ E XAMPLE : The MOV instruction takes the contents of register r5 and
copies them into register r7, in this case, taking the value 5, and
overwriting the value 8 in register r7.

PRE r5 = 5
r7 = 8
MOV r7, r5 ; let r7 = r5
POST r5 = 5
r7 = 5

CHAITHRA.S/AP,CSE/SVCE 9
BARREL SHIFTER

§ In the MOV instruction N can be more than just a register or immediate

value

§ It can also be a register Rm that has been preprocessed by the barrel

shifter prior to being used by a data processing instruction.

§ Data processing instructions are processed within the arithmetic logic

unit (ALU).

§ A unique and powerful feature of the ARM processor is the ability to

shift the 32-bit binary pattern in one of the source registers left or right
by a specific number of positions before it enters the ALU.

§ This shift increases the power and flexibility of many data processing
operations. CHAITHRA.S/AP,CSE/SVCE 10
§ There are data processing instructions that do not use the barrel shift,

§ for example

- MUL (multiply)

- CLZ (count leading zeros)

- QADD (signed saturated 32-bit add) instructions.

§ Pre-processing or shift occurs within the cycle time of the instruction.

§ This is particularly useful for loading constants into a register and

achieving fast multiplies or division by a power of 2

CHAITHRA.S/AP,CSE/SVCE 11
§ Fig shows the data flow between the ALU
and the barrel shifter.
§ a d d a s h i f t o p e ra t i o n t o t h e m o v e
instruction
§ Register Rn enters the ALU without any
pre- processing of registers
§ We apply a logical shift left (LSL) to
register Rm before moving it to the
destination register Figure : Barrel shifter and ALU.
§ The MOV instruction copies the shift
operator result N into register Rd.
§ N re p re s e n t s t h e r e s u l t o f t h e L S L
operation
CHAITHRA.S/AP,CSE/SVCE 12
PRE r5=5

r7=8

MOV r7, r5, LSL #2 ; let r7 = r5*4 = (r5 << 2)

POST r5=5

r7 = 20

CHAITHRA.S/AP,CSE/SVCE 13
§ The five different shift operations that you can use within the barrel
shifter are summarized in Table below

CHAITHRA.S/AP,CSE/SVCE 14
§ Figure below illustrates a logical shift left by one.

• The contents of bit 0 are shifted to bit 1.

• Bit 0 is cleared.
• The C flag is updated with the last bit shifted out of the register.
• This is bit (32 y) of the original value, where y is the shift amount. When y is
greater than one, then a shift by y positions is the same as a shift by one
position executed y times.
CHAITHRA.S/AP,CSE/SVCE 15
CHAITHRA.S/AP,CSE/SVCE 16
CHAITHRA.S/AP,CSE/SVCE 17
ARITHMETIC INSTRUCTIONS
§ implement addition and subtraction of 32-bit signed and unsigned
values.
§ Syntax:
<instruction>{<cond>}{S} Rd, Rn, N

ADC add two 32-bit values and carry Rd = Rn + N + carry

ADD add two 32-bit values Rd = Rn + N
RSB reverse subtract of two 32-bit Rd = N − Rn
values
RSC reverse subtract with carry of two Rd = N − Rn − !(carry flag)
32-bit values
subtract with carry of two 32-bit
SBC Rd = Rn − N − !(carry flag)
values
SUB subtract two 32-bit values Rd = Rn − N
CHAITHRA.S/AP,CSE/SVCE 18
CHAITHRA.S/AP,CSE/SVCE 19
CHAITHRA.S/AP,CSE/SVCE 20
USING THE BARREL SHIFTER WITH ARITHMETIC INSTRUCTIONS

CHAITHRA.S/AP,CSE/SVCE 21
LOGICAL INSTRUCTIONS

§ performs bitwise logical operations on the two source registers.

§ Syntax:

<instruction>{<cond>}{S} Rd, Rn, N

CHAITHRA.S/AP,CSE/SVCE 22
CHAITHRA.S/AP,CSE/SVCE 23
§ BIC instruction is particularly useful when clearing status bits and is
frequently used to change interrupt masks in the cpsr.

§ The logical instructions update the cpsr flags only if the S suffix is
present.

§ These instructions can use barrel-shifted second operands in the

same way as the arithmetic instructions.

CHAITHRA.S/AP,CSE/SVCE 24
COMPARISON INSTRUCTIONS

§ used to compare or test a register with a 32-bit value

§ update the cpsr flag bits according to the result, but do not affect other
registers

§ After the bits have been set, the information can then be used to

change program flow by using conditional execution.

§ Syntax:

<instruction> {<cond>} Rn, N

CHAITHRA.S/AP,CSE/SVCE 25
 CMN compare negated flags set as a result of Rn + N
CMP compare flags set as a result of Rn − N
TEQ flags set as a result of Rn ∧ N
test for equality of two 32-
bit values
TST test bits of a 32-bit value flags set as a result of Rn & N

§ N is the result of the shifter operation

CHAITHRA.S/AP,CSE/SVCE 26
CHAITHRA.S/AP,CSE/SVCE 27
MULTIPLY INSTRUCTIONS
§ multiply the contents of a pair of registers and, depending upon the
instruction, accumulate the results in with another register

§ The long multiplies accumulate onto a pair of registers representing a

64-bit value

§ The final result is placed in a destination register or a pair of registers.

§ Syntax:

MLA{<cond>}{S} Rd, Rm, Rs, Rn

MUL{<cond>}{S} Rd, Rm, Rs

MLA multiply and accumulate Rd = (Rm∗ Rs) + Rn

MUL multiply Rd = Rm∗ Rs

CHAITHRA.S/AP,CSE/SVCE 28
 § Syntax: <instruction>{<cond>}{S} RdLo, RdHi, Rm, Rs

SMLAL signed multiply [RdHi, RdLo]= [RdHi, RdLo]+ (Rm

accumulate long ∗ Rs)

SMULL signed multiply long [RdHi, RdLo]= Rm ∗ Rs

unsigned multiply
UMLAL accumulate long [RdHi, RdLo]= [RdHi, RdLo]+ (Rm
∗ Rs)

UMULL unsigned multiply long [RdHi, RdLo]= Rm ∗ Rs

§ The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL)
produce a 64-bit result.
§ The result is too large to fit a single 32-bit register so the result is placed
in two registers labeled RdLo and RdHi.
§ RdLo holds the lower 32 bits of the 64-bit result, and RdHi holds the
higher 32 bits of the 64-bit result.
CHAITHRA.S/AP,CSE/SVCE 29
CHAITHRA.S/AP,CSE/SVCE 30
3.2 BRANCH INSTRUCTIONS

§ Changes the or is used to

§ Allows programs to have , if-then-else structures, and loops

§ The change of e

§ Syntax:

B{<cond>}

BL{<cond>}

BX{<cond>}

BLX{<cond>}

CHAITHRA.S/AP,CSE/SVCE 31
 B Branch pc = label
BL branch with link pc = label
lr = address of the next instruction after the BL
BX branch exchange pc = Rm & 0xfffffffe, T = Rm & 1
pc = label, T =1
BLX branch exchange pc = Rm & 0xfffffffe, T = Rm & 1
with link lr = address of the next instruction after the BLX

§ The BX instruction uses an absolute address stored in register Rm.

- primarily used to branch to and from Thumb code
- T bit in the cpsr is updated by the least significant bit of the branch
register.
§ The BLX instruction updates the T bit of the cpsr with the least significant
bit and additionally sets the link register with the return address.

CHAITHRA.S/AP,CSE/SVCE 32
CHAITHRA.S/AP,CSE/SVCE 33
3.3 LOAD-STORE INSTRUCTIONS

§ Transfer data between memory and processor registers

§ There are three types of load-store instructions:

i. Single-Register transfer

ii. Multiple-Register transfer

iii. Swap

CHAITHRA.S/AP,CSE/SVCE 34
3.3.1 SINGLE-REGISTER TRANSFER

§ Used for moving a single data item in and out of a register

§ The datatypes supported are signed and unsigned words (32-bit),

halfwords (16-bit), and bytes.

§ Syntax:

<LDR|STR>{<cond>}{B} Rd,addressing1

LDR{<cond>}SB|H|SH Rd, addressing2

STR{<cond>}H Rd, addressing2

CHAITHRA.S/AP,CSE/SVCE 35
LDR load word into a register Rd <- mem32[address]
STR save byte or word from a register Rd -> mem32[address]
LDRB load byte into a register Rd <- mem8[address]
STRB save byte from a register Rd -> mem8[address]

LDRH load halfword into a register Rd <- mem16[address]

STRH save halfword into a register Rd -> mem16[address]
LDRSB load signed byte into a register Rd <- signExtend(mem8[address])

LDRSH load signed halfword into a Rd <- SignExtend (mem16[address])

register

CHAITHRA.S/AP,CSE/SVCE 36
§ The first instruction loads a word from the address stored in register r1
and places it into register r0.
§ The second instruction goes the other way by storing the contents of
register r0 to the address contained in register r1.
§ The offset from register r1 is zero. Register r1 is called the base address
register. CHAITHRA.S/AP,CSE/SVCE 37
3.3.2 SINGLE-REGISTER LOAD-STORE ADDRESSING MODES

§ The ARM instruction set provides different modes for addressing

memory.
§ These modes incorporate one of the indexing methods:
1. preindex with writeback
2. preindex,
3. postindex

CHAITHRA.S/AP,CSE/SVCE 38
CHAITHRA.S/AP,CSE/SVCE 39
CHAITHRA.S/AP,CSE/SVCE 40
§ The addressing modes available with a particular load or store instruction
depend on the instruction class.
§ A signed offset or register is denoted by “+ /- ”, identifying that it is either a
positive or negative offset from the base address register Rn.
§ The base address register is a pointer to a byte in memory, and the offset
specifies a number of bytes.

§ Immediate means the address is calculated using the base address

register and a 12-bit offset encoded in the instruction.
§ Register means the address is calculated using the base address register
and a specific register’s contents.
§ Scaled means the address is calculated using the base address register
and a barrel shift operation.

CHAITHRA.S/AP,CSE/SVCE 41
CHAITHRA.S/AP,CSE/SVCE 42
CHAITHRA.S/AP,CSE/SVCE 43
3.3..3 MULTIPLE-REGISTER TRANSFER

§ Transfer multiple registers between memory and the processor in a

single instruction.

§ The transfer occurs from a

.

§ Multiple-register transfer instructions are more efficient from single-

register transfers for moving blocks of data around memory and saving
and restoring context and stacks.
§ Syntax:
<LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{ˆ}

CHAITHRA.S/AP,CSE/SVCE 44
 load multiple {Rd}∗ N <- mem32[start address + 4∗ N]
LDM registers optional Rn updated
save multiple {Rd}∗ N -> mem32[start address + 4∗ N]
STM registers optional Rn updated

§ The base register Rn determines the source or destination address for a

load- store multiple instruction.

CHAITHRA.S/AP,CSE/SVCE 45
CHAITHRA.S/AP,CSE/SVCE 46
§ The base register r0 points to memory address 0x80010 in the PRE
condition.
§ Memory addresses 0x80010, 0x80014, and 0x80018 contain the values 1,
2, and 3 respectively.

CHAITHRA.S/AP,CSE/SVCE 47
§ After the load multiple instruction executes registers r1, r2, and r3
contain these values as shown in Figure below.

§ The base register r0 now points to memory address 0x8001c after the
last loaded word.
CHAITHRA.S/AP,CSE/SVCE 48
§ Replace the LDMIA instruction with a load multiple and increment before
LDMIB instruction and use the same PRE conditions.

§ The first word pointed to by register r0 is ignored and register r1 is

loaded from the next memory location as shown in Figure below

§ After execution, register r0 now points to the last loaded memory

location.
§ This is in contrast with the LDMIA example, which pointed to the next
memory location. CHAITHRA.S/AP,CSE/SVCE 49
§ The decrement versions DA and DB of the load-store multiple
instructions decrement the start address and then store to
ascending memory locations.
§ This is equivalent to descending memory but accessing the register
list in reverse order.
§ With the increment and decrement load multiples, you can access
arrays forwards or backwards.
§ They also allow for stack push and pull operations

CHAITHRA.S/AP,CSE/SVCE 50
CHAITHRA.S/AP,CSE/SVCE 51
CHAITHRA.S/AP,CSE/SVCE 52
§ This routine relies on registers r9, r10, and r11 being set up before the
code is executed. Registers r9 and r11 determine the data to be copied,
and register r10 points to the destination in memory for the data.
§ LDMIA loads the data pointed to by register r9 into registers r0 to r7. It
also updates r9 to point to the next block of data to be copied.
§ STMIA copies the contents of registers r0 to r7 to the destination memory
address pointed to by register r10. It also updates r10 to point to the next
destination location.
§ CMP and BNE compare pointers r9 and r11 to check whether the end of
the block copy has been reached.
§ If the block copy is complete, then the routine finishes; otherwise the
loop repeats with the updated values of register r9 and r10.
§ The BNE is the branch instruction B with a condition mnemonic NE (not
equal).
§ If the previous compare instruction sets the condition flags to not equal,
the branch instruction is executed.

CHAITHRA.S/AP,CSE/SVCE 53
§ Figure 3.6 shows the memory map of the block memory copy and how
the routine moves through memory.

CHAITHRA.S/AP,CSE/SVCE 54
Stack Operations

§ The ARM architecture uses the load-store multiple instructions to carry

out stack operations.

§ The pop operation (removing data from a stack) uses a load multiple
instruction; similarly, the push operation (placing data onto the stack)
uses a store multiple instruction.

§ When using a stack you have to decide whether the stack will grow up or
down in memory.

§ A stack is either ascending (A) or descending (D).

§ Ascending stacks grow towards higher memory addresses; in contrast,

descending stacks grow towards lower memory addresses.

CHAITHRA.S/AP,CSE/SVCE 55
§ When you use a full stack (F), the stack pointer sp points to an address
that is the last used or full location (i.e., sp points to the last item on the
stack).

§ In contrast, if you use an empty stack (E) the sp points to an address that
is the first unused or empty location (i.e., it points after the last item on
the stack).

§ ARM has specified an ARM-Thumb Procedure Call Standard (ATPCS) that

defines how routines are called and how registers are allocated.

§ In the ATPCS, stacks are defined as being full descending stacks.

§ Thus, the LDMFD and STMFD instructions provide the pop and push
functions, respectively.

CHAITHRA.S/AP,CSE/SVCE 56
CHAITHRA.S/AP,CSE/SVCE 57
CHAITHRA.S/AP,CSE/SVCE 58
§ When handling a checked stack there are three attributes that need to be
preserved: the stack base, the stack pointer, and the stack limit.

§ The stack base is the starting address of the stack in memory.

§ The stack pointer initially points to the stack base; as data is pushed onto the stack,
the stack pointer descends memory and continuously points to the top of stack.

§ If the stack pointer passes the stack limit, then a stack overflow error has occurred.

§ Here is a small piece of code that checks for stack overflow errors for a descending
stack:

; check for stack overflow

SUB sp, sp, #size

CMP sp, r10

BLLO _stack_overflow ; condition

CHAITHRA.S/AP,CSE/SVCE 59
§ ATPCS defines register r10 as the stack limit or sl.

§ This is optional since it is only used when stack checking is enabled.

§ The BLLO instruction is a branch with link instruction plus the condition
mnemonic LO.

§ If sp is less than register r10 after the new items are pushed onto the
stack, then stack overflow error has occurred.

§ If the stack pointer goes back past the stack base, then a stack underflow
error has occurred.

CHAITHRA.S/AP,CSE/SVCE 60
3.3.4 SWAP INSTRUCTION

§ The swap instruction is a special case of a load-store instruction.

§ It swaps the contents of memory with the contents of a register.

§ This instruction is an atomic operation—it reads and writes a location in

the same bus operation, preventing any other instruction from reading
or writing to that location until it completes.

§ Syntax:

SWP{B}{<cond>} Rd,Rm,[Rn]

CHAITHRA.S/AP,CSE/SVCE 61
 SWP swap a word between memory tmp = mem32[Rn]
and a register mem32[Rn] = Rm
Rd = tmp
SWPB swap a byte between memory tmp = mem8[Rn]
and a register mem8[Rn] = Rm
Rd = tmp

§ Swap cannot be interrupted by any other instruction or any other bus

access.
§ We say the system “holds the bus” until the transaction is complete.

CHAITHRA.S/AP,CSE/SVCE 62
§ This instruction is particularly useful when implementing semaphores
and mutual exclusion in an operating system.

CHAITHRA.S/AP,CSE/SVCE 63
§ The address pointed to by the semaphore either contains the value 0
or 1.
§ When the semaphore equals 1, then the service in question is being
used by another process.
§ The routine will continue to loop around until the service is released by
the other process—in other words, when the semaphore address
location contains the value 0.
CHAITHRA.S/AP,CSE/SVCE 64
3.4 SofTWARE INTERRUPT INSTRUCTION

§ A software interrupt instruction (SWI) causes a software interrupt

exception, which provides a mechanism for applications to call
operating system routines.

§ Syntax:

SWI software lr_svc = address of instruction following the SWI

interrupt spsr_svc = cpsr
pc = vectors + 0x8
cpsr mode = SVC
cpsr I = 1 (mask IRQ interrupts)

CHAITHRA.S/AP,CSE/SVCE 65
§ When the processor executes an SWI instruction, it
.

§ The instruction also

.

§ Each SWI instruction has an associated SWI number, which is used to

represent a particular function call or feature.

CHAITHRA.S/AP,CSE/SVCE 66
§ SWI instructions are used to call operating system routines, you need
some form of parameter passing.
§ This is achieved using registers. In this example, register r0 is used to pass
the parameter 0x12.
§ The return values are also passed back via registers.
CHAITHRA.S/AP,CSE/SVCE 67
§ Code called the SWI handler is required to process the SWI call. The
handler obtains the SWI number using the address of the executed
instruction, which is calculated from the link register lr.

§ The SWI number is determined by

§ Here the SWI instruction is the actual 32-bit SWI instruction executed
by the processor.

CHAITHRA.S/AP,CSE/SVCE 68
CHAITHRA.S/AP,CSE/SVCE 69
3.5 PROGRAM STATUS REGISTER INSTRUCTIONS

§ The ARM instruction set provides two instructions to directly control a

program status register (psr).

§ The MRS instruction transfers the contents of either the cpsr or spsr
into a register; in the reverse direction, the MSR instruction transfers
the contents of a register into the cpsr or spsr.

§ Together these instructions are used to read and write the cpsr and
spsr.
§ Syntax:
MRS{<cond>} Rd,<cpsr|spsr>
MSR{<cond>} <cpsr|spsr>_<fields>,Rm
MSR{<cond>} <cpsr|spsr>_<fields>,#immediate
CHAITHRA.S/AP,CSE/SVCE 70
§ In the syntax you can see a label called fields.

§ This can be any combination of control (c), extension (x), status (s), and
flags (f ). These fields relate to particular byte regions in a psr, as shown
in Figure 3.9.

CHAITHRA.S/AP,CSE/SVCE 71
 MRS copy program status register to a Rd = psr
general-purpose register

MSR move a general-purpose register to a psr[field] = Rm

program status register

MSR move an immediate value to a psr[field] = immediate

program status register

§ The c field controls the interrupt masks, Thumb state, and processor
mode.
§ Example 3.26 shows how to enable IRQ interrupts by clearing the I mask.
This operation involves using both the MRS and MSR instructions to
read from and then write to the cpsr.
CHAITHRA.S/AP,CSE/SVCE 72
CHAITHRA.S/AP,CSE/SVCE 73
3.5.1 COPROCESSOR INSTRUCTIONS

§ Coprocessor instructions are used to extend the instruction set.

§ A coprocessor can either provide additional computation capability or be

used to control the memory subsystem including caches and memory
management.

§ The coprocessor instructions include data processing, register transfer,

and memory transfer instructions
§ Syntax:
CDP{<cond>} cp, opcode1, Cd, Cn {, opcode2}

<MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm {, opcode2}

<LDC|STC>{<cond>} cp, Cd, addressing

CHAITHRA.S/AP,CSE/SVCE 74
 CDP coprocessor data processing—perform an operation
in a coprocessor
MRC MCR coprocessor register transfer—move data to/from
coprocessor registers
LDC STC coprocessor memory transfer—load and store blocks
of memory to/from a coprocessor
§ In the syntax of the coprocessor instructions, the field represents the
coprocessor number between and .
§ The opcode fields describe the operation to take place on the
coprocessor.
§ The Cn, Cm, and Cd fields describe .
§ The coprocessor operations and registers depend on the specific
coprocessor you are using.

.
CHAITHRA.S/AP,CSE/SVCE 75
CHAITHRA.S/AP,CSE/SVCE 76
3.6 LOADING CONSTANTS

§ there is no ARM instruction to move a 32-bit constant into a register.

§ Since ARM instructions are 32 bits in size, they obviously cannot specify
a general 32-bit constant.

§ To aid programming there are two pseudoinstructions to move a 32-bit

value into a register.

§ Syntax:

Rd, =constant

Rd, label

CHAITHRA.S/AP,CSE/SVCE 77
 LDR load constant pseudoinstruction Rd = 32-bit constant

ADR load address pseudoinstruction Rd = 32-bit relative address

§ It defaults to
.

CHAITHRA.S/AP,CSE/SVCE 78
CHAITHRA.S/AP,CSE/SVCE 79
§ The first conversion produces a simple MOV instruction; the second
conversion produces a pc-relative load.

CHAITHRA.S/AP,CSE/SVCE 80