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Assignment 1 and Marking Scheme, 2023-24v3

The document provides specifications for Assignment 1 of an Advanced Digital Design module. It details requirements for designing a 4-bit universal decimal to seven segment display counter in VHDL, including submitting a report explaining the design and simulation results.

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Anjana W
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21 views3 pages

Assignment 1 and Marking Scheme, 2023-24v3

The document provides specifications for Assignment 1 of an Advanced Digital Design module. It details requirements for designing a 4-bit universal decimal to seven segment display counter in VHDL, including submitting a report explaining the design and simulation results.

Uploaded by

Anjana W
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Reassessment Assignment 1 Coursework Specification

Module name: Advanced Digital Design


Module code: ENGD3001S
Title of the Assignment: Assignment 1
This coursework item is: Formative
This coursework will be marked anonymously: Yes
The module learning outcomes that are assessed by this coursework are:
1. “Knowledge and specialist analytic development techniques in the areas of VLSI design, ASM
design and implementation, and VHDL design.”
2. “Development of generic and transferable skills in advanced digital system design methodologies
using industry standard design tools.”
This coursework is: Individual
This coursework constitutes 40% to the overall module mark.
Date Set: 12 Nov 2023
Date & Time Due: by 11:59 PM on Sunday, 14 Jan 2024
When completed you are required to submit the following:
Submit an electronic copy of your assignment via LearningZone by the advertised deadline.

Please note that once a submission is made it is final. No resubmissions are allowed under any
circumstances, so please ensure that your report is correct and complete before submitting it.
Your marked coursework and feedback will be available to you on:
If for any reason this is not forthcoming by the due date your module leader will let you 2024-02-04
know why and when it can be expected.
Late submission of coursework policy:
Late submissions will be processed in accordance with current University regulations which state:
“The time period during which a student may submit a piece of work late without authorisation and have the
work capped at 40% [50% at PG level] if passed is 14 calendar days. Work submitted unauthorised more
than 14 calendar days after the original submission date will receive a mark of 0%. These regulations
apply to a student’s first attempt at coursework. Work submitted late without authorisation which constitutes reassessment
of a previously failed piece of coursework will always receive a mark of 0%.”

 MUST READ: Academic Offences and Bad Academic Practices:


These include plagiarism, cheating, collusion, copying work and reuse of your own work, poor referencing or
the passing off of somebody else's ideas as your own. If you are in any doubt about what constitutes an
academic offence or bad academic practice you must check with your tutor. Further information and details of
how DSU can support you, if needed, is available at:
https://www.dmu.ac.uk/current-students/student-support/exams-deferrals-regulations-policies/student-
regulations-and-policies/academic-offences.aspx
and
https://www.dmu.ac.uk/current-students/student-support/exams-deferrals-regulations-policies/student-
regulations-and-policies/bad-academic-practice.aspx
Module leader/tutor name: Duminda Wijesinghe
Contact details: Email: [email protected]
Assignment 1
Design in VHDL a 4-bit universal decimal to SSD (Seven-Segment Display) counter as
presented below:

PL

PD S6 . .
.

3
.
.

. .
PD . .
2 S0

C PL – Synchronous Parallel Load


D PD3,…,PD0 – Parallel Data Input
S6,...,S0 – SSD outputs (corresponds
RS to A,...,G respectively)
RST – Asynchronous Reset Input
CD – Count direction¿
CLK CLK – Synchronizing Clock input

The operation of the universal BCD counter is described by the following function table and design
specifications are given below:
Specifications/Instructions:
RST PL CD Action
 Do not change the names of port identifiers given
0 x x Asynchronous Reset (Zero above. Your code/testbench should correspond to
on SSD) this entity description exactly.
1 0 0 Count Down  Use vectors instead of single-bit ports where
1 0 1 Count Up appropriate.
1 1 x Synchronous Data Load  Assume that each SSD segment requires a logic
HIGH for its illumination.

Simulate this design with the aid of a ‘graphical testbench’ (also known as a “Test Bench
Waveform” file), using the Xilinx ISE v10.1.03 software. It is a mandatory requirement to use
the correct software version and the correct type of testbench. If you have not used the
graphical testbench method, you will receive a zero mark for your test bench and each section
that follows that.

What you should submit:


You should submit a formal report explaining your design and your results. For general guidance
on writing (technical) reports please refer to the following links:
https://www.theiet.org/media/5182/technical-report-writing.pdf
https://library.dmu.ac.uk/ld.php?content_id=31952526
https://library.dmu.ac.uk/class/HEAT
Specifically, your report should contain at least: a) an introduction including the design brief, b) a
background section on counters, their types and their operation, c) a section explaining how
you’ve solved the design task given to you and if applicable why you’ve selected a particular
solution out of several possible, d) the complete listing of the code you’ve written, bearing in
mind good programming and design practice, e) a screenshot of your graphical testbench, f)
the results of the simulations carried out (i.e. suitable, legible and detailed simulation waveforms)
accompanied by detailed comments and explanations, and g) conclusions (and possible further
improvements if applicable). Avoid including simulation waveforms with a black background.
ENGD3001S ‐ ASSIGNMENT 1

Marks Breakdown Possible Your


Marks Marks

Introduction and Design Brief /4

Background on counters, their types and their operation /6

VHDL code for the counter & design efficiency /15

Comments on the code /10

The Graphical Testbench(es) /5

Detailed simulation results outlining the operation of the /25


counter

Detailed comments and explanations for the simulation /20


waveforms

Conclusions /10

Overall layout & presentation /5

TOTAL MARK /100

FOR MARKING DESCRIPTORS PLEASE REFER TO:

https://www.dmu.ac.uk/documents/about‐dmu‐documents/quality‐management‐and‐ policy/academic‐
quality/learning‐teaching‐assessment/ug‐mark‐descriptors.pdf

FOR DETAILED FEEDBACK ABOUT YOUR ASSIGNMENT, PLEASE CHECK THE FEEDBACK
SUMMARY BOX ON LEARNINGZONE

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