Synthesis Lectures on

Engineering, Science, and Technology

Amal Banerjee

Semiconductor
Devices
Diodes, Transistors, Solar Cells, Charge Coupled
Devices and Solid State Lasers
Synthesis Lectures on Engineering, Science,
and Technology
The focus of this series is general topics, and applications about, and for, engineers
and scientists on a wide array of applications, methods and advances. Most titles cover
subjects such as professional development, education, and study skills, as well as basic
introductory undergraduate material and other topics appropriate for a broader and less
technical audience.
Amal Banerjee

Semiconductor Devices
Diodes, Transistors, Solar Cells, Charge
Coupled Devices and Solid State Lasers
Amal Banerjee
Analog Electronics
Kolkata, West Bengal, India

ISSN 2690-0300 ISSN 2690-0327 (electronic)

Synthesis Lectures on Engineering, Science, and Technology
ISBN 978-3-031-45749-4 ISBN 978-3-031-45750-0 (eBook)
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This work is dedicated to
My late father Sivadas Banerjee
My late mother Meera Banerjee
The two professors who taught me all about solid
state physics and semiconductor devices:
Dr. Sanjay Kumar Banerjee
late Dr. James C Thompson
A dear friend and guide: Dr. Andreas Gerstlauer
Acknowledgements

The author is offers his heartfelt thanks to his past thesis advisor Dr. Sanjay Kumar
Banerjee. Dr. Banerjee checked the table of contents and two sample chapters to provide
valuable feedback on the initial book proposal. Dr. Banerjee is the Director, Microelec-
tronics Research Center, Department of Electrical and Computer Engineering, University
of Texas at Austin.

vii
Contents

1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids . . . 1

1.1 Energy Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Physics of Energy Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2 Material Classification Using Quantum States . . . . . . . . . . . . . 6
1.2 Crystal Structure and Semiconductor Energy Bands . . . . . . . . . . . . . . . 8
1.2.1 Crystal Momentum, Effective Mass, Negative Effective
Mass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Effective Mass Schrodinger’s Wave Equation . . . . . . . . . . . . . . . . . . . . . 12
1.3.1 Electron Excitation from Valence to Conduction
Band—Hole Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Recombination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4.1 Band-Band Recombination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4.2 Recombination-Generation Center Recombination . . . . . . . . . 17
1.4.3 Auger Recombination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.4 Recombination Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 Carrier Concentrations [9–16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Thermal Equilibrium and Fermi–Dirac Statistics . . . . . . . . . . . . . . . . . . 21
1.6.1 Collisions and Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.6.2 Fermi–Dirac Statistics and the Fermi Level . . . . . . . . . . . . . . . 22
1.6.3 The Fermi Level and Equilibrium Carrier Concentrations . . . 24
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2 Charge Transport (Current Flow) in Semiconductors . . . . . . . . . . . . . . . . . . . 29
2.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 Relation Between Charge, Current and Energy [1–8] . . . . . . . . . . . . . . 29
2.3 The Boltzmann Transport Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.1 Method of Moments Solution of Boltzmann
Equation—Continuity Equations [1–11] . . . . . . . . . . . . . . . . . . 31
2.3.2 Drift Diffusion Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.3 Hydrodynamic Transport Equations . . . . . . . . . . . . . . . . . . . . . . 33

ix
x Contents

2.3.4 Semiconductor Device Design Equations . . . . . . . . . . . . . . . . . 34

2.4 Ballistic Transport of Charge Carriers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction
Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1 Homogeneous and Heterogeneous Semiconductor Junctions
[1–7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1.1 Homogeneous Semiconductor Junction—np . . . . . . . . . . . . . . . 45
3.1.2 How to Create|Draw np Junction Equilibrium Energy
Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2 Homogeneous np Junction with External Bias . . . . . . . . . . . . . . . . . . . . 49
3.2.1 How to Create Energy Band Diagram for Homogeneous
np Junction at Non-equilibrium . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.2 Quasi Fermi Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 The Ideal Homogeneous np Junction (Diode) Equation . . . . . . . . . . . . 53
3.4 Heterogeneous Semiconductor Junctions Np . . . . . . . . . . . . . . . . . . . . . . 55
3.4.1 Heterogeneous Semiconductor Junction Quasi Fermi
Level Splitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4 Basic Heterogeneous Bipolar|Bijunction Transistor (HBT) Properties . . . . 61
4.1 Types of Heterogeneous Bipolar Transistor and Characteristics
[1–12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 The Collector and Base Current of a HBT . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.1 Emitter Hole Current in a HBT . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3 Heterogeneous Junction Transistor (HBT) Simple DC Equivalent
Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5 Advanced VBIC and Angelov-Chalmers Models
for Heterogeneous|Homogeneous Bipolar|Bijunction Transistor . . . . . . . . . 71
5.1 The VBIC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.1 VBIC Homogeneous Junction Bipolar Transistors [1] . . . . . . 73
5.2 VBIC Based Group 4 Silicon Germanium (SiGe) Heterogeneous
Bijunction Transistor (HBT) Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3 Non-VBIC Group 3–5 and 4 Heterogeneous Junction Transistor
(HBT) Large Signal Model (Angelov Chalmers) [16, 17] . . . . . . . . . . 76
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Contents xi

6 Heterogeneous Junction Field Effect Devices-Schottky Diode, Metal

Semiconductor Field Effect Transistor (MESFET), High Electron
Mobility Transistor (HEMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1 Heterogeneous Junction Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2 Metal Semiconductor Junction—Schottky Barrier
Diode—Ohmic, Rectifying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3 Metal Semiconductor Field Effect Transistor (MESFET) . . . . . . . . . . . 84
6.4 High Electron Mobility Transistor (HEMT) . . . . . . . . . . . . . . . . . . . . . . 86
6.4.1 The Two Dimensional Electron Gas (2 DEG) [1–6] . . . . . . . . 87
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7 AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large Signal Equivalent
Electrical Circuits (Angelov Chalmers Model)-Normally On|Off
HEMT, pHEMT, mHEMT and MODFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1 Large and Small Signal Models of HEMTs and MESFETs . . . . . . . . . 91
7.2 Angelov-Chalmers Large Signal Model for HEMTs
and MESFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.3 Gallium Nitride (GaN) Properties Normally On|Off HEMTs . . . . . . . . 93
7.3.1 P-GaN Gate P-GaN-AlGaN-GaN Normally-Off HEMT
[1–19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.3.2 Recessed Gate Hybrid MISHEMT
(Metal–Insulator–Semiconductor HEMT) . . . . . . . . . . . . . . . . . 95
7.3.3 Cascode Combination of Enhancement NMOS FET
and Normally-On HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.4 AlGaAs-GaAs Normally on HEMT|p (Pseudomorphic) HEMT
and Double Heterojunction HEMT [1–19] . . . . . . . . . . . . . . . . . . . . . . . . 97
7.5 m(Me)tamorphic HEMT and MODFET . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.6 AMS-CMC GaN HEMT Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8 Homogeneous Bipolar|Bijunction Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.1 NPN and PNP Homogeneous Bipolar Transistors . . . . . . . . . . . . . . . . . 103
8.2 Ebers Moll Model of a NPN Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.3 Gummel Poon Model for a Homogeneous Junction NPN
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.4 VBIC Enhancement to Gummel Poon Model . . . . . . . . . . . . . . . . . . . . . 107
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9 Metal Oxide Semiconductor Field Effect Transistor . . . . . . . . . . . . . . . . . . . . 111
9.1 The Long Channel MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9.2 Surface Charge Model of Long Channel MOSFET Drain Current . . . 114
9.3 Strong Inversion Source Reference Model Drain Current HERE . . . . 117
9.4 Threshold Voltage and Body Effect Coefficient Relation . . . . . . . . . . . 119
xii Contents

9.5 Complimentary Metal Oxide Semiconductor Field Effect

Transistor (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.5.1 Lattice Strain and Charge Mobility . . . . . . . . . . . . . . . . . . . . . . 124
9.5.2 High k Dielectrics in Gate Capacitors . . . . . . . . . . . . . . . . . . . . 126
9.5.3 Poly Silicon Gates and Capacitances . . . . . . . . . . . . . . . . . . . . . 126
9.5.4 Gate Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.5.5 Short Channel Effect and Threshold Voltage . . . . . . . . . . . . . . 128
9.6 Silicon on Insulator MOSFET (SOI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.7 Hot Electron Effect in Short Channel MOSFETs . . . . . . . . . . . . . . . . . . 132
9.8 Semiconductor Industry Standard BSIM MOSFET Model . . . . . . . . . . 133
9.9 Three Dimensional Transistors-State-Of-Art MOSFET Structures . . . 136
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10 Noise in Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1 Semiconductor Noise Mechanisms [1–77] . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1.1 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1.2 Diffusion Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1.3 Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.1.4 Generation Recombination Noise . . . . . . . . . . . . . . . . . . . . . . . . 144
10.1.5 Flicker (1/f) Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.1.6 Burst (Popcorn) Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.1.7 Avalanche Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.2 Microwave Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.2.1 Hybrid π Bipolar Transistor Microwave Noise Model . . . . . . 150
10.2.2 Generalization of the Noisy Bipolar Transistor
Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.3 T Equivalent Circuit for Noisy Bipolar Transistor . . . . . . . . . . . . . . . . . 153
10.4 Noisy Gallium Arsenide (GaAs) Field Effect Transistors . . . . . . . . . . . 154
10.5 Noisy Heterogeneous Junction Bipolar Transistor (HBT) . . . . . . . . . . . 157
10.6 Noisy Gallium Nitride (GaN) High Electron Mobility Transistor
(HEMT) Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
10.7 Transistor Noise Factor|Figure Measurement with Laboratory
Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.7.1 Transistor Noise Parameters [55–72] . . . . . . . . . . . . . . . . . . . . . 165
10.7.2 Effect of Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.7.3 Noise Figure Measurement—Linearity, Noise
Equivalent Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.7.4 Y Factor Method for Noise Factor|Figure Measurement . . . . 167
10.7.5 Signal Generator Twice Power Method . . . . . . . . . . . . . . . . . . . 168
10.7.6 The Direct Noise Measurement Method . . . . . . . . . . . . . . . . . . 169
10.7.7 Noise Figure Measurement Equipment . . . . . . . . . . . . . . . . . . . 170
Contents xiii

10.7.8 Laboratory Test Bench for Bijunction Transistor Input

Noise Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
10.7.9 MOSFET Noise Sources—Thermal, Flicker . . . . . . . . . . . . . . . 173
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
11 Semiconductor Device Manufacturing Technologies . . . . . . . . . . . . . . . . . . . . 181
11.1 Creating High Vacuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.1.1 Vacuum Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.1.2 How to Create Vacuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.1.3 How to Measure Vacuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11.2 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.3 Deep and Extreme Ultraviolet Photolithography . . . . . . . . . . . . . . . . . . . 188
11.4 Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.4.1 Ion Implantation Masks and Photoresists . . . . . . . . . . . . . . . . . 192
11.5 Dry and Wet Etching—Anisotropic and Isotropic . . . . . . . . . . . . . . . . . 192
11.6 Chemical Vapor Deposition—CVD, APCVD, LPCVD, PECVD,
MOCVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
11.6.1 Metal Organic Chemical Vapor Deposition
(MOCVD|OMVPE|MOVPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
11.6.2 Ultra High Vacuum Chemical Vapor Deposition
(UHVCVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
11.6.3 Atomic Layer Deposition (ALD) . . . . . . . . . . . . . . . . . . . . . . . . 197
11.7 Molecular Beam Epitaxy (MBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
11.8 Metrology in Semiconductor Device Manufacture . . . . . . . . . . . . . . . . . 200
11.8.1 Critical Dimension Scanning Electron Microscopy . . . . . . . . . 201
11.8.2 Wafer Defect Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
11.8.3 Review Scanning Electron Microscopy . . . . . . . . . . . . . . . . . . . 203
11.9 Thin Film Thickness Measurement Techniques . . . . . . . . . . . . . . . . . . . 203
11.9.1 Oxide Layer Thickness Measurement . . . . . . . . . . . . . . . . . . . . 204
11.9.2 Ray Reflectometry, Scanning and Transmission Electron
Microscopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.10 Maintaining Super Clean, Sanitized Semiconductor Fabrication
Facilities [15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12 Designing Transistors for Specific Applications . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.1 Transistor Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.1.1 MOSFET Capacitances (SPICE Level 1 Model, Triode
Region) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.2 Heterogeneous|Homogeneous Junction Bipolar Transistor
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.3 Transistors for Computer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
xiv Contents

12.3.1 Transistors for Dynamic Random Access Memory

(DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
12.3.2 The Floating Gate NMOS Transistor and Flash Memory . . . 215
12.4 Transistors for Ultra High Frequencies (RF|Microwave) . . . . . . . . . . . . 216
12.4.1 Transition Frequency f T Definition and Expression . . . . . . . . 220
12.4.2 Unity Power Gain Frequency f M AX Definition
and Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.4.3 f T , f M AX For Field Effect Transistors . . . . . . . . . . . . . . . . . . . 223
12.5 Transistors for High Power (High Current and Voltage) and High
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
12.6 Low Noise Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.7 Figures of Merit for High Power and High Frequency Transistors . . . 230
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
13 Performance Characteristics of Selected Commercial Heterogeneous
Transistors and TCAD (Technology Computer Aided Design) Tools . . . . . . 233
13.1 Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
13.2 BFQ790 Heterogeneous Junction (SiGe) Medium Power NPN
RF Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
13.3 TP65H150G4LSG Heterogeneous Junction Gallium Nitride
(GaN) Power FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
13.4 EPC2216 GaN Power FET DC Performance Characteristics . . . . . . . . 234
13.5 NE34018 Gallium Arsenide (GaAs) Field Effect Transistor . . . . . . . . . 236
13.6 Technology Computer Aided Design (TCAD) Tools
for Analyzing, Estimating and Visualizing Internal Electrical
Properties of Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
14 Semiconductor Optoelectronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
14.1 Basic Solar Cell Structure (Photo Diode) . . . . . . . . . . . . . . . . . . . . . . . . . 245
14.1.1 Light Absorption by Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . 245
14.1.2 Generation of Photovoltage and Photocurrent . . . . . . . . . . . . . 247
14.1.3 Heterogeneous Junction Solar Cell . . . . . . . . . . . . . . . . . . . . . . . 251
14.2 Light Emitting Diodes (LEDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
14.2.1 Heterogeneous Junction Light Emitting Diodes . . . . . . . . . . . . 253
14.2.2 Radiative Recombination Efficiency . . . . . . . . . . . . . . . . . . . . . . 255
14.2.3 Extraction and Wall Plug Efficiency . . . . . . . . . . . . . . . . . . . . . 256
14.2.4 Luminous Efficiency and Efficacy . . . . . . . . . . . . . . . . . . . . . . . 257
14.2.5 Organic Light Emitting Diodes (OLED) . . . . . . . . . . . . . . . . . . 258
14.3 Phototransistor Structure and Performance Characteristics . . . . . . . . . . 259
14.3.1 Spectral Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
14.3.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Contents xv

14.3.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

14.3.4 Collector-Emitter Saturation
Voltage—VC E,S AT U R AT I O N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
14.3.5 Dark Current—I D A R K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
14.3.6 Speed of Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
14.4 Charge Coupled Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
14.5 Semiconductor Lasers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
14.5.1 Laser Fundamentals [18] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
14.5.2 Semiconductor Lasers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
15 Gallium Nitride-The Reigning King of Ultra High Frequency|Power
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
15.1 Face Centered Cubic Crystal (Zinc Blende) Gallium Nitride . . . . . . . . 275
15.2 Hexagonal Close Packed Structure (HCP Wurtzite) Gallium
Nitride [1–33] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
15.3 Piezoelectric and Spontaneous Polarization and Symmetry . . . . . . . . . 278
15.4 Two Degree Electron Gas (2DEG) GaN-AlGaN–GaN
Pseudomorphic Heterogeneous Junction Properties . . . . . . . . . . . . . . . . 281
15.4.1 Surface Charge Concentration AlGaN|GaN Interface
2DEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
15.4.2 Surface Charge Concentration GaN-AlGaN–GaN
Interface 2DEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
15.5 High Electron Mobility Transistor Properties . . . . . . . . . . . . . . . . . . . . . 287
15.6 Scattering Processes in GaN HEMTs [33–52] . . . . . . . . . . . . . . . . . . . . 289
15.6.1 Polar Optical Phonon Scattering . . . . . . . . . . . . . . . . . . . . . . . . . 290
15.6.2 Acoustic Phonon Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
15.6.3 Ionized Impurity Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
15.6.4 Alloy Disorder Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
15.6.5 Dislocation Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
15.6.6 Interface Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
15.6.7 Dipole Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
15.7 Basic and Advanced Physical Structures of HV, RF HEMTs . . . . . . . . 293
15.7.1 Gate and Source Connected Field Plates [53] . . . . . . . . . . . . . 294
15.7.2 Deep Recessed Gate HEMTs [53] . . . . . . . . . . . . . . . . . . . . . . . 294
15.7.3 Metal Oxide Semiconductor(MOS) HEMT [53] . . . . . . . . . . . 296
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Fundamental Quantum and Statistical
Mechanics of Crystalline Solids
1

… by nature I am a conservative man, but a theoretical explanation had to be found, whatever

the cost … Max Planck at his Nobel Prize acceptance speech.

1.1 Energy Bands

Quantum mechanics [1–8] explains how and why all fundamental physical entities (elec-
trons, protons, atoms, molecules, etc.,) exist and their properties. Quantum mechanics is
based entirely on experimentally established fact that energy levels of all physical enti-
ties (electrons, protons, neutrons, atoms and molecules) are discrete and quantized.
That is, the allowed energy levels of even the simplest atom—the hydrogen atom are E,
2E, 3E, …. but never E, 1.5E, 2.67E … etc., As the numerical values of these discrete
energy levels are small, from a macroscopic view, these energy levels appear smeared out
into one continuous energy band. Nothing would exist without quantum mechanics, as
everything at the core is made of atoms, electrons, protons etc.
One key foundation of quantum mechanics is the particle|wave duality of matter, pro-
posed by Louis De-Broglie, which states that the momentum and wavelength of a particle
(e.g., electron) are related as:

ℏ
p= wher e p, ℏ, λ D B (1.1)
λD B

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 1

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_1
2 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

are respectively the momentum, Planck’s constant and De-Broglie wavelength. The
behaviour of a fundamental particle (and entities made up of these fundamental parti-
cles—atoms, molecules etc.,) can be explained either by invoking its wave properties or
particle properties.
The Schrodinger’s wave equation explains the behaviour of elementary physical enti-
ties, e.g., the details of an electron’s motion in a solid, by exploiting that entity’s wave-like
properties. This equation, derived in 1925, was first successfully used to explain the exper-
imentally observed, discrete frequencies of light emission from an excited hydrogen atom.
The simplest form of this equation is the time-independent version, i.e., in one dimension
given as:

−ℏ2 d 2 ψ
+ U (x)ψ(x) = Eψ(x) (1.2)
2md x 2
Invoking conservation of energy, the Scrodinger’s wave equation in one dimension can
be re-written in terms of the Hamiltonian operator as:

H ψ(x) = Eψ(x) (1.3)

In both the above expressions,

ψ(x), U (x), m, E

are respectively the particle’s (e.g., electron’s) wavefunction, potential energy, rest mass
and total energy. The fundamental physical importance of the wavefunction is that the
expression

ψ(x)ψ P (x) = |ψ(x)|2 (1.4)

is the probability of finding the particle (e.g. electron) in the 1-dimensional region
bounded by (x, x + dx). The superscript P represents the complex conjugate of the wave
function. This is the Niels Bohr interpretation of the wavefunction. Clearly,
∫
|ψ(x)|2 d x = 1 − ∞ ≤ x ≤ ∞ (1.5)

The solutions to the Schrodinger’s equation are the possible discrete energy levels that
can be occupied by the particle (e.g., electron). These discrete energy levels give rise to
energy bands. Once a potential has been defined, the Schrodinger’s wave equation can be
solved. Of the many possible potential functional forms that might be used, the one very
attractive for solid state physics purposes, is the periodic Dirac delta function potential.
The Dirac delta function, is defined as:

δ(x − a) has value infinity at x = a, and is zero f or all other values of x.

1.1 Energy Bands 3

The periodic (period N) Dirac delta function is:

Σ
U (x) = β δ(x − la) 0 ≤ l ≤ (N − 1)a β constant (1.6)

The periodic Dirac delta function, applied to the Schrodinger’s wave equation,
transforms it to:
d 2 ψ(x)
+ U (x)ψ(x) = 0 (1.7)
dx2
whose general solution, with arbitrary constants A, B is listed below. The constants are
evaluated using boundary conditions:

• The wavefunction is continuous at a boundary.

• The first derivative of the wavefunction is continuous infinitesimally close to the
boundary, but not at the boundary, where the potential is infinite (Dirac delta function):

(√ ) (√ )
2m E 2m E
ψ(x) = A cos x + B sin x (1.8)
ℏ ℏ

A periodic potential has a huge number of boundaries, at each of which the potential
energy U tends to infinity. This problem is easily circumvented by invoking the periodic
potential’s unique properties as embedded in the Bloch’s Theorem. This theorem states
that for a periodic potential U(x + a) = U(x), the solutions to Schrödinger’s equation
satisfy:

ψk (x) = u k (x)e jkx u k (x) lattice periodicit y (1.9)

The subscript k indicates that u(x) has different functional forms for different values
of the Bloch wavenumber k. In case if u(x) is not periodic but a constant, the Bloch wave
becomes a plane wave. Therefore a Bloch wave is a plane wave modulated by a function
that has the periodicity of the lattice. An alternative form of Bloch’s Theorem is:

ψk (x + a) = e jka ψk (x) (1.10)

If there is a discontinuity in the first derivative of the wavefunction, then the kinetic
energy term tends to infinity, but the equation is still satisfied if the potential energy
tends to infinity U → ∞. When the effective mass Schrödinger wave equation, is examined
the boundary condition for the derivative of ψ must include the effective mass, where
ψk (x), |ψk (x)|2 are periodic.
This periodicity property is because an electron has an equal probability of being at
any of the identical sites in the linear array, and breaks down at the edges of the lattice.
The electrons deep within the lattice are unaware that the periodicity property is broken
4 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

at the edges, since the array is very long compared to the separation. between atoms, i.e.,
when N (the number of lattice nodes|sites), is very large. The generalized periodic boundary
condition becomes:

ψk (x + N a) = ψk (x) (1.11)

which leads to
2π n
ψk e jk N a = ψk (x) k = n : integer (1.12)
Na
where k is the Bloch wavenumber. Now, the constants A, B can be determined. In the
linear region −a < x < 0. Schrodinger’s wave equation is re-written as:
(( (√ ) (√ ) ))
− jka 2m E 2m E
ψk (x) = e A cos (x + a) + B sin (x + a) (1.13)
ℏ ℏ

The expressions for the constants A, B are then (evaluated at x = 0):

(( (√ ) (√ )))
− jka 2m E 2m E
B=e A cos a + B sin a (1.14)
ℏ ℏ

As the derivative of the Dirac delta function is discontinuous at x = 0, the derivative

of ψ is also discontinuous at x = 0. Therefore the discontinuity must be evaluated to get
another expression linking A and B. For U(x) = βδ(x) the discontinuity condition implies:
dψ 2mβ
∆ = 2 ψ(0) (1.15)
dx ℏ
Therefore, from the derivatives of ψ at x = 0:
√ ( (√ ) (√ ))
2m E ( − jka
) 2m Ea 2m Ea 2mβ B
A−e A cos − B sin = (1.16)
ℏ ℏ ℏ ℏ2

Equation 1.16 is obtained by integrating the Schrödinger’s equation over a tiny interval
spanning x = 0. The integral of the first derivative term is the required discontinuity and
is equal to the integrals over the Eψ and Uψ terms. In the former term E is a constant
and ψ is finite, so integrating over an infinitesimal interval gives zero. Identical arguments
hold for the Uψ term. However, as U = ∞ at x = 0, a special property of the Dirac delta,
i.e., its integral over all space is 1, is exploited. After some careful manipulation of these
expressions, the fundamental expression that governs the physics of energy bands is
obtained, independent of the constants A, B.
(√ ) (√ )
2m E aβm sin 2m Ea
cos(ka) = cos a + √ (1.17)
ℏ ℏ2 2m Ea
ℏ
1.1 Energy Bands 5

This key equation embodies the secret of energy bands: the right-hand side is a func-
tion of the energy E, but the left-hand side strictly enforces that f(E) must be bounded
by ± 1. Energy
(√ is
) quantized. The energy bands corresponding to the allowed values of
−1 ≤ f 2m Ea
ℏ ≤ +1, and the forbidden regions (bandgaps—separating the permitted
bands), are displayed on a plot of energy E versus Bloch wavevector k (extended zone
plot)—Fig. 1.1a. The first zone extends over −π π
a < k < a ; the second zone is split into
two: −2πa <k < a
−π π
a < k < a . Range of k in each zone is a . The total number of
2π 2π

lattice sites is N. As N is very large in semiconductor devices, the separation of neighbour-

ing k values (= 2Na π ), is so small that the E-k relation appears continuous within a band.
k = 2πλ is the general relationship between wavelength and wavevector. For the specific
case of a Bloch wavevector, P→C RY ST AL = ℏk→ is called the crystal momentum. This is the
momentum of an electron (for a specific Bloch wavevector) in a crystal as a consequence of
applied forces.
A reduced zone [8–16] plot (Fig. 1.1b) also displays the E-k relationship by compress-
ing all of its information into the first zone, by horizontally shifting each of the curves
from the higher order zones in the extended-zone plot by an appropriate multiple of 2π a .
For the positive wavevectors in the 4th and 5th zones, i.e., 3π a < k < 5π
a , the wavevector
can be re-written as:
4π −π π
k= + kP ≤ kP ≤ (1.18)
a a a
So the wavefunction becomes:
j4π x Px
ψk (x) = u k (x)e a e jk = ψk P (x) (1.19)
j4π x
The terms e a and u have the same period a, so can be combined into a new peri-
odic function. Also, as the changes to u and k are complementary, the wavefunction is

Fig. 1.1 a E-k extended zone (k -Bloch wavevector) plot b Reduced zone plot for N = 8 crystal
momenta
6 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

unchanged. The shift in k of 4π/a takes the band of the 4th zone (positive k) to the range
−π π
a < k < 0, and the 5th band to 0 < k < a . The bands in the new scheme are com-
pleted by similar operations on the corresponding, negative-k portions of the 4th and 5th
bands from the extended-zone plot. Identical translations of appropriate multiples of 2π/
a, bring all of the other bands into the first zone. The resulting plot is the reduced zone
plot, Fig. 1.1. The first zone, which now contains all the bands, is first Brillouin zone, or
Brillouin zone. In the reduced-zone plot the crystal momentum is renamed the reduced
crystal momentum.

1.1.1 Physics of Energy Bands

The underlying physics of energy bands is simple [1–16]. Let a beam of electrons of
wavelength λ propagate a one dimensional lattice. Some of the electrons scatter off
two neighbouring lattice sites. The two portions of the reflected beam would reinforce
constructively if the Bragg condition for normal incidence is satisfied.

2a = βλ (1.20)

where a is the spacing between lattice sites and b = 1, 2, 3, … is an integer. As the

number of lattice sites is very large, multiple Bragg reflections would make the beam
bounce around (i.e., reflected back–forth) in the crystal resulting in a standing wave. The
wavevectors at which this occurs are:
±2π ±bπ Gb
k= = = (1.21)
λ λ 2
As a result, energy bandgaps, within which there are no propagating waves, arise at
Brillouin zone boundaries because of the strong Bragg reflection. In the above expression:
2π b
Gb = (1.22)
a
is a set of multiples of 2π and the reciprocal of the lattice spacing a. The multiples are
called reciprocal lattice numbers, and become vectors in two|three dimensional lattices.
The translation numbers used to obtain the reduced zone plot from the extended zone plot
are the reciprocal lattice.

1.1.2 Material Classification Using Quantum States

The reduced zone plot shown above (Fig. 1.1b) is valid for very small number of lattice
sites or primitive unit cells each with a single electron (monovalent). For a reduced zone
plot:
1.1 Energy Bands 7

π N kπ
|k M AX | = |n M AX | = = 0, ±0.2, ±0.4, ±0.6 . . . (1.23)
a 2 a
Thus n is a state of reduced crystal momentum that can be occupied by an electron. As
the end values n = ±N/2 are the same point, the total number of distinct n numbers in the
reduced zone is equal to N, the number of lattice sites of primitive unit cells.
From Pauli’s Exclusion Principle (no two fundamental physical entities (e.g., electrons)
can have an identical set of quantum numbers), each reduced crystal momentum state can be
occupied by two electrons, if and only if they have opposite spin. The quantum number for
electron spin is ±1/2 and there is one quantum number—n, for the crystal momentum. In
the reduced zone scheme, n is restricted to values between −N/2 and N/2, so that another
number is essential to separate states with the same value of reduced wavevector, but
different values of energy. This number is the band index. Summarizing,

• Each band contains 2N states, where N is the number of primitive unit cells that form
the crystal lattice.
• For the special case of a monovalent single atom primitive cell there will be N valence
electrons, which T = 0 K will occupy the bottom half of the first band.
• If there were 2 valence electrons per primitive cell the entire first band would be
occupied at 0 K. This means that bands will be either completely filled or completely
empty if there is an even number of electrons in the primitive unit cell.
• The highest fully occupied band at 0 K is the valence band, and the lowest unfilled
band at 0 K is the conduction band. The energy gap between these bands is called the
bandgap.
• For a full band, a filled state with crystal momentum is matched by a filled state with
crystal momentum.
• Crystal momentum is the electron momentum due to external forces, such as an applied
electric field. So, there can be no net motion of charge carriers, as long as the electrons
stay in the full band.

When thermal energy is added to the system by increasing T, then the monovalent case the
electrons can respond to this stimulus by moving into allowed states of higher energy and
crystal momentum within the half full first band. If in addition an electric field is applied,
electrons will be accelerated into states of higher crystal momentum, and there would be
current flow—as in metals. In the divalent case, the only way to get a net gain in crystal
momentum would be if some electrons could be sufficiently energized to cross the forbidden
energy bandgap and populate some of the states in the empty conduction band, in which
they would gain crystal momentum from an applied field. If this bandgap is very large, the
probability of electrons acquiring sufficient energy to overcome the bandgap is very small,
and this is an insulator. If the bandgap is not too large, some electrons can be excited into
the conduction band, and this is a semiconductor—useful semiconductors have a bandgap
in the range 0.5–3.5 eV.
8 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

1.2 Crystal Structure and Semiconductor Energy Bands

For one dimensional lattice, the reciprocal lattice number is:

2π b
Gb = (1.24a)
a
Thus the reciprocal lattice number is associated with the reciprocal space, which
in the one dimensional lattice, consists of a linear array of points separated by 2π/a,
where a is the spacing of primitive unit cells in the direct lattice. In real three space, the
primitive unit cell is a volume, and have reciprocal lattice vectors which have a magnitude
of some multiple of 2π divided by the spacing between planes of atoms. The direction of the
reciprocal lattice vector in reciprocal space is orthogonal to that of the planes in real space.
The primitive unit cell in reciprocal space for the real space face-centred cubic (FCC)
lattice is a truncated octahedron Fig. 1.2. The Cartesian axes corresponds to directions
of the Bloch wavevector k. These directions are orthogonal to planes in the direct lattice.
Therefore these are denoted in the same way as the normals to crystal planes, using Miller
indices Fig. 1.3. In the Cartesian coordinate system of the direct lattice, the (100) plane
intersects the x,y,z axes at a, ∞, ∞, respectively. The latter set becomes (100) by using
reciprocal of each intercept and reducing to integer values. The normal to this plane is
specified by the same set of numbers, but with a different parenthesis, i.e., [100]. Axis
labelling is arbitrary, so that the (−1,0,0) and (0,1,0) surfaces have exactly the same
properties as (100) surface, denoted as a set {100}: the equivalent normals directions are
designated as 100.

Fig. 1.2 Part of Brillouin

zone|reciprocal lattice for face
centered cubic (FCC) direct
lattice

Fig. 1.3 Direct space diamond

(FCC) lattice
1.2 Crystal Structure and Semiconductor Energy Bands 9

The set [100], denotes the normal to the k x , k y , k z surface that has intercepts in recip-
rocal space of G 1 , 1, ∞ ∞. In Fig. 1.2 this direction is from the origin of k-space—point
out through the center of the square surface at the X-point. Another key direction of inter-
est is [111], which passes from to L at the center of the hexagonal faces of the reciprocal
lattice unit cell. Given the complicated interaction of the direct and reciprocal lattices
and their corresponding vectors the band structure for three dimensional lattice can be
computed only special computer programs.

1.2.1 Crystal Momentum, Effective Mass, Negative Effective Mass

An electron’s crystal momentum is due to an applied external force. A key property of n

electron moving in a crystal with an applied external stimulus is its effective mass.
An electron in a one dimensional lattice is either in the conduction band or the partially
filled valence band/When an external force Fx,ext , is applied, the electron gains energy
from the field according to:
dE dx
= Fx,E X T E R N AL = Fx,E X T E R N AL vx (1.24b)
dt dt
To estimate the appropriate velocity of the electrons in a crystal using Bloch wave-
functions (whose key underlying concept is that the probability of finding an electron at
some point in a primitive unit cell is the same for all of the primitive unit cells of the crys-
tal), an accurate estimation of the electron’s location in the crystal, is required. A single
wavefunction gives the electron’s crystal momentum (with the wavevector k), but no
precise spatial information about the electron. Linear combination of waves of slightly
different k creates a wavepacket. A wide range of wavenumbers (k’s) translates to a
tightly constrained spatial wavepacket. Consequently, the electron will appear to have
mass at a point, i.e., to be particle-like. The electron can then be considered as a classical,
Newtonian mechanics like particle with a trajectory. Thus, the velocity of the center of the
wavepacket—group velocity is used to describe the motion of the wvepacket. Given that
E = ℏω and using the definition of group velocity:
dω dE dE d E dk x
vG R OU P = vx = = (1.25)
dk ℏdk x dt dk x dt
Combining Eqs. 1.24–1.25 and some manipulation gives:

d(ℏk x )
Fx = (1.26)
dt
Therefore the time rate of change of the crystal momentum is the force acting on
the electron, traversing a periodic structure. No knowledge of the mechanical momentum
of the electron, (which changes periodically in response to the crystal field) is needed. The
10 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

response to an external field is calculated by estimating the time dependence of the

crystal momentum. The acceleration acting on the electron is:

dvx d 2 Edk x d 2 Ed(ℏk x )

ax = = = (1.27)
dt ℏdk x dt
2 ℏ2 dk x2 dt

Now using Newton’s force law F = ma the effective mass of the electron is then:
1
m E F F EC T I V E (E) = (1.28)
d2 E
ℏ2 dk x2

The effective mass depends on the direction. In three dimensions, systems it is a tensor.
It also depends on the band structure, which in turn depends on the potential energy of
the crystal. The effective mass is not equal to the free electron mass m.
The effective mass of the electron is positive at the bottom of bands,—where the E-k
relation is concave upwards, and negative at the top of bands, where the E-k relation is
convex upwards.
At the bottom of the conduction band the effective mass is positive, so a positive
force causes a positive change in crystal momentum, forcing the electron to accelerate
in the direction of the applied force. During this traversal, as the electron moves up the
band, it passes through a crystal momentum state at which its effective mass becomes
infinite and so negative. The transition from positive to negative effective mass point
occurs where the acceleration due to the external force is overcome by the increasing
Bragg reflection of the Bloch waves as the Brillouin-zone boundary is approached. The
momentum transfer from the applied force to the electron becomes less than the momentum
transfer from the lattice to the electron. However the conduction band electrons do not
enter this part of the zone, and so stay near the bottom of the band, and accelerate in the
direction of the applied force.
The top of the valence band is most important when analyzing the motion of charge
carriers. For a net change in crystal momentum of the electrons in the valence band,
empty states in the band must exist, so that the electrons can move into them. These
empty states exist near the top of the band because the electrons will want to stay in their
lowest possible energy states, in absence of external stimuli. The empty states near the
top of the valence band are called holes. If an electron is excited into one of these empty
states, an empty state will appear lower down in the band. This energy exchange provides
energy to the hole, i.e., the hole energy increases moving downwards the E-k diagram. The
hole effective mass is positive near the top of the band. So, holes accelerate in the same
direction as the applied external force.
Electrons and holes have positive effective mass and charge with equal magnitude
and opposite polarity. An intrinsic semiconductor with a full valence band and an empty
conduction band, is electrically neutral as the electron|hole charges balance eachother.
From charge balance:
1.2 Crystal Structure and Semiconductor Energy Bands 11

∫
−qn I N T R I N S I C,V AL E N C E B AN D + qn AT O M dΩ = 0 (1.29a)

where q is the electronic charge and Ω the total volume. If the semiconductor is now
perturbed with an with an external stimulus, e.g., thermal excitation, then, using the same
charge balance concept:
∫
−qn IPN T R I N S I C,V AL E N C E B AN D + qn AT O M − qn I N T R I N S I C dΩ = 0 (1.29b)
∫ ( )
q −n IPN T R I N S I C,V AL E N C E B AN D + n AT O M − n I N T R I N S I C dΩ = 0 (1.29c)

n I N T R I N S I C , p I N T R I N S I C are respectively the number of electrons|holes in the conduc-

tion|valence bands.
∫
q( p I N T R I N S I C − n I N T R I N S I C )dΩ = 0 (1.30)

Clearly, the polarity of electron and hole charges are different.

From the previous discussions, it is clear that the bottom|top of the E-k diagram are
very important. Specifically, if the effective mass can be approximated as a constant, rather
than being energy dependent, several important results can be extracted:—this occurs only
when the E-k expression is parabolic. The E-k relationship for a free electron is parabolic.
By analogy, for electrons near the bottom of the conduction band, and for holes near the
top of the valence band the kinetic energy is:

(ℏk)2
E − Ê = (1.31)
2m P

where Ê > 0 is the energy of the extremity of the approximate parabolic band, and m P is
the constant parabolic effective mass. The result obtained after applying this approximation
to a sample E-k diagram is shown in Fig. 1.4. The parabolic band approximation is useful
for quick analysis because charge carriers in real world semiconductor devices are found
in band extremity regions.

Fig. 1.4 a Parabolic curve fit

to conduction band bottom and
valence band top b Band
structure and energy band
diagram relationship for a
homogeneous semiconductor
in uniform electric field
12 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

Fig. 1.4 (continued)

The constant effective mass idea can be extended to three dimensions leading to
constant energy surfaces, where for the bottom of the conduction band:
( )
ℏ2 k x2 k 2y k z2
E − Ê C O N DU C T I O N ,0 = + P + P (1.32)
2 m xP my mz

where m xP , m yP , m zP are the longitudinal effective electron mass, and transverse effective
electron masses in the x, y and z directions respectively.
In case of the valence band, for common semiconducting materials as Si and GaAs,
there are degenerate energy states, and therefore interaction between electrons and holes
cannot be ignored.
( / )
ℏ2 ( )
E(k) − Ê V AL E N C E,0 = Ak ∓ B k + C k x k y + k y k z k z + k z k x
2 2 4 2 2 2 2 2 2 2 (1.33)
2m

where the negative sign corresponds to the heavy hole band and the positive sign to the
light hole band. A, B and C are parameters to be determined experimentally.

1.3 Effective Mass Schrodinger’s Wave Equation

Schrodinger’s wave equation can be re-formulated in terms of the effective mass, when
the potential energy is a superposition of individual values, due to the periodic lattice
U L and some external macroscopic, potential energy U M , e.g., applied electric field; the
potential energy due to a variation in ionized impurities in the crystal, e.g., p–n junction.
Now, Schrödinger Wave Equation becomes:

−ℏ2 d 2 ψ(x)
+ (U L (x) + U M (x))ψ(x) = Eψ(x) (1.34)
2md x 2
1.3 Effective Mass Schrodinger’s Wave Equation 13

under the assumption that the conduction band potential has a parabolic form:

ℏ2 k 2
E ν (k) = E C O N DU C T I O N ,0 + (1.35)
2m P
where ν is the band index and E CONDUCTION,0 is the energy of the lowest level in the
conduction band. The single band effective mass conduction band Schrodinger’s wave
equation is:

−ℏ2 d 2 F(x)
+ U M (x)F(x) = E F(x) − E C O N DU C T I O N ,0 F(x) ψ(x) = u k0 F(x)
2md x 2
(1.36)

where F is the envelope function of the original wavefunction, and u k (0) is the periodic
part of the Bloch wavefunction, evaluated at the bottom of the conduction band.
Several conditions must be satisfied for this equation to generate meaningful results.

• This holds for a single band and will have to be relaxed for the valence band, at the
top of which both heavy and light holes are present in separate bands.
• u is independent of k in the neighborhood of k0 .
• F(x) varies slowly with x, i.e., when compared to the spatial variation of the lattice
potential energy due to the periodicity of the crystal.
• The parabolic-band effective mass is applicable when electron energies are restricted
to near the bottom of the conduction band.
• Information on the atomic scale variation of the electron concentrations is not needed,
as the sum of the probability densities of all the electrons involves the envelope
functions, which produce a smoothed out version of the true electron concentrations.

The effective mass Schrodinger’s wave equation can be re-written as:

−ℏ2 d(d F(x))

( ) + E C O N DU C T I O N (x)F(x) = E F(x) (1.37)
2d x m P (x)d x

where E C (x) = E C (0) + U M (x). The boundary condition for the derivative of F that
conserves current is:
I I
d FC O N DU C T I O N II d FV AL E N C E II
I = P I FC O N DU C T I O N (0) = FV AL E N C E (0)
m CP O N DU C T I O N d x Ix=0 m V AL E N C E d x Ix=0
(1.38)

The band structure of a semiconductor embodies information about the energy in k-

space, which is conveyed by the expression for parabolic energy bands combined with
the external potential energy.
14 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

ℏ2 k 2 ℏ2 k 2
E= P
+ E C O N DU C T I O N ,0 + U M (x) = E C O N DU C T I O N + (1.39)
2m 2m P
E C O N DU C T I O N is the position dependent conduction band potential energy—conduction
band edge. These expressions contain information about the spatial variation of the lowest
conduction band energy level, obtained by drawing E C O N DU C T I O N (x), assuming that
energies above it at any position x are the kinetic energies of electrons at that location. The
resulting plot is an energy band diagram. The relationship between it and the parabolic
dispersion relationship is shown in in Fig. 1.4. The applied electric field uniform, which
causes a linear change in U M (x).

1.3.1 Electron Excitation from Valence to Conduction Band—Hole

Creation

An electron in the valence band can be excited to the conduction band in a number of
ways. Consequently a hole is created in the valence band.

1.3.1.1 Thermal Excitation

For temperatures T > 0 K, the lattice atoms vibrate about their mean positions. Sometimes,
the ambient temperature is high enough to excite the electrons to a level such that the local
amplitudes of vibration are sufficient to break a valence bond—the released electron enters
the conduction band. This transition occurs because the electron absorbs a phonon. A
phonon is the quantum of lattice vibrational energy. As atoms in the lattice are bonded
to their neighbours, these lattice vibrations travel through the material as waves because
the random vibrations of each atom are coupled to its neighbors. The crystal lattice, being
a mechanical structure, can only vibrate in specific modes.

• The atomic displacements in the direction of the atomic chain create longitudi-
nal modes. The associated phonons are acoustic or optic, depending on whether the
displacements of neighboring atoms are in phase or out-of-phase.
• If the atoms vibrate in the two directions perpendicular to the direction of the atomic
chain, the displacements create transverse modes.

In real three dimensional crystals, the lattice periodicity results in band structure of the
phonons that have properties similar to that of electrons. For cubic lattice or cubic lattice
like materials the two transverse modes are the same—doubly degenerate. Other factors
as atomic mass etc., also influence phonon band structure.

1.3.1.2 Optical Excitation

Electron–hole pairs in a crystal lattice can be generated when the crystal absorbs optical
energy at appropriate frequencies. The energy and momentum balance equations are:
1.3 Effective Mass Schrodinger’s Wave Equation 15

< > Σ( )
E electr on 1 P − E hole <1> = ℏω photon + ℏω photon − ℏωelectr on (1.40a)

( < > ) ( Σ( ))
ℏ kelectr on 1 P − khole <1> = ℏ k photon + β phonon − βelectr on (1.40b)

where β phonon , βelectr on are the wavenumbers of the generated phonons and electrons
respectively. Phonons need to be generated to excite the electrons from the valence to
the conduction band. The photon wavenumber is:
Enr
k photon = (1.41)
cℏ
where c, E, nr are the speed of light in vacuum, energy and refractive index of the
crystalline material. In a direct bandgap (maximum of valence band lies vertically below
minimum of conduction band) material, interband electron transitions at energies near the
bandgap need not involve any momentum change, so phonons need not be involved. So
photon absorption in direct bandgap materials occur more readily than in indirect bandgap
materials. But as silicon is widely used in solar cells and photodetectors indicates that
absorption can be strong in indirect bandgap materials as well. For photon energies near
the bandgap, the phonons do not need to have much energy, and there are many acoustic
phonons of this type available.

1.3.1.3 Electrical Excitation

Electrical generation of electron–hole pair is achieve when a highly energized electron
from an external source hits an atom in the lattice. Energy transfer from the incident
electron to the target atom occurs, and this extra gained energy sometimes energizes
some of the valence band electrons to acquire sufficient energy to enter the conduction
band. This is called impact ionization. The energy and momentum balance equations are:
< > < >
E electr on 1 P + E electr on 2 P = E electr on <1> + E hole <2>
< > < > (1.42)
kelectr on 1 P + kelectr on 2 P = kelectr on <1> + khole <2>

Electrons are confined to the lower energies of the conduction band by frequent col-
lisions with atoms, defects, and any impurities in the lattice. If an electron is rapidly
accelerated by an applied electric field, it could gain sufficient energy between collisions
for impact ionization to occur. If the applied electric field is very strong, it could trigger
avalanche breakdown.

1.3.1.4 Chemical Excitation

Unlike all the previous electron–hole pair excitation methods, the chemical excitation
method is permanent and is the basis for all semiconductor devices. If some of the
lattice atoms in a homogeneous material lattice are substituted with some impurity atoms so
16 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

that the resulting lattice has an excess of electrons the resulting material is a n type (electron
rich) type semiconductor. Conversely, substitution of intrinsic lattice atoms with impurity
atoms such that the resulting material has an excess of holes results in a p type semiconductor.
Removing an atom from the lattice is difficult, so that high temperature diffusion or most
widely used ion implantation of the impurities is needed. The impurity atom must have
more|less electrons in its valence band than the atom it is replacing. The extra electrons
left over after the impurity atom is embedded in the lattice are free to enter the conduction
band—n type semiconductor. Similar arguments hold for a p type semiconductor. A donor
impurity atom ‘donates’ an electron, while an acceptor atom removes an electron from the
intrinsic lattice.

1.4 Recombination

An external stimulus can create an electron–hole pair. Similarly, the excited electron in
the conduction band can lose energy by radiating it and then recombine with holes in the
valence band—recombination.

1.4.1 Band-Band Recombination

Band-band recombination is the inverse of optical generation, for a direct bandgap mate-
rial. The energy lost by the electron is usually radiated as a light photon. No phonons are
generated, so that the lattice is not heated up This type of recombination is called radiative
recombination. While the electron in the conduction band is waiting for a large number
of phonons to be simultaneously emitted, as would be required for a direct band-to-band
transition (e.g., gallium arsenide), a single photon is created instead. The recombination
rate is:

R R AD I AT I O N = Bnp (1.43a)

where B, n, p are respectively the radiative recombination coefficient, the concentrations

3
of electrons and holes. For an indirect bandgap material such as Si, B ≈ 10 − 14 cms .
Radiative recombination is much less likely to occur in indirect bandgap materials because
phonons need to be generated as well, to take up the change in crystal momentum. The
energy and momentum relations are:
< >
E electr on <1> − E electr on 1 P = ℏω photon
< > (1.43b)
kelectr on 1 P = kelectr on <1>
1.4 Recombination 17

1.4.2 Recombination-Generation Center Recombination

Recombination-generation (RG)-center recombination is a result of crystal imperfections.

These imperfections include missing atoms from their regular lattice sites, lattice distor-
tions in the vicinity of impurity atoms. As a perfect periodicity gives rise to energy bands
and bandgaps, the presence of crystalline defects disturbs the periodicity of the structure,
resulting in localized energy levels within the bandgap. In contrast to the localized levels
of donors and acceptors, the energy levels of defects and unwanted impurities are not con-
fined to energies close to the band edges. These defect induced localized energy levels are
distributed throughout the bandgap, which facilitate the recombination process by provid-
ing temporary (metastable) states for electrons. Each transition involves fewer phonons
than required for band-band recombination in one step. Clearly, these crystal imperfection
induced energy levels occur near the middle of the bandgap. These are most effective as
recombination centers because the probability of electron capture from the conduction band
is the same as the probability of hole capture from the valence band—Shockley–Read–Hall
recombination process.
The rate of recombination depends on the presence of electrons, holes and traps.
However, the rate limiting step will be the capture of the minority carrier by the trap:
the capture of the majority carrier is far more probable. Thus, for p-type material the
recombination rate is:

RG E N E R AT I O N , R EC O M B I N AT I O N ≃ n N T r ≡ An (1.43c)

where r is the temperature dependent rate constant, N T is the trap concentration and
A is the trap dependent recombination coefficient. The energy and momentum balance
equations are:
< > Σ
E electr on <1> − E hole 1 P = ℏωβ
( < >) Σ (1.43d)
ℏ kelectr on <1> − khole 1 P = ℏ β

1.4.3 Auger Recombination

This is the reverse of the impact ionization electron–hole creation process. The energy and
momentum produced by the electro, hole recombination is transferred to either a second
electron or hole. These excited carriers then lose their energy and momentum by emitting
phonons. The emission process occurs as there an abundance of available states in the
bands. The charge carrier can easily transfer with changes in momentum and energy that
are compatible with the phonon dispersion relationship. When the excited carrier is an
electron, the energy and momentum-balance equations are:
18 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

< > Σ
E electr on <1> − E hole 1 P = ℏωβ
( < >) Σ (1.44a)
ℏ kelectr on <1> − khole 1 P = ℏ β

This recombination occurs when one of the carrier concentrations is very high, yet
both carriers are of importance, such as in solar cells. Similar carrier concentrations exist
in the space charge region of LEDs, and in the base of heterogeneous junction bipolar
transistor(HBT)s. Each recombination event, involves one carrier of one type and one
carrier of the complementary type. The recombination rate for the sum of the process. is
the corresponding process involving the excitation of a hole:

R AU G E R = np(Cn + Dp) (1.44b)

where C, D are Auger recombination coefficients.

1.4.4 Recombination Lifetime

The environment inside a semiconductor device is dynamic. Recombination is always

occurring, and at equilibrium, recombination rate must equal electron–hole pair gener-
ation rate. The net rate of recombination out of equilibrium is given, by the difference
between the non-equilibrium and the equilibrium-recombination rates. This net rate is
often denoted as U and has units of per unit time. For radiative recombination,

U R AD = B(np − n 0 p0 ) (1.45a)

where n 0 , p0 are thermal equilibrium values. For a set of ∆n generated electron hole
pairs, the recombination rate is proportional to:

np − n 0 p0 = (n 0 + ∆n)( p0 + ∆n) − n 0 p0 (1.45b)

which can be re-written as:

np − n 0 p0 = ∆n 2 + ∆n(n 0 + p0 ) (1.45c)

Equation 1.45c, modified for p-type semiconductor and low|high injection cases
respectively is:

np − n 0 p0 = ∆n 2 + ∆np0 = ∆np0 (1.45d)

The above set of expressions show how the general case can be modified to the p
type semiconductor (∆n = ∆ p, n 0 << p0 ), and then low level|high injection. The net
electron recombination rate is:
1.5 Carrier Concentrations [9–16] 19

∆n
Uelectr on,R AD I AT I O N = (1.45e)
τelectr on,R AD I AT I O N

where τe,R AD is the electron minority carrier radiative recombination lifetime. The
expressions for the various recombination process lifetimes are:
1 1
τeletr on,R AD I AT I O N = ∨ (1.45f)
Bp0 B( p0 + ∆n)
recombination-generation center:
1
τelectr on,G E N E R AT I O N −R EC O M B I N AT I O N = (1.45g)
A
For Auger recombination in p type material high level injection:
1 1
τelectr on,AU G E R = ( )+ ( ) (1.46h)
C ∆np0 + n 0 p0 + ∆n 2 D 2∆np0 + p02 + ∆n 2

overall
1 1 1
= +
τelectr on τelectr on,G E N E R AT I O N −R EC O M B I N AT I O N τelectr on,R AD I AT I O N
1
+ (1.46i)
τelectr on,AU G E R

1.5 Carrier Concentrations [9–16]

The electron concentration at position r→ and inside a volume Ω is:

1 Σ
r , t) =
n(→ f illed states (1.47a)
Ω
To convert this sum into an integral two key points must be noted.

• Separation over all momentum space k between states in one dimension is 2π/L, where
L is the length of one dimensional crystal lattice.
• Each momentum state in k space can contain two electrons with opposite spins (Pauli
Exclusion Principle).
• An integral over all k states, including empty ones requires a distribution function to
account for the probability of a particular state being occupied

∫ ( )
1 Σ 1 1 → t d k→
r , t) =
n(→ f illed states = f r→, k, (1.47b)
Ω Ω 2π
Ω
20 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

This general equation is not useful. So, the electron concentration in the three dimen-
sional, time-independent case and to simplify the notation, the position identifier is
removed. The above equation becomes:
∫ ( )
1
n= f k→ d k→ (1.47c)
4π 3
The electrons fill up states from the origin to higher values of momentum (correspond-
ing to higher values of wavevector k) → and as the number of available states is huge, the
approximate surface of the actual volume of k-space being filled is a sphere of radius k,
i.e., the distribution function f depends only on the magnitude of k. Therefore, in spherical
coordinates:
˚
1 → 2 sin(θ )dθ dφdk 0 ≤ θ ≤ π 0 ≤ φ ≤ 2π
n= f (k)k (1.47d)
4π 3
This integral evaluates to:
∫
1 k 2 f (k)
n= 4π 2 f (k)dk = = g(k) f (k) (1.47e)
4π 3 π2

here g(k) us the density of states in the k space, with units of km1 3 . As it is easier to
measure energy than wavenumbers, the above integral for the density of states is re-written
as:
∫ ∫
g(E − E C O N DU C T I O N )d(E − E C O N DU C T I O N ) = g(k)d(k) (1.47f)

To evaluate closed form analytical expressions, the parabolic band approximation with
the density of states effective mass is used, for which the kinetic energy of an electron is:
( )
ℏ2 k x2 k 2y k z2 ℏ2 k 2
E − Ê C O N DU C T I O N = + + =
2 m xP m yP m zP P
2m D E N S I T Y O F ST AT E S
(1.47g)

For materials as gallium arsenide, the constant-energy surfaces are spherical for electrons,
the density of states effective mass is the parabolic-band effective mass. In such cases.
the above equations, after some manipulation give the following equations for the energy
dependent conductance and valence band density of states expressions.
√
( ) 8 2√
gC O N DU C T I O N E − E C O N DU C T I O N = 3 E − E C O N DU C T I O N
ℏ
( )
( ) 3
P
m electr 2 E ≥ E C O N DU C T I O N
on,D E N S I T Y O F ST AT E S
√
8 2√
gV AL E N C E (E F E R M I − E) = 3 E F E R M I − E
ℏ
1.6 Thermal Equilibrium and Fermi–Dirac Statistics 21

( )
( ) 3
P
m electr 2 EFE RM I ≥ E (1.47h,i)
on,D E N S I T Y O F ST AT E S

In the densities of states in three dimensional real space increase parabolically with
energy away from the band edges. After some manipulation of the above equations, the
electron and hole concentrations (unit volume) are:
∫ ∫
n = gC O N DU C T I O N f (E)d E p = gV AL E N C E (1 − f (E))d E (1.47j)

For silicon, the energy of electrons in the conduction band is:

( )
ℏ2 k x2 k 2y + k z2
E − E C O N DU C T I O N ,0 = P
+ P (1.47k)
2 m electr on,longitudinal m electr on,transver se

on,longitudinal , m electr on,transver se are longitudinal|transverse electron effec-

P
where m electr P

tive masses. The electron density of states effective mass is:

( ( )2 )0.66
P
m electr on,D E N S I T Y O F ST AT E S = 6.0 0.66 P
m electr on,longitudinal
P
m electr on,transver se
(1.47l)

For holes, for both silicon and gallium arsenide, the density of states effective mass
includes both light|heavy hole effective masses.
(( )1.5 ( )1.5 )0.66
P
m hole,D E N S I T Y O F ST AT E = P
m hole,heavy + P
m hole,light (1.47m)

1.6 Thermal Equilibrium and Fermi–Dirac Statistics

The expression for the density of states for the valence band contains the term for the
Fermi level. A semiconductor under idealized thermal equilibrium is analyzed to under-
stand the Fermi level. Under thermal equilibrium there are no external sources of energy
to excite electrons except for a constant temperature heat source.

1.6.1 Collisions and Scattering

Generation and recombination processes control the carrier concentrations in the conduc-
tion and valence bands. Under thermal equilibrium, the thermally activated band-to-band
and chemical generation processes are active, with possibly one|all of the others: (radia-
tive, recombination-generation center, Auger). For thermal equilibrium, the net sum of
these various generation|recombination rates must be zero. This means that as energy
22 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

(typically heat) is taken from the device to create an electron–hole pair, so that energy
must be returned to the lattice on recombination—energy balance. Under thermal equi-
librium charge carriers in must remain in their lowest energy states within each band. That
is, charge carriers continuously collide with atoms|ions|crystalline defects and dissipate
energy obtained from the external heat source.
If an electron is a wave a collision between it and a lattice atom would be the interac-
tion of the electron wave with a phonon. As the atoms vibrate about their mean positions
with a temperature dependent amplitude, lattice periodicity is disturbed. Then the potential
in the system non-periodic. But, if the potential perturbations are small, the electron wave-
functions can be approximated with Bloch wavefunctions, with different values from those
for a stationary, periodic lattice—both eigenvalues|eigenfunctions change. Physically the
state of the electron will change on interaction with a vibrating atom i.e., the electron
scatters to a new state on interacting with an atom|electron|ion|another|lattice defect.
At low temperatures, when the atomic thermal vibrations are small, ionized impu-
rity scattering is the dominant scattering mechanism. If there are many carriers present,
they can screen other carriers from the attractive or repulsive effect of the impurity ion’s
charge, leading to screened ionized-impurity scattering. If the concentration of carriers is
extremely large, carrier-carrier scattering becomes important. In doped semiconductors at
higher temperatures, phonon scattering dominates. Longitudinal acoustic phonons alter-
nately compress and dilate the lattice; the resulting strain deforms the band edges, leading
to deformation potential scattering. In semiconductors with no crystal inversion symme-
try, e.g.„ gallium arsenide, the strain may generate a potential via the piezoelectric effect,
leading to piezoelectric scattering. Silicon and GaAs both have two atoms per unit cell,
so when these atoms move in opposite directions, optic phonons are generated, leading
to optical phonon scattering.

1.6.2 Fermi–Dirac Statistics and the Fermi Level

The Fermi Dirac statistics is the most probable distribution of electrons among the available
states in the conduction and valence bands. This probability distribution function is evalu-
ated by considering one of the types of collisions (elastic, electron–electron) responsible
for maintaining thermal equilibrium.
Two electrons have respectively energies E 1 , E 2 , E 1P , E 2P before and after an elastic
collision. Then:

E 1P + E 2P = E 1 + E 2 (1.48a)

This collision occur only when there are filled states at energies E 1 , E 2 , and empty
states at E 1P , E 2P . The second requirement is essential to satisfy Pauli’s Exclusion
Principle. The probability of occupancy is denoted as f(E), and the rate of this collision:
1.6 Thermal Equilibrium and Fermi–Dirac Statistics 23

( ( ))( ( ))
r1,1 P :22 P = c f (E 1 ) f (E 2 ) 1 − f E 1P 1 − f E 2P (1.48b)

where C is the rate constant. Thermal equilibrium is preserved anywhere in the lattice
only when electrons with starting energies E 1P , E 2P , and ending energies E 1 , E 2 collide
with the collision rate stated in Eq. 1.48. No collision occurs without filled states at the
starting energies and empty states at the ending energies. This means that:
( ) ( )
r1 P ,1:2 P ,2 = c f E 1P f E 2P (1 − f (E 1 ))(1 − f (E 2 )) (1.48c)

These two collision rates must be the same, by equating the two expressions and
dividing the result by the product is the probability distribution functions at the four
energy values gives:
( )( ) ( )( )
1 1 1 1
−1 −1 = ( ) −1 ( ) −1 (1.48d)
f (E 1 ) f (E 2 ) f E 1P f E 2P

A solution to this expression is of the form:

1
− 1 = Aeβ E (1.48e)
f (E)
To calculate β, a large energy value E is examined. Selecting a a large value of E
ensures that there is a very small probability of quantum states at this energy being filled by
electrons. Therefore:
e−β E
f (E) = << 1 (1.48f)
A
Then the probability of two electrons occupying the same state, is infinitesimally small
(Pauli’s Exclusion Principle)—i.e., these electrons are non-interacting. Exploiting some
basic thermodynamics concepts, the electron distribution function under conditions of
thermal equilibrium is:
1
f F E R M I ,D I R AC (E) = E−E F E R M I
(1.48)
1+e kB T

where E F , k B , T are respectively the Fermi energy level, Boltzmann constant and
absolute temperature in Kelvin.
The Fermi Dirac distribution is the probability of an electron occupying a state of
energy E at thermal equilibrium because it varies in value from 0 to 1. The probability
of occupancy of states with energy E falls off rapidly as E exceeds the Fermi level E F .
In n-type semiconductor material there are many electrons that must be accommodated
in the conduction band. So states will be filled-up to higher energies than in the case of
p-type material. In p-type material, there are few electrons. For higher energy states to
24 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

have a higher probability of being filled, the Fermi level must be raised, i.e., the Fermi
level is higher in energy for n-type material than it is for p-type.

1.6.3 The Fermi Level and Equilibrium Carrier Concentrations

Using the Fermi Dirac distribution, the thermal equilibrium intrinsic electron, hole
concentrations are:
∫
n 0 = gC O N DU C T I O N (E) f F E R M I ,D I R AC (E)d E E C O N DU C T I O N ≤ E ≤ B AN DT O P
∫
( )
p0 = gV AL E N C E (E) 1 − f F E R M I ,D I R AC (E) B AN D B O T T O M ≤ E ≤ E F E R M I
(1.49a,b)

The limits of integration can be taken to be ± infinity, without adding any error. This is
because the Fermi Dirac distribution function evaluates to zero very high in the conduction
band and likewise very large in the valence band at the top, so that 1 − f F D goes to zero.
Then the equilibrium electron concentration becomes:

n 0 = NC O N DU C T I O N F 1 (a F ) (1.49c)
2

where F 1 (a F ) is the Fermi–Dirac integral of order half. The values of this integral is
2
tabulated in standard look up tables. In special cases, when e.g., a < −2, the integral can
be approximated as:

F 1 (a F ) → ea F (1.49d)
2

In the above integral, the material specific constant terms are combined into NC NC
( P
)3
2
2m electr on,D E N S I T Y O F ST AT E S k B T
NC O N DU C T I O N = 2 (1.49e)
ℏ2

Now combining all these results together, the equilibrium electron concentration is:
E F E R M I −E C O N DU C T I O N
n 0 = NC O N DU C T I O N e kB T (1.49f)

This is the Maxwell Boltzmann equation. The corresponding expression for the holes
is:
E V AL E N C E −E F E R M I
p0 = N V AL E N C E e kB T (1.49g)

The above expressions can be modified to provide information about intrinsic carrier
concentrations in a semiconducting material.
1.6 Thermal Equilibrium and Fermi–Dirac Statistics 25

E F E R M I ,I N T R I N S I C −E C O N DU C T I O N
n I N T R I N S I C = NC O N DU C T I O N e kB T

E V AL E N C E −E F E R M I ,I N T R I N S I C
(1.49h)
p I N T R I N S I C = N V AL E N C E e kB T

where E G A P = E C − E V / In an intrinsic semiconductor, n I N T R I N S I C = p I N T R I N S I C so

that the above two expressions can be equated, to give the intrinsic electron concentration:
√ −E F E R M I
nI NT RI N SIC = NC O N DU C T I O N N V AL E N C E e 2k B T (1.49i)

The intrinsic Fermi level and the valence band energy are related as:
( P )
EG A P 3k B T m hole,D E N S I T Y O F ST AT E S
E F E R M I ,I N T R I N S I C − E V AL E N C E = + ln P
2 4 m electr on,D E N S I T Y O F ST AT E S
(1.49j)

From the above expressions it is clear that the intrinsic concentration is a temperature-
dependent material constant, and that the intrinsic carrier concentration decreases as the
bandgap increases, independent of the Fermi energy:

n 0 p0 = n I N T R I N S I C p I N T R I N S I C = n 2I N T R I N S I C (1.49k)

These expressions hold for moderately doped, non-degenerate semiconductors only.

The charge balance expression is:

q( p0 + N D O N O R − n 0 − N ACC E P T O R ) = 0 (1.49l)

The mean velocity of an equilibrium distribution can be estimated from information

presented above. The analysis exploits the “velocity-sphere” approach to estimate the
average x-directed velocity. The radius vth is the mean thermal speed. Electron velocities
are randomly distributed in direction and the number of electrons with velocities in the
range θ to θ + dθ is related to the area of a strip of length 2π vth sin(θ ) and width vth dθ .
To express this as a fraction of the total number of electrons, divide by 4π vth 2 to get
sin(θ )dθ π
2 and then integrate over 0 ≤ θ ≤ 2 . The result is the mean unidirectional velocity.
The equilibrium carrier concentration for electrons is:

n 0 (E) = gC O N DU C T I O N (E) f 0 (E) (1.49m)

which after simplification with the Maxwell–Boltzmann distribution is:

n 0 EC O N DUk CTT I O N −E
f M AX W E L L−B O L T Z M AN N = e B (1.49n)
NE
19
The result for n 0 = 10
cm 3
is shows that the distribution is split into two. The distribution
on the right is for the electrons with positive crystal momentum, i.e., velocity component
26 1 Fundamental Quantum and Statistical Mechanics of Crystalline Solids

in the positive x-direction. The part on the left is its oppositely directed or complemen-
tary part. Each half of the distribution contains exactly n20 electrons, and is termed a
hemi-Maxwellian (hemispherical Maxwellian). At any plane in the material, the flow of
electrons in the positive going distribution will be opposed by the flow of negative going
electrons from a neighboring distribution. So there is no net current. However, if the con-
ditions in a device were near-equilibrium, due to a non-uniform doping density, then the
opposing charge flows at an intermediate plane would not cancel, resulting in current-
diffusion. Current flow due to a near-equilibrium hemi-Maxwellian or hemi-Fermi–Dirac
(hemispherical Fermi–Dirac) can arise due to injection of carriers into the base of an
HBT(Heterogeneous Bijunction Transistor) or into the channel of a FET. To compute the
current, the mean speed of the electrons in the total distribution in thermal equilibrium is
needed—given by:
∫
− n 0 (v)vdv
vmean,ther mal equilibrium = ∫ 0≤v≤∞ (1.49o)
n 0 (v)dv

where n 0 (v) is the number of electrons per volume per unit velocity. The denominator is
the total electron concentration. Recognizing that:

m CP O N DU C T I V I T Y v 2
E − E C O N DU C T I O N = (1.49p)
2
the expression for the equilibrium thermal mean velocity is, after some manipulation:
/
8k B T F1
vmean,ther mal equilibrium = P
(1.49q)
F
m C O N DU C T I O N 1
2

Mean drift velocity and drift current relation Is simple:

( )
J→electr on,P LU S = −qn 0 v R x̂ J→electr on,M I NU S = −qn 0 v R −x̂ (1.49r)

where ‘PLUS’ and ‘MINUS’ refer to the positive and negative x directions.

References

1. Griffiths, D. J., & Schroeter, D. F. (2019). Introduction to quantum mechanics. Cambridge

University Press.
2. Feynmann, R. P., Leighton, R. B., & Sands, M. L. (1989). The Feynman Lectures on Physics
(Vol. 1). Addison Wesley.
3. Susskind, L., & Friedman, A. (2015). Quantum mechanics: The theoretical minimum. Amazon
Books.
4. Sakurai, J. J., & Napolitano, J. (2020). Modern quantum mechanics. Cambridge University
Press.
5. Nouredine, Z. (2009). Quantum mechanics: Concepts and applications. Wiley.
References 27

6. Shankar, R. (2012). Principles of quantum mechanics. Springer Science & Business Media.
7. Matthews, P., & Venkatesan, K. (1978). A textbook of quantum mechanics. Tata McGraw Hill.
8. Huang, K. Introduction to statistical physics (2nd ed.). ISBN 10 9781420079029; 13 978–
1420079029.
9. Reichl, L. E. (2016). A modern course in statistical physics. Wiley VCH. ISBN 10 3527413499;
13 978-3527413492.
10. Landau, L. D., & Lifschitz, E. M. Statistical physics, Part 2, Course of Theoretical Physics (3rd
ed., Vol. 5). ISBN 10 0750633727; 13 978-0750633727.
11. Beale, P. D. Statistical mechanics (3rd ed.). ISBN 10 0123821886; 13 978–0123821881.
12. Kittel, C., & Kroemer, H. Thermal physics (2nd ed.). ISBN 10 0716710889; 13 978-
0716710882.
13. Griener, W., Neise, L., Stocker, H., & Rischke, R. Thermodynamics and statistical mechanics
(Classical theoretical physics). ISBN 10 0387942998; 13 978-0387942995.
14. Sze, S. M., & Ng, K. K. Physics of semiconductor devices. Copyright © 2007 John Wiley &
Sons, Inc. All rights reserved. Print ISBN 9780471143239, Online ISBN 9780470068328.
https://doi.org/10.1002/0470068329
15. Streetman, B., & Banerjee, S. K. (2013). Solid state electronic devices: Pearson new interna-
tional edition. Pearson Education Limited. ISBN 10 1292025786; 13 9781292025780.
16. Pullfrey, D. (2013). Understanding modern transistors and diodes. Cambridge University Press.
ISBN 13 978-0521514606.
Charge Transport (Current Flow)
in Semiconductors
2

2.1 General Concepts

From the previous chapter, electrons and holes move through the semiconductor in
momentum states. These carriers are both continually generated, annihilated and scat-
tered to new momentum states (collisions with vibrating atoms, ionized impurities, inter
carrier scattering etc.,). In thermal equilibrium large charge carrier fluxes are present, but
no net current flows. This equilibrium is broken to get a non-zero net flow of charge only
when a driving force within the semiconductor is introduced, in the form of an energy gra-
dient. This energy gradient is related to the electrostatic potential ψ, as well as a kinetic
energy gradient. If each of the n electrons per unit volume have a kinetic energy u, the
total kinetic energy density W is nu. This is dissipative transport, i.e., the directed momen-
tum of electrons injected into a region from a hemi-Maxwellian distribution, is dissipated by
scattering events. If the region is so short that the injected electrons can traverse it without
scattering, then it is ballistic transport. Ballistic transport occurs in tunnelling nanoscale
devices.

2.2 Relation Between Charge, Current and Energy [1–8]

The fundamental definitions of charge, current and energy densities can be obtained using
very simple physical concepts. To simplify the analysis, parabolic bands with an isotropic
effective mass, is assumed. The electron charge density is:
∫ ( )
−q
−qn = f k→ d k→ (2.1)
4π 3

Defining the x direction velocity as vx = dE

ℏdk x the x direction current flux is:

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 29

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_2
30 2 Charge Transport (Current Flow) in Semiconductors

∫ ( )
−q
J→electr on,x = vx f k→ d k→ (2.2)
4π 3
and the corresponding energy density is:
∫ ( )
1
Welectr on,x = P
m electr on v 2
x f k→ d k→ (2.3)
8π 3
( )
m P v2 → t , that
which includes the kinetic energy term ( 2 x ). The distribution function f r→, k,
accurately describes the non-equilibrium conditions necessary for a net current, is a dif-
ficult to determine analytically. So an equation is formulated that describes how the
distribution function changes in both real space and in k-space.

2.3 The Boltzmann Transport Equation

The full six dimensional r→, k→ space is called phase space [1–7]. The following analysis
uses the two dimensional sub-space x, k x . The crystal momentum ℏk is the momentum
due to forces other than the periodic crystal forces. These external forces determine the
functional form of f (x, k x , t) as the probability of an electron at position x having a
momentum ℏk x at time t. The subsequent analysis uses the semi-classical model of the
electron, since by Heisenberg’s Uncertainty Principle, it is impossible to determine the
position and momentum of an electron simultaneously. The classical electron is compat-
ible with the effective-mass formalism in which the group velocity of a wave packet is
involved. Group velocity introduces elements of quantum mechanics.
An applied force Fx acts on an electron which moves a distance vx ∆t in time ∆t where
the x-direction velocity is vx = ℏdk dE
x
. The electron’s momentum changes, Fx = ℏ ∆k x
∆t .
As the electron moves from one state in to another state in the same phase space, the
probability of occupancy of these two states must be equal.
( )
Fx ∆t
f (x, k x , t) = f x + ∆x, k x + , x + ∆x (2.4)
ℏ

In the limit ∆t → 0 Eq. 2.4 is expanded in a Taylor’s series and re-written as:
( )
∂f vx ∂ f ∂ Fx ∂ f
=− + (2.5)
∂t ∂x ∂ x∂k x

The external force is due to an applied electric field E x which makes the electrons
collide with a force Fx,coll , so that:
I
∂ f II −∂ f Fx,collision
I = (2.6)
∂t collision ℏ∂k x

Now, combining all the forces gives the Boltzmann Transport equation:
2.3 The Boltzmann Transport Equation 31

I
∂f −vx ∂ f q∂ E x ∂ f ∂ f II
= + + (2.7)
∂t ∂x ℏk x ∂t Icollision

The method of, moments is used to solve this equation indirectly, so that useful
expressions for charge density, current density and kinetic-energy density can be obtained
without very complicated mathematical manipulations. The method of moments consists of
d k→
multiplying each term of the above equation by some factor Υ and integrating over 4π 3.
The velocity vx is included in Υ and the resulting moments are labelled according to the
power to which vx is raised. The goal is to solve for: −qn using the 0th order moment,
J→electr on using the first order moment, followed by solving for Welextr on using the second
order moment.
Introducing a dummy variable Φ that can represent any of the quantities
−qn, J→electr on , Welectr on etc., depending on moment order, the Boltzmann Transport
equation is transformed to:
∂Φ
+ ∇ · J→Φ = G Φ − RΦ (2.8)
∂t

where the flux of Φ is J→Φ , and G Φ , RΦ respectively the generation|annihilation rates of

Φ. The order of the terms above is different from that in the original equation, and is in
three dimensional form to distinguish between divergence and gradient. The reformulated
transport equation has a clear physical interpretation: the difference between generation
and loss of Φ in a volume increases it with time, or outward flow.

2.3.1 Method of Moments Solution of Boltzmann

Equation—Continuity Equations [1–11]

The first three generated moments, from the Boltzmann Transport equation contain the
required key information and are examined in detail. For charge density, there is no gener-
ation or loss term. The electric field does not generate any charge, and there is no scattering
loss: the energy loss from collision is redistributed amongst other allowed momentum states.
The charge density continuity equation is:
∂n ∂ Jelectr on
= (2.9)
∂t q∂ x
The current density continuity equation exploits the physical fact that current is gener-
ated by the external applied electric field, and lost due to scattering—momentum loss. The
momentum loss is characterized by the momentum relaxation time τ M . The time depen-
dency of the current, after removal of the external applied field, must be of the form
−t
J→(t) = J→(0)e τ , so that the current density variation with time is:
32 2 Charge Transport (Current Flow) in Semiconductors

d J→ − J→(t)
= = −RΦ (2.10)
dt τM
The expression for τ is obtained by replacing RΦ in the first order moment term
involving ∂∂tf :
∫ −
→ I
− kx f d k ∂f I
<<τ M >> = ∫ I
→ K K = ∂t
− I (2.11)
kx K K d k collision

where the double averaging term is very important. J→Φ in the first-involves vx2 , which
is related to the x-direction kinetic energy density. Therefore, ∇ · J→Φ is a flux of kinetic
energy density. Thus, the first order moment equation is that if the loss of x direction
momentum due to scattering is greater than the gain of x direction momentum due to
the field, then to maintain the steady state, there must be a net inflow of kinetic energy.
In the kinetic energy–density continuity equation the generation term is the product of
the current density and the field, i.e., the electrons in J→electr on,x are accelerated by E x ,
thereby gaining kinetic energy. This kinetic energy gain is dissipated by scattering events.
The total kinetic energy is randomized. The scattering events are embodied in an averaged
energy relaxation time τ E .

2.3.2 Drift Diffusion Equations

The Drift Diffusion equation pair is used by semiconductor design engineers to do the
first-cut design. The Drift equation applies when there is an electric field and zero charge
carrier concentration gradient. On the other hand, the Diffusion equation describes the
situation when there is a charge carrier concentration gradient and zero electric field
gradient. Normally charge carrier movement in a semiconductor device has both drift and
diffusion contributions, with one dominating the other. Electron kinetic-energy density is
a result of concentration of n electrons, in where each electron possesses some kinetic
energy. In one dimension for a total of n electrons:
∫
1 −
→
Welectr on,x = n · x K I N E T I C E N E RGY = 3
P
m electr on vx f d k
2
(2.12)
8π
defining <u x > as the averaged kinetic energy of the electron in the x direction:
∫
1 →
<u x > = P
m electr on vx f d k
2
(2.13a)
8nπ 3
The derivative of the total electron kinetic energy with respect to x is:
( )
dWelectr on,x dn d<u x >
= <u x > +n (2.13b)
dx dx dx
2.3 The Boltzmann Transport Equation 33

−2qdW electr om,x

and so the divergence term is mP dx
.
The Drift Diffusion equation is based on the notion that the contribution to the
kinetic energy density gradient from the spatial change in the electron concentration
is much larger than the contribution from any spatial change in the average kinetic
energy of each electron. Then in steady state, the the Drift Diffusion equation becomes:
( )
→ → dn
Jelectr on,x = q nμelectr on E + Delectr on (2.14)
dx

where the electron mobility and diffusivity terms are:

q<<τ M >> 2μelectr on <u x >

μelectr on = P
Delectr on = (2.15a,b)
m electr on
q

The expression for diffusion Is also called the Einstein Relation, and reduces to
Delectr on
= k BqT when the mean, x-directed kinetic energy is u x = k B2T . These expressions
μelectr on
hold for low doping densities under near-equilibrium conditions. Electron mobility is a
statistically estimated macroscopic property obtained by aggregating the microscopic
scattering of individual electrons specified by the average momentum relaxation time.
The approximation underlying the above Drift Diffusion equation is justified in situations
where the regions of a device is long enough for any gradients in u x due to injection
of energetic carriers from a neighboring region. These assumptions are inapplicable to
state-of-the-art ultra small dimension (e.g., sub-micron gate length MOSFET) devices.

2.3.3 Hydrodynamic Transport Equations

Moving from the idealized one dimensional situation to a more realistic configuration,
when component of the gradient in kinetic energy density cannot be ignored, the second
order of continuity equation must be used. To fully exploit the continuity equation for W
the flux of kinetic energy density S must be estimated first. S is the product of W and
some velocity that describes the electron ensemble. This velocity has a component due
to the applied field, and a component due to the scattering processes. The ideal electron
gas model is used and components due to the external applied field are neglected. The
electrons’ kinetic energy is related to their random motion. In analogy with the Kinetic
Theory of Gases, electron kinetic energy is characterized by a temperature—electron tem-
perature Tekectr on . At equilibrium, the electron and lattice temperatures are the same. Then
the electron kinetic energy, as a junction of the temperature is:
nk B Telectr on
Welectr on,x = n<u x > ≈ (2.16)
2
The drift component of the electron energy is ignored, so that the kinetic energy density
flux or power density S is a diffusive flow, which depends on the gradient of the electron
34 2 Charge Transport (Current Flow) in Semiconductors

temperature:
−κelectr on ∂ Telectr on
Selectr on,x ≈ (2.17)
∂x
where κelectr on is the thermal conductivity of the electron gas.
Applying the above expression to the previous first order expressions, in combination
with the current continuity equation, gives a revised expression for the steady-state current
density:
( ( ))
dn dTelectr on
Jelectr on,x = μelectr on n E x q + k B Telectr on +n (2.18)
dx dx

Some manipulation with the above expressions gives the kinetic energy density
continuity equation:

∂ Welectr on,x ∂ 2 Telectr on k B (Telectr on − Tlattice )

− κelectr on = Jelectr on,x E x − (2.18a)
∂t ∂x2 2<<τ E >>
Combining the above equations and concepts in an unified set of equations are the
hydrodynamic continuity equations based on the concept of electron gas—hydrodynamic:
∂n ∂ Jelectr on
= (2.18b)
∂t q∂ x
( )
∂ Jelectr on,x q ∂ Welectr on,x Jelectr on,x
= P + nq E x − (2.19)
∂t m electr on ∂x <<τ M >>

2.3.4 Semiconductor Device Design Equations

The hydrodynamic equations are the basis for a master set of equations to design and
analyse semiconductor devices devices with a semiclassical approach. The first and third
equations in the set of hydrodynamic equations describe the conservation of charge den-
sity and kinetic energy density of electrons only in the conduction band. To generalize
these equations for real world semiconductor devices, additional terms that allow for
interband transfer of electrons are required, to account for recombination and genera-
tion processes. The charge continuity equation must include generation of charge carriers
from optical and impact-ionization processes. The sum of the effects of these processes
is denoted as G optical,inpactionisation . Thermal generation and recombination mechanisms
are combined in a net recombination rate U. This introduces an additional term in the right
hand side of the kinetic energy density equation given by G optical,impact ionisation − U .
The continuity equation for kinetic energy density must also include recombination and
generation as these processes change the number of carriers in a band and the kinetic
2.3 The Boltzmann Transport Equation 35

energy density. Recombination of one electron removes 3k N Telectr

2
on
of kinetic energy from
the electron ensemble in the conduction band. Impact-ionization generation involves a
loss of kinetic energy by one electron, accompanied by the boosting of another electron
to the conduction band, so now two electrons can gain energy from the field. The overall
change in kinetic energy density due to recombination and generation is
3k B TC H A RG EC A R R I E R U
H= + E G A P G I M P AC T I O N I Z AT I O N (2.20)
2
Recombination, generation processes involve electrons and holes, so a separate set of
equations is needed to express conservation of hole charge, and kinetic energy density.
Like the second equation in the hydrodynamic set(continuity of electron flow|current den-
sity), a corresponding equation for holes is essential. Also, the concentrations of electron
and hole charge densities, −qn|qp respectively could lead to local space charge, perturb-
ing the electrostatic potential ψ. Thus, Poisson’s Equation must be added to the master
set.
⇀ − →
−∇ · J electr on
= G O P T I C AL I M P AC T I O N I Z AT I O N − Uelectr on
q
⇀ −
(2.21a,b)
→
−∇ · J hole
= G O P T I C AL I M P AC T I O N I Z AT I O N − Uhole
q
( )
k B Telectr on ∇n
J→electr on = nμelectr on + k B Telectr on − q∇ψ
n
( ) (2.22a,b)
k B Thole ∇ p
J→hole = pμhole + k B Thole + q∇ψ
p
→ · (κelectr on ∇Telectr on ) = E G A P G electr on,I M P AC T I O N I Z AT I O N
−∇
( )
3k B n(Telectr on − Tlattice )
+ U Telectr on − − J→∇electr on · ∇ψ
2 <<τ E >>
→ · (κhole ∇Thole ) = E G A P G hole,I M P AC T I O N I Z AT I O N
−∇
( )
3k B n(Thole − Tlattice )
+ U Thole − − J→hole · ∇ψ (2.23a,b)
2 <<τ E >>
q
∇2ψ = ( p + N ACC E P T O R − n − NDONOR ) (2.23c)
ε
Generation|recombination terms G,U in the charge continuity equations depend on the
carrier concentrations n,p. The parameters μ and energy relaxation time τ E are material
properties, so can be determined experimentally. Energy relaxation time and the carrier
thermal conductivities are dependent on carrier temperature, and the mobility is field
dependent, since the momentum relaxation time τ M is dependent on the applied force.
36 2 Charge Transport (Current Flow) in Semiconductors

These dependencies can be expressed empirically, or derived from detailed theoretical

calculations. The two assumptions underlying the above set of design equations.

• Carrier transport is semi-classical, as Newton’s Laws were used to formulate the

Boltzmann Transport equation.
• Kinetic energy density contribution to W of the average velocity that the carriers might
have is neglected.

The set of equations consists of five independent equations in five unknowns, n, p,

Telectr on , Thole , and ψ. The set has to be solved numerically. Even though the car-
rier temperatures Telectr on , Thole are functions of position, the lattice temperature is
constant—isothermal equation set. Spatial variation in the lattice temperature a lattice
energy balance equation is needed. A real semiconductor has physical heat dissipation
mechanisms A simple expression for heat balance in the steady state is:
( ) ( )
−∇ · κ M AT E R I AL ∇ T→lattice = E→ · J→electr on + J→hole (2.24)

2.3.4.1 Electron and Hole Mobility

Mobility is defined in terms of the average momentum relaxation time τ M . An applied
force changes momentum, and since some scattering mechanisms are momentum depen-
dent, mobility is be field dependent—electrons are accelerated by an electric field, and
move to new momentum states. In the parabolic band approximation, the field moves
electrons to new velocities. The average of these field related velocity changes is the drift
velocity. From the current density expressions, the component of current that is directly
related to the electric field is, for the electron current, qnμelectr on E. The electron drift
velocity is:
I I
I → II def
= μelectron E
velectron,DRIFI (E) = Ivelectron, DRIFT ( E) (2.25)

The drift velocity for electrons is in the opposite direction to the applied electric field.

2.3.4.2 Conductivity Electron, Hole Effective Masses

The definition of mobility includes effective mass. For a single, spherical constant energy
surface, as utilized in the drift diffusion and hydrodynamic equations, the relevant effec-
tive mass is the band effective mass. For multiple spherical surfaces in the valence band,
and multiple prolate spheroids in the conduction band of Si, a modified definition for
mobility is needed. To derive this modified definition of mobility, the expression for the
material conductivity must be re-written Its value is given by the ratio of the drift current
density to the electric field:
2.3 The Boltzmann Transport Equation 37

1
σ = = q(nμelectr on + pμhole ) (2.26)
ρ
The unit is Mho.
In both Si and GaAs, there are two (light|heavy) hole bands. Both are degenerate at
the top of the band. If the average momentum relaxation times are the same for holes in
both of these bands, then the hole conductivity is:
( )
def J→hole, DRIFT p heavy hole p light hole
σhole = = q 2 <<τ M >> + p
E→
p
m heavy hole m light hole
( )
pheavy hole + plight hole
= q <<τ M >>
2
p (2.27)
m hole,CONDUCTION

The corresponding conductivity effective masses for holes is:

⎛ / / ⎞
m P m P
1 ⎜ heavyhole lighthole ⎟
P
= ⎝( )1.5 + ( )1.5 ⎠ (2.28)
m hole,C O N DU C T I O N P
m heavyhole P
m lighthole

Using similar reasoning as above, the conductivity and conductivity effective mass for
electrons in silicon is:

def J→electron, DRIFT

σelectron =
E→ ( )
1 2
= nq <<τ M >>
2
p + p
3m electron LONGITUDINAL m electron, TRANSVERSE
( )
1
= nq <<τ M >>
2
p (2.29)
3m electron, CONDUCTION

2.3.4.3 Drift, Diffusion and Thermal Currents

The electron|hole drift current densities based on mobility arguments, are as below.
Although the current densities are in the same direction, the electrons and holes move
in different directions.

J→electr on,D R I F T = −qnμelectr on (E)∇ψ = qnμelectr on (E) E→ = −qn

(2.30)

The actual distribution of the carriers in k-space is not explicit in these equations:
it is implicitly taken into account in either the expressions for the mobility or the drift
velocities, both as functions of the applied electric field. The drift current expressions can
be used when the distribution function is different from its equilibrium form.
38 2 Charge Transport (Current Flow) in Semiconductors

At low fields, e.g., 100 V/cm, the distribution of carriers is slightly perturbed from its
equilibrium value. Each electron in a velocity state (parabolic bands) of could be shifted
to a state mℏkP + v D R I F T due to acceleration by the field between collisions. Denoting the
forward| backward-going parts of the distribution by ‘RIGHTDIR|LEFTDIR’

J→electr on,D R I F T = J→electr on,D R I F T ,R I G H T D I R + J→electr on,D R I F T ,L E F T D I R

= nq −→v electr on,D R I F T (2.31)

where n, not n 0 , is used to denote small perturbation from equilibrium. The electron
distribution is described in these conditions by a quasi Fermi energy. The distribution in
this low field case is called a displaced Maxwellian. The velocity distribution function is:

n0
P
m electr (
on,C O N DU C T I O N v−velectr on,D R I F T )2
f (v) = e 2k B T (2.32)
NC O N DU C T I O N
The carrier concentration in this small perturbation case is function of drift velocity
and is approximately:
( )1.5
P
8π m electr m P
on,D E N S I T Y O F ST AT E S electr on,C O N DU C T I O N v2
n 0 (v) = P v2
(2.33)
m th E−E C O N DU C T I O N
h3e 2k B T e kB T

The diffusion electron and hole current densities are:

J→electr on,D I F FU S I O N = k B Telectr on ∆n J→hole,D I F FU S I O N = k B Thole ∆ p (2.34)

where the quantity k B Telectr on , k B Thole measures the mean kinetic energy of each car-
rier. This means that a kinetic energy gradient and therefore a kinetic energy and charge
flow is set up at constant electron|hole temperature. For a given concentration gradi-
ent electrons|holes diffuse in the same direction, but the current densities have opposite
signs.:Like the drift velocity current, the distribution function is not the same as for the
equilibrium case. Likewise, the diffusion currents differ from equilibrium or near equilib-
rium currents. For quick analysis, diffusion currents can be considered to originate from
equilibrium distributions. Let two Maxwellian distributions with different electron con-
centrations n 1 , n 2 be separated by a distance 2 l. The current density at an intermediate
plane at x = 0, is:

J→electr on = −qn(n 1 − n 2 ) (2.35)

The two distributions have to be close enough so that the electrons from each can cross
the plane at x = 0 without collisions. Collisions change the distributions. The mean
distance between collisions is called the mean free path. The concentration difference
n 1 −n 2
2 is calculated by a first order Taylor’s series expansion about the plane x = 0.
2.4 Ballistic Transport of Charge Carriers 39

ldn
n 2 = n(0) + (2.36)
dx
n1
Now, using the expression for 2 the final expression for the diffusion current density
is:
Here two Maxwellian distributions have produced a net current, apparently incon-
sistent as Maxwellian distributions are equilibrium distributions, and a net current
is not allowed. This means that if there were a diffusion current at equilibrium, then
it would be negated by a current due to some other mechanism, e.g., np junction at
equilibrium.

d n→
J→electr on,D I F FU S I O N = q Delectr on (2.37a)
dx
The thermal currents in a semiconductor are
−
→
J→electr on,T H E R M AL = k B Telectr on μelectr on ∇ Telectr on (2.37b)

J→hole,T H E R M AL = −k B Thole μhole ∇T

→ hole (2.37c)

These currents exist when neighbouring carrier ensembles have different average
kinetic energies—the injection of high energy electrons into a p-type region in which
the existing carriers are at near equilibrium. Gradually the hot electrons cool towards the
near equilibrium distribution by scattering and recombination. The newly created elec-
tron temperature gradient drives the injected carriers forwards. Thermal current occurs in
HBTs and HEMTs operating at high currents.

2.4 Ballistic Transport of Charge Carriers

Previously considered drift, diffusion and thermal currents are a consequence of scat-
tering that dissipates any momentum imparted to charge carriers by an applied force.
Ballistic|collisionless transport occurs in regions of a semiconductor that are shorter
than the mean free path l. The mean free path in near equilibrium conditions is:
k B Tlattice μ0 k B Telectr on μ
Delectr on = = (2.38)
2qv R q
where the subscript ‘0’ indicates near equilibrium with a low applied field. The electron
gas is in equilibrium with the lattice.
2
For very low doping densities μ0 is about 1300 cm V s for Si, and about six times larger
for GaAs. For typical values of 2v R at low doping and lattice temperature 300 K is
approximately 107 cms for Si, and about twice this value for GaAs. Then l0 is about 30 nm
for Si and about 100 nm for GaAs, and are inversely proportional to the doping density.
40 2 Charge Transport (Current Flow) in Semiconductors

Ballistic charge transport is a consequence of quantum mechanical tunnelling. A real

world semiconductor device (e.g., MOSFET) is analyzed to explain how ballistic transport
works. A potential profile consists of two regions of constant potential energy, U1 and
U3, which are separated by a thin barrier, with a triangular top, as e.g., the potential
profile in the oxide of a MOSFET. Quantum mechanics permits an electron in region
1 to tunnel through the barrier to region 3—wave particle duality. For an electron with
wavefunction Ψ the corresponding probability density is ΨΨ P and the time rate of change
of this probability density as the electron tunnels from region 1 to region 3 is (using the
effective mass form of the Schrodinger equation and neglecting envelope function)

dP ψ∂ψ P ψ P ∂ψ
= +
dt dt( ( dt ) ( ))
ℏ2 ∇ 2 ψ ℏ2 ∇ 2 ψ P
= − jℏ ψ P
U (x) − P
+ ψ U (x) − P
(2.39a)
2m electr on 2m electr on

The probability density current J→P is related to the time rate of change of probability
as:
dP − jℏ ( )
= P
∇ · ψ P
∇ψ − ψ∇ψ P
= −∇ · J→P (2.39b)
dt 2m electr on

The key metric is the transmission probability that controls whether an electron in
region 1 will tunnel into region 3. This is the same as computing the probability density
current. Schrodinger’s wave equation, using the effective mass, and valid from regions 1
to 3 is:
ℏ2 d 2 ψ
(U − E)ψ − P 2
=0 (2.39c)
2m electr on d x

The two boundary conditions are that the wavefunction be continuous at each boundary
and the product of the reciprocal of the effective mass times the first derivative of wave
function is continious across each boundary/ The potential U has no time dependency.
The solutions in the three regions are:

ψ1 (x) = Ae jk1 x + Be− jk1 x ψ2 (x) = Ce− jk2 x + De jk2 x ψ3 (x) = Fe jk3 x (2.40)

where the parameters are:

/ / /
2m 1P (E − U1 ) 2m 2P (E − U2 ) 2m 2P (U2 − E)
k1 = k2 = k2P =
ℏ/ ℏ ℏ (2.41a,b)
2m 3 (E − U3 )
P
k3 = k1 , k2P , k3 r eal k2 imaginar y
ℏ
2.4 Ballistic Transport of Charge Carriers 41

The constants A, B, C, D and F are evaluated using the boundary conditions. The
probability density in the first region is purely oscillatory, inside potential barrier region
exponential and in region 3 oscillatory. Physically, a wave enters region 1 and propagates
sinusoidally. When it enters the potential barrier region. its magnitude is reduced
exponentially as it traverses the barrier region—an evanescent wave. If the barrier
region is thin and some fraction of the probability density wave exits the barrier into
region 3. So relative amplitudes can be calculated. The probability density currents are

ℏk1 |A|2 ℏk3 |F|2

J P,A = J P,F = (2.42)
2m 1P 2m 3P

The transmission coefficient is:

k1 m 1P |A|2
T = (2.43)
k3 m 3P |F|2

The analytical|functional form of the transmission coefficient is very difficult to

compute. Using simplifying assumptions, the following simpler expressions are:
/
−2d
ℏ 2m 2P (U2 −E)
16e
T = ( )2 (2.44a)
kPm k3 m 2
4 + k21 m 21 −
k2P m 3

This expression is simplified further, using more simplifying assumptions:

/
−2d
2m 2P (U2 −E)
T =e ℏ (2.44b)

As expected, these simplified expressions for the transmission coefficient are inaccu-
rate, and the best estimates for the transmission coefficient are obtained by carefully
analyzing experimental data. It is left for the interested reader to determine what
simplifying assumptions were used to derive the above expressions.
The above concepts are easily extended to transitions from a continuum of states. The
electrons in region 1 are not confined and E C is flat. The fundamental expression for the
x-directed current density in region 1 multiplied by the transmission probability gives the
expression for the x-directed electron current density in region 3.
∫ ( )
−q
J→electr on,x = Ttunnelling (k x )v x f k→ d k→ (2.45a)
4π 3
Assuming that:
P
m 1,y = m 1,z
P
= mO
P
RT H OG O N AL (2.45b)

the energy can be simplified as:

42 2 Charge Transport (Current Flow) in Semiconductors

( )
ℏ2 k 2y + k z2
E = Ex + P
(2.45c)
2m O RT H OG O N AL

Transforming to polar coordinates, the expression for the electron current density in
the x direction becomes:
∫ ∫ ( P )
−q m O RT H OG O N AL f (E)d E
Jelectr on,x = Ttunnelling (k x )vx dk x
2π π ℏ2
0 ≤ k x ≤ ∞ E O RT H OG O N AL ≤ E ≤ ∞ (2.46)

The second integral represents an areal density. It is the density of electrons n 2D in

the two dimensional sheet of electrons at the insulator semiconductor interface having
an energy E x i.e., each of the electrons spread across the surface that has energy E x
has a probability of tunnelling T (k x ) with a velocity vx . The integral solved by variable
substitution, gives:
( E F E R M I −E x
)
m 2O RT H OG O N AL k B T ln 1 + e kB T

n 2D (E F E R M I − E x ) = (2.47)
π ℏ2
Applying another appropriate change of variables, (left as an exercise for the interested
reader) the current density is:
∫
−q
J= Ttunnelling (E x )n 2D (E F E R M I − E x )d E x U1 ≤ E x ≤ ∞ (2.48)
ℏ
These arguments can be extended to quasi bound states. This is left as an exercise for
the reader.

References

1. https://doi.org/10.1007/978-3-7091-6963-6
2. https://doi.org/10.1007/978-3-030-35993-5
3. Jerome, J. W. Analysis of charge transport: A mathematical study of semiconductor devices.
ISBN 10 3642799892 ISBN 13 978–3642799891
4. Ferry, D. Semiconductor transport (1st ed.). Published March 16, 2000 by CRC Press ISBN
9780748408665.
5. El-Saba, M. Transport of information-carriers in semiconductors and nanodevices. ISBN 13
9781522523123 ISBN10 152252312X EISBN13: 9781522523130
6. Scholl, E. Nonlinear spatio-temporal dynamics and chaos in semiconductors. Online ISBN:
9780511524615.
7. Blokhin, A. M., et al. Qualitative analysis of hydrodynamical models of charge transport in
semiconductors. Nova Science Publishers Inc ISBN: 9781617617911, 9781617617911.
8. Askerov, B. M. (1994). Electron transport phenomena in semiconductors. World Scientific.
References 43

9. Brennan, K. F., & Ruden, P. P. Topics in high field transport in semiconductors. ISBN 10
9810246714 ISBN 13 978-9810246716.
10. Seeger, K. H. Semiconductor physics. ISBN: 978-3-662-02576-5 https://doi.org/10.1007/978-3-
662-02576-5
11. Pullfrey, D. (2013). Understanding modern transistors and diodes. Cambridge University Press.
ISBN 13 978-0521514606.
Homogeneous (np) and Heterogeneous (Np)
Semiconductor Junction Fundamentals
3

3.1 Homogeneous and Heterogeneous Semiconductor Junctions

[1–7]

• A homogeneous semiconductor junction is created when the base material on the two
sides of a semiconductor junction is the same—e.g., n doped silicon in contact with p
doped silicon.
• A heterogeneous semiconductor junction is created when the base material on two
sides of the junction are different—e.g., galliun nitride (GaN) in intimate contact with
aluminum arsenide (AlAs). The doping type on the two sides of the junction could be
either n or p.
• A homogeneous semiconductor junction is denoted np and a heterogeneous semi-
conductor junction as e.g., Np. For a heterogeneous semiconductor junction, the
uppercase letter denotes the doping type of the side with the larger bandgap: i.e., for
the Np heterogeneous semiconductor junction, the n doped region has higher bandgap
than the p doped region.

Semiconductor junctions are the building blocks of solar cells, LEDs, homoge-
neous|heterogeneous bipolar transistors (BJT, HBT), homogeneous|heterogeneous field
effect transistors (JFET, MOSFET, MESFET, HEMT), IGBT, solid state lasers etc.

3.1.1 Homogeneous Semiconductor Junction—np

The equilibrium energy levels and the corresponding energy band diagram for a homo-
geneous np junction is shown in Fig. 3.1a, b. In Fig. 3.1a shows the separated n|p type
regions, including the conduction|valence band edges, related to the potential energies

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 45

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_3
46 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

Fig. 3.1 a, b Energy band (a) (b)

diagram for separate n|p type
material (a) and n|p material in
intimate contact with band
bending (b)

of the electrons|holes respectively. The force free vacuum energy reference level E 0 is
conventionally assigned the value 0. All other energy levels are defined with reference to
it, and are negative. The vacuum reference energy level is the energy that an electron
would have if it were removed from the semiconductor, in absence of potential energy
gradients (electrostatic forces) in the semiconductor. The positive energy required to
remove the electron (E 0 − E C O N D ) is the electron affinity of the material, denoted as χ.
Starting with the expression for the equilibrium carrier concentration:
E F E R M I −E C O N D
n 0 = NC O N D e k B Tlattice
(3.1a)

where E C O N D , NC O N D are respectively the conduction band energy bottom and effective
density of states. The Fermi energy is:

E F E R M I = E C O N D + k B Tlattice (ln(n 0 ) − ln(NC O N D )) (3.1b)

E F E R M I = E 0 − χ + k B Tlattice (ln(n 0 ) − ln(NC O N D )) (3.1c)

E F E R M I = k B Tlattice (ln(n 0 ) − ln(NC O N D )) − χ = μ (3.1d)

The final equation indicates that the Fermi energy is equal to the chemical potential
energy µ in field free conditions. As χ and NC O N D are material constants, the Fermi
energy increases as more electrons are added to the material. The difference between the
Fermi energies in the two separate materials of Fig. 3.1a is the difference in chemical
potential energy:
n 01
E F E R M I 1 − E F E R M I 2 = k B Tlattice = Δμ (3.2)
n 02
When the two materials are put in contact (Fig. 3.1b), this difference in chemical
potential energy between the two differently doped regions cannot be maintained any
more, and the system equilibrates. The minimum energy state of thermal equilibrium is
reached when the difference in the chemical potential energies vanishes, i.e., when sufficient
electrons have been transferred from the n side to the p side so that E F = E F1 = E F2 .
3.1 Homogeneous and Heterogeneous Semiconductor Junctions [1–7] 47

The transferred electrons at start increase the np product on the p side near the junc-
tion, increasing recombination rate, and the annihilation of many electron–hole pairs. This
creates a region of negative space charge (acceptor ions) on the p side of the junction. A
region consisting of equal magnitude of positive space charge (donor ions) appears on the n
side from the departure of the transferred electrons. This space-charge region is a source of
internal potential energy, with an internal electrostatic potential difference called the built-
in potential|voltage VB I , expressed as a positive quantity. The actual, position dependent
electrostatic potential ψ(x) is shown in Fig. 3.1b. In this graph, the potential energy −
qψ(x) is a positive potential. So the local vacuum level E I N T R I N S I C is negative with
respect to the reference energy E 0 . The reference potential (ψ = 0) is conventionally set
to zero at the end of the p region: x = x P . Otherwise:

E F E R M I = μ(x) − qψ(x) (3.3)

The Fermi energy is the electrochemical potential energy, based on thermodynamics

of a system with both chemical potential energy and electrostatic potential energy.
Expressions for the built-in potential and its corresponding profile are obtained easily.
At equilibrium, the drift and the diffusion currents cancel each other resulting in:

Jelectr on = μelectr on (k B Tlattice ∇n − qn∇ψ) = 0 (3.4)

   
k B Tlattice dn
dψ = n 0 p ≤ n ≤ n 0n (3.5)
q n

Equation 3.5, after integration gives the expression for the built-in potential:
   
k B Tlattice n 0n det NA ND
VB I = ln = VT H E R M AL ln (3.6)
q n0 p n i2

With reference to Fig. 3.1a, b, simple expressions for the potential profile for a bias
free homogeneous np semiconductor junction, are obtained:

−qψ(x) = El (x) − E 0 − qψ(x) = E C O N D (x) − E C O N D (x P ) (3.7a, b)

Under equilibrium conditions, applying Maxwell–Boltzmann statistics, the one dimen-

sional electron|hole concentrations are:
ψ(x)
n 0 (x) = n 0 (x P )e VT H E R M AL (3.8a)

−ψ(x)
p0 (x) = p0 (x P )e VT H E R M AL (3.8b)

Now applying these expressions to Poisson’s equation (equilibrium conditions) gives

the following non-linear differential equation, to be solved numerically:
48 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

−d 2 ψ q
= ( p0 (x) + N D O N O R − n 0 (x) − N ACC E P T O R ) (3.9a)
dx 2 ε
where N ACC E P T O R , N D O N O R are the acceptor and donor concentrations.
The space charge region inside a homogeneous np junction is very important for
its operation and therefore its properties must be determined accurately. But (3.9a) is
a nonlinear equation and can be solved accurately only using numerical techniques.
The depletion approximation scheme fully linearizes (3.9a) and so the results so
obtained with the linearized version are not very accurate. According to the depletion
approximation, the width of the space charge region is:
√  
 1 1
W = N D O N O R xdn + N ACC E P T O R xd p
2 2 + (3.9b)
N ACC E P T O R NDO N O R

3.1.2 How to Create|Draw np Junction Equilibrium Energy Band

Diagram

The energy band diagram of a homogeneous np semiconductor junction is created using

the following step-by-step method, starting with the n, p region are not in contact.

• Draw a horizontal solid line to represent the reference energy level E 0 .

• The electron affinities for the n, p regions are different. With respect to the reference
energy level, draw two horizontal lines, below the reference energy level. The vertical
distance with respect to the reference level of each of the horizontal lines is equal to
that region’s (n|p) electron affinity. This horizontal line is the bottom of the conduction
band for that region—E C O N D .
• Using the horizontal line for the bottom of the conduction band for each of the regions
(n|p) as reference, draw two new horizontal lines, below the horizontal line that denotes
the bottom of the conduction band for that region. For each of the n|p regions the vertical
distance between the bottom of the conduction band and the new horizontal line is
the bandgap. This new horizontal line for each region is the top of the valence band
E V AL for that region.
• Draw a horizontal line in between the horizontal lines for the conduction and valence
bands to indicate the approximate doping level—e.g., for a highly doped n region, this
line must be close to the bottom of the conduction band. This is the Fermi level.

Now the n, p regions are put in contact—np junction is created.

• Draw a horizontal line across the length of the entire n, p regions combined. This is
the Fermi level.
3.2 Homogeneous np Junction with External Bias 49

• Add the conduction band bottom and valence top for both the n, p regions keeping
a gap in the middle where there would be a discontinuity between the conduction,
valence band levels of the n, p regions.
• Select one side of the device as a reference side and draw a horizontal line to indicate
E I = E 0 for that side only. The line must not extend into the interfacial region.
• For the non-reference side, insert a horizontal line a vertical distance equal to the
electron affinity, above the conduction band bottom. This is E I = E 0 for the non-
reference side.
• Connect the E I = E 0 horizontal lines for reference|non-reference regions with straight
lines. Repeat for the conduction and valence band bottom|top horizontal lines for the
reference|non-reference regions respectively.

3.2 Homogeneous np Junction with External Bias

An external bias (voltage) V A P P is applied to the two extremities of the np junction, via
metal contacts at each extremity. With reference to the p side, as the zero reference for
electrostatic potential, the applied bias is negative and the total potential difference across
the device is:

E F E R M I (−x N ) − E F E R M I (x P ) = VB I + V A P P (3.10)

In metals with an odd number of valence electrons per primitive unit cell, the highest
occupied band is half-filled with electrons. As a metal has a huge number of free elec-
trons, any electron exchange between a metal contact and semiconductor occurs without
disturbing the metal from its thermal equilibrium state. External bias applied to an np-
junction is a difference in electrochemical potential between the metal end contacts and
is:

E F E R M I (−x N ) − E F E R M I (x P ) = −q V A P P (3.11)

E F E R M I (x P ) is taken as the reference energy for the electron potential energy

−q V A P P due to an applied voltage V A P P . A forward bias condition is when the applied
potential on the n side is less than or negative compared to the p side. The opposite case
when the n side is more positive than the p side is reverse bias.
The applied voltage is dropped across the junction, because conductivity is much
lower in the space-charge region compared to either in the n or p regions of the device.
With miniscule number of charge carriers (electrons|holes) in the space charge region it
acts as a resistor. So most of the voltage is dropped across the resistive space charge
region. For the forward bias case the potential barrier at the junction would be lowered
by |V A P P |. This lowering enables more electrons to pass from the n side to the p side of
50 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

(a) (b)

(c) (d)

Fig. 3.2 a, b Energy band diagram for separated (equilibrium) and in contact (forward biased)
homogeneous n, p semiconductors. c, d Electron concentration (hatched area) and flow (arrow)
across separated (equilibrium) and in contact (forward biased) homogeneous n, p semiconductors.
Thick arrow shows direction of maximum electron flow in (d)

4
the junction, resulting in a net current. When the current density is large, e.g., 10 A
cm2
, the
flow of electrons extends into the n side the device starting from the p side. For a test
19
case doping density of 10 cm3
the field needed to support the chosen current density, the
field is approximately 6μmmV
. Thus, in microelectronics, the actual voltage dropped across
this region will be very small compared to the value for the applied voltage of a few
volts. Therefore the applied voltage is dropped entirely across the space charge region.
The energy band (equilibrium separated, contact forward biased) and related (electron
concentration) diagrams are shown in Figs 3.2a–d.

3.2.1 How to Create Energy Band Diagram for Homogeneous np

Junction at Non-equilibrium

The scheme elaborated on earlier to create the energy band diagram for a homogeneous
np junction at equilibrium is extended to address the common non-equilibrium case. Right
at start, identify the selected reference side (n|p) for the homogeneous case. Then:
3.2 Homogeneous np Junction with External Bias 51

• Copy the selected reference portion of the unbiased homogeneous np junction band
diagram without the Fermi level.
• On the non-reference side of the new diagram, a new horizontal line is added for E I
at a depth of −q V A P P below the previous position of E I . For the forward bias np
junction this will raise E I on the n side above its equilibrium position.
• The non-reference side (of the original homogeneous np junction) is now completed
by adding E C O N D at a vertical position χ below E 0 and similarly E V AL is added
at a vertical position E G A P below E C O N D .
• E I must join up smoothly across the junction. Forward bias reduces the potential drop
across the junction, so less charge is needed to support the potential difference, and the
space charge region shrinks. Thus the horizontal sections of E I are extended further
towards the external metal contacts before E I segments from the two sides of the non-
equilibrium np junction are joined by a smooth curve. This process is repeated for the
conduction and valence band edges. In reverse bias, the procedure is the same, but
the larger voltage drop across the junction means that the depletion region is widened
relative to its equilibrium value.

As the electric field in regions of a np junction outside the space charge region is very
weak, there is little deviation from charge neutrality. The response of the majority carrier
(holes) to the injection of electrons from the n side shows the presence of new negative
charge beyond the edge of the depletion region on the p side which attract holes. These
electrons flow in from the metal contact. Finally, holes drawing energy from the tiny electric
field in this region, reach the site of the excess electrons. Their positive charge is negated
by the negative charge of the contact site electrons. Thus, the region of length L between
the contact and the excess electrons is a parallel plate capacitor of capacitance C. The
corresponding resistance is R. The associated RC time constant defines the dielectric relax-
def
ation time as τ D = RC Q N R = σε and ε, σ are the electrical permittivity and material
conductivity respectively. So the majority carriers respond to any changes in a time of the
order of the dielectric relaxation constant. These regions are called quasi neutral region
(QNR). Under low-level injection of minority carriers, the majority carrier concentration
remains very close to its equilibrium value, and is subjected to a very small field and the
distribution of the majority carriers is quasi Maxwellian.
In reverse bias (Fig. 3.3a, b) a positive potential is applied to the n side contact with
and a negative bias is applied to the p side contact—i.e., the n side is node is more positive
than the p side. Equivalently, with the p side grounded, and the n side connected to a
positive bias, the np junction diode is reverse biased. The barrier height of the junction is
q(VB I + V A P P ). The space charge layer becomes wider:
√  
2q 1 1
W = (VB I + V A P P ) + (3.12)
ε N ACC E P T O R NDO N O R
52 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

Fig. 3.3 a, b Reverse biased (a)

homogeneous np junction and
effect of the reverse bias on
electron movement across
junction

(b)

If the barrier becomes so high that few electrons on the n side have enough energy
to diffuse over the barrier, then the electron current is carried mainly by the equilibrium
concentration of minority carriers on the p side drifting down the potential barrier. There
are very, very few of these electrons, so the reverse n bias current is very small.
The space charge region has larger physical length in the reverse bias condition compared
to forward bias condition. As the space charge region is practically free of mobile charges,
it acts as a resistor. So the resistance value is much larger for the reverse bias case than the
forward bias case. So the simple np junction has two resistances associated with it—one
for the forward bias case, and a larger value one for the reverse bias case. This is the
basis for transconductance and so a very, very important property.

3.2.2 Quasi Fermi Levels

In the quasi neutral regions for both equilibrium|non-equilibrium conditions, when large
currents are present, the potential profile is flat, and the majority carrier concentration
deviates slightly from its equilibrium value. So in the quasi neutral regions, carrier
concentrations can be described by equilibrium carrier concentrations with perturba-
tions. Equilibrium Fermi levels for pure equilibrium conditions are replaced by Maxwell
Boltzmann distributions and the corresponding energy levels are called quasi Fermi levels.
E F E R M I n −E F E R M I i E F E R M I i −E F E R M I p
n = ni e k B Tlattice
p = ni e k B Tlattice
(3.13a, b)

Here E F E R M I n , E F E R M I p are the electron|hole quasi Fermi levels respectively. Quasi

Fermi levels do not have any basis in thermodynamics, unlike pure Fermi levels—
these describe carrier concentrations in non-equilibrium conditions. The electron|hole
3.3 The Ideal Homogeneous np Junction (Diode) Equation 53

concentrations in terms of the potential  are:

ψ E F E R M I n −E F E R M I −ψ E F E R M I −E F E R M I p
+ +
n = n 0 (x P )e VT H E R M AL k B Tlattice
p = p0 (x P )e VT H E R M AL k B Tlattice

(3.14a, b)

Then the quasi Fermi potentials are:

−q n (x) = EFE RM In − EFE RM I −q p (x) = EFE RM I p − EFE RM I (3.15a, b)

The electron|hole concentrations, expressed in terms of the quasi Fermi potentials are:
ψ− n p −ψ
n = n 0 (x P )e VT H E R M AL p = p0 (x P )e VT H E R M AL (3.16a, b)

The total non-equilibrium current, the sum of the diffusion and drift currents is:

JT O T AL = Jelectr on + Jhole = −q nμelectr on ∇ n + pμhole ∇ p (3.17)

3.3 The Ideal Homogeneous np Junction (Diode) Equation

The current|current density (I|J) versus voltage equation for a forward biased np junction
is based on following assumptions.

• Carrier temperature is zero—the diffusion-drift equations can be used.

• Negligible electric fields in the quasi neutral regions, allowing minority carrier trans-
port in these regions to occur via diffusion only. The applied voltage is dropped entirely
across the space charge region.
• Quasi neutral regions are so long that the few injected minority carriers recombine
before reaching the end contacts.
• The number of injected carriers is low enough so that quasi Fermi levels are constant
across the space charge layer.
• There is no generation|recombination in the space charge region so that the elec-
tron|hole currents at the boundaries of the space charge region can be added to calculate
the total current.
• Thermal generation is the only process to generate charge carriers.
• Impurity doping is uniform in the n, p regions.

For electrons injected into the p side, the electron current density is:
 
∂ Jelectr on q(n − n 0hole )
Jelectr on = Delectr on − (3.18a)
∂x τelectr on
54 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

The electron current density under steady state conditions becomes:

d 2n n − n 0hole n − n 0hole
− = 2 =0 (3.18b)
dx 2 Delectr on τelectr on L electr on
√
where L electr on = Delectr on τelectr on is the minority carrier diffusion length. Using the
boundary conditions:
−V A P P
n x p ≡ n(∞) = n 0 p n xd p = n 0 p e VT H E R M AL (3.19a)

the general solution is:

−x x
n(x) − n 0hole = Ae L electr on + Be L electr on (3.19b)

Using the stated boundary conditions the solution is:

 −V A P P xd p −x 
−1
n(x) = n 0hole 1 + e VT H E R M AL e L electr on (3.19c)

Then the electron current density at the edge at the edge of the space charge region is:

−V A P P
−1
−qn 0hole Delectr on e VT H E R M AL
Jelectr on xd p = (3.20a)
L electr on
Using identical reasoning, the hole current density at the edge of the space region is:

−V A P P
−1
−qn 0electr on Dhole e VT H E R M AL
Jelectr on xd p = (3.20b)
L hole
Combining these two results, the electron and hole current is:
 
n 0hole Delectr on n 0electr on Dhole V −V A P P −1
J = −q + e T H E R M AL (3.20c)
L electr on L hole

This is the ideal diode equation.

A real world diode’s properties differ noticeably from the ideal, the reasons being:

• Quasi neutral regions are often short, so not all injected minority carriers recombine
before reaching the junction extremities. Appropriate boundary conditions must be
used, and the saturation current density is different from the ideal value.
• For very high currents, the quasi Fermi levels in the space charge region deviate from
constant values.
• High currents trigger increased injection of minority carriers, and a possible loss of
charge neutrality in parts of the quasi neutral regions. This leads to local fields outside
3.4 Heterogeneous Semiconductor Junctions Np 55

of the depletion region, in which case not all of the applied voltage appears across
the junction. This can be represented in the diode equation by replacing V A P P with
VA P P
γ γ > 1, where γ (often called η) is the diode ideality factor. At high bias, the
diode current still increases exponentially, but the dependency on bias is weaker.
• At low bias including the recombination current of electrons and holes in the
space charge region, leading to values of saturation current density greater than
n 9hole Dekectr on
L electr on + n 0electr on Dhole
L hole , and γ ≈ 2.

Electron hole pairs generated in the space charge region are often separated by the junction
field, leading to a current in the reverse bias direction. At large reverse bias, the space
charge region can be so wide that this generation current is much larger than the ideal
diode saturation current. At even higher reverse bias, carriers traversing the space charge
region can gain sufficient kinetic energy to impact ionize lattice atoms, leading to current
multiplication and avalanche breakdown—high power transistors.

3.4 Heterogeneous Semiconductor Junctions Np

A heterogeneous semiconductor junction is created when the base material on the two
sides of the junction are different e.g., GaAs (gallium arsenide) and InP (indium phos-
phide) since gallium and indium are two different elements on the periodic table. Very
often the dopant concentration on the two sides of the junction are different. Thus with
the Np heterogeneous junction the n side has larger bandgap compared to the p side.
The two key semiconductor properties of a heterogeneous junction that differ compared
to a homogeneous junction are electron affinity and energy bandgap. Based on these two
properties, heterogeneous semiconductor junctions are classified into Type I, Type II or
Type III (broken heterogeneous junction) Fig. 3.4a, b. For a Np heterogeneous junction„
the wider bandgap straddles the narrower one. For a type II heterogeneous junction, the
two bandgaps are staggered. With reference to Fig. 3.4a, b for both (Type I, II), the built-in
potential is:

q VB I = q(VN + V P ) = χ P + q V2 − χ N − q V1 (3.21a)

which gives after some manipulation (left as an exercise for the reader):
 
NC O N D P n 0N
q VB I = k B Tlattice ln + χP − χN (3.21b)
NC O N D N n 0P

If the two semiconductors of the heterogeneous junction have similar density-of-states

electron effective masses, then the built-in potential for Type I heterogeneous junction will be
greater than that for the corresponding homogeneous junction and for Type II heterogeneous
junction the built-in potential is lower than that for the corresponding homogeneous junction.
56 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

(a) (b)

Fig. 3.4 a, b Energy band diagrams for heterogeneous Np and Pn semiconductor junctions

From Fig. 3.4a, b the local vacuum level E I (x) varies smoothly with position, as it
tracks the electrostatic potential. But electron affinities on the two sides differ and the
band edges E C O N D (x), E V AL (x) show discontinuities at the interface (heterogeneous
junction) between the two different semiconductors. These discontinuities are called
band offsets, and labelling them as ΔE C O N D , ΔE V AL , gives:

ΔE C O N D + ΔE V AL = |χ N − χ P | + ΔE V AL = E G A P N − E G A P P (3.22)

The physical dimensions of the heterogeneous junction space charge region can be
estimated by extending the above concepts. The potential across the space charge region
at an Np heterogeneous junction is given by appropriate modification of the correspond-
ing expression for a homogeneous junction, allowing for different permittivities of the
two semiconductors. The ionic charge on both sides of the heterogeneous junction can
be equated, provided there is no free charge density at the interface between the two
semiconductors. Therefore the two dimensions of the space charge region, centered at the
junction are:
√
2ε N ε p N ACC E P T O R VI U N C
xd N =
q N D O N O R (ε N N D O N O R + ε P N ACC E P T O R )
√
2ε N ε p N D O N O R V J U N C
xd P = (3.23)
q N ACC E P T O R ε N N D O N O R + ε p N ACC E P T O R
3.4 Heterogeneous Semiconductor Junctions Np 57

3.4.1 Heterogeneous Semiconductor Junction Quasi Fermi Level

Splitting

For heterogeneous junctions with a conduction band potential ‘spike-well’ at the dissim-
ilar semiconductor interface, e.g., Type-I Np junction shown in Fig. 3.5, the quasi Fermi
level splits. In any junction (homo|heterogeneous), an applied forward bias reduces both
|q VN |, q V p . For a heterogeneous Np junction, this reduces the barrier to electron
flow into the base, while increasing the barrier to electron flow from the base. So the
net electron flow is not small compared to each of the counter directed flows. That means
that unlike in a homogeneous junction, the flow of electrons is not a minor perturbation of
the equilibrium condition. This significant departure from equilibrium results in dis-
continuous electron quasi Fermi levels at the dissimilar semiconductor interface. The
forward|backward electron current densities injected over the potential barrier, expressed
as hemi-Maxwellian (hemispherical Maxwellian) fluxes are:
 
Jelectr on,F O RW A R D = −qn 0 M I NU S V R Jelectr on,B AC K W A R D = qn 0 P LU S V R
(3.24)

where the MINUS/PLUS indicate flow directions along the positive|negative x axis, about
x = 0. After applying the Maxwell–Boltzmann distribution and some simplification
(n(0) = n 0 P LU S , VB I = VN + V P n(−xd N ) = n(−xdn )), the current is:

Jelectr on1 = Jelectr on,F O RW A R D − Jelectr on,B AC K W A R D

 −V A P P

−Δn
= −q V R n 0 (xd P )e T H E R M AL − n(xd P ) e k B Tlattice
V (3.25a)

and the diffusion current is:

−q Delectr on (n(xd P ) − n(x2 ))
Jelectr on2 = (3.25b)
W
where W is the width of the depletion region, and x = x2 is the position of the end
contact to region 2. The first version of the of the diffusion current equation is obtained
by assuming that recombination in region 2 is negligible, and the second version implies
that the contact at the end of region 2 is Ohmic. The negligible recombination assumption
gives the boundary condition for n xd p :
⎛ −V A P P ⎞
Delectr on
e VT H E R M AL + −E n
⎜ ⎟
n(xd P ) = n 0P ⎜
⎝
W e k B Tlattice
Delectr on
⎟
⎠ (3.26)
1+ −E n
W e k B Tlattice

The new equation, via γ , incorporates both the finite velocity v R of carriers crossing
the heterogeneous junction, and the presence of an energy difference at the interface.
58 3 Homogeneous (np) and Heterogeneous (Np) Semiconductor Junction …

Fig. 3.5 Forward biased

heterogeneous Type I Np
junction, with quasi Fermi
level splitting

Alternatively, recognizing that the impeding effect of the junction itself is via quasi
Fermi level splitting, gives:
E Fn P −E C O N D (xd P ) E F P −E C O N D (xd P )
n(xd P ) = NC O N D P e k B Tlattice
n 0 (xd P ) = NC O N D P e k B Tlattice
(3.27)

Then the actual splitting of the electron quasi Fermi level at the heterogeneous junction
interface is:
  
n(xd P )
E F E R M I Fn = E F E R M I n N − E F E R M I n P = − q V A P P + k B Tlattice ln
n0 p
(3.28)

Using (3.28), the diffusion equation becomes:

 −(q V +ΔE ) 
AP P Fn
−q Delectr on n 0P e k B Tlattice
−1
Jelectr on2 = (3.29)
W
A key property of a heterogeneous Type I Np diode is emitter injection efficiency: the ratio
of the injected electron emitter current to the total current. It is used in a heterogeneous
bipolar|bijunction transistor(HBT) analysis. The electron current density is given by (3.29)
and the hole current is:
 −(q V +ΔE ) 
AP P Fn
−q Dhole p0N e k B Tlattice −1
Jhole (−xd N ) = (3.30a)
L hole
Assuming that the effective densities of states are the same in both materials, and in
forward bias the ‘−1’ terms in the expressions for the current components can be dropped,
the emitter injection efficiency is:
References 59

1
ηE M I T T E R = −(ΔE G A P −ΔE Fn )
(3.30b)
Dhole N B AS E W B AS E e k B Tlattice
1+ D E M I T T E R L hole N E M I T T E R

where ‘BASE, EMITTER’ refer to the conventional bipolar transistor device regions.

References

1. Streetman, B. G., & Banerjee, S. (2000). Solid state electronic devices. Prentice Hall.
2. Sze, S. M. (1969). Physics of semiconductor devices. Wiley and Sons. ISBN 0-471-84290-7; 2nd
ed., 1981, ISBN 0-471-05661-8; 3rd ed., with Kwok K. Ng, 2006.
3. Neaman, S. A. Semiconductor physics and devices basic principles (4th ed.). https://www.
amazon.in/Semiconductor-Physics-Devices-Basic-Principles/dp/935460112X/ref=asc_df_935
460112X/?tag=googleshopdes-21&linkCode=df0&hvadid=545233384715&hvpos=&hvnetw=
g&hvrand=3864533311912858920&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvl
ocint=&hvlocphy=1007828&hvtargid=pla-1435439439101&psc=1
4. Fiore, J. M. (2018). Semiconductor devices: Theory and applications. ISBN 13: 9781796543537.
https://open.umn.edu/opentextbooks/textbooks/573
5. Hess, K. Advanced theory of semiconductor devices. https://ieeexplore.ieee.org/book/5265897.
https://www.amazon.com/Advanced-Theory-Semiconductor-Devices-Karl/dp/0780334795
6. Nair, B. S., & Nair, R. S. Solid stare devices. https://www.amazon.in/Books-B-Somanathan-Nair/
s?rh=n%3A976389031%2Cp_27%3AB.+Somanathan+Nair
7. Pulfrey, D. L., & Tarr, N. G. (1989). Introduction to microelectronic devices. Prentice Hall. ISBN
10 0134881079. ISBN 13 9780134881072.
Basic Heterogeneous Bipolar|Bijunction
Transistor (HBT) Properties
4

4.1 Types of Heterogeneous Bipolar Transistor

and Characteristics [1–12]

A bipolar transistor has two semiconductor junctions np inside it, hence bipolar|bijunction
transistor. For a homogeneous [1–12] bipolar transistor, the base material for each side of
both the junctions is the same—silicon. A heterogeneous transistor can be either single
heterogeneous junction, or double heterogeneous [1–12] junction. A single heterogeneous
junction transistor is a combination of a homogeneous junction and a heterogeneous
junction. A double heterogeneous junction bipolar transistor has a different base mate-
rial for each of the base, collector and emitter regions. To design|fabricate a Npn(single
heterogeneous junction bipolar transistor), the starting point is:

• Select two materials that give a barrier height for holes that is much higher than that
for electrons, allowing a much larger doping density in the base, compared to homo-
geneous junction devices. The base resistance is minimized and correspondingly the
base-emitter hole current is very low. This is bandgap engineering.

This type of transistor is constructed using molecular beam epitaxial semiconductor lay-
ers deposited sequentially. The key property of epitaxial layers is that the substrate layer’s
lattice constant must be as close as possible to that of the deposited layer. This key
property eliminates interface defects responsible for unwanted recombination generation
centers, and charge carrier scattering. For gallium arsenide(GaAs) substrates, the AlAs-
GaAs(aluminum arsenide-gallium arsenide) materials, and GaP-InP(gallium phosphide
indium phosphide) are ideal candidates for HBTs.
Silicon does not naturally have these advantages. Defect free junctions are constructed
between silicon and a dilute alloy of Si 1−x and germanium(Ge) with the germanium mole

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 61

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_4
62 4 Basic Heterogeneous Bipolar|Bijunction Transistor (HBT) Properties

fraction x not exceeding 15%. Increasing Ge mole fraction through the base forces the
bandgap decrease, and a field is created in the base. This field enhances electron transport
from the base to the collector, in turn improving the high frequency performance of the
transistor. All HBTs are bandgap engineered devices.
Figure 4.1a shows the basic physical structure of a HBT using semiconductor materials
of the periodic table group III-V elements, for which various semiconducting layers are
deposited epitaxially. The pairs of contacts for both the base and collector, reduce both
the base spreading resistance and the series resistance and access regions to the main part
of the transistor. The energy band diagram for a single heterogeneous HBT (Fig. 4.2) is
constructed using the sequential procedure detailed in the previous chapter.
This HBT consists of: emitter I nd0.49 Ga0.51 P, a base of p + gallium arsenide(GaAs)
and a collector of n doped GaAs. The particular mole fractions for In and Ga in the indium
gallium phosphide(InGaP) layer are chosen to give a good lattice match to GaAs. The
bandgap for this material is 1.86 eV. The electron affinities of GaAs and I nd0.49 Ga0.51 P

Fig. 4.1 a Basic layered physical structure of a HBT (Heterogeneous Junction Bipolar Transistor)

(a) (b)

Fig. 4.2 a, b Energy band diagram corresponding to Fig. 4.1, in equilibrium and active mode
4.1 Types of Heterogeneous Bipolar Transistor and Characteristics [1–12] 63

are the same, so the difference in bandgaps (0.4 eV) is entirely due to the band edge
offset in the valence band. This clever bandgap engineering trick results in different
energy barriers for electrons and holes at the emitter base junction. Consequently,
performance characteristics of heterogeneous bijunction transistors is vastly superior
to that of homogeneous junction transistors. In all subsequent discussions, regions of
higher bandgap is denoted with uppercase symbol.
A higher hole barrier does not interfere with the doping density in the base which can
be increased without compromising the current gain. Also, the high base doping density
allows a very narrow base to be used without boosting the base access resistance. The
advantages of a narrow base are:

• The minority carrier concentration has a steep profile leading to a high collector cur-
rent resulting in less minority carrier storage and consequently reduced base storage
capacitance.

These properties in combination result in a ultra high frequency transistor have very high
values for two key performance metrics unity power gain frequency, unity current gain
frequency f max , f T .
 
NC O N Dp n 0N
q VB I = k B Tlattice ln (4.1a)
NC O N D P n 0P

An extremely important distinction between an ideal transistor and a real world

HBT is the width of the base region—important for accurate current calculation. An
ideal diode has infinite base width, so any carriers injected from the emitter can collide with
other carriers etc., so that their distribution at the edge of the emitter–base space charge
region is of a near equilibrium form.
In a modern HBT, the base width can be≈30 nm. To determine the approximate mean
free path for the example HBT mentioned previously, the required parameters are the
electron mobility in GaAs, and the mean unidirectional velocity for injection from an
emitter. Using available data for these parameters from standard references [1–12], the
mean free path for the carriers is approximately 10 nm. This is insufficient distance for
all the carriers injected into the base to get ‘thermalized’ by collisions. A key assumption
is that the electrons injected from the emitter maintain a hemi-Maxwellian(‘hemisperical
Maxwellian’) distribution through the emitter–base space charge region. Denoting the elec-
n EP M I T T E R
tron distribution moving towards the collector that overcomes the barrier as 2 and
assuming quasi equilibrium conditions gives:
−(V B I −V B E ) VB E
n EP M I T T E R = n 0E M I T T E R e VT H E R M AL = n B AS E e VT H E R M AL (4.1b)
64 4 Basic Heterogeneous Bipolar|Bijunction Transistor (HBT) Properties

4.2 The Collector and Base Current of a HBT

Just like a homogeneous bipolar|bijunction transistor, an expression for the collector cur-
rent of a heterogeneous bipolar transistor must be evaluated, with an applied bias. The
transistor’s controlling voltage is V A P P,J U N C T I O N = VB E , and the collector current is
estimated by first evaluating the electron flow in the transistor’s base region. The elec-
tric field free portion of the base between the junction space charge regions is the quasi
neutral base. Minority diffusion carrier currents this region are controlled by carrier con-
centration gradients. So the electron profile in the quasi neutral base is estimated first, by
combining equations for electron continuity and transport.
Under steady state conditions the drift–diffusion equations give:

d 2n n − n 0B AS E
− =0 (4.2)
dx2 L 2electr on

where L electr on is the electron minority-carrier diffusion length. This equation is the same
as in the case of homogeneous junction ideal diode. For the heterogeneous junction device,
the solution is different different because of different boundary conditions. The minority-
carrier diffusion length is a measure of the distance a minority carrier diffuses before it
recombines with a majority carrier. To eliminate recombination in the base region, the
quasi neutral base width in a Npn HBT must be less than electron minority-carrier diffu-
sion length: W B AS E < L electr on , and the electron diffusion current is a constant. A short
base guarantees a high collector current—essential for ultra high frequency operation of
the HBT.
With reference to Fig. 4.2b, the forward bias lowers the energy barrier at the base-
emitter junction, boosting electron injection from the emitter into the base. These electrons
are drawn from the positive-going hemi-Maxwellian at x = −xdn . The total width of
the depletion region is W = xd p + xdn , W < L electr on . Then the right going part of
the electron distribution at x = xd p , upon entering the base will scatter, and some will
be re-directed towards the emitter, thus contributing to the left going concentration at
x = xd p . Another small contribution (due to reverse biased base collector junction) to
the left going distribution is due to electrons injected into the base from the collector.
Considering scattering of these electrons from the collector:

n EP M I T T E R
n(xd P ) = + nLE FT GO I NG (4.3a)
2
where n L E F T G O I N G are the left going electrons.
Scattering reduces the left going electron distribution to a hemi-Maxwellian, so that
the electron current density at x = xd p is:
 
n EP M I T T E R
Jelectr on (xd P ) = 2qv R n L E F T G O I N G − (4.3b)
2
4.2 The Collector and Base Current of a HBT 65

Then the boundary condition is:

P
Jelectr on (xd P ) n electr on
n(xd P ) = + (4.3c)
2qv R 2
Under quasi neutral conditions the electron concentration at the extremity of the base
region is:

Jelectr on (xd P + W B AS E )
n(xd P + W B AS E ) = n CP O L L EC T O R − (4.3d)
2qv R
nP
where C O L L2EC T O R is the concentration of electrons in the collector with enough left
directed kinetic energy to cross over the collector base barrier:
V BC
n CP O L L EC T O R = n B AS E e VT H E R M AL (4.3e)

So the current density flowing through the base region is the difference of the current
densities at the two boundaries of the same region:

n(xd P + W B AS E ) − n(W B AS E )
Jelectr on = (4.3f)
W B AS E
Substituting the charge carrier concentrations in 4.3f and some rearrangement gives:
 VB E V BC

−qn 0B AS E e VT H E R M AL −e VT H E R M L

Jelectr on = W B AS E
(4.3g)
Delectr on + v R
1

Clearly the charge and velocity terms influence the current density. The reciprocal of
the velocity is the sum of two reciprocal velocities. If the ‘diffusion velocity’ DWelectr on
B AS E
is
much less than the ‘injection’ velocity v R , then diffusion limits the current, strictly for real
world bipolar transistors. State-of-art fabrication techniques routinely allow base widths
< 50 nm, so that the v1R term also must be taken into account, without which the current
would be overestimated, non-asymptotic to its ballistic limit. The electron current exiting
the collector is viewed as a positive charge flow into the collector from the external circuit:
Adhering to IEEE (Institute of Electrical and Electronics Engineers) convention this is a
positive current:
 VB E V BC

IC O L L EC T O R = −Jelectr on A = I S e VT H E R M AL −e VT H E R M AL (4.3h)

where A is the area of cross section, and I S collects all the non exponential terms from
the equations that are combined in this equation. Each of these parameters are obtained
from experimental data of HBT performance characteristics, using sophisticated numerical
techniques—parameter extraction.
66 4 Basic Heterogeneous Bipolar|Bijunction Transistor (HBT) Properties

Fig. 4.3 Active mode operation, forward biased electron–hole flow from|to base—recombination
currents

In a bipolar junction transistor there is a DC current at the controlling base electrode.

Holes flow into the base to (Fig. 4.3):

• Replace holes lost to recombination with electrons in the base.

• Replace holes lost to recombination with electrons in the base emitter depletion region.
• Supply hole current across the reverse biased base–collector junction.
• Supply the hole current due to injection of holes into the emitter across the forward
biased base-emitter junction.

This analysis for the collector current ignores the recombination current in the HBT base,
i.e., any recombination current in the base is small compared to the collector current. In
real world transistors, the recombination current may|may not be small compared to the
base current, and so cannot be ignored in the base current calculation process.
The large number of electrons and holes in the forward biased base-emitter depletion
region results in recombination. Recombination current will manifest itself in the emitter
and base leads at low base-emitter voltages, when the base-emitter barrier is high and there
is little net hole injection into the quasi neutral emitter. At moderate forward bias, this
injection current becomes large and dominates over the space charge region recombination
current.
The expressions for the base recombination current are obtained by starting with the
continuity equation:

n B AS E (x) − n 0B AS E
Jelectr on,R EC O M B I N AT I O N = xd P ≤ x ≤ xd P + W B AS E
τelectr on
(4.4)
4.2 The Collector and Base Current of a HBT 67

where n B AS E (x) is the coordinate dependent electron concentration in the HBT base
region, expressed as:
  
Jelectr on (xd P ) x
n B AS E (x) = n E M I T T E R +
P
1−
2qv R W B AS E
 
x J electr on (x + W B AS E )
+ n P
− (4.5a)
W B AS E C O L L EC T O R 2qv R

After substituting (4.5a) into (4.4) and integrating the current density over the area of
cross section(‘A’ in expression below) of the base region, the base current, is:
⎛ ⎞
   
VB E V Bc ⎜ 1 ⎟
I B AS E, R EC O M B I N AT I O N = Aqn 0B AS E + ⎝ 2T ⎠
e VT H E R M AL − 1 e VT H E R M AL − 1 electr on + 1
W B AS E VR
(4.5b)

4.2.1 Emitter Hole Current in a HBT

The hole current flowing through the quasi neutral emitter region
−(W E M I T T E R + xdn )  x  −xdn due to hole injection through the base-emitter
barrier is evaluated using the drift–diffusion equations. The emitter is much wider than
the base so recombination of the injected holes cannot be ignored. Thus for the hole
diffusion current and the hole charge continuity in the drift diffusion approximation
gives:

d2 p p − p0,E M I T T E R
− =0 (4.6a)
dx2 L 2electr on

where p0E M I T T E R , L hole are respectively the equilibrium hole concentration in the emit-
ter and the hole minority carrier diffusion length in the emitter region. The general
solution to (4.6a) is:
   
x x
p(x) = p0E M I T T E R + B cosh + C sinh (4.6b)
L hole L hole

where B, C are constants to be estimated from boundary conditions.

As the emitter length is greater than the hole minority carrier diffusion length, recom-
bination of the injected holes in the quasi neutral emitter cannot be ignored. The relatively
long length of the emitter means that the carrier velocity can have any permissible value.
Thus, the boundary conditions for the hole concentration at the emitter edge of the
depletion region and the other end are:
VB E
p(−xd N ) = p0E M I T T E R e VT H E R M AL p(−xd N − W E M I T T E R ) = p0E M I T T E R (4.6c)
68 4 Basic Heterogeneous Bipolar|Bijunction Transistor (HBT) Properties

Using a simple change of variables x P = x + xd N the boundary conditions give the

following values for the constants B,C:
⎛ ⎞ ⎛ ⎞
VB E VB E  
−W E M I T T E R
B = p0E M I T T E R ⎝e VT H E R M AL − 1⎠ C = − p0E M I T T E R ⎝e VT H E R M AL − 1⎠coth (4.6d)
L hole

Combining Eqs. 4.6a–4.6d the emitter region hole current density is:
 −q D d p     
hole −q Dhole x hole x hole
Jhole x P
= = B sinh + C cosh (4.6e)
dx L hole Dhole Dhole

Now substituting for the values for B, C gives the hole current at a particular location,
as:
   
−q Dhole p0E M I T T E R V VB E WE M I T T E R
Jhole (−xd N ) = e T H E R M AL − 1 coth (4.6f)
L hole L hole

4.3 Heterogeneous Junction Transistor (HBT) Simple DC

Equivalent Circuit Model

A simple DC equivalent circuit model of the HBT (Fig. 4.4) combines the base, collector
and emitter currents. This equivalent circuit includes the current due to holes injected
from the base into the collector. In the equivalent circuit, the base recombination term
has been separated into two diode like terms. Each of the two terms are associated with
each junction. This way, the origin of the electrons going into the base is identified. Base,
collector and emitter resistors represent the resistances of the various quasi neutral and
access regions.
A key performance metric for a bipolar transistor is the forward DC common emitter
current gain β. In this configuration, the emitter is common to both the input and output,
so that the controlling parameter is the base current.
IC O L L EC T O R
β=
I B AS E
In the active mode of operation the upper two diodes have negligible contributiom to
the output, and so these two in the equivalent circuit can be ignored, and the current gain
is expressed in a constant, bias independent form Thus, if the parameter in Fig. 4.4 were
I B rather than VB E , then a family of curves can be generated, which have equal base steps
and equally spaced collector currents in the active region. In the common base connection
the input current is the emitter current and the DC common base current gain is:
IC O L L EC T O R
α=
|I E M I T T E R |
References 69

Fig. 4.4 Simple DC

equivalent circuit model for the
Npn heterogeneous
bipolar|bijunction transistor

References

1. Pulfrey, D. L. (1999). Heterojunction bipolar transistor, wiley encyclopedia of electrical and

electronics engineering, Webster, J. G., Ed., John Wiley & Sons, Inc., vol. 8, 690–706.
2. Pulfrey, D. L., & Tarr, N. G. (1989). Introduction to microelectronic devices, Prentice-Hall
p. 348.
3. Anholt, R. (1995). Electrical and thermal characterization of MESFET’s HEMTs, and HBTs.
Boston: Artech House.
4. McAndrew, C., et al. (1996). VBIC95. The Vertical Bipolar Inter Company Model, IEEE Journal
of Solid State Circuits, 31(10), 1475–1483.
5. Scott, J., Nonlinear III-V HBT Compact Models: Do we have what we need? 2001 IEEE
Transactions on Microwave Technology and Techniques Symposium Digest, pp. 663–666.
6. Pehlke, D., & Pavlidis, D. (1992). Evaluation of the factors determining HBT high frequency
performance by direct analysis of S-parameter data. IEEE Transactions on Microwave Theory
and Techniques, 40(12), 2367–2373.
7. Teeter, W., & Curtice, W. Comparison of hybrid Pi and Tee HBT circuit topologies and their
relationship to large signal modelling, 1997 Microwave Theory and Techniques Symposium
Digest, pp.375–378.
8. Rudolph, M., Lenk, F., Doerner, R., & Haymann, P. On the implementation of transit time effects
in compact HBT Large-Signal models, 2002 Microwave Theory and Techniques Symposium
Digest, pp.997–1000.
9. Linder, M., Ingvarson, F., Jeppson, K., & Grahn, J. (2000) Extraction of emitter and base
series resistances of bipolar transistors from a single DC measurement, IEEE Transactions On
Semiconductor Manufacturing, 13(2), pp.119–125.
10. Angelov, I., Choumei, K., & Inoue. An empirical HBT large signal model for CAD, 2002
Microwave Theory and Techniques Symposium Digest, pp. 2137.
70 4 Basic Heterogeneous Bipolar|Bijunction Transistor (HBT) Properties

11. Dawson, D., & Gupta, A. (1992). CW measurement of HBT thermal resistance. IEEE Transac-
tions on Electron Devices, 39(10), 22–35.
12. Maas, S., & Tait, D. (1992). Parameter-Extraction method for heterojunction bipolar transistors.
IEEE Microwave and Guided Wave Letters, 2(12), 5.
Advanced VBIC and Angelov-Chalmers
Models for Heterogeneous|Homogeneous
5
Bipolar|Bijunction Transistor

5.1 The VBIC Specification

The VBIC (Vertical Bipolar Inter Company) [1] model enhances the original Gummel
Poon model of the bipolar transistor by including unavoidable parasitic capacitances and
inductances, missing in the original Gummel Poon model. The original Gummel Poon
bipolar transistor model included in the gold standard electrical|electronic circuit simula-
tion and performance evaluation tool SPICE (Simulation Program with Integrated Circuit
Emphasis) [10–14], is enhanced by including the VBIC model. The ‘Vertical Bipolar’ arises
from the fact that components (base, collector, emitter) of a modern BJT are stacked vertically
during fabrication.
For decades the SPICE [10–14] Gummel Poon [2] (SGP) model Nagel [3] has been
the semiconductor industry standard for circuit simulation for bipolar junction transistors.
Despite its sound physical basis, the SGP model has deficiencies.

• SGP model ignores collector resistance modulation (quasi saturation).

• SGP model does not account for unavoidable parasitic substrate transistor action.
• Early effect is not accurately modelled and output conductance not accounted for.

The approximations that underlie the SGP Early effect model [3], McAndrew [4] are
sufficient for modelling wide base BJTs (Fig. 5.1a), but generate inaccurate results when
applied to modelling narrow base BJTs (Fig. 5.1b). For narrow base BJT, a significant
portion of the capacitances are from bias independent dielectric capacitances, not included
in the original SPICE BJT model.
Although improved BJT models have been presented [5–9], none have become an
industry standard to replace the SGP model. VBIC (Vertical Bipolar Inter-Company
model) was defined by a group of representatives from the semiconductor and CAD

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 71

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_5
72 5 Advanced VBIC and Angelov-Chalmers Models …

Fig. 5.1 a Junction isolated (a)

diffused NPN. b Trench
isolated double polysilicon
NPN

(b)

industries to try to rectify this situation. VBIC is public domain, and complete source
code is publicly available. VBIC is as similar as possible to the SGP model, to leverage the
existing knowledge and training of characterization and semiconductor design engineers.
The main modelling enhancements of VBIC that overcome the deficiencies of the original
SGP BJT model are:

• Improved Early effect modelling

• Quasi-saturation modelling
• Parasitic substrate transistor modelling
• Parasitic fixed (oxide) capacitance modelling
• Avalanche multiplication modelling
• Improved temperature dependence modelling
• Decoupling of base and collector currents
• Electrothermal (self heating) modelling
• C ∞ continuous (smooth) modelling
• Improved heterogeneous junction bipolar transistor (HBT) modelling.

Although VBIC offers many advantages over SGP, it was designed to default to being
as close to SGP as possible, so that existing SPICE [10–14] simulators could be used to
estimate performance characteristics of electronic circuits that include VBIC based bipolar
transistor device models. The Early effect model used in VBIC is vastly improved ver-
sion of the rudimentary model used in the original SGP. The other features of VBIC are
additions that, with the default parameters, are not active. To include the enhancements
offered by the VBIC formulation in a circuit simulation with SPICE [10–14], the VBIC
5.1 The VBIC Specification 73

Fig. 5.2 a, b Intrinsic NPN (a)

and parasitic PNP transistors.
c, d Thermal and extra phase
circuits

(b)

enhancements are incrementally included to refine and fine tune the SPICE simulation
results. The mapping between VBIC and pure SGP parameters is provided in [1].

5.1.1 VBIC Homogeneous Junction Bipolar Transistors [1]

The equivalent electrical circuit network [1] of VBIC NPN transistor includes:

• Intrinsic NPN transistor

• Parasitic PNP transistor (Fig. 5.2a)
• Parasitic resistances and capacitances (Fig. 5.2b)
• A local thermal network (Fig. 5.2c) used only with the electrothermal version of the
model). A circuit that implements excess phase for the forward transport current It z f
(Fig. 5.2d).

The electrothermal version of VBIC, branch currents and charges in the electrical part
of the model depend on the local temperature rise. The thermal equivalent circuit includes
two external nodes that allow the local heating and dissipation to be connected to a ther-
mal network that models the thermal properties of the BJT substrate material Although
the equivalent network is often shown with fixed value resistances, bias dependent capac-
itances, and current sources, in reality the elements are voltage controlled current sources
I (V1 , V2 , V3 , . . .) and voltage controlled charge sources Q(V1 , V2 , V3 , . . .). Simple resis-
tors and capacitors are current and charge sources, controlled only by the voltage across
them. If a branch current and|or charge is controlled by more than one branch voltage,
can include transconductance and transcapacitance elements when they are linearized, as
is required for DC solution and for AC, noise and transient simulations.
Elaborate explanation of how the VBIC model addresses the deficiencies of the original
SPICE [10–16] SGP transistor model (e.g., accurate treatment of Early effect etc.,) is in
[1].
74 5 Advanced VBIC and Angelov-Chalmers Models …

5.2 VBIC Based Group 4 Silicon Germanium (SiGe)

Heterogeneous Bijunction Transistor (HBT) Model

The main features of the SiGe HBT in terms of the VBIC model are enumerated here, as
compared to the original SPICE Gummel Poon (SGP) model [15].

• The VBIC HBT is a four terminal device—base, collector, emitter and substrate. The
SGP bipolar transistor is a three terminal device.
• The VBIC HBT has self heating properties, absent in the Gummel Poon based SGP
model.
• Parasitic capacitances C B E0 , C BC0 are included by default. SGP requires manual
insertion of these parasitic capacitances.
• Detailed substrate model—absent in SGP.
• Excess phase during signal transit through device is modelled with sub-circuit and
delay time—SGP has forward delay time.
• Temperature mapping Is done through 21 parameters for HBT, compared to 4 for SGP.
• Enhanced Flicker noise model for HBT, compared to very simple one for SGP.

The HBT collector current equation is:

 VB E I V BC I

IS
IC E = e T H E R M AL − e T H E R M AL
N F V N RV (5.1a)
qb

The related Early effect equations, included into the VBIC model without any
simplifications are:
/
q1 q12 qJ E qJC
qb = + + q2 q1 = 1 + + (5.1b)
2 4 VE R VE F
 VB E I
  V BC I

IS IS
q2 = e VT H E R M AL −1 + e N RVT H E R M AL −1 (5.1c)
IK F IK R

The SGP model includes a rudimentary Early effect model. The independent and
distributed forward base current for a SiGe HBT is:

I B E = I B E I + I B E N = W B E I B,G E S I B E X = I B E X I + I B E X N = (1 − W B E )I B,G E S
(5.2a,b)
 V BC I
  V BC I

I B E N + I B E I = I BC I e N C I VT H E R M AL − 1 + I BC N e N C N VT H E R M AL − 1 (5.1c)

The forward base current in SGP is coupled to the collector current. The reverse base
current is decoupled from the emitter current, in the VBIC model, unlike that in the SGP
model:
5.2 VBIC Based Group 4 Silicon Germanium (SiGe) Heterogeneous … 75

 V BC I
  V BC I

I B E N + I B E I = I BC I e N C I VT H E R M AL − 1 + I BC N e N C N VT H E R M AL −1 (5.3a)

The VBIC model includes a weak base collector avalanche current, absent in the
original SGP formalism.
(MC−1)
IGC = A V C1 (ICC − I BC )(PC − VBC I )e−A V C1 (PC−VBC I ) (5.3b)

For both the SGP and VBIC models, the emitter resistance is constant. The VBIC base
resistance is modulated by the conductivity; empirically obtained in the original SGP
formalism.
RB I
RB = + RB X (5.3d)
qB
The VBIC collector resistance consists of both a constant and variable parts to model
quasi saturation.

RC = RC X + RC (VBC X , VBC I ) (5.4a)

/
IE P I 0 0.5 0.01 + V RC1
2
I RC = /  2 AA = (5.4b)
I E P I 0 RC I
V0 H RC F
1+ V0 (1+A A)
   
1+K BC I
V RC I + VT H E R M AL K BC I − K BC X − ln 1+K BC X
IE P I 0 = (5.4c)
RC I
/ /
V BC I V BC X
K BC I = 1 + G AM Me VT H E R M AL K BC X = 1 + G AM Me VT H E R M AL (5.4d)

The SGP model excludes substrate effects, while the VBIC model allows a constant
substrate resistance. The VBIC space charge capacitance model is the same as that for
the SGP model under certain conditions:
C J C,E,S0
C J C,E,S =   MC,E,S VB AS EC,E,S < FC · PC,E,S (5.5)
V B AS EC,E,S
1− PC,E,S

In the VBIC model, the SGP diffusion capacitance model is enhanced by QTF. The
interested reader is requested to check the details [1]. Both germanium and silicon (Ge,
Si) belong to group 4 of the periodic table. The next section examines in detail the case
of group 3–5 element based HBT, without using any VBIC model.
76 5 Advanced VBIC and Angelov-Chalmers Models …

5.3 Non-VBIC Group 3–5 and 4 Heterogeneous Junction

Transistor (HBT) Large Signal Model (Angelov Chalmers) [16,
17]

Formulating a large signal model for high frequency and power transistors is complicated
because:
For high power devices, the operating power densities and currents are very broad.

• Poor thermal conductivity of Group 3–5 elements used in some of these devices leads
to self heating problems at high operating frequencies and power densities.
• The forward DC current gain β is not constant. It rises to a maximum value and then
drops, as in a Lorentzian curve.
• Both the base and collector currents show exponential and logarithmic behaviour,
depending on the applied bias (e.g., base-emitter).
• The complicated underlying physics makes it difficult to include the corresponding
large signal model in a CAD (Computer Aided Design) tool. A CAD tool that generates
inaccurate results is meaningless.

These issues have been addressed by [16, 17] which presents a general large signal model
applicable to transistors based on group 3, 4 and 5 elements (AlGaAs/GaAs, InGaP and Si).
The data obtained with steady state DC sweeps and AC (small signal) S parameters are
carefully analysed numerically to extract the characteristic device parameters—parameter
extraction.
The equivalent circuit model of a HBT is in Fig. 5.3, used to formulate the base and
collector current expressions. Although the device physics dictate use of an exponential
function to describe the junction current, the reference point for measuring I B , IC is
changed to operating currents and voltages e.g., close to currents (voltages) at which β
is maximum. The junction current equation has a power series as its argument. These
modifications allow a flexible device model that can be used with a number of related but
different devices. The base current equations are:
  IP K C q
I B E = I B E J e PB E − e PB E0 I B E J = PB E1 = (5.7a,b,c)
β M AX K B Tlattice Nb1
Pb1
PB E = tanh 2 (VB E − V J ) + Nb2 (VB E − V J )2 + Nb3 (VB E − V J )3 + · · ·
2
(5.7d)
Pb1 1
PB E0 = tanh 2 −V J + Nb2 V J2 − Nb3 V J3 + · · · Pb1 = (5.7e,f)
2 Nb1 VT H E R M AL
When VB E = V J E base current I B E = I J B E VB E = 0 I B E = 0. The PB E0 defines
the junction current equals 0 when the junction voltage is 0, and its equation is
5.3 Non-VBIC Group 3–5 and 4 Heterogeneous Junction Transistor (HBT) … 77

Fig. 5.3 Heterogeneous junction bipolar transistor (HBT) equivalent electrical circuit correspond-
ing to Angelov Chalmers scheme

PB E f or VB E = 0. Usually, one term in the power series is sufficient for better than
5% accuracy in 5 to 6 decades of the diode current. For higher accuracy or to maintain
accuracy in a range of currents more then 6 decades, more terms can be used.
Similarly, the collector current equations are obtained with similar reasoning.

I P K C e PC F − e PC F0
IC = IC F tanh(αVC E )(1 + λVC B + λ M AX ) IC F =
cosh(B(VB E − VB E P M ))
(5.8a,b)
19.347   
PC F = tanh 2 (V B E − V B E P ) + NC2 (V B E − V B E P )2 + NC3 (V B E − V B E P )3 + · · ·
NC1
(5.8c)
19.347
PC F0 = tanh 2 −VB E P + NC2 VB2 E P − NC3 VB3 E P + · · ·
NC1
 38.695V 
CE
α = α I + αS e NC1
−1 (5.8d)

VB E P M = VB E P + ∆VB E P (1 + tanh(PC F1 VC E ) − VS B2 (VC B − VT R )) (5.8e)

  
38.685(VB E − VB E P ) λ2
λ M AX = λ2 VC B 1 + tanh + (5.8f)
NC F 1 + VC2 E

With 3 terms in the power series, the number of model parameters is 15 and 11 in the
single term case for the collector and base currents. These are:

α I , α S , β M AX , I P K C , VB E P , VB E , λ, N B1 , NC1 V J E = VB E P

The model flexible and more parameters can be added to model more complicated
effects in HBTs and BJT.
The HBT capacitances consist of both diffusion and depletion capacitances. The
diffusion capacitances are:

C B E,D I F FU S I O N = C B E P + C B E0 (1 + tanh(C B E10 + C B E11 VB E ))

78 5 Advanced VBIC and Angelov-Chalmers Models …

C BC,D I F FU S I O N = C BC P + C BC0 (1 + tanh(C BC20 + C BC21 VB E )) (5.10a,b)

The depletion capacitance is:

  2 
C D E P0 m − (2n − 1) VVBBEEI
CDE PL ET I O N = CDE P P +   2 n+1 (5.11)
VB E
m + VB E I

where n is the grading coefficient. The parameter m denotes the maximum to minimum
capacitance ratio. C D E P P represents undesirable parasitic elements.
HBTs suffer from self heating issues, because of the temperature dependencies of
collector-emitter, base emitter currents and the forward DC current gain. The changes
of the model parameters with changes in IC E , I B E , β are quasi linear with respect to
the temperature. This can be used to model self-heating in a simple way; but biasing
the device with a constant DC voltage source at the base results in a thermal runaway.
However, as the temperature dependency of the model parameters on temperature is of the
order of 1 in 1000, a linear model can be used to model self heating in small temperature
ranges. Details may be found in [16, 17].
An accurate model of the signal delay through a HBT is very important to analyse the
performance characteristics of the circuit in which it is embedded. The delay increases
with the collector current and saturates and decreases as the collector voltage is increased.
In simulators the bias dependency of the delay is defined via the collector emitter current.
It can be defined using the intrinsic controlling voltages and expressed empirically as:
    V
XT F VB E − V J E BE
TF F = TF 1 + 1 + tanh e 1.44VT F (5.13)
2 N

There are two DC transfer characteristics of a bipolar|bijunction transistor:

• Collector emitter current with linearly or pulsed varied base emitter voltage and
constant collector emitter voltage.
• Collector emitter current with linearly or pulse varied collector emitter voltage and
constant base emitter voltage.
Both methods create a family of curves.

References

1. https://designers-guide.org/vbic/documents/VbicText.pdf
2. Gummel, H. K., & Poon, H. C. (1970). An integral charge control model of bipolar transistors.
Bell System Technology Journal, 49, 827–852.
References 79

3. Nagel, L. W. (1975) SPICE2: A computer program to simulate semiconductor circuits. Memo.

no. ERL-520. Berkeley: Electronics Research Laboratory, University of California.
4. McAndrew, C. C., & Nagel, L. W. (1996). Early effect modeling in SPICE. IEEE Journal of
Solid State Circuits, 31, 136–138.
5. Turgeon, L. J., & Mathews, J. R. (1980) A bipolar transistor model of quasi-saturation for use in
Computer-Aided Design (CAD). In Proceeding of IEEE International Electron Devices Meeting
(pp. 394–397).
6. Kull, G. M., Nagel, L. W., Lee, S.-W., Lloyd, P., Prendergast, E. J., & Dirks, H. K. (1985). A uni-
fied circuit model for bipolar transistors including quasi-saturation effects. IEEE Transactions
on Electron Devices, 32, 1103–1113.
7. de Graaff, H. C., & Kloosterman, W. J. (1985). New formulation of the current and charge
relations in bipolar transistors for modeling for CACD purposes. IEEE Trasactions Electron
Devices, 32, 2415–2419.
8. Stubing, H., & Rein, H.-M. (1987). A compact physical large-signal model for high-speed bipo-
lar transistors at high current densities−part i: one-dimensional model. IEEE Transactions on
Electron Devices, 34, 1741–1751.
9. Jeong, H., & Fossum, J. G. (1989). A charge-based large-signal\bipolar transistor model for
device and circuit simulation. IEEE Transactions on Electron Devices, 36, 124–131.
10. https://ngspice.sourceforge.io/docs/ngspice-34-manual.pdf
11. https://resources.pcb.cadence.com/i/1180526-pspice-user-guide/25?
12. https://www.ti.com/tool/TINA-TI
13. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
14. https://www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-hspice.html
15. https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.200.1131&rep=rep1&type=pdf
16. https://ep.liu.se/ecp/008/posters/034/ecp00834p.pdf
17. https://www.researchgate.net/profile/Iltcho-Angelov/publication/292138930_10AngelovHBT
article/links/56a9c81308aeaeb4cef96107/10AngelovHBTarticle.pdf
Heterogeneous Junction Field Effect
Devices—Schottky Diode, Metal
6
Semiconductor Field Effect Transistor
(MESFET), High Electron Mobility Transistor
(HEMT)

6.1 Heterogeneous Junction Properties

The heterogeneous junction semiconductor [1–6] has dissimilar base materials on the two
sides of the junction. The dissimilarity in the bandgaps of the two materials create unique
electrical properties (when the materials are brought in contact) that make a transistor
with one|more heterogeneous junctions ideal for ultra high frequency(100 s of MHz–10 s
of GHz) and high power(100’s of Amperes and Volts) switching applications.
The very high input impedance of a MOSFET (teraOhm range due to its gate insula-
tion) differentiates it from the BJT. So heterogeneous junction field effect transistors exploit
the advantages of non-silicon semiconductor materials (e.g., vastly superior electron mobil-
ity) and the insulating properties of silicon dioxide. The electric field is created by using
a metal–semiconductor junction, that enables a vertical electric field to control the charge
in the channel. The two main devices that exploit this property are the MESFET (metal–
semiconductor FET), and HEMT (high-electron-mobility transistor). These transistors are
HJFETs (heterogeneous junction field effect transistors) because of the presence of a
metal/semiconductor heterogeneous junction in their structure.
The high electron mobility semiconductors in MESFETs and HEMTs ensure high
transconductance, which is a prerequisite for ultra high frequency(100 s of MHz–10 s of
GHz) and high power applications. Electron mobility is enhanced in a HEMT is boosted
using a variety of device fabrication tricks—e.g., by reducing the doping density in the
barrier layer neighbouring the channel, exploiting spontaneous and piezoelectric polariza-
tion. The key feature of a heterogeneous junction field effect transistor is the two dimensional
electron gas (2DEG) which behaves like free electrons in a metal. The heterogeneous junction
field effect transistor’s superb performance characteristics result from carefully controlling
the two dimensional electron gas.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 81

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_6
82 6 Heterogeneous Junction Field Effect Devices—Schottky Diode, Metal …

6.2 Metal Semiconductor Junction—Schottky Barrier

Diode—Ohmic, Rectifying

A metal–semiconductor junction that normally acts as a rectifier are called Schottky bar-
rier. The simplest case is when the electrostatics of the junction is determined by the
work functions  of the two components, and by the electron affinity X S of the semi-
conductor. Figure 6.1a–d show the energy bands for the following cases of this simple
metal–semiconductor junction.

• The metal and the semiconductor are not in contact.

• The metal and semiconductor are in contact and the junction is in equilibrium.
• The metal semiconductor junction is forward biased.
• The metal semiconductor junction is reverse biased.

When brought in contact, electrons flow from the metal to the semiconductor, resulting
in a depletion region. The width of this depletion zone can be controlled (modulated) by
applying a bias (forward|reverse).

(a) (b)

(c) (d)

Fig. 6.1 a, b metal and semiconductor junction before contact and after contact. c, d forward and
reverse biased metal semiconductor junction
6.2 Metal Semiconductor Junction—Schottky Barrier Diode—Ohmic, … 83

The applied bias also changes the the barrier height for electrons crossing the junction
from the semiconductor to the metal—just like that of an homogeneous np junction. A
key difference between a heterogeneous and homogeneous semiconductor junction is that
for a homogeneous np junction, the net flow across the junction is determined to by the
subsequent diffusion of the injected electrons in the p-region. This impedes charge transport,
and perturbs the junction from the equilibrium state. Thus, the quasi Fermi levels are
almost constant across the junction.
For a metal semiconductor junction there is an abrupt change in the Fermi levels at the
interface—equilibrium conditions are irrelevant. This arises because the electrons injected
into the metal are not controlled by diffusion—they simply join other electrons already in the
conduction band of the metal, and a large current can be maintained by an infinitesimal field.
Then charge transport across the junction is controlled by itself and the current across the
junction has to be driven by a change in the Fermi level. An identical situation arises in
an Np heterogeneous junction with a very short base. From the current density due to
electrons injected into the metal is:
−V A P P χ S E M I − M E T AL −V A P P
Jelectr on = qn 0 v R e VT H E R M AL = q NC O N D v R e VT H E R M AL (6.0)

where  M E T AL − X S E M I is the Schottky barrier height. At zero-bias, electron current

density from the semiconductor to the metal must be matched by the electron current density
from the metal to the semiconductor. This flow from the metal is not affected by the applied
bias. The full expression for the current is:
 χ 
−V A P P S E M I − M E T AL −V A P P χ S E M I − M E T AL
Jelectr on = qn 0 v R e VT H E R M AL = q NC O N D v R e VT H E R M AL − e VT H E R M AL
(6.1)

The two main modes of charge transport for a metal semiconductor junction are
thermionic emission and tunnelling. Although there is an abrupt discontinuity in the
quasi Fermi level at the junction, quasi|weak equilibrium conditions can still be applied—
Fig. 6.2a, b. The current due to a small number of highly energetic electrons, from a much
larger pool of electrons (that remain in an equilibrium distribution), lead to thermionic
emission. The number of electrons contributing to thermionic emission is small if the
depletion-region potential drops by at least k B T eV within one mean free path length l
of the junction. If the doping density is very large, then the bands bend very steeply in
the semiconductor—if the barrier becomes less than ≈5 nm, then tunnelling of electrons
can take place. Electrons can pass through such a barrier in either direction. The junction
loses its rectifying property. The I-V characteristic becomes linear about the origin, and the
contact is said to be ohmic—essential when the metal is required merely to connect the
semiconductor to external circuitry with minimal voltage drop. Both ohmic and rectifying
contacts are used in heterogeneous junction field effect transistors.
84 6 Heterogeneous Junction Field Effect Devices—Schottky Diode, Metal …

(a) (b)

Fig. 6.2 a, b Thermionic and tunnelling across metal semiconductor junction

6.3 Metal Semiconductor Field Effect Transistor (MESFET)

The physical structure of a metal semiconductor field effect transistor (MESFET) is in

Fig. 6.3a. The n P LU S ‘cap’ layer provides ohmic contacts for the source and drain, while
the gate metallization is chosen to make a rectifying contact to the less heavily doped n
type active layer. The n regions are grown epitaxially on a weakly doped p region or on
a semi-insulating substrate.
Figure 6.3b shows the space-charge region underneath the gate in a MESFET with
VDS > 0. This bias makes the semiconductor potential at the drain more positive than the
source. So the drain side of gate-semiconductor Schottky barrier is reverse biased with
reference to the gate—the space-charge region is wider in the vicinity of this junction.
The band bending in this layer, and at the n semiconductor insulating junction creates a
channel through which charge must pass while traversing to the drain from the source,
Fig. 6.3c. The space-charge region width W(x) is controlled by the bias VG S applied to
the Schottky diode. If, at zero bias, W is less than the thickness of the active layer, then
the channel is ‘open’. To ‘close’ it the Schottky diode must be reverse biased sufficiently
for the depletion-region edge to reach the interface between the active and semi-insulating

(a) (b)

Fig. 6.3 a, b physical structure and channel formation in MESFET

6.3 Metal Semiconductor Field Effect Transistor (MESFET) 85

regions. The gate source voltage required to achieve this is the threshold voltage VT —
negative for n-type semiconductors. FETs which are conducting when VG S = 0 are called
depletion mode FETs.
A closed channel for a MESFET is equivalent to a MOSFET’s ‘pinch-off ’ condition. It
denotes drain current saturation in ‘Level 1’ model FET. The channel charge goes to zero at
the drain end of the channel, though in reality the charge is small, but finite, and the current
is sustained at a high value because the electrons are moving very quickly in this part of the
channel. No channel charge condition occurs if the semiconductor active layer is so thin
that the depletion region at zero bias reaches right through the semiconductor. The channel
is opened up by forward biasing the Schottky junction—then current grows exponentially
with forward bias. So the upper limit on the forward bias is set by the leakage current to
the gate that can be tolerated, and is only a few tenths of a volt. A MESFET working in
this mode has a positive threshold voltage and is an enhancement-mode device.
A depletion mode Level 1 MESFET has drift current density:

→ ∂ VC H AN N E L
= −nqμelectr on (6.2)
Jelectr on,D R I F T ∂x

The drain current is by definition:

I D R AI N = − Jelectr on wtransistor (Channelthickness − W (x))

/
2εs
W (x) = (VB I + VC S (x) − VG S ) (6.2a)
NDO N O R

where  S , N D are the semiconductor material permittivity and doping density of the active
layer. Combining the Eq. 6.2a–d gives the general expression for the drain current:
Aqμelectr on N D O N O R Wtransistor
I D R AI N =
 L
2  
VDS − √ (VDS + VB I − VG S )1.5 − (VB I − VG S )1.5
3 VB I − VT H RS H
(6.3a)

After some manipulation, the the saturation drain current is:

Aqμelectr on N D O N O R Wtransistor
I D R AI N ,S AT =
L

2  
1.5 1.5
VG S − VT H R S H − √ V B I − VT H R S H − V B I − VG S (6.3b)
3 V B I − VT H R S H
86 6 Heterogeneous Junction Field Effect Devices—Schottky Diode, Metal …

6.4 High Electron Mobility Transistor (HEMT)

In a high electron mobility transistor (HEMT) unlike a MESFET, the channel exists
in an underlying, undoped, semiconducting layer Fig. 6.4. Absence of impurity dopant
atoms translates to elimination of ionized impurity scattering. Consequently, electrons
move inside this transistor just like free electrons in a metal. The barrier semiconductor
forms a heterogeneous junction with the gate metal, and a heterogeneous junction with
the channel layer—Fig. 6.5. For the AlGaAs/GaAs case examined here, the electron affini-
ties of the two semiconductors are not equal, so there is a discontinuity in the conduction
band edge. This discontinuity defines one side of the channel, containing confined the
electrons induced into the undoped semiconductor during charge transfer at the time the
system equilibrates. The large band-bending in the undoped semiconductor forms the
other side of the confining potential well. The confinement in the x, y directions is such that
the electrons are free to move only in the two, mutually orthogonal directions (x, y). These
highly mobile electrons form a two dimensional electron layer (two dimensional electron
gas—2DEG). Chapter 15 is dedicated to detailed discussion on state-of-art gallium nitride
(GaN) HEMTs.

Fig. 6.4 Physical planar

layered structure of a
AlGaAs-GaAs HEMT

Fig. 6.5 Heterogeneous

junction structure and
formation
6.4 High Electron Mobility Transistor (HEMT) 87

Fig. 6.6 Triangular potential

well and rectangular well
approximation for
heterogeneous junction of
HEMT

6.4.1 The Two Dimensional Electron Gas (2 DEG) [1–6]

The two dimensional electron gas is so unique that it requires careful analysis, with two
simplifying assumptions.

• The triangular potential well at the AlGaAs/GaAs interface is approximated by a

rectangular potential well Fig. 6.6.
• This asymmetrical finite barrier is approximated by a symmetrical barrier stretching to
infinite energy.

In this potential well, Schrodinger’s wave equation becomes:

√
d 2 ψ(x) 2m P E
+ k x ψ(x) = 0 k x = (6.4a)
dx 2 ℏ
The boundary conditions for an infinitely high potential barrier, the corresponding
simplest solution, the wave vectors and associated energy levels are:

nπ ℏ2 n 2 π 2
ψx (0) = ψx (a) = 0 ψx (x) = A0 sin(k x x) k x = n = 1, 2, 3, . . . E x,n =
a 2a 2 m P
(6.4b)

The allowed energy levels are quantized. Each allowed energy level depends on k, which
is quantized—integer multiples of the reciprocal of the length of the region of interest. The
length a is small, so the allowed energy levels are widely separated, and cannot be viewed
as a continuum. However there are bands in the orthogonal directions to that of the channel
thickness. Each of the allowed energy levels are allowed bands of energy in the unconstrained
perpendicular directions y and z. Assuming that electrons are confined near the bottom of
these bands, then a parabolic E-k dispersion relationship is used to characterize these bands.
Assuming an isotropic effective mass, the total energy is:

ℏ2 k 2P E R P
E = E x,n + (6.4c)
2m P
88 6 Heterogeneous Junction Field Effect Devices—Schottky Diode, Metal …

(a) (b)

Fig. 6.7 a–d Energy band diagrams for AlGaAs-GaAs heterogeneous junction interface under var-
ious HEMT operating conditions. Dark dots are electrons, ‘ + ’ are holes

Electrons are trapped in an infinite potential well. This is ensured by setting ψ = 0 at

y = 0, in deriving the discrete energy level expressions. T he wavefunctions are sinusoidal
and the probability density function, for the first energy level, e.g., indicates the greatest
probability of finding the electrons at the centre of the well. This is the ideal condition for
correct FET operation since it keeps the electrons away from the vicinity of the junction—
crystalline imperfections at the interface can trigger scattering and a reduction in mobility
in real world devices—Fig. 6.7a–c. The well is not finite, so electrons can escape through
the sides of the potential well—i.e., the probability density function for channel electrons
is not zero in the barrier.
Although penetration into the barrier cannot be prevented, its effect on the mobility
can be minimized by inserting a thin, undoped region of AlGaAs barrier material spacer
layer, next to the interface. This minimizes ionized impurity scattering.
The concentration of electrons in the potential well region can be estimated easily, by
estimating the number of states in a two dimensional region of area π k 2P E R P . The annular
surface of this circle has an area of 2π k P E R P ∂k P E R P . In one dimension a state occupies
2π/L of k-space, where L is the real space length in that direction. The number of states
in the annulus, is:
4π k P E R P ∂k P E R P k P E R P ∂k P E R P L y L z
N2D I M = = (6.5a)
4π 2 π
L y Lz

where L y , L z are the physical dimensions of this region. After dividing the above expres-
sion by the real space area L y L z , and after converting ∂k P E R P to ∂ E and finally dividing
by ∂E, the two dimensional density of states per unit area and per unit energy, for each
sub-band, is
References 89

mP
g2D I M = (6.5b)
π ℏ2
This density of states expression for each sub band is independent of energy. Estimating
electron concentration in each sub-band is straightforward:
 P 
m f (E x , n)d E x,n
n 2D I M,n = (6.5c)
π ℏ2

Each sub band starts at an energy E x,n , and assuming that the top of each sub band is
at infinity, then using Fermi–Dirac distribution function and integrating gives:
 E F E R M I −E x,n

m k B Tlattice 1 + e
P k B Tlattice

n 2D I M,n = (6.5d)
π ℏ2
Finally, the total concentration of electrons in the channel is a summation of the number
of electrons for each sub band:

n T O T AL = n 2D I M,n 1 ≤ n ≤ ∞ (6.5e)

The underlying physical processes of the heterogeneous junction inside a HEMT can
be understood with reference to Fig. 6.7a–c. At start, to equilibrate the transistor, the
donors in the AlGaAs barrier layer supply electrons to both the gate metal and to the 2-
DEG in the channel, creating depletion regions at both ends of the barrier layer, provided
that the barrier layer is sufficiently thick so that the two depletion regions do not overlap. So,
n S will reach its highest value n S0 . Figure 6.7b shows two depletion regions just meeting
at equilibrium without any overlap. This is the ideal equilibrium for HEMT operation.
Now a reverse bias applied to the gate barrier Schottky diode forces electrons from to
the channel region to move into the gate region—n S decreases—Fig. 6.7c. This shows
the electron quasi Fermi level E Fm dropping towards the first allowed energy level. With
gradual increase of the reverse bias, a situation will be reached where all the donors donate
electrons to the gate. In this case n S tends to 0, and the applied voltage V A P P = VT .

References

1. Sze, S. M. (2002). Semiconductor devices, physics and technology (2nd ed.). Wiley.
2. Berz, F. (1985). The bethe condition for thermionic emission near an absorbing boundary. Solid
State Electronics, 28, 1007–1013.
3. Kabiraj, D., Grötzschel, R., & Ghosh, S. (2008). Modification of charge compensation in semi-
insulating semiconductors by high energy light ion irradiation. Journal of Applied Physics., 103,
053703.
4. Roblin, P., & Rohdin, H. (2002). High-speed heterostructure devices. Cambridge University
Press.
90 6 Heterogeneous Junction Field Effect Devices—Schottky Diode, Metal …

5. Griffiths, D. W. (1995). Introduction to quantum mechanics. Prentice-Hall.

6. Pulfrey, D. L. (2010). Understanding modern transistors and diodes. Cambridge University Press.
ISBN 13 978-0-521-51460-6.
AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large
Signal Equivalent Electrical Circuits (Angelov
7
Chalmers Model)—Normally On|Off HEMT,
pHEMT, mHEMT and MODFET

7.1 Large and Small Signal Models of HEMTs and MESFETs

The large signal model and the corresponding equivalent electrical circuit of a HEMT
represent the model of the transistor that can be used to analyze and understand the
behaviour and performance of the transistor under steady state operating conditions. As
both the HEMT and the MESFET are unipolar, field effect transistors, the large signal
model represents the drain source current under steady state conditions. In contrast,
the large signal model for a HBT (heterogeneous bipolar|bijunction transistor) is more
complicated as the large signal model must represent both the collector-emitter and base
emitter currents under steady state operating conditions.
The small signal model representation of the same HEMT|MESFET is essential for all
signal frequency based analysis. The small signal analysis is used to extract the scatter-
ing parameters (S-parameters). The measured S-parameters are used to estimate essential
frequency dependent device properties as input|output impedances, device internal capac-
itances (parasitic|non-parasitic), parasitic impedances etc., Of large number of available
large|small signal device models, widely used ones are the Angelov [1–12], Curtice,
CMC (Compact Modelling Consortium), MVSG (MIT Virtual Source GaN field effect
transistor) have been included in available commercial CAD tools.

7.2 Angelov-Chalmers Large Signal Model for HEMTs

and MESFETs

The equivalent electrical circuit for the Angelov [1–12] large signal model for a HEMT
Fig. 7.1. The drain source current is nonlinear:

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 91

A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_7
92 7 AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large Signal Equivalent Electrical …

IDSP − IDSN
IDS = (7.1a)
2
   
IDSP = IPK0 1 + tanh(ψ P ) 1 + tanh(α P VDS ) 1 + λ P VDS + L S B0 e VDG −VT R
(7.1b)

IDSN = IPK0 (1 + tanh(ψ N )(1 − tanh(α N VDS )(1 − λ N VDS ))) (7.1c)

ψ P = P1M (VGS − VPK ) + P2M (VGS − V + P K )2 + P3M (VGS − VPK )3 (7.1d)

ψ N = P1M (VGD − VPK ) + P2M (VGD − V + PK)2 + P3M (VGD − VPK )3 (7.1e)

VPK (VDS ) = VPKS − ∆VPKS + ∆PPKS tanh(α S VDS + K BG VBG ) (7.1f)

P1M = P1 ( f (T ))((1 + ∆P1 )(1 + tanh(α S VDS ))) (7.1g)

P2M = (1 + ∆P2 )(1 + tanh(α S VDS )) P3M = (1 + ∆P3 )(1 + tanh(α S VDS )) (7.1h)

gm,MAX
α P = α R + α S (1 + tanh(ψ P )) α N = α R + α S (1 + tanh(ψ N )) P1 = (7.1i)
IPK0
Here Ψ P is a power series centred around VPK . K BG controls the dispersion through the
intrinsic gate voltage at RF frequencies. ∆P1 , ∆P2 control the second and third harmonic
dependencies through VDS .
The temperature dependency of P1 is embodied in f(T) which represents the tem-
perature dependencies of the carrier velocities. The temperature dependency of carrier
concentrations is embodied in the temperature dependency of IPK0 . The other parameters
are:

• IPK , VPK are the drain current and gate voltage for gm,M AX

Fig. 7.1 Basic Angelov Chalmers HEMT equivalent circuit model

7.3 Gallium Nitride (GaN) Properties Normally On|Off HEMTs 93

• αn , α p are the saturation parameters

• λn , λ P are channel length modulation parameters

The total number of parameters is 11. The numerical values of these parameters for a
given transistor are estimated from a combination of DC sweep (large signal) and small
signal AC frequency dependent experimental data.
The large and small signal models do not include any transcapacitances, as the time
derivatives of the charge depend only on their own terminal voltage. So the small signal
equivalent circuit consists of these capacitances evaluated at the corresponding DC volt-
age. CGS , CGD are continuous functions of voltages with well defined derivatives—this
guarantee that they converge in harmonic balance simulations.
To measure the frequency dispersion and signal delay, a back-gate scheme is used.
In this case the RF feedback voltage, VBGATE , controls the RF voltage at the gate and
provides both a large and small signal description.
With reference to Fig. 7.1 the delay network (CDEL1 , CDEL2 , RDEL ), connected at
the input accounts for high frequency delay effects. At high frequency, the capacitor
CDEL1 shunts the input and decreases the amplitude of the control voltage VGSC —this is
experimentally observed delay. The value of the delay capacitance is estimated to be in the
femtoFarad range [1–12]. The time constant CDEL RDEL determines the frequency at which
high frequency|power limitations. The frequency dependency of the output power can be
tuned using the capacitance CDEL2 . Both delay capacitors are similar, often assumed to
be equal.
Silicon carbide (SiC) devices exhibit effects found in some GaAs FETs,—an increase
of magnitude of S21 versus frequency. These are due to channel on the spreading resis-
tance Rs. This basic model has been extended [12]. Parameter extraction measurement is
performed with both pure DC sweep and pulsed DC sweeps, resulting in a more robust
large signal model.

7.3 Gallium Nitride (GaN) Properties Normally On|Off HEMTs

Gallium nitride has become the material of choice for constructing HEMTs, because of its
unique properties [13]. State-of-art GaN HEMTs derive their outstanding performance
characteristics by exploiting both spontaneous and piezoelectric polarization induced
inside the device by virtue of its physical layered structure. Basically, the two degree
electron gas (2DEG) is generated without doping. Chapter 15 is devoted to gallium nitride
(GaN) properties and transistors. It (GaN) is a wide band gap semiconductor with both
face centered cubic (FCC) and hexagonal close packed (HCP) wurtzite crystalline struc-
ture, with HCP being the preference for HEMT fabrication. One very attractive property is
the wide band gap (3.4 eV) that gives an intrinsic carrier concentration n I N T R I N S I C sev-
eral orders of magnitude lower than in Si—the advantages being reduced leakage current
94 7 AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large Signal Equivalent Electrical …

and high operating high temperatures. The high critical electric field and the maximum
reachable breakdown of GaN are very important for fabricating high current|voltage (10 s
of Amperes and 100 s of Volts) devices. The breakdown voltage can be engineered to
a target value, and in combination with an equally engineered thin drift layers vastly
reduces the specific on-resistance compared with Si based devices. Consequently, very
compact devices are fabricated, with minimum static and dynamic losses. GaN’s high
electron saturation velocity allows ultra high frequency switching.
High frequency switching is possible mainly due to the two dimensional electron gas
(2DEG) in typical heterogeneous junctions (e.g., AlGaN/GaN) for which the electron
cm2
mobility values exceed 1000V s .
The only disadvantage of the 2DEG is that the GaN HEMT is normally on (depletion
mode) device. Such a GaN HEMT can achieve switching action if a negative voltage is
applied to the gate—channel interruption.
However, normally-off devices are preferred in both ultra high frequency
RF|microwave circuits and high power electronics—creating negative gate voltage pulses
is difficult.
To push the threshold voltage above zero for a normally-off HEMT, the region near the gate
must be appropriately modified, e.g., by near surface processing, or bandgap engineering
techniques.

• The “recessed gate” approach to creating a “normally-off” HEMT, involves reduction

of the AlGaN barrier layer thickness under the gate. Below a certain AlGaN thickness,
the Fermi level at the interface will lie below the AlGaN conduction band minimum—
effectively depleting the 2DEG below the gate, and thus a positive threshold voltage.
• Another approach is the “fluorine gate” HEMT. Negatively charged fluorine ions are
added below the gate electrode, either by plasma or ion implantation. The freshly
added negative charge produces a positive shift of the threshold voltage and depletes
the 2DEG. Also the negative fixed charges will force an upward conduction band
bending of the AlGaN, increasing the metal/AlGaN barrier height and reduce the gate
leakage current.

These and some related solutions are difficult to implement in large scale real-world
HEMT fabrication processes. Currently, three solutions for fabricating normally-off GaN
HEMTs are the “cascode” configuration, the “p-GaN gate” and the “recessed gate hybrid
MISHEMT”.

7.3.1 P-GaN Gate P-GaN-AlGaN-GaN Normally-Off HEMT [1–19]

Figure 7.2a–c show respectively the physical layered structure and energy band diagram of
a p-GaN gate AlGaN-GaN HEMT [14]. The p-GaN cap layer forces the the Fermi level
7.3 Gallium Nitride (GaN) Properties Normally On|Off HEMTs 95

Fig. 7.2 a–c p-Gate scheme to (a) (b)

convert normally on
AlGaN-GaN HEMT a to
normally off HEMT b and
corresponding conduction
energy bands

of the AlGaN to move below its conduction minimum, thereby disrupting the 2DEG.
So a normally on AlGaN-GaN HEMT becomes a normally-off HEMT. In a normally-on
AlGaN-GaN HEMT, the Fermi level is in the middle of the potential well at the junction
interface, allowing electrons to collect and form the 2DEG.
To achieve an efficient 2DEG depletion and push the HEMT threshold voltage to above
zero, the properties of the AlGaN-GaN heterostructure such as thickness of the AlGaN
barrier and Al-concentration must be accurately monitored. Typically, in a normally-off
p-GaN-AlGaN-GaN heterostructure the AlGaN barrier layer thickness is approximately
18
10–15 nm, with Al concentration of about of 15–20%. A high doping level (> 10 cm3
) of the
p-GaN layer is necessary. To improve the threshold voltage for a fixed Mg concentration
of the p-GaN layer the Mg electrical activation is boosted by carefully controlling p-GaN
layer growth parameters and annealing conditions. This is an active topic of research and
development [13].

7.3.2 Recessed Gate Hybrid MISHEMT

(Metal–Insulator–Semiconductor HEMT)

In this novel HEMT structure (Fig. 7.3), shows the recessed gate hybrid GaN MISHEMT.
In the gate region the AlGaN barrier layer is removed by plasma etch and the recessed
GaN region is passivated by an insulator. This device is a hybrid transistor connecting in
series the recessed MIS channel with two access regions having a low resistance—2DEG
[15, 16]. Li [15] and Ikeda [16] have reported recessed gate hybrid GaN MISHEMTs
with threshold voltage 2 V, specific on-resistance of 10 mΩ cm2 and breakdown in the
kV range. With reference to Fig. 7.3, the on resistance of this device is:

RON, MISHEMT = 2RCONTACT + RCHANNEL + RSG, 2DRG + RGD, 2DEG

96 7 AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large Signal Equivalent Electrical …

Fig. 7.3 Recessed gate hybrid

MISHEMT method to convert
normally on AlGaN-GaN
HEMT to normally of HEMT.
Dark spots are electrons

The channel resistance is directly proportional to the channel length and inversely
proportional to the electron mobility.
The recessed gate region is the most important part of this normally-off transistor. The
surface roughness of the recessed area, the presence of electrically active defects, and the
electronic quality of the insulator/GaN interface all control the properties of this device.
The channel mobility also affects the total on-resistance. Consequently, the insulator-GaN
interfaces in the recessed channel of MISHEMTs ia an active research topic [13].

7.3.3 Cascode Combination of Enhancement NMOS FET

and Normally-On HEMT

This is a very simple way to convert a normally on HEMT to a normally off device, by
connecting an enhancement mode NMOS in the cascode configuration—Fig. 7.4.
The advantages/disadvantages of the three schemes are listed as follows:
p-GaN gate:
Advantages:
Low resistance under gate and no dielectric problems.
Disadvantage:
p-GaN etching must be optimized for low access resistance and better reliability. Gate
voltage swing is limited.
Recessed gate hybrid MISHEMT

Fig. 7.4 Cascode

configuration of normally on
AlGaN-GaN HEMT with
enhancement mode (normally
off) NMOS to covert HEMT to
normally off HEMT. Dashed
line represents 2DEG
7.4 AlGaAs-GaAs Normally on HEMT|p (Pseudomorphic) HEMT and Double … 97

Advantages:
Large forward breakdown and standard device driving in applications.
Disadvantages:
Inappropriate for low voltage (<100 V) applications due to gate channel resistance.
Gate region properties (interface roughness, dielectric properties) affect device reliability
and performance.
Enhancement NMOS and Normally On HEMT Cascode:
Advantages:
Stable, tried and tested silicon MOSFET technology.
Disadvantages:
Inappropriate for low voltage (<600 V) and high frequency (>1 MHz) applications. Sil-
icon NMOS needs to be optimized for each application resulting in increased package
complexity.

7.4 AlGaAs-GaAs Normally on HEMT|p (Pseudomorphic) HEMT

and Double Heterojunction HEMT [1–19]

The structure and energy band diagram of the alumimum-gallium-arsenide—gallium

arsenide (AlGaAs-GaAs) HEMT|pHEMT are shown in Fig. 7.5a–d. AlGaAs is an alloy of
aluminum and gallium arsenide(Al x Ga1−x As x → mole fraction) but is commonly writ-
ten in its shortened form AlGaAs. The original AlGaAs GaAs HEMT exploited the ultra
high electron mobility of the two dimensional electron gas (2DEG) at the heterogeneous
junction interface between AlGaAs and GaAs. AlGaAs has a higher bandgap than GaAs
and is n doped. So electrons are transferred from the AlGaAs layer (also called the supply
layer) into the GaAs quantum well channel as it is energetically more stable for them. It
is also known as the barrier layer due to its higher bandgap energy compared to the chan-
nel material. But due to the small discontinuity of the conduction band energy at the
AlGaAs—GaAs heterojunction interface, the immobile donor charge in the AlGaAs
supply layer is also modulated by the applied gate potential. Consequently the channel
sheet charge density is easily saturated, resulting in degraded modulation efficiency and
speed of the AlGaAs/GaAs HEMT device. Using clever bandgap engineering tricks, if
the GaAs channel is substituted with an indium gallium arsenide (InGaAs) thin film
inserted between the GaAs buffer and the AlGaAs supply layer, the resulting AlGaAs/
InGaAs heterostructure has a larger conduction band discontinuity. Now electrons are
tightly confined within the InGaAs quantum well and the electron mobility of InGaAs is
98 7 AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large Signal Equivalent Electrical …

(a) (b) (c)

Fig. 7.5 a–c AlGaAs-GaAs HEMT, pseudomorhic AlGaAs HEMT and double pseudomorphic
AlGaAs-GaAs HEMT

higher compared to GaAs.So there is a significant improvement in the modulation effi-

ciency and performance of the HEMT device. InGaAs has a lattice constant mismatch
between AlGaAs and GaAs, but it can be grown dislocation free as long as its thickness
is less than a certain critical thickness. Below this critical thickness value, the InGaAs
layer can be compressed and distorted from its normal cubic crystalline structure to match
the lattice constant of both AlGaAs and GaAs. The strain from this lattice mismatch is con-
tained entirely within the InGaAs layer. As the InGaAs layer is unnaturally compressed
to match the lattice constant and structure of GaAs, the device is called pseudomorphic
HEMT.
While the single InGaAs layer pseudomorphic HEMT is ideal for ultra high frequency
RF|microwave applications, in order to use it for ultra high power applications, a double
pseudomorphic HEMT structure is required. there is an n-AlGaAs supply layer not only
on top but also below the channel. The common power pHEMT structure has a InGaAs
channel between the two n-AlGaAs supply layers.

7.5 m(Me)tamorphic HEMT and MODFET

The indium gallium arsenide (InGaAs) layer that gives the pHEMT its enhanced ultra high
electron mobility also introduces crystalline imperfections due to strain. As all the layers of
a HEMT are deposited using molecular beam epitaxy, this means that the deposited layer
must have the same crystalline structure as the substrate layer on which it is laid down.
So, channels with indium mole fractions >25% are not fabricated on GaAs substrates,
Fig. 7.6a, b. Indium phosphide (InP) overcomes the strain induced performance limitation
since it is lattice matched with 53% mole fraction InGaAs channels. But manufacturing
these devices is complicated and increases manufacturing costs.
GaAs based metamorphic HEMT (mHEMT) technology addresses this issue by pro-
viding a properly grown buffer between the substrate and active device layers. In the
mHEMT, the device active layers are grown on a strain relaxed, compositionally graded
buffer layer which transforms the lattice constant from GaAs up through InP, allowing a
high In content channel layer to be grown on low cost GaAs substrates. The buffer layer
7.6 AMS-CMC GaN HEMT Model 99

Fig. 7.6 a–c 30% InGaSd (a) (b) (c)

pHEMT (a), 50% InP HEMT
(b) and 60% InP mHEMT on
GaAs substrate (c).
Compositions for the top
Schottky layer InGaAs channel
and substrate are shown

provides the ability to tailor the lattice constant to any indium content channel desired (20–
70%), and allows the device designer an additional degree of freedom to optimize transistors
for high frequency gain, power, linearity and low noise. For example, using a metamor-
phic buffer layer, InP-based high electron mobility transistors (53% In) can be grown on
GaAs substrates for a substantial cost reduction and manufacturability improvement over
InP-substrate based devices—Fig. 7.6c.
The MODFETs exceptional switching frequency arise from its structure. The wide
band element is doped with donor atoms (excess electrons in its conduction band). These
electrons diffuse to the adjacent narrow bandgap material’s conduction band due to the
available lower energy states. Immediately, a potential and attendant electric field is gen-
erated, between the materials. The electric field pushes electrons back to the wide band
material’s conduction band. Finally diffusion and electron drift processes balance each
other, creating a junction at equilibrium. The undoped narrow band gap material now has
excess majority charge carriers. The concentration of majority charge carriers (electrons)
results in high switching frequencies, and the undoped low bandgap semiconductor means
donor atoms do not generate unwanted scattering sites.
The secret underlying the MODFET is that the band discontinuities across the conduction
and valence bands can be modified separately. Consequently, the type of carriers in and out
of the device can be controlled. Therefore, a graded doping can be applied in one of the
materials making the conduction band discontinuity smaller, and keeping the valence band
discontinuity the same. This diffusion of carriers leads to the accumulation of electrons
along the boundary of the two regions inside the narrow band gap material.

7.6 AMS-CMC GaN HEMT Model

The AMS CMC (Compact Modelling Constortium) model [19–33] for the GaN HEMT
is used in all commercially available CAD (Computer Aided Design) tools as AWR
Microwave Office and Agilent ADS.
The AMS CMC HEMT model has been developed based on surface potentials, and
the Fermi level is:
100 7 AlGaAs-GaAs, AlGaN-GaN, SiC, HEMT Large Signal Equivalent Electrical …

 Vgo

2VTHERMAL ln 1 + e THERMAL
2V

E FERMI, CMC = Vgo − −Vgo

(7.2a)
C g e VTHERMAL
1
H (Vgo, p )
+ qD

where Vgo = VGS − VOFF VOFF is the cut-off voltage and CGATE , D are the gate
capacitance per unit area and density of states respectively.
Vgo, p = Vgo : VGS ≥ VTHRSH Vgo, p = VTHERMAL : VGS < VTHRSH H contains infor-
mation about the Fermi level when Vgo > VOFF . The gate charge is:
 
 
Q GATE = − qW nd x = − qW CGATE VGS − VOFF − E f − V (x) d x 0 ≤ x ≤ L
(7.2b)

Using the surface potential concept, the drain current is:

  
μeffective CGATE (ψ D − ψ S ) 1 + λVDS, effective Vgo + VTHERMAL − ψm W
IDS = / (7.2c)
L 1 + θSAT
2 (ψ − ψ )2
D S

where λ, θSAT are channel length modulation and velocity saturation parameters respec-
tively.
Ψm = Ψ D +Ψ
2
S
and mobility degradation due to the vertical field is:

U0
μeffective =    2 (7.2d)
1 + UA Vgo − ψm + U B Vgo − ψm

where U0 , U A , U B are curve fitting parameters. The drain current implementation includes
drain induced barrier lowering (DIBL), via the bias dependency of the cut-off voltage. The
total source, drain access region resistance is implemented as a sum of the source, drain
contact resistance and the bias dependent access region resistance.
Depending on the underlying mechanism, the gate current is divided into three
components. The current density for the Poole–Frenkel part of the gate current is:
√
JPoole, Frenkel = C Eeα+β E
B = ∊S K (7.2e)

−Φd
where α = VTHERMAL Φd is the barrier height for electron emission from the trap state.
/
q
π ∊S
β= VTHERMAL C is a parameter dependent on the trap concentration and E is the electric
qα −C
field. E = p GATE (Vgo −Ψ ) α .
εS P
The thermionic emission and trap assisted tunnelling currents are:
  V 
GATE −ψ
ITHERMIONIC EMISSION = W JTE0 e ηVTHERMAL − 1 dx 0 ≤ x ≤ L
References 101

−Φ B
JTE0 = A P Tlattice
2
e VTHERMAL (7.2f)

  V 
GATE −ψ−V0
ITRAPASSIST TUNNEL = W JTE0 e ηVTHERMAL − 1 d x 0 ≤ x ≤ L (7.2g)

JT A0 is the reverse saturation current density, and

J1 = JT E0 K L W J2 = JT A0 K L W (7.2h)

A P is the effective Richardsons constant, ΦB is the Schottky barrier height, η is the

ideality factor and V0 curve is a fitting parameter.
There are two DC transfer characteristics of a field effect transistor:

• Drain source current with linearly or pulsed varied gate source voltage and constant
drain source voltage.
• Drain source current with linearly or pulse varied drain source voltage and constant
gate source voltage.
Both methods create a family of curves.

References

1. Angelov, I., Desmaris, V., Dynefors, K., Nilsson, P. A., Rorsman, N., & Zirath, H. (2005). On
the large signal modelling of AlGaN/GaN HEMTs and SiC MESFETs (pp 309–311). 13th GAAS
Symposium Paris.
2. Trew, R. J. (2002). SiC and GaN transistors—Is there one winner for microwave power appli-
cations? Proceedings of the IEEE, 90, 1032–1047.
3. Neudeck, P. G., Okojie, R. S., & Yu, C. L. (2002, June). High-temperature electronics—a role
for wide bandgap semiconductors? Proceedings of the IEEE, 90, 1065–1076.
4. Wu, Y. F., Saxler, A., Moore, M., Smith, R. P., Sheppard, S., Chavarkar, P. M., Wisleder, T.,
Mishra, U. K., & Parikh, P. (2004). 30-W/mm GaN HEMTs by field plate optimization. IEEE
Electron Device Letters, 25(3), 117–119.
5. Binari, S. C., Klein, P. B., & Kazior, T. E. (2002). Trapping effects in GaN and SiC microwave
FETs. Proceedings of the IEEE, 90, 1048–1058.
6. Canfield, P. C., Lam, S. C., & Allstot, D. J. (1990). Modeling of frequency and temperature
effects in GaAs MESFETs. IEEE Journal of Solid State Circuits, 25(1), 300–306.
7. Scheinberg, N., Bayruns, R., & Goyal, R. (1988). A low-frequency GaAs MESFET circuit
model. Solid State Circuit, 23, 605–608.
8. Lee, M., et al. (1990, October). A self-backgating GaAs MESFET model for low-frequency
anomalies. IEEE Transactions on Electron Devces, 37, 2148–2157.
9. Curtice, W. R., Bennett, J. H., Suda, D., & Syrett, B. A. (1998). Modeling of current lag in GaAs
IC’s. Microwave Symposium Digest, 2, 603–606.
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10. Desmaris, V., Eriksson, J., Rorsman, N., & Zirath, H. (2004). High CW power 0.3 μm gate
AlGaN/GaN HEMTs grown by MBE on sapphire. In Material science forum, ICSCRM 2003,
(Vol. 457–460, No. II, pp. 1629–1632).
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4H-SiC MESFETs for high frequency applications. In Material science forum, ICSCRM 2003
(Vol. 457–460, No. II, pp. 1229–1232).
12. Angelov, I., Bengtsson, L., & Garcia, M. (1996). Extensions of the Chalmers nonlinear HEMT
and MESFET model. IEEE Transactions on Microwave Theory and Techniques, 44, 1664–1674.
13. Roccaforte F., Greco G., Fiorenza P., & Iucolano, F. (2019). An overview of normally-off high
electron mobility transistors. Materials, 12, 1599. https://doi.org/10.3390/ma12101599
14. Uemoto, Y., Hikita, M., Ueno, H., Matsuo, H., Ishida, H., Yanagihara, M., Ueda, T., Tanaka,
T., & Ueda, D. (2007). Gate injection transistor (GIT)—A normally-off AlGaN/GaN power
transistor using conductivity modulation. IEEE Transactions on Electron Devices, 54, 3393–
3399.
15. Li, Z., & Chow, T. P. (2011). Channel scaling of hybrid GaN MOS-HEMTs. Solid-State Elec-
tronics, 56, 111–115.
16. Ikeda, N., Tamura, R., Kokawa, T., Kambayashi, H., Sato, Y., Nomura, T., & Kato, S. (2011).
Over 1.7 kV normally-off GaN hybrid MOS-HFETs with a lower on-resistance on a Si substrate.
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for-rf-applications.
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Homogeneous Bipolar|Bijunction Transistor 8

8.1 NPN and PNP Homogeneous Bipolar Transistors

Conceptually, two common homogeneous np junction diode can be connected in two

ways—anodes (p-doped regions) joined together or the cathodes (n-doped regions joined
together). The first configuration conceptually forms the NPN transistor (negative–posi-
tive–negative) while the second is the PNP (positive–negative–positive) transistor [1–15].
For the NPN transistor, the p-doped region forms the base, with one of the other two n-
doped regions the collector, and the remaining n-doped region the emitter. The collector
and emitter regions are not interchangeable:—the emitter region is orders of magnitude
heavily doped compared to the collector region. For a PNP transistor, the common n-
doped region is the base terminal. The majority charge carrier in the NPN transistor are
electrons, while for the PNP it is holes. As holes are defects in the crystal lattice, rather
than actual particles (electrons) the NPN transistor is much faster and easier to analyse.

8.2 Ebers Moll Model of a NPN Transistor

The Ebers Moll model [1–6] was the first attempt to analyse the bipolar|bijunction transis-
tor. The model was improved from Eber Moll I to Ebers Moll II and Ebers Moll III, but it
has been superseded by the superior Gummel Poon model that addresses the deficiencies
of the Ebers Moll model. With reference to the simplest Ebers Moll model (Fig. 8.1a),
considering the base-emitter junction in isolation, the current is:

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 103
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_8
104 8 Homogeneous Bipolar|Bijunction Transistor

  
D E n i2 D B n i2 V B AS E−E M I T T E R
IF W D = q A + e VT H E R M AL −1
L E NE NB WB
  (8.1a)
D E n i2 D B n i2
IE S = q A +
L E NE NB WB

and similarly for the base collector junction in isolation,

  
DC n i2 D B n i2 V B AS E−C O L L EC T O R
IREV = q A + e VT H E R M AL −1
L C NC NB WB
  (8.1b)
DC n i2 D B n i2
IC S = q A +
LC NE NB WB

where:

D B , DC , D E are the charge carrier diffusivities in the base, collector and emitter
regions.
LC , L E are the mean charge carrier diffusion lengths in the collector and emitter
regions.
N B , NC , N E are the charge carrier concentrations in the base, collector and emitter
regions.
q, A, n i , W B are the electronic charge, junction area of cross-section, intrinsic carrier
concentration and base width respectively.

From Kirchoff’s current law:

IE M I T T E R = IF W D − αR E V IR E V IC O L L EC T O R = α F I F W D − I R E V
(8.1c)
I B AS E = I E M I T T E R − IC O L L EC T O R

Fig. 8.1 a Basic Ebers Moll

model of the NPN
homogeneous junction
transistor. b Charge
concentrations in base (B),
collector (C) and emitter (E)
regions of a homogeneous
junction NPN transistor under
four possible bias conditions
8.3 Gummel Poon Model for a Homogeneous Junction NPN Transistors 105

The charge concentrations in the base, collector and emitter regions under various
biasing conditions is shown in Fig. 8.1b. The analysis for a PNP transistor proceeds on
similar lines, and is left for the reader.

8.3 Gummel Poon Model for a Homogeneous Junction NPN

Transistors

The Gummel Poon model [1–6] includes the missing details of the simple Ebers Moll
model.

• Low current drop in transistor beta (forward DC current gain) because of recombination
of carriers in the base emitter junction.
• Full analysis of Early effect (base-width modulation).
• High-level injection during device saturation.
• Base emitter and base collector junction leakage currents.
• Base collector and base emitter junction capacitances.
• Base, collector and emitter terminal resistances.

The Gummel Poon model is included in SPICE [12–16] (Simulation Program with
Integrated Circuit Emphasis) the gold standard electrical|electronic circuit simulation
and performance evaluation tool, widely available in both open source and proprietary
versions.
The equivalent circuit model for a NPN homogeneous bijunction transistor is in
Fig. 8.2. Based on this equivalent circuit, the base and collector currents are listed next.
Here I LC , I L E E are the collector and emitter leakage currents.
/
 
I SS VVB E −1 n F k B Tlattice q1 q12
ICC = e TE VT E = qb = + + q2
qb q 2 4
 V   V  (8.2a)
BE BC
I SS e T E − 1
V I SS e T C − 1
V
VB E VBC
q1 = + + 1 q2 = +
VB VA IK F IK R
   
I SS VVBC −1 n R k B Tlattice IS E VB E
−1
I EC = e TC VT C = IL E E = e VT E L
qb q qb
(8.2b)
n E k B Tlattice
VT E L =
q
 
V BC
I SC −1 n C k B Tlattice
I LC = e VT C L
VT C L = (8.2c)
qb q
The junction capacitances in Fig. 8.2 are both nonlinear, because of depletion region
and diffusion processes. Here
106 8 Homogeneous Bipolar|Bijunction Transistor

Fig. 8.2 Basic Gummel Poon model

τ F ∂ ICC CJ E
C B E (VB E ) = + m E VB E < FC V J E (8.3a)
∂ VB E 1 − VVBJ EE
 
τ F ∂ ICC CJ E m E VB E
C B E (VB E ) = + VB E F3E + FC ≥ V J E
∂ VB E F2E VJ E (8.3b)
F2E = (1 − FC) 1+m E
F3E = 1 − FC(1 + m E )
τ R ∂ IC E CJC
C BC (VBC ) = + m C VBC < FC V J C (8.3c)
∂ VBC 1 − VVBC
JC
 
τ R ∂ IC E CJC m C VBC
C BC (VBC ) = + VBC F3C + FC ≥ V J C
∂ VBC F2C VJ C (8.3d)
F2C = (1 − FC)1+m C F3C = 1 − FC(1 + m C )

The Gummel Poon model parameters, included in SPICE[12–16] are listed below:

I SS transport saturation current

βF , βR ideal forward|reverse DC current gain
nF, nR forward|reverse current emission coefficient
V A , VB forward|reverse Early voltages
IK F , IK R forward|reverse beta high current roll-off corner
I SC , I S E base–collector|emitter leakage saturation current
nC , n E base collector|emitter leakage current transmission coefficient
mC , m E base collector|emitter np grading coefficient
VJ C , VJ E base collector|emitter junction built-in voltage
CJC , CJ E base collector|emitter zero bias capacitance
τF , τR ideal forward|reverse transit time FC-forward bias depletion capacitance
coefficient
R B , RC , R E base, collector and emitter terminal resistances
8.4 VBIC Enhancement to Gummel Poon Model 107

There are two DC transfer characteristics of a bipolar|bijunction transistor:

• Collector emitter current with linearly or pulsed varied base emitter voltage and
constant collector emitter voltage.
• Collector emitter current with linearly or pulse pulse collector emitter voltage and
constant base emitter voltage.
Both create a family of curves.

8.4 VBIC Enhancement to Gummel Poon Model

The Vertical Bipolar Inter Company (VBIC) [7–10] model was formulated entirely by the
semiconductor and Computer Aided Design (CAD) industry to correct the deficiencies of
the SPICE [12–16] Gummel Poon Model, while exploiting its power and flexibility. The
bijunction transistor properties not addressed by the original Gummel Poon model are:

• Improved Early effect analysis.

• Inclusion of quasi-saturation.
• Parasitic substrate transistor modelling.
• Parasitic fixed (oxide) capacitance modelling.
• Avalanche multiplication analysis.
• Improved temperature dependence modelling.
• Decoupling of base and collector currents.
• Inclusion of self heating (electrothermal) effects.
• C∞ continuous (smooth) modelling.
• Improved heterogeneous junction bipolar transistor (HBT) modelling.

In the VBIC formulation bipolar transistors are 4 terminal: 5 terminal transistors can
be modelled by embedding the VBIC four terminal equivalent circuit model inside a
subcircuit. Figure 8.3a, b show typical planar, vertical layered NPN transistors that VBIC
is designed to model. The VBIC model can also be used for planar, vertical layer PNP
and HBT devices, but is inappropriate for lateral BJTs. VBIC four terminal equivalent
circuit embedded inside a five terminal circuit does not accurately model transistor action
of the second parasitic BJT.
Compact models for circuit simulation must scale properly with device geometry. But
because of the large number of available BJT layout topologies, this scaling does not
work very well—this explains lack of geometry features in VBIC. Geometry scaling for
VBIC is left to either pre-processing for the generation of model libraries for circuit
simulation, or via scaling relations specific to a particular technology implemented either
in the simulator or the CAD system.
108 8 Homogeneous Bipolar|Bijunction Transistor

Fig. 8.3 a–d VBIC enhanced

Gummel Poon NPN
homogeneous junction
transistor model parasitic PNP
transistor and intrinsic NPN
transistor (a, b). Thermal and
phase circuits (c, d). e VBIC
enhanced homogeneous
junction NPN transistor
equivalent circuit model

The equivalent circuit of a VBIC based NPN transistor consists of an intrinsic NPN
transistor, a parasitic PNP transistor, parasitic resistances and capacitances, a local thermal
network (used only with the electrothermal version of the model), and a delay circuit to
account for excess phase for the forward transport current (Fig. 8.3a, b).
In the electrothermal version of VBIC branch currents and charges in the electrical part
of the model depend on the local temperature rise, the voltage on the node dt. The thermal-
2-equivalent circuit has two nodes external to the model so that the local heating|dissipation
can be connected to a thermal network. This thermal network models the thermal properties
of the material in which the BJT and surrounding devices are built.
The equivalent network (Fig. 8.3e) has fixed and bias dependent resistances, capaci-
tances, and current sources, these circuit elements are in reality voltage controlled charge
and current sources Q(V1 , V2 , . . . Vn ) I (V1 , V2 , . . . .Vn ). Therefore resistors and capaci-
tors are then voltage controlled current and charge sources. Branch currents and charges
that are controlled by more than one branch voltage, include transconductance and tran-
scapacitance elements when they are linearized, to enable DC solution, AC, noise and
transient simulations. The VBIC circuit parameters [6] are listed below:

• Zero|non-zero phase forward transport current.

• Non-zero phase forward charge and inductance.
• Reverse transport. forward|reverse base emitter currents.
References 109

• Intrinsic base collector, weak base collector avalanche currents.

• Forward|reverse parasitic transport currents.
• Parasitic base emitter|collector currents.
• Intrinsic|external depletion, diffusion and parasitic base emitter charge.
• Intrinsic (diffusion, depletion), external (diffusion only) and parasitic base collector
charges.
• Intrinsic (modulated), external (fixed) collector resistance.
• External fixed base, fixed emitter and substrate resistances.
• Modulated intrinsic and parasitic base resistances.
• Parasitic overlap base collector|emitter capacitances.
• Thermal current, capacitance and resistances.

The details of the formulation of the VBIC model are in [6].

References

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4. Hess, K. Advanced theory of semiconductor devices. Wiley, IEEE Press. ISBN 100780334795;
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9789332555082.
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14. https://www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-hspice.html
15. https://www.ti.com/tool/TINA-TI
16. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
Metal Oxide Semiconductor Field Effect
Transistor
9

9.1 The Long Channel MOSFET

The MOSFET [1–19] is a minority carrier four terminal (drain, gate, source,
body|substrate) device. For a p doped substrate, electrons flow between drain and source,
and this device is a NMOS. Similarly, for a n doped substrate, holes conduct current
between the drain and source, and this device is a PMOS. So, a MOSFET is either a
“p-channel n-substrate” or a “n-channel p-substrate” device. Originally, MOSFETs had
their gate length greater than 1 micron—“long channel” MOSFET. State-of-art MOSFETs,
as used in microprocessors and computer memory integrated circuits, have gate lengths in
the low nanometer range. Short channel MOSFETs are examined in detail later in this
chapter. The layered structure of a NMOS is in Fig. 9.1a. In a typical circuit, the source
and substrate|body at the same potential, conventionally the ground.
There are two key DC transfer characteristics for a MOSFET.

• Drain source current with linearly or pulse varied gate source voltage and constant
drain source voltage.
• Drain source current with linearly or pulse varied drain source voltage, and constant
gate source voltage.

Both measurements generate a family of curves. The sequence of physical steps involved
in a drain source current versus gate source voltage sweep at constant drain source voltage
are:

• The applied positive gate source voltage repels holes from the substrate close to the
oxide|semiconductor gate substrate interface (surface), resulting in a space charge layer,
across which some of the applied gate-body voltage gets dropped.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 111
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_9
112 9 Metal Oxide Semiconductor Field Effect Transistor

Fig. 9.1 a, bPhysical structure (a) (b)

of a silicon homogeneous
junction MOSFET and charge
distribution in a MOS capacitor

• The potential in the top part of the substrate also causes a voltage drop across the
depleted body source pn junction. The source body diode is forward biased and
electrons are injected into the body.
• The electron injection is highest at the surface corresponding to the highest sub-
strate potential at the surface. The electrons form a thin channel at the surface, which
increases exponentially with applied bias.
• This electron charge becomes dense enough to electrostatically screen the body from
the gate. Gate body voltage increase are absorbed mostly in the oxide. Then the channel
charge and gate bias do not satisfy any exponential relationship.

The basic, exponential current–voltage relationship of a forward-biased diode is still

present at high gate bias. The relevant bias for the forward-biased source-channel diode
is (Ψ S − VS ), where Ψ S is the surface potential in the substrate|body, and VS is the source
potential. The potential-divider action of the series arrangement of the oxide capacitance
and the semiconductor capacitance (Fig. 9.1b) has its effect. Then the drain current is
exponentially related to the surface potential. The surface potential is approximately equal
to the applied gate substrate bias.

∆VG AT E,SU B ST R AT E ∈O X I D E
∆ψ SU R F AC E = C SU R F AC E
CO X I DE = C SU R F AC E
1+ CO X I DE
tO X I D E
∆Q SU R F AC E + ∆Q SU B ST R AT E
= (9.1a)
∆ψ
At low gate bias the charge in the semiconductor is small, so C SU R F AC E << C O X I D E ,
and the surface potential changes directly proportionally to the applied gate substrate
bias. Then the drain current is exponentially related to the gate bias. The surface capac-
itance increase with increasing gate bias due to increased charge in the channel. The
change in the surface potential with the applied gate substrate bias decreases. The
electron charge increases exponentially with the surface potential, but no longer expo-
nentially with the applied gate substrate bias. The boundary between the exponential and
non-exponential regions is gradual, and is associated with the threshold voltage. When
VG AT E S OU RC E ≤ VT the transistor is operating in the sub-threshold region, and the drain
current at zero gate source voltage is the OFF current. When VG AT E S OU T C E ≥ VT the
drain current in this region is the ON current.
9.1 The Long Channel MOSFET 113

The region of the MOSFET in between the drain and source with the gate at the top
and the substrate at the bottom with a metallic substrate contact is a parallel plate MOS
capacitor—gate (top plate), insulating oxide (middle), p-doped substrate (bottom plate). The
energy band diagram of the MOS capacitor is in Fig. 9.2a, b. The gate is heavily doped,
n-type polysilicon, for which the Fermi level is coincident with the conduction band
edge, the insulator is silicon dioxide, and the substrate is p-type silicon. To equilibrate
the system, the Fermi level in the body must be raised, accomplished by transfer of electrons
from the gate. The transferred electrons recombine with holes in the p-type body, creating a
space-charge region of ionized acceptors near to the interface with the oxide. There is band-
bending in this region. The gate acquires a net positive charge due to loss of electrons. The
charge difference across the oxide creates an electric field. The total potential differences
across the oxide and semiconductor are Ψ O X I D E , Ψ SU B ST R AT E . Their sum gives:

Φ SU B ST R AT E − ΦG AT E
VB I = (9.1b)
q

where Φ SU B ST R AT E , ΦG AT E are the respective work functions.

Work function difference between the gate and substrate surface region ensures that
the substrate surface is less p-type than the rest of the bulk, i.e., it is n-type—channel
inversion. In order to create a high electron concentration at the substrate-gate oxide
interface surface, at lower positive applied gate substrate voltage than what would be
required if there were no band bending at equilibrium, i.e., if the built in voltage was
zero. The no band bending condition is flat band condition (Fig. 9.3a), achieved by
applying a negative potential to the gate. The electron concentration (per unit volume) in
the semiconductor is:

ψ(x)−Φ SU B ST R AT E
n(x) = n i e VT H E R M AL (9.1c)

Fig. 9.2 a, b Energy band (a) (b)

diagram for MOS capacitor
with layers separated and in
contact
114 9 Metal Oxide Semiconductor Field Effect Transistor

Fig. 9.3 a, b Flat band and (a) (b)

strong inversion in MOS
capacitor

Deep inside the substrate, where the acceptor doping concentration is uniform,

n i2
n SU B ST R AT E = Φ SU B ST R AT E
N ACC E P T O R
E F E R M I ,SU B ST R AT E − E F E R M I ,I N T R I N S I C,SU B ST A RT E
= (9.1d)
q
Using Eqs. 9.1c, d, e can be re-written as:

ψ(x)−2Φ SU B ST R AT E
n(x) = N ACC E P T O R e VT H E R M AL (9.1f)

With the onset of strong inversion (Fig. 9.3b) of the oxide substrate interface surface,
the total electron charge is:

∫
Qn = −qn(x)d x 0 ≤ x ≤ L (9.1g)

9.2 Surface Charge Model of Long Channel MOSFET Drain

Current

The MOSFET being examined is invariant in the z-direction. So Poisson’s equation for the
body and channel regions ignoring hole charge in the substrate’s depletion|space-charge
region is:

( )
∂ 2ψ ∂ 2ψ q N ACC E P T O R ψ−2Φ SU B ST R AT E −VC H AN N E L,SU B ST R AT E
+ = 1+e V T H E R M AL (9.2a)
∂x2 ∂x2 ∊ SU B ST R AT E
9.2 Surface Charge Model of Long Channel MOSFET Drain Current 115

The electric field at the substrate surface is strongest in the y direction. Assuming the
Gradual Channel Approximation, the variation of surface potential Ψ in the x direction is
negligible compared to that in the y direction—the above equation now one dimensional.
To solve (9.2a), both sides of it are multiplied by ∂Ψ∂ y
∂ y and then integrated from deep
in the substrate, where ψ = 0 (assuming that zero bias is applied to the substrate terminal).
and ∂ψ/∂y = 0, to the surface, where Ψ = Ψ SU R F AC E ∂Ψ SU∂RyF AC E = E y (0).
The last limit is the field in the semiconductor at the oxide-substrate interface. Using
this and Gauss’s law the charge per unit area in the substrate is:
√
Q SU R F AC E = 2q ∈ SU B ST R AT E N ACC E P T O R
/
( )
k B Tlattice −(2Φ SU B ST R AT EV+VC H AN N E L,SU B ST R AT E ) ψVSU B ST R AT E
ψ SU R F AC E + e T H E R M AL e T H E R M AL − 1
q
(9.2b)

As any MOSFET operates with external voltages, for the applied gate-substrate bias,

VG AT E,SU B ST R AT E − VF L AT B AN D = ψ O X I D E (x) + ψ SU R F AC E (x) (9.2c)

Once more applying Gauss’s law gives the charge per unit area of the gate electrode:

Q SU R F AC E (x) = −C O X I D E (VG AT E SU B ST R AT E − VF L AT B AN D − ψ SU R F AC E (x))

(9.2d)

Careful manipulation of 9.2 a-d gives an implicit relation between surface potential
and applied gate-substrate voltage:

ψ SU R F AC E = VG AT E SU B ST R AT E − VF L AT B AN D − γ A A
√
2q ∈ SU B ST R AT E N ACC E P T O R
γ = (9.2e)
CO X I DE

where
⌜
I ( )
I − 2Φ SU B ST R AT E +VC H AN N E L,SU B ST R AT E ( ψ )
I k B Tlattice SU B ST R AT E
A A = √ψ SU R F AC E + e VT H E R M AL e VT H E R M AL −1
q

Denoting inversion as the presence of electrons at the oxide-substrate interface surface,

as required for a drain current, three types of inversion conditions are possible: weak,
moderate and strong respectively, defined as:

0 < ψ SU R F AC E (x) ≤ Φ SU B ST R AT E + VC H AN N E L,SU B ST R AT E (x)

116 9 Metal Oxide Semiconductor Field Effect Transistor

Φ SU B ST R AT E + VC H AN N E L SU B ST R AT E lt; ψ SU R F AC E (x) ≤ 2Φ SU B ST R AT E
+ VC H AN N E L,SU B ST R AT E (x)

ψ SU R F AC E (x) > 2Φ SU B ST R AT E + VC H AN N E L,SU B ST R AT E (x) (9.2f)

The charge per unit area in the substrate consists of electrons near the surface and
ionized acceptors in the depleted region of the substrate:

Q SU R F AC E (x) = Q electr on (x) + Q SU B ST R AT E I O N I Z E D (9.2g)

Using the Charge Sheet Approximation that states that all electrons reside in a sheet at
the substrate surface, so that there is no voltage drop through such a sheet in the y direction.
Then if any potential is applied to the substrate, voltage Ψ SU R F AC E − VSU B ST AT E ,
is dropped entirely across the space-charge region of ionized acceptors. Using the
Depletion Approximation for the substrate space charge region (neglecting hole charges)
gives:

√
Q SU B ST R AT E (x) = − 2q∊ SU B ST R AT E N ACC E P T O R ψ SU R F AC E (x) (9.2h)

After applying the above expressions in 9.2h, it can be re-written as:

Q electr on (X ) = −C O X I D E (VG AT E SU B ST R AT E
√
− VF L AT B AN D − Ψ SU R F AC E (X ) − γ Ψ SU R F AC E (X )) (9.2i)

The electron current in the two dimensional sheet is:

( )
−→ Q eletr on d ψ SU R F AC E (x) k B Tlattice d Q eletr on
Ieletr on = W J eletr on = μeletr on W −
dx qd x
(9.2j)

where W is the channel’s width. The total drain current is:

∫ ∫ ∫
I DS d x = − Ielectr on d x = −W μelectr on dψ SU R F AC E
∫
k B Tlattice W
+ μelectr on d Q electr on (9.2k)
q
9.3 Strong Inversion Source Reference Model Drain Current HERE 117

where μelectr on is the substrate bulk electron mobility. The electron mobility at the
substrate-oxide interface is different from the substrate bulk electron mobility due to scat-
tering. Assuming that the effective electron mobility is one dimensional without any x
direction dependency, the drain current can be re-expressed as:

∫ ∫ ∫
μelectr one f f ecti ve W k B Tlattice W
I DS d x = −Q electr on dψ SU R F AC E + d Q electr on
L q
(9.2l)

C O X I D E μelectr one f f ecti ve k B Tlattice W

I DS,D I F FU S I O N =
Lq
( (√ √ ))
(ψ SU R F AC E (L) − ψ SU R F AC E (0)) + γ ψ SU R F AC E (L) − ψ SU R F AC E (0)
(9.2m)

The expression for the drift current is left as an exercise for the reader.

• The electron charge Q electr on (x) can never equal zero if current is to be maintained.
The condition for drain current saturation |(Q electr on (L))| << |Q SU B ST R AT E (L)|.
Thus, the channel never pinches off completely.
• As VD E AI N ,SU B ST R AT E increases beyond the value at which |(Q electr on (L))| <<
|Q SU B ST R AT E (L)| then the condition |(Q electr on (x))| << |Q SU B ST R AT E (x)| is
satisfied at x values closer to the source.

This effect—decrease in effective channel length of the MOSFET, increases the drain current
and is called channel-length modulation.

9.3 Strong Inversion Source Reference Model Drain Current HERE

The strong inversion source reference model (simplified surface potential model) is used
in SPICE [20–25] as the level 1 MOSFET model. SPICE [20–25] is the universally used
electrical|electronic circuit simulation and performance evaluation software tool. It is a
simplification of the surface potential model. It is based on three assumptions.

ψ SU R F AC E (x) = 2Φ SU B ST R AT E (x) + VC H AN N E L,SU B ST R AT E (9.3.1)

118 9 Metal Oxide Semiconductor Field Effect Transistor

VC H AN N E L,S OU RC E (x) = VC H AN N E L,SU B ST R AT E (x) − VS OU RC E,SU B ST R AT E

(9.3.2)

VC H AN N E L,S OU RC E (x) << 2Φ SU B ST R AT E (x) + VS OU RC E,SU B ST R AT E (9.3.3)

From the surface potential model the drain current is due to drift when the source is in
strong inversion. Strong inversion source reference model starts with the drift portion of
the drain current from the surface potential model. This expression contains the surface
potentials at both the source and drain ends of the channel. From the above assumptions:

ψ SU R F AC E (0) = 2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E ψ SU R F AC E (L)

= 2Φ SU B ST R AT E + VD R AI N ,SU B ST R AT E (9.3.4)

ψ SU R F AC E (L) = ψ SU R F AC E (0) + VD R AI N ,SU B ST R AT E ψ SU R F AC E (L)

= 2Φ SU B ST R AT E + VD R AI N ,SU B ST R AT E + VS OU RC E,SU B ST R AT E
(9.3.5)

Combining 9.3.1- 9.3.5 gives:

VD R AI N ,S OU RC E << 2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E (9.4)

This inequality is used for a binomial expansion to the second order of the term
3
Ψ SU R F AC E in the drift current expression for the drain current in the surface potential
2

model, resulting in the expression for the drain current in the strong inversion model:

C O X I D E μelectr on,e f f ecti ve VD R AI N ,S OU RC E W

I D R AI N =
( L )
mVD R AI N ,S OU RC E
VG AT E,S OU RC E − VT H RS H − (9.4a)
L

The threshold voltage and body effect coefficient are defined as:

VT H RS H = VF L AT B AN D + 2Φ SU B ST R AT E
√
+ γ 2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E
γ
m =1+ √ (9.4b)
2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E
9.4 Threshold Voltage and Body Effect Coefficient Relation 119

This is a very simplified version of the surface potential model, based on the
assumption that the drain voltage and current both reach a maximum saturation value:

VG AT E,S OU RC E − VT H RS H
VD R AI N ,S AT U R AT I O N = I D R AI N ,S AT U R AT I O N
m
( )2
C O X I D E μe f f ective,electr on VG AT E,S OU RC E − VT H RS H W
=
2Lm
(9.4c)

9.4 Threshold Voltage and Body Effect Coefficient Relation

The threshold voltage and body effect coefficient can be related to eachother in a straight-
forward way. Using the same assumptions as in the SPICE [20–25] level 1 MOSFET
model, the channel charge is related to the gate source, flat band, channel substrate and
source substrate voltages as:

( )
Q electr on (x) = − AC O X I D E + BVC H AN N E L,S OU RC E
A = VG AT E,S OU RC E
√
−VF L AT B AN D − 2Φ SU B ST R AT E − γ 2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E
γ
B =1+ √
2 2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E
(9.5a)

The channel charge at the source end of the channel is:

( )
Q electr on (0) = −C O X I D E VG AT E,S OU RC E − VT H RS H (9.5b)

The body effect coefficient m, is introduced into the strong inversion model when
3 3
terms involving Ψ SU3
R F AC E (0), Ψ SU R F AC E (L) are expanded in a Taylor’s series, in the
2

equation for the drift current in the surface potential model. The body effect coefficient
denotes the effect of the body|substrate in reducing the channel charge when the drain
source voltage is increased.
In a two terminal structure, e.g., parallel-plate capacitor, there is a one to one corre-
spondence between the charges on the two plates, represented by the surface and gate
charges in the MOS capacitor. However, the presence of a third region, the body, causes a
loss of channel charge in excess of the corresponding loss of gate charge. This degrades
the drain current, and to compensate, m is included in the expression for the drain cur-
rent in the strong-inversion model. Considering a change in the drain source voltage that
120 9 Metal Oxide Semiconductor Field Effect Transistor

changes the channel source voltage from 0 to a non-zero value at some location x in the
region the changes in the respective charges are:

∆Q G AT E = −C O X I D E VG AT E,S OU RC E (x) ∆Q SU B ST R AT E
= −C SU B ST R AT E (x)VG AT E,S OU RC E (x) (9.5c)
∆Q electr on (x) = C O X I D E m(x)VG AT E,S OU RC E (x)

Now the body effect coefficient can be re-written as:

C SU B ST R AT E (x) ∆Q electr on (x)

m =1+ m=
CO X I DE ∆C G AT E (x)
When electron mobility in the direction of the electron flow (longitudinal) direction is
field dependent, the electron drift velocity is given as:

1 1 1
= + (9.5d)
VD R I F T μelectr one f f ective |E| v S AT U R AT I O N

The expression for the drain current, after integrating over the entire channel, is:

C O X I D E μelectr on,e f f ecti ve VD R AI N ,S OU RC E W

I D R AI N = μelectr on,e f f ecti ve V D R AI N ,S OU RC E
L+ v S AT U R AT I O N
( )
mVD R AI N ,S OU RC E
VG AT E,S OU RC E − VT H RS H − (9.5e)
2

In this equation, the charge appears as if it is evaluated where.

V
VC H AN N E L,S OU RC E = D R AI N2,S OU RC E , but the velocity is modified. If the saturation
velocity was infinite, the two equations would be the same. In addition, the drain current
shows a maximum value when the basic assumption of strong inversion breaks down at
the drain end of the channel. The maximum values for the drain voltage and current are:

I D R AI N ,S AT U R AT I O N
( )
( ) A−1
= C O X I D E VS AT U R AT I O N VG AT E,S AT U R AT I O N − VT H RS H
A+1
( )
2 VG AT E,S OU RC E − VT H RS H (9.5f)
VD R AI N ,S AT U R AT I O N =
m(1 + A)
/ ( )
μelectr one f f ective VG AT E,S OU RC E − VT H RS H
A = 1+
m Lv S AT U R AT I O N
9.4 Threshold Voltage and Body Effect Coefficient Relation 121

The sub-threshold region of operation is when the gate source voltage is less than the
threshold voltage. The channel is everywhere either in weak or moderate inversion. This
operating condition holds the key to two important MOSFET properties: the ratio of the
onset of the ON-current to the OFF-current, and the inverse sub threshold slope. These
two properties are key to operation of MOSFETs in high speed digital circuits.
√
Q electr on = 2q ∈ SU B ST R AT E N ACC E P T O R
⎛⌜ ⎞
I
I ψ SU R F AC E −2Φ SU B ST R AT E −VC H AN N E L,SU B ST R AT E
⎜I V √ ⎟
⎜√ k B Tlattice e T H E R M AL ⎟
⎜ ψ SU B ST R AT E + − ψ SU R F AC E ⎟
⎝ q ⎠

(9.5g)

In moderate inversion Ψ SU R F AC E < 2Φ SU B ST R AT E + VC H AN N E L,SU B ST R AT E , the

first square root term in the above equation can be expanded using the Taylor’s series.
Keeping terms to first order gives:
ψ SU R F AC E −2Φ SU B ST R AT E −VC H AN N E L,SU B ST R AT E
√ e VT H E R M AL
Q electr on = 2q∊ SU B ST R AT E N ACC E P T O R k B Tlattice √
2q ψ SU R F AC E
(9.5h)

In weak inversion, the surface potential is barely influenced by channel sub-

strate voltage. Therefore no electric field in the x direction exists E x ≈ 0. Then
the drain current is due to diffusion. From the above equations, under the condi-
tions Q electr on (0) evaluated at VC H AN N E L,SU B ST R AT E = VS OU RC E,SU B ST R AT E , and
Q electr on (L) at VC H AN N E L,SU B ST R AT E = VD R AI N ,SU B ST R AT E gives:

√
μelectr one f f ecti ve W k 2B Tlattice
2 2q∊ SU B ST R AT E N ACC E P T O R
I D R AI N = AA √
2Lq ψ SU R F AC E
( −V D R AI N S OU RC E
)
1−e VT H E R M AL (9.5i)

ψ SU R F AC E −2Φ SU B ST R AT E −VSU R F AC E SU B ST R AT E
AA = e VT H E R M AL

The dominant effect of the surface potential on the current occurs via the expo-
nential term in the numerator, so that the accuracy is not reduced from selecting
some constant value for the surface potential in the denominator. If value of the
surface potential is selected to be that at the extreme √ end of the weak inversion
(2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E ), then the term 2q∊√SU B ST R AT E N A can be re-
2 Ψ SU R F AC E
written as C O X I D E (m − 1). In sub-threshold region of operation, the electron charge is
less than the substrate charge, for the body effect coefficient and the potential divider
action of the oxide and body capacitances, gives:
122 9 Metal Oxide Semiconductor Field Effect Transistor

dψ SU R F AC E 1 2Φ SU B ST R AT E + VS OU RC E,SU B ST R AT E − ψ SU
P
R F AC E
= =
d VG AT E SU B ST R AT E m VT H RS H − VG AT E S OU RC E
P

(9.5j)

9.5 Complimentary Metal Oxide Semiconductor Field Effect

Transistor (CMOS)

All modern digital integrated circuits are fabricated with this technology consisting of a
n channel, p substrate enhancement mode field effect transistor (NMOS) and a p channel
n substrate enhancement mode field effect transistor (PMOS). For both transistors, the
charge carriers are minority carriers.
Digital logic involves charging and discharging capacitors as quickly as possible. If
∆V is the change in voltage required to denote a change in logic level (1–0 or 0–1) at a
node of constant capacitance C, then the switching time is:

C∆V
τ= (9.5k)
I
where I is the average current during the switching cycle. So a successful digital logic
technology needs only small voltage swings, and must be capable of supplying large
currents to circuits of low capacitance.
Fabricating a NMOS and PMOS on the same substrate is very advanced, tried, tested
and universally used technology consisting of, the following core steps (Fig. 9.4a, b):

Fig. 9.4 a Steps A, B of

CMOS fabrication process,
b Steps C, D of CMOS
fabrication process
9.5 Complimentary Metal Oxide Semiconductor Field Effect Transistor (CMOS) 123

• A: Shallow isolation trench creation, n, p well ion implantation.

• B: Gate oxidation and polysilicon layer creation, followed by source, drain extension
halo layer implementation.
• C: Drain, source layers are ion implanted.
• D: Drain, gate and source passivation and silicidation.

Modern digital integrated circuit fabrication process work flows use advanced and enhanced
versions of the above key steps. In CMOS technology, the threshold voltage of the PMOS
is opposite, and nearly equal in magnitude, to that of the complimentary NMOS transistor.
In an CMOS inverter, the two gates of the NMOS and PMOS are are connected
together, and the threshold voltages are such that in either of the logic states (HI or
LO) only one of the transistors is ON, minimizing static power drain. Also, CMOS logic
gates can be made with much fewer transistors than their emitter coupled logic (ECL)
rival, enabling cost effective fabrication of dense, high speed logic circuits. Further, in
integrated circuits, each transistor has to be connected at the top surface, and this is easy
to achieve with CMOS. In CMOS, in which two of the contacts (drain, source) are closely
aligned with the third contact (gate).
In CMOS logic the ON-current is the drain current when the source end of the channel
is in strong inversion condition, VG AT E,S OU RC E > VT H RS H . The drain current increases
with the drain source voltage to reach a maximum value—saturation current I DS AT .
The supply voltage sets the upper limit on both the drain source and gate source volt-
ages. MOSFET gate lengths have been progressively reduced to increase packing density
(reduced device area for each MOSFET) reduce parasitic capacitances and improve the
saturation current of the device. Shorter gate lengths L no longer has a strong effect on
the saturation current. This is because L is already sufficiently small for the lateral field
E x to attain a sufficiently high value for velocity saturation to occur over a significant part
of the channel. Consequently the inclusion of saturation gives a much smaller increase
in the saturation current, as L is reduced, than is predicted by the basic SPICE Level
1 model, which does not limit the electron velocity to v S AT . To attain their saturation
velocity, electrons still have to be accelerated over the source side of the channel, so a
high mobility is essential. The reduced channel length in a MOSFET increases the drain
current in the linear and saturation regions of operation.
The ON-current can be increased by both the effective electron mobility
μelectr on,e f f ective and by increasing the channel charge, achieved by increasing the oxide
capacitance as well as the overdrive voltage (VG AT E,S OU RC E − VT H RS H ). CMOS uses
unipolar power supply, increasing the gate source voltage would mean increasing the drain
source voltage. But increasing the drain source voltage is limited by the necessity of keep-
ing E x < E y . Also, a low supply voltage value is needed for CMOS enabled portable
electronic devices. The alternative to increasing the overdrive voltage is to reduce the
threshold voltage—with consequences for the sub threshold current. In densely packed
CMOS circuits with hundreds of thousands of transistors per unit area, the current per
124 9 Metal Oxide Semiconductor Field Effect Transistor

transistor when the it is OFF (VG AT E,S OU RC E = 0 for NMOS) must be very very small,
else the static power drain would be very high. Unwanted power dissipation also occurs
during switching.

9.5.1 Lattice Strain and Charge Mobility

The channel region of silicon based sub-micron gate length field effect transistors is
mechanically strained to improve both electron and hole mobility. The strain modifies
the band structure, and calibrated strain application exploits this feature to reduce the
effective mass in the desired direction of conduction.
Hooke’s Law relates the mechanical deformation of a one dimensional object to the
−
→
applied force F E X T E R N AL = K where K is a material specific constant.
When generalized to a three dimensional object, e.g., a cube of crystalline semiconductor,
normal and shear forces are introduced which deform a given side length in a given face
arising from all the possible normal and shear forces. Each force per unit area is a stress
and each component of deformation is a strain. The force required to produce a given strain
is determined by the elastic stiffness constants of the material. In cubic crystals e.g., as Si
and GaAs, there are three independent such constants. In Si, their magnitudes range from 64
to 166 Gpa (Giga Pascal), which indicates the immense pressures within a crystalline solid.
The resulting strain from a given stress is determined by the elastic compliance constants
of the material, in turn related to the elastic stiffness constants.
The simple one dimensional crystal model used in Chap. 1 illustrates the importance of
atomic spacing on how band structure is related to crystal structure. In short, mechanical
stress|strain imposed on the crystal lattice will change atomic spacing, in turn modi-
fying electron band structure. For example, it is advantageous to lower the heavy hole
band energy with respect to the light hole band energy. Achieving this in real world semi-
conductor integrated circuits requires very careful process engineering as strain introduced
in one region must be compensated else the crystal would crack and be destroyed. Valence
bands become so warped by the added strain that they cannot be classified as ‘heavy’ nor
‘light’. Rather, as the strain splits the bands, they are referred to as ‘top’ and ‘bottom’
bands. As holes want to occupy the higher band, it is important that the curvature
of the top band be such that the effective mass in the desired direction of conduction
be reduced. One way to achieve this for a < 110 > channel on a {001} Si surface in a
sub-100 nm device is to apply a uniaxial compressive stress of about 1 GPa to the p-type
channel. A common method to add such a high stress in the crystal is to etch recesses in
the silicon at the source and drain regions, and then fill-in by epitaxially growing SiGe.
With a Ge mole fraction of x ≈ 0.3, the more expansive SiGe puts the Si channel under
a compressive stress of the required magnitude.
For n-channel silicon MOSFETs on {001} substrates, a < 110 > tensile stress induces
a shear strain that enhances electron conduction in this direction. Specifically, the six fold
9.5 Complimentary Metal Oxide Semiconductor Field Effect Transistor (CMOS) 125

symmetry of the conduction band minima is broken, resulting in two [001] valleys moving to
lower energies. The conduction band minimum moves towards the X-point as the shear strain
increases. So the degeneracy of the two conduction band minima at the X-point is removed.
Physically, the two transverse effective masses are no longer equal, i.e., the Brillioun zone is
no longer symmetrical in directions perpendicular to the new k x direction. The beneficial
effect of breaking the six fold symmetry of the conduction bands in unstrained bulk
material is illustrated in Fig. 9.5a, which represents the E-k relationship for silicon near
the conduction band edge E C O N D . The valley is steeper in two of the principal directions
than in the remaining orthogonal direction. The equivalent constant energy surfaces in
three dimensions are shown in Fig. 9.5b. The four spheroids in the horizontal plane are
called the ∆4 valleys, and the two in the perpendicular direction are called ∆2 valleys.
The tensile strain breaks the six fold degeneracy of these valleys, raising the energy of
the ∆4 set, and lowering the energy of the ∆2 set. For a given energy E with respect to
the bottom of the conduction band in the ∆4 valleys, E − E C O N D for the ∆2 valleys is
increased. The electrons seek the lower energy states, so the ∆2 valleys become heavily
populated. If the in-plane effective mass in the ∆2 valleys remains at m tP . less than the
longitudinal effective mass m lP , then the electron mobility in the channel is increased.

(a) (b)

Fig. 9.5 a Symmetry breaking of unstrained semiconductor conduction band due to imposed lattice
stress. b Equivalent constant energy surfaces, elliptical rings represent high energy, low occupancy
∆4 states

Fig. 9.6 Polysilicon gate

energy band diagram
126 9 Metal Oxide Semiconductor Field Effect Transistor

9.5.2 High k Dielectrics in Gate Capacitors

Increasing the oxide capacitance puts more charge in the channel for a given gate source
voltage and increases the drain current. With gate lengths in the nanometer range, e.g.,
90 nm, the oxide thickness is approximately 2 nm, leaving little room for further shrinking
the oxide thickness. Thinner oxide films that satisfy predefined standards of integrity and
uniformity are very difficult to fabricate. Also leakage to the gate of drain intended current
increases sharply. Traditionally, the gate oxide has been silicon dioxide as the physics of
the silicon–silicon dioxide interface is very well understood.
However, the relative dielectric constant of silicon dioxide is 3.9. Including nitrogen in
the oxide boosts the dielectric constant to 4–5. This is an active research area, under the
constraint that the properties of the silicon–silicon dioxide interface must be preserved.
For example, using a dielectric material derived from hafnium with traces of nitrogen pre-
serves the silicon–silicon dioxide properties, but makes the dielectric later thicker, while
boosting the overall dielectric constant by ≈15–20%, and reduces leakage current. The
ON current is increased if the dielectric layer thickness is selected as:

tsilicondi oxide ∊high−k

thigh−k <
∊silicondi oxide

9.5.3 Poly Silicon Gates and Capacitances

State-of-art MOSFETs in digital circuits have a gate stack consisting of a metal gate
electrode and high-k dielectric. For long highly doped polycrystalline silicon gates have
been used to counter the disadvantages of pure metal (e.g., aluminium) such as penetration
into the silicon dioxide, during thermal processing prevented using metal as a mask to
facilitate the self-alignment of the source and drain regions to the gate. Polycrystalline
silicon does not have any such problems, but creates depletion layers at the gate oxide
surface. So, an additional potential drop is introduced in the device. Therefore,

VG AT E SU B ST R AT E − VF L AT B AN D = ψ P O LY + ψ O X I D E + ψ SU R F AC E (9.6)

where Ψ P O LY is the potential drop inside polycrystalline silicon gate layer. Clearly, the
charge in the channel, experiences less of the gate substrate voltage than it would oth-
erwise. For state-of-art ultra high speed digital circuits, this is a problem, and so metal
gates, less reactive than aluminium with high-k dielectrics need to be used. The energy
band diagram of the polysilicon layer gate MOSFET is in Fig. 9.7.
9.5 Complimentary Metal Oxide Semiconductor Field Effect Transistor (CMOS) 127

Fig. 9.7 Parasitic capacitances

inside a short channel
MOSFET. Dashed line shows
depletion layer

9.5.4 Gate Leakage Current

As MOSFET physical dimensions are scaled down, specifically oxide thickness, electrons
can flow from the channel (and overlapped part of the drain) in an NMOS to the gate.
This tunnelling current (called leakage current) reduces the drain current. Expressions for
the tunnel current are based on the assumption that the electrons in the channel form a
classical two dimensional sheet where the electrons are confined to quasi-bound states.
The tunnel current density is:

∫
q
JT U N N E L = n 2D (E)T (E)d E (9.7a)
ℏ

where n 2D (E) is the electron density of the two dimensional sheet of electrons at the
oxide semiconductor interface, and T(E) is the tunnelling transmission probability. If the
rectangular tunnelling barrier is assumed, then an analytical expression for T(E) can be
obtained in a straightforward manner. The denominator for this expression contains hyper-
bolic functions that involve the thickness of the tunnelling barrier, the electron effective
mass in the oxide and the height of the potential barrier.

E C O N D O X I D E − E C O N D (0) = X S I L I C O N − X O X I D E (9.7b)

where the χ’s are electron affinities. Then the tunneling probability is:

√
X I D E ( E C O N D O X I D E −E )
−2t O X I D E P
2m O
T ≈e ℏ (9.7c)

The tunnelling depends both on the thickness of the barrier and on its height. Therefore,
for low tunnelling, the oxide must have a low electron affinity. For silica, χ = 0.9 eV and
2.9 eV for hafnium.
128 9 Metal Oxide Semiconductor Field Effect Transistor

9.5.5 Short Channel Effect and Threshold Voltage

The expressions presented in previous sections for the ON and sub-threshold current,
indicate a lower limit for the sub-threshold current. Denoting I D R AI N ,O N to be the current
when VG AT E,S OU RC E = VT H RS H and I D R AI N ,O F F when VG AT E,S OU RC E = 0, then the
ratio of these two currents is:

I D R AI N (O N ) −VS OU RC E
= e mVG AT E S OU RC E (9.7d)
I D R AI N (O F F)

So for a current ratio of 10−4 m (body effect coefficient) at its optimum value of unity
indicates that the minimum threshold voltage is about 0.24 V.
Both the currents are dependent on the depth of the drain and source regions inside
the substrate, and the gate length L. To include the depth into the drain current current
calculations, the device equations need to be solved numerically. Analytical expressions
are too complicated to extract meaningful insights from them.
The numerical calculation results show that for a given channel length the sub-
threshold current increase is directly proportional to the depth of the drain, source regions.
Also, for a given drain, source depth, the threshold voltage is directly proportional to the
channel length.
The numerically computed drain characteristics indicate that increase in the drain, source
regions enhance the drain ON current with increasing drain source voltage. This effect is
not the same as channel length modulation in longer devices after the drain source voltage
is increased beyond the pinch-off value. Current saturation in sub-micron channel length
MOSFETs is dependent more on velocity saturation than pinch-off conditions.
These effects can be quantified by a reduction in the threshold voltage as either the
junction depth is increased, or as the length of an already short channel is decreased. These
MOSFET performance characteristics, applicable to short gate length devices are called
short channel effect.
The short channel effect is an electrostatic effect, when field lines emanate from the
positively biased drain, and must terminate on negative charges: the p type substrate provides
negatively charged sites, leading to a space charge region extending from the drain. This
region is wider than the space charge region around the source because of the greater reverse
bias at the drain substrate np junction. The drain related space charge at some location x
increases the surface potential at that location. This increases both |Q electr on (x)|, E(x),
resulting in drain current increase, called charge sharing. This is because the total space
charge (depletion) at point x is now determined by both the gate and drain potentials. A
given surface potential value at a location x can now be achieved with a lower gate source
voltage than would be needed in absence of depletion due to the drain source voltage. As L
decreases, the space charge region from the drain progressively encroaches on the source.
Eventually, the surface potential at x = 0 is affected by the drain source voltage. The
9.6 Silicon on Insulator MOSFET (SOI) 129

Fig. 9.8 a, b (a) Cross section

of a thin body SOI MOSFET
for SOI MOSFET dynamic
logic circuits (b) Electric field
lines just below

surface potential at x = 0 sets the potential barrier height at the source-channel junction,
and thereby controls the electron flow into the junction and the drain current, called drain
induced barrier lowering (DIBL).
The effect of the short channel and drain induced barrier lowering are embodied in the
effective threshold voltage given by:

VT H RS H ,E F F EC T I V E = VT H RS H + ∆VT H RS H ( junction D E P T H , L, VD R AI N S OU RC E )
(9.7e)

The electrostatic interaction between the drain and the channel via the depletion region
in the substrate is a capacitive phenomenon, Fig. 9.8. Therefore, |∆VT H RS H | is reduced
by decreasing the drain source capacitor. As the sidewall of the np junction defines one
of the lengths of this plate of the capacitor, the drain source depth must be be decreased.
The chief drawback of this depth reduction is that the lateral access resistance to the
channel from the source and drain contacts is increased. To counter this, only the part of
the source and drain closest to the channel is thinned.
Alternatively, to reduce the influence of the drain on the surface charge at x = 0 is
to shield the source from the field issuing from the drain. This is achieved by raising
substrate acceptor concentration, but this in turn boosts the threshold voltage. This is
countered by having a non-uniform substrate doping profile N A (x, y). The desired high
doping is achieved deeper into the substrate using fast-diffusing dopants such as B, As
and P. Doping of the sensitive surface region is achieved by lightly doping using slower
diffusants such as In and Sb. The resulting doping profile is called retrograde. In the x
direction, acceptor concentration is increased only close to the source and drain junctions.
The feature is called halo doping. These highly doped regions are also called pocket
implants.

9.6 Silicon on Insulator MOSFET (SOI)

Silicon MOSFETs can also be fabricated as silicon on insulator (SOI) structures

(Fig. 9.9a), which have interesting properties; a layer of silicon oxide is implanted into
the silicon wafer, and the CMOS FETs are then fabricated in the overlying surface layer
130 9 Metal Oxide Semiconductor Field Effect Transistor

of silicon. However, oxygen implant disturbs the crystalline structure of the silicon sur-
face layer, and it is costly to recover the perfection of this critical region. An easier way
to construct SOI structure is to exploit Van der Waals forces to bond one silicon wafer to
the oxide-coated surface of another silicon wafer. Then the thickness of the wafer with the
oxide layer is carefully reduced resulting in the SPO structure. This process is known as
Smart Cut, but expensive. The source and drain regions reach through to the buried oxide,
so there is no ‘floor’ component of parasitic capacitance at the drain|source substrate np
junctions. The SOI MOSFET’s speed improvement is also due to the dynamic threshold
voltage effect. The dynamic threshold voltage is a result to the separation of the substrate
and the other components of the MOSFET.
When the MOSFET is switched on by applying a positive gate source bias, the poten-
tial of the floating components also rise momentarily, boosting the forward bias across
the source channel junction, and increasing the current. Also, when both the upper sil-
icon layer and the buried oxide are thin, and the underlying substrate is heavily doped.
The field issuing from the drain preferentially penetrates the two thin oxides and termi-
nates on the gate and the substrate, Fig. 9.9b. The surface potential potential at the source
Ψ SU R F AC E (0) is screened from the applied drain potential and the short-channel effect is
reduced. The thin oxide substrate combination acts like a ‘bottom’ gate, making the SOI
MOSFET a template for the multiple gate MOSFET, e.g.,the FinFET. The insulating layer
of partially depleted SOI MOSFETs isolates devices from each other, which is vital for
RF circuitry, and decouples noisy logic blocks from sensitive analogue circuitry, useful in
mixed-signal applications.
There are two types of power dissipation in SOI MOSFETs—dynamic and static. The
various DC leakage and sub-threshold currents in an NMOS are shown in Fig. 9.10.
When the device is ON, a high drain current is required and, this current is drawn from
the power supply. If the latter is more than the drain current, current leakage paths exist
in the transistor.
Leakage currents are curbed by using thin oxides only where they are absolutely nec-
essary. For example, transistors in the input/output parts of an integrated circuit do not
need thick oxide layer.
Current leakage also occurs via the substrate, e.g., the usual current in a reverse
biased np junction. Another current leakage mechanism is the gate induced drain leakage
(GIDL). GIDL is similar to Zener breakdown, and arises from band-to-band tunnelling in

Fig. 9.9 CMOS inverter

9.6 Silicon on Insulator MOSFET (SOI) 131

the depletion region where the gate overlaps the drain, in np diodes with heavy doping
on either side of the junction. GIDL becomes a significant current leakage mechanism
because of very high fields arising from the heavy doping of the pocket implant. As
the gate substrate voltage increases, the bands bend more and leakage current increases.
These leakage currents exist when the transistor is ON. Current can also be drawn from
the power supply when the transistor is OFF, but the drain source voltage is greater than
zero. Such currents are the junction leakage current, and the sub-threshold current due to
injection from the source. The latter is non-zero because the electric field from the drain
affects the surface potential Ψ SU R F AC E (0).
In integrated circuits it is necessary that the OFF|ON ratio be as small as pos-
sible: i.e., switching between OFF and ON would be a vertical transition in the
I D R AI N , VG AT E,S OU RC E plane. In reality the transition has a finite slope due to inverse
sub-threshold slope. This is the change in gate source voltage needed to reduce the drain
current by a factor of 10.

∂ VG AT E S OU RC E
S= = 2.303mVT H E R M AL (9.8a)
∂log(I D R AI N )
The common CMOS inverter (Fig. 9.10) illustrates dynamic power loss. The two
capacitors C P LU S , C M I NU S in combination represent the total capacitance C T O T AL at
the output node, specifically the intrinsic and extrinsic capacitances of the transistors in
both the logic gate and in the element that it drives and the interconnect capacitance.
It is charged through the PMOS, and discharged via the NMOS.. During discharge of
the capacitor C M I NU S , v I N PU T is HI and the PMOS is OFF. The output goes LO and
C P LU S charges up. The current drawn from the power supply during this event is

C 2 (VD D − VOU T )
iPS = (9.8b)
∂t
T
The average power dissipated during this half-period 2 is

∫
2
PAV G = (VD D − VOU T )i P S dt = f C P LU S VD2 D 0 ≤ t ≤ T (9.8c)
T
where f is the clock frequency. Over one clock period, the average power dissipated per
gate is:

PAV G,CY C L E = f VD2 D (C M I MU S + C P LU S ) = f VD2 D C T O T AL (9.8d)

The static power dissipated is:

132 9 Metal Oxide Semiconductor Field Effect Transistor

PST AT I C = VD D I D R AI N ,SU BT H R E S H O L D (9.8e)

9.7 Hot Electron Effect in Short Channel MOSFETs

‘Hot carriers’ are holes or electrons (‘hot electrons’) that have gained very high kinetic
energy after being accelerated by a strong electric field in regions of high field intensities
within a semiconductor (e.g., MOS) device. Their high kinetic energy, enables hot carriers
to get injected and trapped in regions of the device where they are normally absent.
The resulting space charge degrades the device’s performance characteristics—‘hot carrier
effects’. According to the Hitachi Semiconductor Device Reliability Handbook [28], there
are four commonly encountered hot carrier injection mechanisms.

• Drain avalanche hot carrier injection (DAHC)

• Channel hot electron injection (CHE)
• Substrate hot electron injection (SHE)
• Secondary generated hot electron injection (SGHE).

In the remainder of this discussion, the device being examined is the MOSFET.
Drain avalanche hot carrier (DAHC) injection causes the worst MOSFET per-
formance and device degradation under normal operating temperature range. DAHC
occurs when a high voltage applied at the drain under non-saturated conditions
(VD R AI N ,S OU RC E > VG AT E,S OU RC E ) results in very high electric fields near the drain,
which accelerate channel carriers into the drain’s depletion region. Experimentally, it has
been proved that the worst effects occur when the drain source voltage is twice the gate
source voltage. The accelerated channel carriers collide with silicon lattice atoms, creat-
ing dislodged electron–hole pairs in the process—impact ionization. Some of the displaced
electron hole pairs also gain enough energy to overcome the electric potential barrier
between the silicon substrate and the gate oxide. Under the influence of drain-gate field,
hot carriers that surmount the substrate-gate oxide barrier get injected into the gate oxide
layer where they might get trapped. This hot carrier injection process occurs mainly in
a narrow injection zone at the drain end of the device where the lateral field is at its
maximum.
Hot carriers can be trapped at the silicon–silicon dioxide interface (‘interface states’)
or within the oxide itself, forming a space charge (volume charge) that increases with
addition of more charges are trapped. These trapped charges change both the threshold
voltage (Vth) and its transconductance (gm ).
Injected carriers that do not get trapped in the gate oxide become gate current. Majority
of the holes from the electron hole pairs generated by impact ionization flow back to
the substrate. These returning holes form a large portion of the substrate’s drift current.
9.8 Semiconductor Industry Standard BSIM MOSFET Model 133

Excessive substrate current is an indication of hot carrier degradation. In extreme cases,

abnormally high substrate current can upset the balance of carrier flow, resulting in latch-
up.
Channel hot electron (CHE) injection occurs when both the gate voltage
and the drain voltage are significantly higher than the source voltage, with
VG AT E,S OU RC E > VD R AI N ,S OU RC E Channel carriers that travel from the source to the
drain are often driven towards the gate oxide even before they reach the drain because of
the high gate voltage. CHE occurs when the substrate back bias is very positive or very
negative. Carriers of one type in the substrate are driven by the substrate field toward
the silicon–silicon dioxide interface. As they move toward the substrate-oxide interface,
they gain additional kinetic energy from the high field in surface depletion region. They
eventually overcome the surface energy barrier and get injected into the gate oxide, where
some of them are trapped.
Secondary generated hot electron (SGHE) injection is the generation of hot carriers
from impact ionization involving a secondary carrier that was created by an earlier inci-
dent of impact ionization. This occurs when the applied voltage at the drain is high,
which is the driving condition for impact ionization. The main difference is the influence
of the substrate’s back bias in the hot carrier generation. This back bias results in a field
that drives the hot carriers generated by the secondary carriers toward the surface region,
where they further gain kinetic energy to overcome the surface energy barrier.
Hot electron effects in MOSFETs can be controlled by:

• Increasing channel length

• Drain and source should be double diffused—n P LU S , n M I NU S
• Drain junctions must be graded
• Use self aligned n M I NU S regions between the channel and n P LU S regions to create
offset gate
• Use buried p P LU S regions.

9.8 Semiconductor Industry Standard BSIM MOSFET Model

The BSIM are a family of semiconductor industry standard SPICE [22–27] MOSFET
large|small signal device model libraries, freely available from [27]. These libraries were
developed by the IGFET (Insulated Gate Field Effect Transistor) Group at the University
of Califormia Berkeley. The family of libraries consist of:

• BSIM Bulk: Bulk MOSFET library which started out as BSIM1, BSIM2,.. and after
BSIM6 was renamed as BSIM Bulk.
• BSIMSOI BSIM SPICE [22–27] library for Silicon On Insulator (SOI) MOSFETs
134 9 Metal Oxide Semiconductor Field Effect Transistor

• BSIMCMG/IMG BSIM SPICE [20–27] library for multi gate MOSFETs

The focus here is on the most commonly used library, BSIM Bulk. All BSIM libraries
have been designed with the Compact Model concept, that enables easy exchange of infor-
mation between the designers and foundaries. Such a model must guarantee convergence
on various types of operating conditions, and the results must be accurate with minimum
simulation time.
The BSIM Bulk Compact Model scheme exploits SPICE [20–27]’s built in threshold
voltage model examined earlier. The threshold voltage model expresses currents in terms
of voltages, with different equations for sub-threshold, linear and saturation regions of
operation. Judicious use of interpolation smooths out the interface regions of the three
regions of operation. The threshold voltage based model is much faster than surface
potential based counterpart, avoid many iterations, and produce results as accurate as
those generated with the surface potential models.
The core BSIM Bulk model has two main sub-components—the current voltage (I-V)
and capacitance voltage (C-V) models. In combination these two account for all properties
of sub-micron MOSFETs. The I-V component explains:

• Channel length modulation (CLM) and drain induced barrier lowering (DIBL)
• Velocity saturation and mobility degradation
• Gate induced drain leakage current (GIDL)
• Impact ionization current and direct tunnelling gate current
• Drain source and parasitic resistances

The C-V component accounts for:

• Fringe and overlap capacitances

The remainder of the BSIM Bulk model elaborates on the electronic noise, short channel,
quantum and temperature related effects.
The BSIM Bulk MOSFET model has a huge set of SPICE [22–27] parameters divided
into the basic model parameters, ultra high frequency (RF|microwave) parameters, tem-
perature parameters etc., Some of the basic parameters essential for circuit design are
mentioned below. The interested reader can easily download excellent free literature on
this topic [27].

• Length of extracted long channel device

• Width of extracted long channel device
• Interface trap capacitance
• Sub-threshold swing factor
• Drain-bias sensitivity of sub-threshold swing
9.8 Semiconductor Industry Standard BSIM MOSFET Model 135

• Body-bias sensitivity of sub-threshold swing

• Coefficient of drain induced threshold voltage shift for log channel devices with pocket
implant
• Vertical non-uniform doping effect on surface potential
• Threshold voltage shift due to non uniform vertical doping
• Drain induced barrier lowering (DIBL) coefficient
• DIBL exponent coefficient
• Body bias sensitivity to DIBL effect
• Low field mobility
• Effective field parameter
• Phonon|surface scattering parameter
• Coulombic scattering parameter
• Body|substrate bias sensitivity on mobility
• Saturation velocity
• Smoothing factor to drain source voltage to saturation drain source voltage transition
• Correction factor for velocity saturation
• Velocity saturation exponent for non-zero substrate source voltage
• Channel length modulation parameter
• Gate bias bias dependent modulation for channel length modulation
• Substrate current body effect coefficient
• Drain induced threshold voltage shift
• Length dependency of drain induced threshold voltage shift
• Drain source dependency of drain induced threshold voltage shift
• Source extension resistance per unit width at high gate source voltage
• Zero bias source extension resistance per unit width
• Drain extension resistance per unit width
• Zero bias drain extension resistance per unit width
• Lightly doped drain (LDD) resistance per unit width at high gate source voltage
• Zero bias LDD resistance per unit width
• Gate bias dependency of source drain extension resistance
• Body|substrate dependency of source drain extension resistance
• W dependency parameter of source drain extension resistance
• Sheet resistance
• Drain induced barrier lowering (DIBL) effect on global scaling parameters
• Body|substrate sensitivity on DIBL
• Gate source voltage dependency on early voltage
• Drain source G degradation factor due to pocket implant
• Pre-exponential coefficient for gate induced drain leakage (GIDL)
• Exponential coefficient for GIDL
• Band bending parameter for GIDL
• Pre-exponential coefficient for gate induced source leakage (GISL)
136 9 Metal Oxide Semiconductor Field Effect Transistor

• Exponential coefficient for GISL

• Band bending parameter for GISL
• First parameter of impact ionization
• First drain source voltage dependent parameter of impact ionization current
• Parameter for Igcs and Igcd
• Parameter for gate source current (Igs)
• Drain source overlap length for Igs
• Drain source overlap length for gate drain current
• Parameter for gate drain current
• Factor for gate oxide thickness in drain source overlap regions
• Drain source dependency of Igcs and Igcd
• Exponent for gate oxide ratio
• Nominal gate oxide thickness for gate dielectric tunnelling current model only
• Flat band offset parameter
• Channel (body|substrate) doping concentration for CV
• Saturation velocity for CV
• Channel length modulation parameter for CV
• Outer fringe capacitance
• Outer fringe capacitance coefficient
• Non LDD region source gate overlap capacitance per unit channel width
• Non LDD region drain gate overlap capacitance per unit channel width
• Overlap capacitance between gate and lightly doped source region
• Coefficient of bias dependent overlap capacitance for source side
• Coefficient of bias dependent overlap capacitance for drain side
• Gate body|substrate overlap capacitance per unit channel length
• Quantum mechanical effect prefactor|switch in inversion
• Charge centroid parameter—slope of capacitance voltage curve under QME in inver-
sion
• Charge centroid parameter—starting point for QME in inversion
• Bulk charge coefficient for for charge centroid in inversion

The BSIM Bulk model is complex. The above was just the list of basic SPICE [22–27]
parameters.

9.9 Three Dimensional Transistors—State-Of-Art MOSFET

Structures

As silicon based MOSFET technology has become mature, tried and tested, and most
importantly synchronous logic circuit clock frequencies have increased higher and higher,
the MOSFET has evolved from the initial planar layered to a three dimensional structure.
References 137

(a)

(b)

Fig. 9.10 a Three dimensional structure of FinFET, b Nanosheet (Gate All Around—GAAFET)
MOSFET

This evolution is because of the necessity of curtailing unwanted effects of short channel
MOSFETs, viz., leakage current. One is the FinFET (Fig. 9.10a) and the other is the
nanosheet MOSFET (Fig. 9.10b). Simultaneously, both MOSFET channel length and width
have sub-micron dimensions, enabling more three dimensional MOSFETs to be packed into
a single wafer die, i.e., increased packaging density.

References

1. Sze, S. M., & Lee, M. K. (2021). Semiconductor physics and devices John Wiley and Sons.
ISBN 9789354243226.
2. Martins, E. R. (2022, June). Essentials of Semiconductor Device Physics John Wiley and Sons.
ISBN 987-1-119-88413-2.
3. Pierret, R. Semiconductor device fundamentals. ISBN 10 0201543931 ISBN 13
978–0201543933.
4. Hess, K. Advanced theory of semiconductor devices Wiley IEEE Press ISBN 10 0780334795
ISBN 13 978–0780334793.
5. Streetman, B. G., & Banerjee, S. K. Solid state electronic devices. ISBN: 9789332555082,
9789332555082.
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138 9 Metal Oxide Semiconductor Field Effect Transistor

7. Mead, C. (1972). Fundamental limitations in microelectronics—I. MOS Technology, Solid State

Electronics, 15, 819–829.
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(1974). Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE Journal
of Solid-State Circuits, SC-9, 256–268.
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10. 16. Pullfrey D. Understanding Modern Transistors and Diodes Cambridge University Press
2013 ISBN 13 978–0521514606.
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Noise in Semiconductor Devices
10

10.1 Semiconductor Noise Mechanisms [1–77]

10.1.1 Thermal Noise

“Thermal” noise is a temperature dependent common noise characteristic of any semi-

conductor device, caused by random variations in the position of the free electrons
(Brownian motion) that induces a time varying random electromotive force at the ter-
minals. Random thermal motion of electrons inside the semiconductor material causes
temporary concentration of carriers at one end or the other. Thus one end contact will be
at a more negative potential than the potential at the other end contact. A time varying
polarity and magnitude voltage, called the thermal noise voltage appears. Random motion
of free electrons is unavoidable at all temperatures. Thermal noise corrupts low amplitude
signal output or the device is operating at RF|microwave frequencies.
The Nyquist theorem states that for a linear resistance in thermal equilibrium at tem-
perature T, the noise current or voltage variations are independent of the conduction
mechanisms, type of material and geometry|shape of the resistor. The generated noise
depends only on the resistance value and its temperature T. The noise voltage spectral
density (open circuit conditions) and the corresponding noise current spectral density
(short circuit condition) are:
2
v 2N O I S E V2 i 4k B T A2
S(VN O I S E ) = = 4k B T R S(I N O I S E ) = N O I S E = (10.1a)
∆f Hz ∆f R Hz
The noise power spectral density (the noise power delivered to an identical resistor
R, per unit bandwidth) and the Norton, Thevenin (corresponding to a noiseless resistor
in parallel|series with a noise source) equivalent current and voltage are:

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 139
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_10
140 10 Noise in Semiconductor Devices

2 4k B T ∆ f
SP = k B T i N O I S E = (N or ton) v 2N O I S E = 4k B T R∆ f (T hevenin)
R
(10.1c)

• The previous four expressions are equivalent. One can be used to derive another.
• Nyquist theorem is valid for linear devices in thermal equilibrium.
• The spectral density of thermal noise is constant with respect to frequency (till
frequencies at which the quantum mechanical correction is imposed)—e.g., light.
• The total available noise power of a resistor is infinite at infinite bandwidth. The
BT)
quantum correction limits it to a finite value: (π k6h
2

For a general impedance with non-zero complex component, the noise current spectral
density is:
4k B T R
S(I N O I S E ) = (10.1e)
X 2 + R2
For a linear two terminal network containing only noisy resistors, capacitors, and induc-
tors, the noise current|voltage at its terminals can be calculated by substituting each
resistor with its appropriate model. Then each individual contribution at the output is
calculated and the resulting mean square values are added. An easier approach involves
evaluation of the real part of the complex impedance Z seen when looking into the
terminals and then application of Thevenin equivalent circuit, to get:

v N O I S E = 4k B T ℜZ d f 0 ≤ f ≤ ∞
2
(10.1f)

This is the Nyquist’s formula. For a one-port containing only linear resistors, 10.1f
reduces to:

v 2N O I S E = 4k B T Requi valent ∆ f 0 ≤ f ≤ ∞ (10.1g)

Nyquist’s theorem is not valid for arbitrarily high frequency, since by integrating the
expression for noise signal spectral power density over the entire frequency range results
in infinite noise power. So a quantum correction is imposed. Specifically, if khRfT >> 1 the
noise spectral power density is:

ℏf
S( p) = ℏf
(10.1h)
e kB T −1
Denoting the Planck factor as:
ℏf
kB T
H( f ) = ℏf
e kB T − 1
10.1 Semiconductor Noise Mechanisms [1–77] 141

the mean square value of the open-circuit noise voltage delivered by a resistor is re-written
as

v 2N O I S E = 4k B T H ( f )R( f )d f f 1 ≤ f ≤ f 2 (10.1i)

For linear multiports containing some non-reciprocal devices, Thevenin’s and Nyquist’s
theorems must be formulated differently—the previous impedance expressions must be
replaced by a linear combination of some elements of the impedance matrix used to
describe the non-reciprocal network. Nyquist’s theorem can be applied to linear dissipative
and distributed networks e.g., a transmission line or waveguide.
Nyquist’s theorem cannot be directly applied to nonlinear devices|circuits. If the nonlin-
ear system is in thermal equilibrium and the resulting variations are small, Nyquist’s theorem
holds in the small signal approximation of the input impedance of the circuit. Therefore, the
noise model of a nonlinear resistor is in the form
 I
dV I d 2 V II
v N O I S E = 4k B T
2
+ (10.1j)
dI 2d I 2 I I =ICC

• The frequency distribution of thermal noise power is uniform, at up to

f C = 0.15k B T x1034 H z
• The instantaneous amplitude of the thermal noise has a Gaussian distribution. The
mean value of the fluctuation is zero.
• The peak factor is roughly 4 if only peaks occurring at least 0.01% of the samplingtime
are considered

The Nyquist theorem based thermal noise model is valid for lightly doped semiconductors
and linear resistors only.

10.1.2 Diffusion Noise

Diffusion noise arises from charge carrier velocity variations due to collision|scattering
during charge carrier diffusion. Charge carrier diffusion is a nonuniform carrier distri-
bution. If carrier density increases at one end of a semiconductor, a carrier concentration
gradient is set up, causing carriers to move from high concentration region to low con-
centration region. The moving electrons are scattered via collisions with the lattice and|or
with ionized impurity atoms. Scattering is random, so that the instantaneous value of the
diffusion current is also random, resulting in diffusion noise.
To quantify diffusion noise, a volume of semiconductor material (e.g., n type) is par-
titioned into cells of dimensions ∆x, ∆y, ∆z. The event of any electron moving from one
cell to any of the neighbouring cells is independent of any other electron moving from the
142 10 Noise in Semiconductor Devices

same cell to any other neighbouring cell. The diffusion noise current spectral density is:

4Delectr on n(x)q 2 ∆y∆z

S(I D I F FU S I O N N O I S E ) = (10.2a)
∆x
Using Einstein’s expression relating electron diffusivity and electron mobility, the
diffusion noise spectral density can be re-written as:

k B μelectr on T 4k B μelectr on n(x)∆y∆z 4k B T

Delectr on = S(I D I F FU S I O N N O I S E ) = =
q ∆x ∆R
(10.2b)

where Delecr on , μelectr on , ∆R are respectively the electron diffusivity, mobility and
resistance of a cell. Diffusion noise reduces thermal noise when Einstein’s relation
holds. While thermal noise is due to random motion of carriers, diffusion noise arises from
random collisions charge carriers move through the semiconductor device. Diffusion noise
spectrum is flat.
Diffusion noise is present in all semiconductor devices, as the forward current versus
forward voltage curve for each does not follow Ohm’s law. A transistor operating in the
linear region has weak diffusion noise current, but diffusion noise current is measurable
and strong in the transistor’s saturation region of operation.

10.1.3 Shot Noise

Shot noise arises as charge carriers are discrete. All semiconductor devices contain a
potential barrier. The current through the device is due to those electrons that possess
sufficient energy to cross the potential barrier. The passage of charge carriers (elec-
trons) across this barrier is a series of independent, random events. For example, for a
stream of electrons in vacuum, between two electrodes, the number of electrons crossing
a reference plane will vary with each sampling time, due to both the random emission
rate of electrons at the source plane, and the random distribution of individual velocities.
Every time an electron crosses the reference plane, an elementary current pulse appears
in the external circuit. The area of this reference plane is equal to the elementary charge
q and the transit time (the average time needed to traverse the distance from the source to
the reference plane). This noise mechanism is shot noise and is due to the discrete nature
of electric charge.
Shot noise appears in all devices collecting a flow of electrical charges, under the
condition that the charge carriers have ballistic trajectories with no interactions during
flight. This holds strictly when charge carrier density is low with high external electric field.
Otherwise, the randomness of their position and velocity is reduced by repulsion between
identical charges or collisions with lattice atoms.
10.1 Semiconductor Noise Mechanisms [1–77] 143

Shot noise analysis starts with the arrival of an electron at the reference plane. Ignoring
transit time the instantaneous current is the sum of elementary Dirac pulses of weight q,
with average value and spectral density given as:
∑ A2
I (t) = q δ(t − ti )I (t) = I0 = λq S(I ) = 2q 2 λ (10.3a)
Hz

where λ is the average number of electrons collected per second. The spectrum, computed
while ignoring transit times, is white. If transit times are included a cut-off frequency
ωCU T O F F = Ttransit
3.5
is introduced. Shot noise is modelled as a noise current with mean
square value:

i 2electr on = S(I )∆ f (10.3b)

where ∆ f is the measurement system bandwidth.

The current flowing through a homogeneous np junction is due injection of minority
carriers into the bulk region, followed by their diffusion and recombination. Shot noise
is a combination of diffusion noise and generation-recombination noise for the minority
carriers. There might also be noise contributed by emission across the junction potential
barrier: the passage of each carrier is an independent random event. The junction current
of a homogeneous pn junction diode is:

 qV 
I = IS e kB T − 1 (10.3c)

where I S V are the saturation current and applied diode voltage respectively. Assuming
that the two current components generate independent random variations,
 qV 
i 2electr on,total = 2q I S ∆ f e k B T + 1 = 2q∆ f I S (I + I S ) (10.3d)

From the small signal low frequency conductance expression, the transconductance is:
dI qI
gm = = (10.3e)
dV kB T
Combining the above two expressions, the total averaged shot noise current is:

i 2electr on = 2q I ∆ f = 2k B gm ∆ f T A2 (10.3f)

For a metal semiconductor junction (e.g., Schottky diode), the current flow is due to
majority carriers. There are two types of carriers::
144 10 Noise in Semiconductor Devices

• Carriers going from metal into semiconductor, which encounter a potential barrier of
height E O , producing a current −I S , which is independent of the applied voltage.
• Carriers flowing in the reverse direction, from semiconductor into metal,which
encounter a barrier of height q(ΦC O N T AC T P O T E N T I AL − V ), where V is the volt-
age applied to the metal. The overall current is the sum of these two components, the
total current spectral density is

 
I + 2I S
S(Itotal ) = 2q(I + I S ) = 2k B gm T (10.3g)
I + IS

• Shot noise depends only on the DC current, not temperature. through the device, mod-
ifying the bias current represents an easy way to control the noise level. This property
is useful in the design of calibrated noise sources.
• A junction diode always generates shot noise, the potential barrier is associated with its
depletion layer. Since fluctuations are increasingly smoothed out as the average current
increases, in forward biased junctions the noise current is much lower than predicted.
• The power distribution versus frequency is uniform—white noise up to frequencies
close to the reciprocal of the transit time.
• Shot noise instantaneous amplitude distribution is Gaussian The ratio of variations to
the average current can be reduced by increasing the number of electrons reaching the
collector terminal.
• Shot noise could ideally be reduced if the magnitude of an individual charge could be
diminished.

Shot noise is always generated in junction diodes, and its effects are observed in reverse-
biased diodes or forward biased junctions operating at very low currents.

10.1.4 Generation Recombination Noise

Generation recombination noise is due to statistical variation in the population of charge

carriers due to random generation|recombination, random trapping, and the release of
carriers in a semiconductor.
When a covalent bond is broken, an electron–hole pair is generated, and each covalent
bond breaking event requires a small amount of extra energy This energy can be supplied
either thermally or by illuminating the semiconductor surface. Since the flow of energy
(phonons or photons) is quantized and non-uniform, the generation of charge carriers is a
random process, both in space and in time.
10.1 Semiconductor Noise Mechanisms [1–77] 145

Opposing charge generation is simultaneous electron hole recombination. Recombina-

tion depends on the Brownian motion of carriers. Recombination is also a random process.
On average, generation must balance recombination.
Traps in the bulk or on the surface of a semiconductor are very important in this noise
mechanism. Electrons and holes are captured, and then released after a variable but finite
time interval, additional variations in the population of charge carriers. All crystal lattice
defects—impurity atoms or molecules that contaminate the surface of the semiconductor
during fabrication, act as traps.
Variations in charge current density in a semiconductor material results in current
fluctuations—as per Langevin’s method, and is controlled by a differential equation:

d(∆N ) ∆N
= H (t) − (10.4a)
dt τ0

where ∆N is the variation in the number of carriers τ O is the average lifetime of added
carriers, and H(t) is a random white noise source that controls the variation. The power
spectrum of the generation recombination noise is:

4∆N 2
S( p) = (10.4b)
1 + ω2 τ O2

Generation recombination noise is modelled as noise current generator with power

spectral density given by (10.4b), and the mean square value:

4I 2 τ
i 2electr on =   (10.4c)
N 1 + ω2 τ 2

where N is the average number of carriers, I is the average (DC) current through the
device, and τ is the generation-recombination time constant. The level of generation-
recombination noise is proportional to the square of the average (DC) current through the
device. Since τ may be as brief as 1 ns, the generation recombination noise spectrum is
flat up to a frequency of about 1/τ. Then it falls at about 20 dB per decade. Generation
recombination noise induces variations in the conductivity of the material as the number
of charge carriers is fluctuating; in contrast, for thermal noise, the number of carriers is
roughly constant, but their spatial distribution fluctuates.
Generation recombination noise shows up in regions of a semiconductor material
where carriers concentrations are low, e.g., in intrinsic semiconductors, lightly doped
semiconductors, and in the space charge layer of every junction.
146 10 Noise in Semiconductor Devices

10.1.5 Flicker (1/f) Noise

The exact physical cause for flicker noise is unclear, it occurs in many non-electrical sit-
uations as well. 1/f noise is inversely frequency dependent—increasing with decreasing
frequency, often extending to very low frequencies 10 − 4 Hz.
Flicker noise is a general process in discontinuous, non-equilibrium systems e.g., DC
current flow through a semiconductor device. Possible underlying causes could be either
defects affecting the semiconductor lattice (e.g., unwanted impurity atoms), or to interac-
tions between charge carriers and the surface energy states of the semiconductor, imperfect
contacts (e.g., between granules of carbon in carbon resistors) etc., Flicker noise in carbon
resistor is called “excess noise”, as it adds to the thermal noise of the resistor—a wire
wound resistor has no excess noise.

• Model A relates flicker noise to surface states, and is based on the time constants
associated with the recombination process.
• Model B proposes an empirical approach relating flicker noise to bulk effects in
dissipative media.
• Model C uses quantum mechanics to propose that flicker noise is conditioned photon
emission each time a charge carrier collides with the lattice.
• Model D states that flicker noise is produced by the fluctuation of a parameter u,
subject to the diffusion equation

∂u
= D∇ 2 u (10.5a)
∂t
Here ∇ is the Laplacian operator and D is a constant. This equation is of the same form
as that used to describe thermal conductivity or carrier diffusion. The solution to this
equation is not an accurate representation of flicker noise, for finite dimension systems,
the power spectral density has a 1/f region covering several decades. Below and
above this region the frequency dependency is of the form f1k , k being an integer or a
real number.
Flicker noise generated in semiconductor materials e.g., GaAs is a bulk phenomenon
associated with local high frequency and long range low frequency variations, the lowest
frequency being limited only by the bulk volume. Perturbation theory states that any large
dimension distributed system and high resistance and some capacitance will generate
flicker noise when disturbed. Then the 1/f noise is modelled by a current generator with
mean square value:

K I α∆ f
i 2electr on = (10.5b)
fn
10.1 Semiconductor Noise Mechanisms [1–77] 147

where K is a device dependent constant; α is a constant (0.5≤α≤2), n = 1 for pink noise

characterized by constant power per octave (n could be 2 due to variations in the Earth’s
rotational speed, and 2.7 for galactic radiation). ∆f is the bandwidth of the measurement
system and I is the DC current through the device.
Flicker noise in homogeneous semiconductors can be represented using a parameter α
such that the power spectral density of a resistance R is:

α R2
SR = (10.5c)
fN

where f the measurement frequency, and N the total number of free charge carriers. α
corresponds to the normalized contribution to the relative noise of a single electron, per
unit bandwidth (independent of contributions of other electrons). An initial trial average
value of 0.002 was proposed for α [1–77]. α also depends on the quality of the crystal—in
a impurity free|perfect material its value could be 2 or 3 orders of magnitude lower.

• The probability distribution function of flicker noise amplitudes is not Gaussian.

• The spectrum increases with decreasing frequency, never reaching frequency zero.
• Flicker noise is prominent whenever electric currents are due to a very small number
of charge carriers.

In bipolar transistors flicker noise is generated due to lattice defects or unwanted impuri-
ties present in the emitter base region. Carriers are trapped, then released randomly. The
associated time constants are long and this explains why the noise spectral density is more
important at low frequency. It has been determined that flicker noise current in a bipolar
transistor is:
K1 I α δ f
i 2electr on = (10.5d)
fβ
K 1 is a constant weakly dependent on temperature; I is the forward current through
the device; δf is the bandwidth centred on f: (0.5≤α≤2) and β ≈ 1.
Flicker noise is absent in carbon resistor, while for an integrated resistor the mean
flicker noise voltage is:

K R R S H E E T δ f VDC
2
v2 = (10.5e)
AR f
R S H E E T is the sheet resistance, A R is the area of the resistor, and K R is a tech-
nological constant. For a diffused or ion-implanted resistor, its value is approximately
148 10 Noise in Semiconductor Devices

5x10−24 S 2 cm 2 , while for thick-film resistors, it is roughly 10 times greater. For inte-
grated gallium arsenide resistors, flicker noise is proportional to the square of the applied
voltage.
In a field effect transistor, the drain current shows variations with a 1/f spectrum, due to
fluctuations in the population of charge carriers in the channel—a result of carrier trapping
in the surface states situated at the silicon–silicon dioxide interface. For a MOSFET the
surface state density at the Fermi level is the only parameter that influences flicker noise.
So to reduce MOSFET flicker noise, the surface state density in the vicinity of the Fermi
level must be reduced. Flicker noise increases with decreasing temperature, as the density
of surface states increases toward the conduction band. For MOS transistors operating
in strong inversion, flicker noise does not depend on the gate bias, because the surface
potential varies very slowly with gate charge. Thus the only way to lower the noise level is
to modify the device geometry.
Heterogeneous junction devices have higher levels of flicker noise. Any inhomogene-
ity in the lattice structure or materials as well as contamination during processing, poor
ohmic contacts, etc. can increase the flicker noise. Flicker noise is low in devices with
homogeneous structure and a significant volume of material for instance a 1-W resistor is
less noisy than a 0.25-W resistor of the same value and type.
In modern integrated circuits, reduction of physical dimensions of transistors increases
flicker noise. The effects of flicker noise are not limited to low frequency, since it can
be up-converted by an existing nonlinearity, as in active mixers, frequency dividers, and
voltage-controlled oscillators.

10.1.6 Burst (Popcorn) Noise

The underlying physical reason behind burst (popcorn) noise is not clear. Burst noise
occurs in planar diffused devices, tunnel diodes, bipolar transistors, integrated circuits and
film resistors. Material contamination by heavy metal atoms during processing, or crys-
tallographic damage of regions close to junctions may cause burst noise. Bursts appear
commonly in small dimension devices operating in high current|voltage density condi-
tions, in single trap activity in a region with few free carriers e.g., the depletion region of
the emitter junction.
For a bipolar transistor, burst noise is modelled as a current generator with mean square
value:
K1 IB ∆ f
i 2electr on = (10.6a)
π2 f 2
1+ 4a 2

where a is the burst rate, K 1 is a constant, and I B is the transistor base current.
10.1 Semiconductor Noise Mechanisms [1–77] 149

Burst noise corrupts bipolar transistor collector current at a random rate, between sev-
eral hundred per second to one every few minutes, with variable burst widths: between
several microseconds and a few minutes. For a particular device under test, the amplitude
remains the same. Bursts can overlap. The burst noise spectrum is proportional to f12 .

• Burst noise is observed at low frequencies.

• The instantaneous burst noise amplitude is 2 to 100 times that of thermal noise. For
a device under test, this amplitude is constant, as it is determined only by the specific
defect of the junction.
• Burst noise can appear|disappear at random.
• Among all devices fabricated in a single run, this noise might affect only a few,
indicating poor quality.

State-of-art semiconductor device manufacturing technologies, in ultra clean fabrication

facilities have eliminated this problem.

10.1.7 Avalanche Noise

Avalanche noise is the result of carrier multiplication due to impact ionization in a

reverse-biased np junction. In a reverse biased np junction with a large applied bias, the
electric field in the depletion region is enhanced, such that minority carriers (holes in the
n region and electrons in the p region) are accelerated hard and their energy is increased.
A chance collision with a neutral lattice atom generates one or more electron–hole pairs
by impact—impact ionization.
Due to positive feedback, these pairs of impact generated carriers are accelerated and
undergo collisions themselves producing additional pairs of charge carriers. Crystal struc-
ture imperfections result in microplasma generation in low-volume regions and the current
through the junction is increased. Uncontrolled avalanche process leads to breakdown.
Every carrier crossing the junction induces an elementary current pulse. Total current is
a superposition of all elementary current pulses, which varies with the number of carriers
traversing the junction potential barrier per second. The movement of avalanche gener-
ated carriers across the junction is more complicated, since the carriers are multiplied by
a factor M—random variable of both space and time. The probability of generating new
pairs by collision is different for electrons and holes and breakdown does not occur simul-
taneously. Applying some simplifying assumptions, (e.g., M is independent of position x)
the mean square avalanche noise current and its corresponding spectral density are:
  
2
i = 2q M 2 ∆ f Ihole (0) + Ielectr on (w) + 2q A g(x)d x S(I )
  
= 2M 2 Ihole (0) + Ielectr on (w) + 2q A g(x)d x 0≤x ≤∞ (10.7a)
150 10 Noise in Semiconductor Devices

w is the width of the depletion region and g(x) is the number of charge pairs generated at
coordinate x per unit volume per unit time, and A is the junction area. With the adopted
simplifications, the avalanche noise spectrum is white.
10.7a applies to reverse voltages higher than 8 V, where the breakdown mechanism
comes into play. For reverse voltages less than 5 V, breakdown is the result of the Zener
effect. If the reverse voltage lies between 5 and 8 V, the power spectral density is:
  
S(I ) = 2q Ihole (0) + Ielectr on (w) + 2q A g(X )d X X = 1 + f MP (10.7b)

 
f M P is a function of the averaged ionized rates. In this case, primary carriers are
generated by the tunnel effect, and the secondary carriers by collision.
Avalanche noise has a typical waveform with several levels separated by a few mil-
liVolts. At start there is fast random switching among all levels. As the reverse current
increases, the highest level becomes dominant. The avalanche noise spectrum is white.
Avalanche noise mainly occurs in reverse-biased diodes operating at more than 8 V.

10.2 Microwave Noise

As transistors are nowadays increasingly operating at microwave frequencies (100 s of

MHz—10 s of GHz) the types of noise specific to this frequency range is analysed in
detail, using accurate small signal scattering parameters (S parameters) analysis.

10.2.1 Hybrid π Bipolar Transistor Microwave Noise Model

The noise free and noisy hybrid π common emitter bipolar transistor microwave noise
equivalent circuits [24] are in Figs. 10.1a, b respectively. The emitter junction is conduc-
tive, and generates shot noise on the emitter. The emitter current is a combination of the
base and collector currents (I B , IC ),
Collector reverse current also generates shot noise. The emitter, base, and collector are
made of semiconductor material and each have a finite resistance resulting in thermal
noise. The base resistance is value higher than both the collector and emitter resistances,
So the thermal noise contribution of the collector, emitter resistances can be neglected in
the initial analysis. Three sources are introduced in a noiseless transistor: noise due to
variation in the DC bias current (I B,N ), the DC collector current (IC,N ), and the thermal
noise of the base resistance. The signal source would also have internal conductance and
thereby generate noise and its susceptance affects the noise level through noise tuning.
In silicon transistors, the collector reverse current (IC O,B ) is very small, so the noise
(IC O,N ) generated by this current can be neglected. The mean square value of the above
noise generator in a narrow frequency interval ∆ f is given by:
10.2 Microwave Noise 151

(a) (b)

(c)

Fig. 10.1 a, b Hybrid π common|grounded emitter noiseless and noisy bipolar transistor microwave
noise equivalent circuit. c BJT noise sources transformed to input, with noiseless intrinsic transistor

i 2B,N = 2q I B ∆ f i C,N
2
= 2q IC ∆ f i C
2
O,N = 2q IC O,B ∆ f v B,N
2

= v 2S,N = 4k B T R B ∆ f (10.8abcd)

The corresponding current|voltage noise power spectral densities are:

  i C,N
2
  i 2B,N
S i C,N = = 2q IC = 2k B gm T S i B,N = = 2q I B
∆f ∆f
2k B gm T   v 2B,N   v 2S,N
= S v B,N = = 2k B T R B S v S,N = = 2k B T R S
β ∆f ∆f
(10.8efgh)

where R B , R S are the base and source resistances.

10.2.2 Generalization of the Noisy Bipolar Transistor Equivalent Circuit

The equivalent circuit model for the noisy silicon bipolar transistor [24] (Fig. 10.1b) is
generalized to a two port network with all the noise current|voltage sources transformed
to the input (Fig. 10.1c) and a noiseless two port network for the transistor. The noise
free two port transistor is represented in the [ABCD] matrix form, whose elements are:
1 −1
AC R = gm BC E = CC E = AC E (gm + g BC + j ωC B E )
1− jωC BC gm
1
RB E + j ω(C B E + C BC )
DC E = (10.8ijkl)
gm − j ωC BC
152 10 Noise in Semiconductor Devices

The DC forward current gain and the transition frequencies are:

ge
β = ge ( f )R B E fT =
2π (C BC + C B E )
In silicon transistors the collector reverse current is very small, and so the noise gen-
erated by this current can be neglected. The noise factor F is the ratio of the total
mean square noise current and the thermal noise generated from the source resis-
tance. The total noise is that obtained from the entire network, defined as (with reference
to Fig. 10.1c):

v N ,N E T W O R K = VB N + I B N R S + R BP + A A R S + R BP + j (I B N X S + A AIC N )
1 jf
− IC M R E A A = + (10.8m)
β fT
The total nose and noise factor are:

V 2
N ,T O T AL
VN ,T O T AL = VN ,S OU RC E + VN ,N E T W O R K F=
VN2 ,S OU RC E
VN2 ,N E T W O R K + VN2 ,N E T W O R K
= (10.8no)
VN2 ,S OU RC E

The expression for the noise factor F can be re-written in terms of the A, B, C, D
parameters examined previously. This is left as an exercise for the reader. The noise
factor expression, in the special case when the source reactance is zero, is:
 
1 RE
F =1+ R BP +
RS 2
   
1 1 βf
+ R BP + R S 2R E + R S + R BP + R BP + R S + (10.8p)
2β R E R S β fT

It can be simplified further for the following conditions:

 P 2
1 R B + RS RE
F= ( RB + <
P
>+<
RS 2β R E 2
  P 2
f R B + RS
+ > β >> 1 ωC BC R E << 1 (10.8q)
2β f T2

where the contribution of the first, second and last terms are due to the base resistance,
base current, and collector current respectively.
10.3 T Equivalent Circuit for Noisy Bipolar Transistor 153

10.3 T Equivalent Circuit for Noisy Bipolar Transistor

The T equivalent circuit model for the bipolar transistor at microwave frequencies [24] is
in Fig. 10.2. C T E , Z S are respectively the emitter junction capacitance and the complex
source impedance.
The T-configuration is simpler than the hybrid π model for minimum noise current
calculation. Formulating the noise correlation matrix with the base collector capacitance
C BC , is easy in the hybrid π topology. Silicon bipolar transistor noise can be modelled
with three noise sources—base resistor thermal noise, forward biased base emitter junc-
tion resistance shot noise and and collector junction noise. The mean square values of
noise sources in a narrow frequency range ∆ f are:

e 2E = 4k B R E T ∆ f e 2B = 4k B R B T ∆ f e 2S = 4k B R S T ∆ f (10.9abc)

α0 α 1 kB T
I C P e EP = 0 α = β= gE = RE = (10.9d)
1+ jf 1−α RE q IE
fn

where the base resistance thermal noise voltage source is e B . The shot noise voltage
source e E is generated by the forward-biased emitter base junction R E . The collector
noise current source IC P comes from the collector partition, which is strongly correlated
to the emitter–base shot noise.
The noise factor by definition is the ratio of the input signal to noise ratio to the output
signal to noise ratio. Alternatively, the noise factor can be re-written as:
SI N P
NI N P N OU T N OU T I 2L
F= S OU T
= = F= (10.9ef)
N OU T
G NI N P BGk B T I 2L O

where i L O is the value of i L due to the source generator noise e S only, and i L is the
total load current or the collector current (AC short-circuited current) due to all the noise
sources. These are expressed as:

Fig. 10.2 T equivalent circuit

model for noisy silicon bipolar
transistor
154 10 Noise in Semiconductor Devices

IC P
α e B + e S + e E (1 + j ωC T E (R B + Z S )) + α ((1 + j ωC T E R E )(R S + Z S ) + R E )
IL =
(1 + j ωC T E R E − α)(R B + Z S ) + R E
(10.9g)
αe S
IL O = (10.9h)
(1 − α + j ωC T E R E )(R B + Z S ) + R E
The expression for the noise factor is evaluated easily, and simplified in the source
impedance zero case. It is then used for determining the minimum noise factor and the
generator thermal noise are expressed as (∆ f = 1 Hz):
kB T
e 2E = 4k B R E T e 2S = 4k B R S T e 2B = 4k B R B T RE = IC P
q IE
  α0
= 2q I E α0 − |α|2 α = jf
(10.9i)
1+ fB

10.4 Noisy Gallium Arsenide (GaAs) Field Effect Transistors

A noise model of a grounded source GaAs field effect transistor (FET) [24] with the noise
sources at the input and output is in Fig. 10.3a, b. This configuration is the field effect
transistor equivalent of the common emitter bipolar transistor, examined earlier. The mean
square values of the noise sources in the narrow frequency range ∆ f are:
2 ω2 RT ∆ f
4k B C G S
I 2D = 4k B gm P T ∆ f I 2G = I P
G ID
gm
√
= 4 j ωC G S k B T C PR ∆ f S(I D ) = 4k B gm P T (10.10abcd)

 
2 ω21 RT
4k B C G √ − j I G I DP
S(IG ) = S
S IG I DP = −4 jC G S ωk B T C PR C= /
g−m I D2 IG2
I 2D gm I 2G
P= /hz R = 2 k ω2 T
/H z
4gm k B T 4C G S B
(10.10defg)

where C, P, R are curve fitting parameters. The values of these three parameters for
MESFET are: C: 0.6–0.9 P: 1.2 R: 0.4
Y parameters are used to determine the noise parameters of the GaAs field effect
transistor. First the transistor’s equivalent circuit is transformed to an equivalent circuit in
which all the output noise sources are transformed to the input, with a noiseless transistor
attached to the output of the noise source circuit (Fig. 10.4a, b). With respect to Fig. 10.4a,
10.4 Noisy Gallium Arsenide (GaAs) Field Effect Transistors 155

(a) (b)

Fig. 10.3 a, b GaAs field effect transistor with noise sources and noise sources transformed to input
and output noise sources only

the noise matrix is:

2 ω2 T
4k B C G S
[CY ] F E T = [CY 11 CY 12 CY 21 CY 22 ] CY 11 =
gm
√ (10.10h)
CY 12 = −4 jk B ωC G S C P RT
√
CY 21 = −4 j AC G S k B C P RT CY 22 = 4gm k B P T

(a) (b) (c)

(d)

Fig. 10.4 a Lumped element model for drain, gate connection manifold b drain, gate air bridge
lumped parasitic element noise circuit c source connection via lumped parasitic element noise circuit
d GaN HEMT connected to printed circuit board—intrinsic noiseless HEMT and peripheral noise
generating sub-circuits
156 10 Noise in Semiconductor Devices

Fig. 10.5 Test bench for

measuring bijunction transistor
base spreading resistance

After the noise source transformation, the noiseless GaAs field effect transistor can
be expressed in terms of its ABCD matrix, and this in turn can be related to the noise
matrix before the transformation.
The transformed transistor noise matrix, is expressed in terms of the noise matrix of
the nontransformed noise matrix is:
 
[Ca ]T R = [T ][CY ]T R [T ]TP R = e N e N i NP e NP i N i NP [T ]
 
= [0BC S 1DC S ] [T ]TP R = 01BCPS DCP S (10.10i)

where BC S , DC S are the elements of the noiseless transistor’s ABCD matrix, and [T] is
the transformation matrix.
After substituting all the values for the elements of the respective matrices, followed
by considerable manipulation, a number of intermediate parameters are generated:

g DS + j ω(C G S + C G D + C DS )
C O N ST = Cuu P = 4k B T (A AB B)
j ωC G D − gm
gm P(1 + C O N ST R S ( j ωC G D − gm ))
AA = (10.10jkl)
j ωC G D − gm
1 + C O N ST ( j ωC G D − gm )
BB =
( j ωC G D − gm )
√
4 j ωk B C G S C P RT (1 + C O N ST ( jωC G D − gm ))
Cui P = + A1 A1 = P B BC O N ST P
j ωC G D − gm
√
B1 = C O N ST P gm PC O N ST − j ωC G S C P R
(10.10mn)
  
C G S ω2 R
Cu P = 4k B T C G S + j ω( j ωC G D − gm )C O N ST P + B1 (10.10o)
gm

Now using the intermediate parameters, the noise parameters for the GaAs field effect
transistor, e.g., noise resistance, optimized Y parameter matrix, minimum noise factor
10.5 Noisy Heterogeneous Junction Bipolar Transistor (HBT) 157

etc., are as below (10.10 p, q, r, s)

/   2  
Cuu P Cu P Cu P Cui P
RN = YO P T = +j +j
2k B T Cuu P Cuu P Cuu P
Y O P T − Y0 (10.10pqrs)
= G O P T + j BO P T ΓO P T =
Y O P T + Y0
Cui P + Cuu P Y O P T
FN O I S E,M I N = 1 +
kB T
These expressions can be simplified assuming that the drain gate capacitance is
neglected. This is left as an exercise for the reader.

10.5 Noisy Heterogeneous Junction Bipolar Transistor (HBT)

Using identical arguments as for the noisy homogeneous junction bipolar transistor, the
primary RF noise sources in a SiGe heterogeneous bipolar transistor HBT [25–37] are the
noises associated with the DC base and collector currents and the thermal noise of the
base resistance.
The power spectral densities (PSD) of the base and collector current noises have the
characteristics inherent to shot noise. The shot noise current is assumed to be a Poisson
distributed stream of an elementary charge q. These charges need to overcome a potential
barrier, and thus flow in a completely uncorrelated manner. In a bipolar transistor, the
base current shot noise is 2q I B arising from the flow of base majority holes across the
emitter–base junction potential barrier. As the hole current overcoming the emitter base
barrier is determined by the minority hole current in the emitter I B , it reappears again in
the base shot noise current expression. Similarly, the collector current shot noise results
from the flow of emitter majority electrons over the emitter base junction potential barrier,
and has a spectral density 2q IC .
Any DC current through any np junction has shot noise, and the collector current
passing through the collector–base junction has the value 2q IC for the shot noise. The
transition of carriers across a reverse biased collector–base junction (for low noise amplifi-
cation), is a drift process. A DC current passing through such a junction alone does not have
intrinsic shot noise. The collector current shows shot noise as the electron current injected
into the collector–base junction from the emitter already has shot noise.
The emitter current shot noise has two independent components, one due to electron
injection into the base, and the other due to hole current injection into the emitter, both
with “shot” like characteristics.
2
i elecr 2
i hole,emitter
on,emitter
S I N J ,E,E = = 2q IC S I N J ,H ,E =
∆f ∆f
= 2q I B < 2
i electr on,emitter i hole,emitter >= 0 (10.11abc)
158 10 Noise in Semiconductor Devices

The collector current shot noise is a delayed version of the emitter electron injection
induced shot noise:

i C,S H O T = i electr on,emitter = i in jected,electr on,emitter e− j ωτelectr on (10.11d)

where τelectr on is the transit time of the electrons of the emitter injected shot noise current.
The averaged values of the shot noise currents are:

< i 2N O I S E,C,S H O T > = 2q IC ∆ f < i 2N O I S E,E,S H O T >= 2q I E ∆ f < i N O I S E,C,S H O T i N

P
O I S E,E,S H O T >
= 2q IC ∆ f e jωτelectr on (10.11efg)

For the widely used common emitter configuration of bipolar transistors, the above
expressions for the averaged currents are re-written as: HERE HERE

< i 2N O I S E,B AS E > =< i 2N O I S E,E,S H O T > + < i 2N O I S E,C,S H O T > −2ℜ(< i N O I S E,E,S H O T i N
P
O I S E,C,S H O T >)
= 2q(I B + 2IC ∆ f (1 − ℜe jωτelectr on )) (10.11h)

< i N2 O I S E,C O L L EC T O R >= 2q IC ∆ f

< i NP O I S E,B i N O I S E,C >= 2q IC ∆ f (e− jω,τelectr on − 1) (10.11i)

This transport shot noise model is also called the unified model, because it can be
reduced to the conventional SPICE [73–77] noise model by setting electron noise current
transit time to zero, or when ω << τelectr 1
on
. This model enables accurate modelling of
both experimental noise data and hydrodynamic noise simulation data in SiGe HBTs.
Minority carrier velocity fluctuations also contribute to shot noise. Velocity variations
lead to current density fluctuations, which propagate towards the terminals. The collec-
tor current shot noise originates from the neutral base, which is close to the physical
explanation underlying the transport noise model.
Noise factor is a noise performance characteristic. It is defined as the ratio of the input
signal-to-noise (SNR) to the output signal-to-noise (SNR). Often, the noise figure, defined
as the logarithm of the noise factor to base 10, is used. For a source termination admittance

RB + 1
gm   1
Y S = G S + j B S F = FM I N + Y S − Y S,O P T RN = RB + (10.11k)
GS gm

where Y S,O P T is the optimum source admittance, and R N is the noise resistance—noise
parameters. Noise figure reaches its minimum when the source is noise matched. The
source resistance determines the sensitivity of noise figure to deviations from the opti-
mum source admittance. The smallest possible noise figure and smaller source resistance
are obviously desired. The noise parameters are intrinsic properties of the linear two port
10.5 Noisy Heterogeneous Junction Bipolar Transistor (HBT) 159

network, as the S|Y|Z parameters. They are functions of the equivalent input noise volt-
age, current and their correlation, denoted as Si ,n , Sv,n , Sin vnP . Under certain simplifying
assumptions, the equivalent input noise current|voltage can be approximately obtained as:
 
IC
S I ,N O I S E = 2q I B + SV O L T ,N O I S E
|H21 |2
   
IC IC Y11
= 4k B R B T + 2q I B R 2B + S I ,V ,N O I S E = 2q I B R B +
|Y21 |2 |Y21 |2
(10.11l)

Y, H refer to the conventional small signal parameters. They can be expressed using
equivalent circuit parameters β, collector current, base emitter, base collector capacitances
and transconductance. For a given collector current, a higher β reduces the base current
and Si ,n , which is also inversely proportional to H21 . A high transition frequency also
in increases H21 and reduces Si ,n . The inherent high β and high transition frequency of
SiGe HBTs enables these devices to have low input noise current. For the same β, the
additional bandgap engineering leverage in SiGe HBTs allows higher base doping than
in homogeneous junction implanted-base Si BJTs, which reduces the input noise voltage.
The real and imaginary parts of Y S,O P T are:
/  
gm ω2 C I2 1 −ωC I
G S,O P T = + 1− B S,O P T = (10.11o)
2β R N 2gm R N gm R N 2gm R N
/  
gm ω2 C I2 1 −ωC I
G S,O P T = + 1− B S,O P T = (10.11p)
2β R N 2gm R N gm R N 2gm R N

where C I = C BC + C B E . The imaginary part of the source admittance is negative. There-

fore series inductor at the base is thus needed for noise matching of the imaginary part.
As the collector current dependence of C I through the transconductance, it is observed
that:

• The real part of the optimum source admittance increases with the collector current
and frequency.
• When the diffusion capacitance dominates the combined capacitance, the imaginary
part of the source admittance becomes independent of the collector current.
• The absolute value of imaginary part of the source admittance increases with frequency.
The minimum noise figure is:

/
1 √ 1 f2
FM I N = 1 + + gm R B + 2 (10.11q)
β β fT
160 10 Noise in Semiconductor Devices

when f = √f T the minimum noise figure changes from white noise (no frequency depen-
β
10d B
dency) to decade frequency dependency. Also, a low base resistance is important to reduce
the minimum noise figure when f > √f Tβ .
RF semiconductor devices are also affected by low frequency 1/f noise, and is influ-
enced by the SiGe HBT’s size and biasing current. The value of such noise can be high
near DC. 1/f noise is a problem for low noise, low frequency analog circuits, e.g., ampli-
fiers used in zero intermediate frequency direct conversion receivers. This noise can also
be upconverted to phase noise that degrades signal integrity of frequency translations.
Although base and collector currents have flicker noise, the part due to the base cur-
rent dominates. The low frequency base noise current spectrum for a SiGe HBT shows
both the contribution of the 1/f noise and the shot noise component 2q I B component.
The performance characteristic for flicker noise is the corner frequency, is defined by the
intercept of the 1/f component and the shot noise level. At higher base current values, the
shot noise contribution cannot be observed easily, but inferred from the corner frequency
value.
The flicker noise spectrum is:

K F I Bα
SI u = (10.11r)
f

where K F and α correspond to the KF and AF SPICE [73–77] model parameters. α = 1

indicates carrier mobility fluctuations, and α = 2 for carrier number variations for typical
SiGe HBTs its value is approximately 2, and varies only slightly with SiGe profile and
collector doping profile (2 ± 0.2).
If 1/f noise is assumed only to be a function of the number of minority carriers injected
into the emitter, means the same base current for a SiGe HBT and its homogeneous
junction Si counterpart.
1/f noise performance is characterized by the corner frequency, defined as the
frequency at which the 1/f noise equals the shot noise level. Assuming α = 2,
K IB K JC O R N E R IC IC Su
f C O R N E R, 1 = = JC O R N E R = β= SΦ ∝
f 2q A E 2qβ AE IB 4π 2 f 2
(10.11r)

Minimizing voltage controlled oscillator (VCO) and frequency synthesizer phase noise,
is a key concern for designers of these two circuits. Phase noise is a result of variations
in time period of a periodic time varying current, voltage waveform. For a target fre-
quency is f, if perturbations in the time period is less than the time period corresponding
to the specified|target frequency f, the actual frequency is higher than f, and vice-versa.
In the spectrum, the higher frequency appears to the right of f, and the lower frequency
to the left of f. Consequently the spectrum has decaying tails on both sides of the center
frequency f. For an arbitrary signal u, the corresponding phase noise Φ and the PSD of ϕ
10.6 Noisy Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) … 161

is related to the PSD of the physical noise u by


Su
Φ(t) ∝ u(τ )s(t − τ )dτ − ∞ ≤ τ ≤ t SΦ ∝ (10.11s)
4π 2 f 2

10.6 Noisy Gallium Nitride (GaN) High Electron Mobility

Transistor (HEMT) Model

A widely used noise model [40–54] for the common low noise GaN HEMT consists
of a noiseless semiconductor device (intrinsic GaN HEMT) embedded inside a network
of capacitors, inductors and resistors. These passive circuit components are the parasitic
capacitors, inductors and resistors resulting from the way a surface mount HEMT is sol-
dered to its printed circuit board. The surface mount HEMT soldered to a printed circuit
board is ideal for very accurate electromagnetic solver analysis.
Common commercially available GaN HEMT has metal “fingers” drain, gate connec-
tions, and the source is a metal pad underneath the device, The corresponding drain, gate
connectors on the printed circuit board are called drain-gate manifold. The HEMT source
connection is a metal pad underneath the device that is soldered to a printed circuit board
via. Also, there is a very small (fraction of a millimeter gap between the periphery of the
HEMT and the locations of the drain-gate connections with the printed circuit board—air
bridge. At RF|microwave frequencies, each of these external (to the intrinsic semicon-
ductor device) physical structures act as a network of parasitic capacitors, inductors
and resistors (Figs. 10.4a, b, c and 10.5).
With reference to Figs. 10.4a, b, c and 10.5 the admittance(Y) matrix of the drain, gate
manifold network is:
1
[Y ] X ,M = [Y 11Y12 Y21 Y22 ] Y11 = j ωC1,X ,M +
R X ,M + j ωL X ,M
−1 1
Y12 = Y22 = j ωC2,X ,M + (10.12a)
R X ,M + j ωL X ,M R X ,M + j ωL X ,M
−1
Y21 = X :D R AI N , G AT E
R X ,M + j ωL X ,M

The series resistance of the drain-gate manifold (Fig. 10.4a) is frequency dependent
(skin effect)
√
R X ,M (ω) = R DC,X ,M + ω(1 + i )R R F,X ,M X :D R AI N , G AT E (10.12b)

The drain-gate manifold model parameters are extracted from electromagnetic solver
simulations—R DC,X ,M , R R F,X ,M are determined by linear regression:
162 10 Noise in Semiconductor Devices

 
1 √
−ℜ = R DC,X ,M + ω R R F,X ,M X :D R AI N , G AT E (10.12c)
Y12 , X , M

The drain, gate manifold parasitic capacitance, inductance are extracted using identical
linear regression techniques:

Y11,X ,M − 1
R X ,M (ω)+ jωL X ,M
C1,X ,M =< > C2,X ,M
ω
Y22,X ,M − 1
R X ,M (ω)+ j ωL X ,M
=< > (10.12d)
ω
−1 R R F,X ,M
L X ,M (ω) =< ( )− √ > X :D R AI N , G AT E (10.12e)
Y21,X ,M ω

The impedance parameters(Z) related to the source printed board connector via, are:
√  √ 
Z V I A = RV I A,DC + ω RV I A,R F + j ωL V I A (ω) + ω RV I A,R F (10.12f)

The via inductance obtained using linear regression is:

Z V I A − RV I A,R F
L V I A (ω) = (10.12g)
ω
The impedance matrix(Z) corresponding to the air barrier between the drain, gate
manifolds and the physical boundary of the HEMT is:

Z = [Z G + Z S Z S Z S Z D + Z S ] (10.12h)

where each impedance has a real and imaginary component as:

1
Z X = R X + jΩL X + X = D R AI N , G AT E, S OU RC E (10.12i)
j ωC X
Linear regression, applied to the source impedance Z S gives:
1
R S =< ℜZ S > ω Z S = ω2 L S − (10.12j)
CS
Substituting for the real and imaginary parts of the source impedance in the the
other impedance terms of 10.12 l, followed by careful linear regression on experimen-
tal impedance data allows the extraction of the real and imaginary parts of the other two
impedances.
Defining the intermediate parameter CC O M P and a subsequent ∆ − Y transformation
enables the drain, gate and source capacitances for the air barrier network to be denoted
as:
10.7 Transistor Noise Factor|Figure Measurement with Laboratory Equipment 163

CC O M P
CC O M P = C D C S + C G C S + C D C G C DS = C DG
CG
CC O M P CC O M P
= CG S = (10.12k)
CS CD
The AMS-CMC GaN HEMT model examined at the end of Chap. 7 includes both
high and low frequency noise models. The low frequency (flicker) noise model probability
spectral density (PSD) function is (10.12 l):
2 KLP ( f)
I DS 1
Si,F L I C K E R = 2
CG AT E
   
1 1  2 
C G AT E Γ1 VT H E R M AL − + A A + B B + 0.5Γ3 N D − n S
2
nD nA (10.12l)
 
nD
A A = (Γ1 + C G AT E Γ2 VT H E R M AL )ln
nS
B B = (Γ2 + C G AT E VT H E R M AL )(n S − n D )

where P1 ( f ) = f EkFBLT2 W E F, Γ1 , Γ2 , Γ3 , n D , n S are curve fitting parameters and

drain, source charge carrier densities respectively.
Similarly, the high frequency PSD is:
⎛ ⎞2
4k B T ⎝ qC G AT E μe f f ective W ⎠
Si,T H E R M AL = /
I DS L 2E F F 1 + θ S2 AT (ψ D − ψ S )2
   
 3  1
Vgo Vgo (ψ D − ψ S ) + ψ D − ψ S3 −1 (10.12m)
Vgo

10.7 Transistor Noise Factor|Figure Measurement with Laboratory

Equipment

Transistor noise factor, or its more commonly used variation noise figure [55–72] is the
key noise performance metric—the noise factor|figure concept can be applied to a cir-
cuit, sub-circuit or a transistor. While the discussions in the previous sections elaborate
on the analytical models and expressions for estimating the noise probability spectral den-
sities of various transistor noise mechanisms, they cannot be used directly. Therefore the
noise factor|figure, which can be measured accurately with sensitive test equipment is so
important.
The basic definition of noise factor is the ratio of signal to noise power at the input
divided by the signal to noise power at the output. So the noise factor of a two port
network is the decrease|degradation in the signal-to-noise ratio as the signal traverses
164 10 Noise in Semiconductor Devices

the network from the input to the output port—the concept is inapplicable for one port
networks (e.g., oscillator). A real world transistor, unlike an ideal device, adds some extra
internal noise and degrades the signal-to-noise ratio. A low noise factor means that very
little noise is added by the two port network. Noise factor is independent of the modulation
format and of the fidelity of modulators and demodulators.

• Noise factor is different from gain. Once noise is added to the signal, subsequent gain
amplifies signal and noise together and does not change the signal-to-noise ratio.
• The degradation in a two port network’s signal-to-noise ratio is dependent on the
temperature of the input signal source that excites the network—the source thermal
noise:
SI SI
NI NI G N I + N AD D N AD D + Gk B TO ∆ f
F= = = = (10.13a)
SO G SI G NI Gk B TO ∆ f
NO N AD D +G S I

where G, S I , S O , N I , N O are respectively the two port network gain, input|output

signal and noise, G, N AD D , TO = 290K are the gain, added noise and reference
temperature respectively.

• The thermal noise power spectral probability distribution is k B TO ∆ f where TO is a

reference temperature (290 K) and ∆ f is the bandwidth.
• Noise factor is a function of frequency, but independent of bandwidth (so long as the
measurement bandwidth is sufficiently narrow to resolve variations with frequency).
• The linearized form of the noise factor is the noise figure
• For a cascaded, interconnected n stage network, for which each stage is a two port
network,the total noise factor is:

F2 − 1 F3 − 1 Fn − 1
F = F1 + + + ... + (10.13b)
G1 G1G2 G 1 G 2 . . . G n−1

where Fi G i are the noise factor and gain of the ith stage.
Device gain is a key parameter in noise calculations. When an input power of k B TO ∆ f
is used in these calculations, it is the maximum that can be delivered to a matched load.
A large input impedance mismatch decreases the actual power delivered to the device. If
the gain of the device is defined as the ratio of the actual power delivered to the load to
the maximum power available from the source, the mismatch loss present at the input can
be neglected, as it is included in the gain definition. This definition of gain is transducer
gain, G T When cascading devices, mismatch errors arise if the input impedance of the
device differs from the load impedance. So the total gain of a cascaded series of devices
does not equal the product of the gains.
10.7 Transistor Noise Factor|Figure Measurement with Laboratory Equipment 165

Available gain G A is routinely quoted as a transistor parameter, it is the gain that

results when a given source admittance Y S drives the device and the output is matched
to the load. It is very common to use insertion gain,G I or the forward transmission
2 , is the quantity specified or measured for gain in a 50 Ω system. If the
coefficient,S21
measurement system has low reflection coefficients and the device has a good output
match the cascade noise figure equation given earlier gives accurate results. With poor
output match or measurement system with significant mismatch errors results in an error
between the actual system and calculated performance characteristics. e.g.„ the output
impedance of the first stage is different from the 50 Ω source impedance used with a
second stage characterized for noise figure, the noise generated in the second stage could
be altered. Fortunately, the second stage noise contribution is reduced by the first stage
gain so that errors involving the second stage can be ignored. The complete analysis of
mismatch effects in noise calculations is very complicated requiring understanding the
dependence of noise figure on source impedance.
Noise figure is a simplified model of the actual noise generated in a transistor, which
can have multiple noise contributors: thermal noise, shot noise, generation-recombination
noise and partition noise. The effect of source impedance on these noise generation pro-
cesses is very complex. The noise figure that results from a measurement is influenced
by the match of the noise source with the match of the measuring instrument; the noise
source is the source impedance for the transistor, which itself is the source impedance
for the measuring instrument. The actual noise figure performance of the transistor will
be determined by the match of other system components in the circuit in which it is a part
of.
Designing low noise RF|microwave amplifiers requires tradeoffs between the gain of a
stage and its corresponding noise figure—requiring knowledge of how the RF transistor’s
gain and noise figure varies as a function of the source impedance|admittance. The mini-
mum noise figure does not have to occur at either the system impedance, or at the conjugate
match impedance that maximizes gain.

10.7.1 Transistor Noise Parameters [55–72]

The effect of impedance mismatch is fully understood only with two characterizations
of the device under test- noise figure measurement and gain measurement. S-parameter
measurement only enables calculation of the available gain in a perfectly matched device.
Optimum noise figure estimation requires a special tuner—for which noise factor—source
impedance dependency is:
( )
4R N O I S E |Γ O P T − Γ S RC |2
F = FM I N +   (10.13c)
Z0 |1 + Γ O P T |2 1 − |Γ S RC |2
166 10 Noise in Semiconductor Devices

where Γ S RC is the source reflection coefficient.

The three transistor noise parameters are FM I N , R N O I S E , Γ O P .
The available gain of the transistor when driven by a specified source impedance, can
be calculated from its S-parameters measured with a network analyzer.
 
|S11 |2 1 − |Γ S RC |2
GA =  I I2  (10.13d)
I 12 S21 Γ S RC I
|1 − S11 Γ S RC |2 1 − IS22 + S1−S 11 Γ S RC
I

When the source reflection coefficient Γ S RC is plotted on a Smith chart corresponding

to a set of fixed gains, gain circles are created—a convenient format to display the relation
between source impedance and gain.

10.7.2 Effect of Bandwidth

Noise factor|figure is independent of bandwidth. The key assumption behind noise mea-
surements is that the device under test has an amplitude-versus-frequency characteristic that
is constant over the measurement bandwidth. So noise measurement bandwidth should
be less than the device bandwidth. State-of-art measurement|test equipment can tackle
this issue.
The bandwidth defining system sub-circuits e.g., a receiver, will be the intermediate
frequency or the detector will have a bandwidth much narrower than the RF circuits. Only
then noise factor|figure is a valid parameter to characterize the noise performance of the
RF circuitry. Otherwise, noise figure may still be used as a figure of merit for compar-
isons. Complete system signal-to-noise (SNR) ratio will require the input bandwidth as a
parameter.

10.7.3 Noise Figure Measurement—Linearity, Noise Equivalent

Temperature

Noise factor|figure measurements depend on a key property of linear two-port networks,

noise linearity. The noise power out of a device is linearly dependent on the input noise
power or temperature. Using the slope (of the output power versus source temperature
curve) and a reference point, the output power corresponding to a noiseless input power
(intercept of curve on the power axis), can be estimated. Then the noise figure or effective
input noise temperature can be calculated. To ensure noise measurements linearity, all
automatic gain control (AGC) circuitry (working in a feedback loop) must be deactivated.
Often effective input noise temperature, TE Q , is used to quantify the noise performance
of a device instead of the noise factor|figure, (NF). TE Q is the equivalent temperature of
a source impedance into a perfect (noise-free) device that would produce the same added
10.7 Transistor Noise Factor|Figure Measurement with Laboratory Equipment 167

noise N AD D —defined as:

N AD D
TE Q = = TO (F − 1) (10.13f)
k B G∆ f
Noise factor|figure measurement requires a noise source with a calibrated output noise
level, denoted as excess noise ratio (ENR units dB). A noise source is a circuit that
provides two known levels of noise, e.g., widely used reverse biased low-capacitance
diode driven into avalanche breakdown with a constant current. A 0 dB ENR noise source
produces a 290 K temperature change between its on and off states. ENR is not the “on”
noise relative to k B T ∆ f k B T ∆ f
 
TH O T − TC O L D
E N R(d B) = 10log (10.13g)
TO

10.7.4 Y Factor Method for Noise Factor|Figure Measurement

The Y-Factor method is the basic noise factor|figure measurement scheme (auto-
mated|manual) performed internally in a noise figure analyzer. Using a noise source,
this method allows the determination of the internal noise in the device under test (e.g.,
transistor) and the noise factor|figure or effective input noise temperature.
With a noise source connected to the device under test, the output power is mea-
sured with the noise source on and the noise source off (N O N N O F F ). The ratio of these
two powers is the Y-factor. Output power measurement device could be a power meter,
spectrum analyzer, or special internal power detector inside noise figure meters|analyzers.
The relative level accuracy is important. State-of-art noise figure analyzers have very lin-
ear internal power detectors, that can measure input power level changes very accurately.
The absolute power level accuracy of the measuring device is not important since a ratio
is measured ( Y = NNOOFNF ).
The calibrated ENR of the noise source is a reference level for input noise. So an
equation for the noise added by the device under test itself (internal noise), N AD D can
be derived. State-of-art noise figure analyzers determine this internal noise by modulating
the noise source between the on and off states and applying internal calculations.
 
ENR
N AD D = G 1 k B TO ∆ f −1 (10.13h)
Y −1

An expression for the total “system noise” factor FSY S can be estimated, based on
these estimated noise parameters. System noise factor includes the noise contribution of
each of the individual sub-circuits of the system. The noise generated in the measuring
instrument is included as a second stage contribution. If the device under test gain is large
168 10 Noise in Semiconductor Devices

(G 1 >> G 2 ), the noise contribution from this second stage will be small. The second stage
contribution can be removed from the calculation of noise figure if the noise figure of the
second stage and the gain of the device under test is known. The device gain is not needed
to find the system noise factor.

ENR E N R − Y TTCOO−1
LD
ENR TC O L D
TO
FSY S = FSY S = FSY S = (10.13ijk)
Y −1 Y −1 Y −1
When the noise figure is much larger than the ENR, the device noise masks the noise
source output. So the Y-factor is approximately 1. Accurate measurement of small ratios is
difficult. The Y-factor method is not used when the noise figure is more than 10 dB above
the ENR of the noise source, depending on the measurement. When the noise source cold
temperature is not 290 K, the system noise factor expression is modified to 10.13 j.
This expression is inapplicable for semiconductor noise sources, as the hot and and
cold temperatures are interlinked. Since the physical noise source is at the cold temper-
ature TC O L D the internal attenuator noise due to TC O L D is added both when the noise
source is on and off—effectively the noise change between the on and off state remains
constant (TH O T − TC O L D ). This is most important for low ENR noise sources when
TH O T < 10TC O L D . An alternate equation is used to correct for this case 10.13 k.

10.7.5 Signal Generator Twice Power Method

In absence of accurate noise sources and devices with very high noise figure such that
the Y factors can be very small and difficult to accurately measure, the signal generator
twice power method is used. First, the output power is measured with the device input
terminated with a load at a temperature of approximately 290 K. Then a signal generator
is connected, providing a signal within the measurement bandwidth. The generator output
power is adjusted to produce a 3 dB increase in the output power. If the generator power
level and measurement bandwidth are known the noise factor is calculated easily. The
gain of the device under test gain is not required.
PG E N E R AT O R
FSY S = (10.13l)
k B TO ∆ f
The results of this measurement are not very accurate. The noise bandwidth of the
power-measuring device must be known. Noise bandwidth, ∆ f , is a calculated equiva-
lent bandwidth, with a rectangular spectral shape with the same gain bandwidth product as
the actual filter shape. The output power must be measured on a device that measures true
power. This is essential, as a combination of noise and a CW signal is present. Thermal
based power meters measure true power very accurately but often require amplification
to read a low noise level and will require a bandwidth-defining filter. Spectrum analyzers
10.7 Transistor Noise Factor|Figure Measurement with Laboratory Equipment 169

have good sensitivity and a well-defined bandwidth but the detector may respond dif-
ferently to CW signals and noise. Absolute level accuracy is not needed in the power
detector since a ratio is being measured.

10.7.6 The Direct Noise Measurement Method

This scheme for noise factor measurement of high noise figure devices, involves device output
power measurement with an input termination at a temperature of approximately 290 K.
If the gain of the device and noise bandwidth of the measurement system is known, the
noise factor can be estimated with a very sensitive power meter. In addition, the gain of
the device under test must be known and the power detector must have absolute level
accuracy.
N0
FSY S = (10.13m)
Gk B TO ∆ f
Each of the noise factor estimation schemes examined so far measure the total system
noise factor, starting with the noise source and ending with the measurement system.
However the goal is to measure the noise factor of the device under test only. From the
cascade noise factor equation it is clear that if the device under test gain is large, the
contribution of the measurement system will be small, and can be ignored for preliminary
estimates. The noise figure of a high gain device under test can be directly measured
with the previously discussed methods. When a low gain device is tested, or the highest
possible accuracy is needed, a correction is required, provided the gain of the device under
test and the noise figure of the system are known.
F2 − 1 F2 − 1
FSY S = F1 + F1 = FSY S − (10.13n)
G1 G1
A simple sequence of measurements are used to achieve this goal.

• The noise source is connected to the measurement instrument, The noise power levels
corresponding to the noise source switched on|off are measured. These measured values
N O N , N O F F are used to calculate the system noise factor FSY S with the Y factor
method.
• The device to be tested is now added to the measurement test bench along with
the noise source. The noise power levels with the noise source switched on and off
(N O N ,DU T , N O F F,DU T ) are measured. The gain of the device under test is:

N O N ,DU T − N O F F,DU T
G DU T =
NO N − NO F F
170 10 Noise in Semiconductor Devices

• The system noise factor is then computed from these measured noise power values,
and then the device noise factor is then easily computed.

Noise is a series of random electrical impulses. Any noise measurement device|system

estimates the mean noise level at the output of the device. The actual noise figure of
the device under test is calculated using these measured noise power levels, with some
correction terms. As the time required to calculate the true mean noise level is infinite,
averaging is performed over some finite time period. The difference between the measured
average and the true mean will fluctuate and give rise to a repeatability error.
1
For small variations, the deviation is proportional to √<t> so that longer averaging
times produce better averages. The average includes more events and so is closer to the
1
true mean. The variation is also proportional to √<∆ f>
. Larger measurement bandwidths
produce a better average because there are more noise events per unit of time in a large
bandwidth, thereby improving the average value. Noise figure must be measured with
the widest possible bandwidth narrower than that of the device under test.

10.7.7 Noise Figure Measurement Equipment

The noise figure analyzer is designed to measure noise figure using the Y factor method.
It consists of a receiver with an accurate power detector and a circuit to power the noise
source. It allows ENR entry and displays the calculated noise figure value corresponding
to the frequency it is tuned to, along with gain.
The versatile signal|spectrum analyzer can be used to measure noise figure, using any
of the methods examined previously. They are ideal for measuring high noise figure
devices using the signal generator or direct power measurement method. The variable
resolution bandwidths allow measurement of narrow band devices.
Like a spectrum analyzer, a network analyzer is also very flexible test equipment that
can perform a variety of tasks, e.g., noise figure measurement, gain analysis, in addition
to their primary task of network analysis.
As a network analyzer uses the same internal signal receiver for network analysis
as well as for noise figure measurement, there are minor performance limits. Often the
receiver is a double side band (DSB) type, where noise figure is measured at two frequen-
cies and an internal correction is applied. When a wide bandwidth measurement is made,
an error may be introduced if the analyzer noise figure or gain is not constant over this
frequency range. When narrow bandwidth measurement is used to measure narrow-band
devices, the unused frequency spectrum between the upper and lower side-band does not
contribute to the measurement and a longer measurement time is needed to reduce jitter.
Network analyzers are designed to primarily measure the S-parameters of the device
under test. S-parameter data can reduce noise figure measurement uncertainty by offer-
ing mismatch correction, providing a more accurate gain measurement of the device so
10.7 Transistor Noise Factor|Figure Measurement with Laboratory Equipment 171

that the second stage noise contribution can be subtracted with more precision. But mis-
match also affects the noise generation in the second stage which cannot be corrected for
without knowing the noise parameters of the device. Likewise, if there is a impedance
mismatch between the noise source and device under test input, appropriate corrections
are essential. Noise parameter measurements require a tuner and additional firmware.
The resulting measurement system can be complex and expensive. Error correction in a
network analyzer is for gain measurements and calculation of available gain.
A complete noise parameter measurement requires a test set along with software, a
vector network analyzer and a noise analyzer to make a series of measurements, to mea-
sure the noise parameters of a semiconductor device. The estimated noise parameters can
be used to calculate the minimum device noise figure, the optimum source impedance,
and the effect of source impedance on noise figure. The test set has an adjustable
tuner to present various source impedances to the device under test. Bias is provided
to semiconductor devices that may be tested. A noise source is included for noise figure
measurement,. at different source impedances. The corresponding source impedances are
measured with the network analyzer. From this data, the complete noise parameters of the
device can be calculated.
The complete device S-parameters are also measured so that gain parameters can also
be determined. Complete noise figure measurement is complicated and time consuming
process, since a number of accurate measurements have to be made.
Power meters and true RMS voltmeters can be used to measure noise figure with any
of the methods described earlier. Some computer|manual calculations are needed. Being
broadband devices, they need a filter to limit their bandwidth to be narrower than that of
the device under test. Such a filter will be fixed in frequency and allow measurements
only at this frequency. Power meters are often used to measure receiver noise figures
where the receiver has a fixed IF frequency and much gain. The sensitivity of power
meters and voltmeters is usually poor but the receiver may provide enough gain to make
measurements. If additional gain is added ahead of a power meter to increase sensitivity,
temperature drift and oscillations must be avoided.

10.7.8 Laboratory Test Bench for Bijunction Transistor Input Noise

Measurement

The mean-square equivalent noise equivalent input noise of a resistively loaded BJT
amplifier (with zero small-signal impedance from both base—ground and emitter—
ground) is measured over a narrow frequency band ∆f centered at frequency f is expressed
as:
172 10 Noise in Semiconductor Devices

(     )
IC r x2 Kf rx VT H E R M AL 2
v inputnoise
2
= 4k B T r x + 2q + + 2q IC + ∆f
β f β IC
(10.14a)

where, r x is the base spreading resistance (Ohms), β is the small-signal current gain
(dimensionless), IC is the DC collector current, I B is the DC base current, K f is the
flicker noise-coefficient, and f is the frequency at which the mean-square noise voltage is
measured. If the noise measurement is made at a frequency f where the flicker noise can
be ignored, the expression for the mean-square equivalent input noise becomes:
  2  
r rx VT H E R M AL
v inputnoise
2
= 4k B T r x + 2q IC x + + ∆f (10.14b)
β β IC

Accurate measurement of the base spreading resistance requires the circuit as shown
in Fig. 10.5. Assuming that the operational amplifier is ideal and that the thermal noise
in the feedback resistor, R F can be ignored, the output noise is:
  ( )2
R F1 2 1
v inputnoise
2
= 1+ rx VT H E R M AL
β +
R
IC
⎛ ⎞
 
⎜ K f Ib 2q IC ⎟
R 2F ∆ f ⎝4k B T r x + r x2 2q Ib + + 2⎠
(10.14c)
f rx VT H E R M AL
β + IC

If the measurement is made at a large frequency, the flicker noise component can be
neglected. The base spreading resistance satisfies:
    
1 A 2 AV T H E R M AL
− k B IC ∆ f r x2 + − 4k B T ∆ f r x2
β β β IC
 2
VT H E R M AL v noiseout pur
2
+A =0 A= − 2q IC ∆ f (10.14d)
IC A21 R 2F

Thus 10.14d is solved to determine the base spreading resistance using the measured
value of the output noise. Only the positive solution for the base spreading resistance
is used since the negative value has no physical meaning. A more exact solution may
be obtained by directly solving 10.14c. The coupling capacitor C1 prevents DC current
from the transistor from flowing into the feedback resistor while forcing the entire signal
component of the collector current to flow though this feedback resistor. The op amp
inverting terminal is at a virtual ground so that the signal component of the collector
voltage is zero which eliminates the Early effect. The capacitor C2 is a bypass capacitor
which places the emitter at signal ground. Both these capacitors are electrolytic, chosen
to be large so that the low frequency noise spectra is not altered.
10.7 Transistor Noise Factor|Figure Measurement with Laboratory Equipment 173

10.7.9 MOSFET Noise Sources—Thermal, Flicker

The common noise sources in a MOSFET are:

• channel thermal noise

• 1/f noise
• resistive polysilicon gate material noise
• distributed substrate resistance noise
• shot noise from the leakage current of the drain source reverse diodes

Under normal operating conditions, only the flicker and thermal noises are relevant. Other
noise sources are relevant in low temperature operating conditions.
A MOSFET in normal working conditions has an inverse resistive channel between the
drain and the source. Applying a gate voltage induces minority carriers to collect and form
the conducting channel between the drain and the source. This conducting layer is at the
interface of the gate oxide and the substrate. With zero drain source voltage, the channel
is a homogeneous resistor. The noise in the channel is:

4k B T μ2 W 2
i 2D,T H N = 4k B TO V DS = 0 i 2D,T H N = Q 2n (V (x))d V 0V V DS V DS / = 0
I DS L 2 (10.15a)
 
Q n (x) = C O X I D E VG S − VT H R S H (x) − V (x)

Assuming that the effect of position dependence of both the channel potential V(x)
and the threshold voltage is small, the above equation can be integrated to give:
( )
8C O X I D E k B T W 3VDS (VG S − VT H RS H ) − 3(VG S − VT H RS H )2 − VDS
2
i D,T H N =
2
3L 2(VG S − VT H RS H ) − VDS
(10.15b)

A MOSFET has three regions of operation linear, saturation point and saturation
region, defined as: VDS < VG S − VT H RS H VDS = VG S − VT H RS H VDS > VG S − VT H RS H .
At the saturation point, 10.15b is simplified to:

8C O X I D E k B T W (VG S − VT H RS H ) 8gm k B T
HN = =
2
i D,T (10.15c)
3L 3
In the saturation region 10.15c cannot be used. However, experimentally it has been
found that 10.15c is a good approximation, as long as the device shows a good saturation.
This is because the cut-off region near the drain is much smaller then the resistive reverse
channel which is responsible for the noise. This expression predicts the thermal noise in
the channel without the substrate effect. In practice the thermal noise is higher. This is a
result of thermal noise depending on the channel potential V(x). The integral in Eq. 10.15a
is now hard to calculate, so that:
174 10 Noise in Semiconductor Devices

H N = 4k B γ gm T
2
i D,T (10.15d)

The factor γ is a complex function of the basic transistor parameters and bias con-
ditions, evaluated using numerical analysis of experimental data. For modern CMOS
processes with oxide thickness in the order of 50 nm or less, and with a lower substrate
doping of about 1013 − 1016 cm −3 the factor γ is between 0.67 and 1.
The current noise in the channel also generates noise in the gate through the gate-
channel capacitance. The gate noise is due to the capacitative coupling frequency
depending. The gate noise is approximately:

16π 2 f 2 k B T 4 f 2 k B gm T gm
HN ≈ ≈ fT ≈
2
i G,T (10.15e)
5gm f T2 2πC G S

Flicker or 1/f noise is observed in all kinds of devices, from homogeneous metal film
resistors to semiconductor devices and even in chemical concentration cells. Because 1/
f noise is spread over the components, there is a misconception that there is fundamen-
tal physical mechanism is behind it. Experimental evidence suggests that several internal
physical mechanisms combine to generate 1/f noise, with the MOS transistor having the
highest 1/f noise of all active semiconductors, due to its surface conduction mechanism.
Although there are several physical models competing to explain the 1/f noise in a MOS-
FET, they are all based on Hooge’s empirical mobility fluctuation model and the carrier
density|number fluctuation model first introduced by McWhorter.
In the Mobility Fluctuation model the 1/f noise is referred to as ∆μ-1/f noise. The
model is described by the Hooge empirical equation (only for homogeneous junction
devices):

i F2 L I C K E R αI
2
= (10.15f)
I SC fN

where αl is Hooge’s 1/f noise parameter, N is the number of free carriers and I SC is the
short circuit current. Experimental data shows that this expression is valid for a number
of common semiconductor devices, with αl ≈ 2x10−3 . Deriving this expression from fun-
damental principles results in expressions that do not predict values for the flicker noise
current accurately. The discrepancies arise as the electron mobility in a particular region
of MOSFET operation is an effective value (Mathieson’s rule) controlled by the various
scattering processes occurring in the device at the time of measurement. The Mobility
Fluctuation model 1/f noise voltage spectrum is:

α I μ f q(VG S − VT )
v 2F L I C K E R,M O B I L I T Y F LU C T U AT I O N = (10.15g)
2C O X I D E f μe f f ecti ve L W
References 175

The Number Fluctuation model denotes the 1/f flicker noise as ∆n-1/f noise. The
fluctuation in the number of mobile carriers is caused by the random trapping and de-
trapping of the mobile carriers. The traps are located at the silicon–silicon dioxide interface
within the gate oxide. This causes a signal with a Lorentzian generation-recombination
spectrum. Superposition or a large number of these signals with the proper time constant
result in a 1/f-noise spectrum.
According to this model, the ∆n-1/f noise is proportional to the effective trap density
near the quasi-Fermi level of the inverse carriers, as verified by a large number of experi-
ments. This model explains the 1/f noise in the MOSFET’s weak inversion region, where
the relative 1/f noise current has a plateau. At the silicon–silicon dioxide interface in the
gate oxide (oxide traps) additional energy states exist. These states and traps communi-
cate randomly with the free charges in the channel. The flicker noise voltage spectrum,
as per the Number Fluctuation model is:

KF Kf
v 2F L I C K E R,NU M B E R F LU C T AU T I O N = =
2
2C O X I DE f μL W 2C 2
O X I DE f LW
(10.15h)

where K f is an experimentally determined parameter. The discrepancies between the

mobility fluctuation and number fluctuation models are:

• The Mobility Fluctuation model predicts that the flicker noise spectrum is directly
proportional to DC voltages (VG S − VT H RS H ) but the Number Fluctuation flicker noise
spectrum is independent of DC voltages.
• The Mobility Fluctuation model predicts that the flicker noise spectrum is inversely
proportional to oxide capacitance, while the Number Fluctuation model states that the
flicker noise spectrum is inversely proportional to the square of the oxide capacitance.

This does not mean that both or one of the model(s) are incorrect—actual flicker noise is
a result of a combination of these two mechanisms.

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Semiconductor Device Manufacturing
Technologies
11

11.1 Creating High Vacuum

This discussion starts with the standardized vacuum units, followed description of how to
create ultra high vacuum conditions [1–5].

11.1.1 Vacuum Units

The Pascal (named after the French mathematician|physicist Blaise Pascal) is the official
SI unit for vacuum pressure—widely used in physical sciences. One Pascal is the force
of one Newton per square meter acting perpendicular to a surface. It is easily converted
to other common vacuum units.
1 Pa = 0.01 mbar = 0.0075 Torr = 7.5 micron(mTorr) = 0.0075 mm Hg = 0.000145
PSI
Another common metric vacuum unit is millibar (mbar). Millibar, related to the bar
pressure unit, originated as a pressure measurement unit in meteorology. One mbar is
equal to 100 Pa or one hPa(Hectopascal). It is related to the common pressure units as:
1 mbar = 100 Pascal = 1 hPa = 0.75 Torr = 750.0 mTorr = 0.75 mm Hg = 0.145
PSI One Torr is the pressure equivalent of 1 mm of mercury at 0 Celsius.

11.1.2 How to Create Vacuum

Fore vacuum pumps extract air from the chamber they are connected, to the atmospheric
pressure. Also, a fore vacuum pump must be able to support secondary pumps. There are
two types of fore vacuum pumps:

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 181
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_11
182 11 Semiconductor Device Manufacturing Technologies

1. Dry running diaphragm, scroll and screw pumps.

2. Oil sealed rotary vane pumps.

The multistage Roots vacuum pumps are used widely to create ultra low vacuum
in semiconductor processing equipment. The single stage Roots vacuum pump is in
Fig. 11.1a.
Versatile multistage Roots pumps are dry vacuum pumps used in low, medium, high
and ultra-high vacuum systems to produce “dry” conditions. The single-stage Roots pump
is used as a booster pump in combination with several types of fore pumps (e.g., screw,
liquid ring pumps and rotary vane pumps) to boost pumping speeds. Multistage Roots
pumps do not need any fore pump and can operate from atmospheric pressure. A mul-
tistage Roots pump can consist of up to eight stages with sets of rotors on a shared
shaft. Roots pumps are suitable where a dry and clean atmosphere is essential—ideal for
interiors of ultra low vacuum semiconductor processing equipment chambers.
Each single stage Roots pump has two counter-rotating interconnected lobed rotors
within a stator housing or casing. Gas enters through an inlet flange located perpendicular
to the rotors and is then “isolated” between the rapidly counterrotating rotors and the
stator. The compressed gas is then expelled via the exhaust port.

11.1.3 How to Measure Vacuum

Vacuum levels referenced in semiconductor industry processes are classified as below:

Atmospheric 760 T orr Low V acuum 760 − 25 T orr

Medium V acuum 25 − 10−3 T orr H igh V acuum 10−3 − 10−9 T orr
Ultra H igh V acuum 10−9 − 10−12 T orr E xtr eme
H igh V acuum < 10−12 T orr

So special vacuum gauges are required to measure vacuum levels, each optimized to
a specific vacuum range. With reference to the ultra clean environment used in semicon-
ductor device manufacture, only those vacuum level measurement devices that operate in
dry conditions are allowed. The first is the capacitance manometer gauge (Fig. 11.1b).
The capacitance manometer gauge measures vacuum levels from atmospheric pressure
to 10-5 Torr depending on the given sensor applied. As seen from Fig. 11.1b the key
component of this gauge is the diaphragm. A thin diaphragm will distort easily at a low input
pressure, while a thicker one will not respond to that low pressure, since the capacitance value
of a parallel plate capacitor is inversely proportional to the plate separation. A capacitance
sensor operates by measuring the change in electrical capacitance from the distortion of
a sensing diaphragm compared to some fixed capacitance electrodes. In some designs
11.1 Creating High Vacuum 183

Fig. 11.1 a Single stage Roots (a)

pump. b Capacitive
manometer. c Pirani gauge.
d Thermocouple vacuum
gauge. e Hot cathode vacuum
gauge. f Inverted magnetron
cold cathode ionization gauge

(b)

(c)

(d)

(e)

(f)
184 11 Semiconductor Device Manufacturing Technologies

a variable DC voltage is applied to keep the sensor’s Wheatstone bridge in a balanced

condition. The amount of voltage required is directly related to the pressure.
The Pirani gauge (Fig. 11.1c) is a thermal conductivity gauge used to measure pres-
sure in a vacuum chamber. The gauge is able to give a pressure reading due to a heated
metal filament suspended in the vacuum chamber. Gas molecules in the system collide
with the wire allowing it to emit heat and cool. As the vacuum is pumped down, there
are fewer gas molecules to collide with the wire and the wire heats up. The wire’s inter-
nal electrical resistance increases and a circuit attached to the wire detects the change
in resistance. With appropriate calibration, the circuit can directly correlate the amount
of resistance to the pressure in the vacuum chamber. The Pirani gauge is used to mea-
sure pressures between 0.5 to 10-4 Torr. Each device needs calibration to obtain accurate
readings depending on the thermal conductivity and the heat capacity of the gas.
Pirani gauges can be constant current|resistance. The constant current gauge has a
power supply to provide a fixed amount of energy to the metal filament. A current change
implies a corresponding resistance change. The varied resistance is proportional to the
pressure in the vacuum. The constant resistance gauge has a power supply which varies
the current based on the constant resistance. The variation in the current is proportional
to the pressure in the vacuum.
The thermocouple gauge (Fig. 11.1d) is very similar to a Pirani gauge, which has
an internal heater adjacent to the thermocouple. The voltage across the thermocouple is
measured, and calibrated to correspond to the chamber pressure.
Ultra high vacuum levels can only be measured with some form of ionization gauge.
These come in two varieties, cold|hot cathode and measure pressures in the range 10–2
10–10 Torr. They sense pressure indirectly by measuring the electrical ionic current pro-
duced when gas is bombarded with electrons. Decreasing pressure decreases the available
number of ions for the electrical ionic current—i.e., decreasing ionic current means higher
vacuum.
The hot cathode ionization gauge (Fig. 11.1e) has three electrodes acting as a triode,
where the cathode is the filament. The three electrodes are a collector, plate, a filament and
a grid. Electrons emitted from the filament move to and fro around the grid before finally
entering the grid. During these movements, some electrons collide with a gas molecule,
ionizing it, to form a ion|electron pair. The number of these ions is proportional to the
gas molecule density multiplied by the electron current emitted from the filament, and
these ions enter into the collector to form the ion current. Since the gas molecule density
is proportional to the pressure, the pressure is estimated by measuring the ion current.
There are two types of cold cathode ionization gauges—the Penning gauge and the
inverted magnetron, also known as the redhead gauge. The inverted magnetron (Fig. 11.1f)
exploits the physical fact that ion production rate by a stream of electrons in a vacuum
system is dependent on pressure and the ionization probability of the residual gas.
There are two parallel connected cathodes. An anode is placed midway between them.
The cathodes are metal plates or shaped metal bosses. The anode is a loop of flattened
11.2 Photolithography 185

metal wire, the plane of which is parallel to that of the cathode. A high voltage is applied
between the anode and cathode halves. A external permanent magnet applies a magnetic
field between cathode halves and the anode. Electrons emitted from the cathode travel
in helical paths, eventually reaching the anode, thus increasing the amount of ionization
occurring within the gauge. Normally the anode is operated at about 2kV, giving rise
to a direct current caused by the positive ions arriving at the cathode. The pressure is
proportional to the magnitude of the direct current produced. The pressure range covered
by this gauge is from as low as 10-7 Torr. The simple rugged design makes this vacuum
gauge ideal for a number of common industrial systems.

11.2 Photolithography

Photography, or “writing with light” is one of the key processing steps in semiconductor
device fabrication. Unlike all other semiconductor device manufacturing technologies to
be examined in the next several sections, photolithograpy and wet etching does not need
any vacuum conditions. For a long time, state-of-art semiconductor devices were planar.
For example, the drain and source regions of a field effect transistor must be at the right
locations, with respect to the gate region. Photolithography enables accurate alignment of
these regions, using appropriately designed masks.
Photolithography is the process of transferring geometric shapes and patterns
from a mask, to a smooth, clean surface. It uses a ultraviolet light to image the
mask on to a surface coated with chemicals whose molecular structure changes (de-
polymerize|polymerize) when irradiated with ultraviolet light. Figure 11.2a shows a
general photolithography system.
Photolothography consists of the following steps.

• Surface cleaning
• Spin coating with photoresist
• Baking at low temperature to dry|harden the deposited phororesist
• Mask alignment, exposure and development
• Hard baking and post process exposure.

Successfully imprinting a pattern on the wafer with photolithography involves tightly

controlling the resolution tolerances|limits for the final imprinted pattern. With refer-
ence to Fig. 11.2a, smaller distances on the illuminated mask translate to large distances
on the projection plane (projection pupil and lens). In standard optical microscopes, the
detector sees the light in the far field region. So, connecting the reciprocal wavevector
space (k-space) with the real space:
186 11 Semiconductor Device Manufacturing Technologies

(a)

(b)

Fig. 11.2 a General ultraviolet light based photolithography system. a Photolithography mask,
wafer alignment

/ I I
K 2 = ω2 μ0 ∊ = K x2 + K y2 + K z2 K x2 + K y2 < nω
C ⇒ I K par ,max I = 2π n
λ (11.1a)
λ λ E F F EC T I V E
Resolving power = 2n = 2 = Di f f ration Limit

where n is the lens material refractive index. In a real optical system, the spatial cutoff
frequency is controlled by the size of the lens, quantitatively described by its numerical
aperture NA. With reference to Fig. 11.2a,
k par ,max
N umerical Aper tur e (N A) = n sin(α) = sin(α) ⇒ k par ,max
k
2π N A λ
= Resolving power = (11.1b)
λ 2 NA
The photoresist is applied using a spinning chuck (3000–6000 rpm) with the wafer
held in position by applying a vacuum from underneath. The final photoresist thickness
(1–2 μm) is controlled by its viscosity and the applied rotational speed. The spinning
11.2 Photolithography 187

process introduces unwanted nanometer scale striations, edge beads etc., The photoresist
coated wafer is then baked to evaporate the photoresist solvent, harden the phororesist and
minimize the nanometer scale photoresist surface imperfections. Subsequent baking using
hot plate ensures fast, uniform photoresist solvent evaporation. Two types of photoresist
are used:

Positive photoresist:
Exposure to ultraviolet light de-polymerizes (breaks up long chain molecules to individual
ones) the exposed photoresist regions. The de-polymerized photoresiat is soluble in the
photoresist developer. These exposed areas are subsequently washed away, exposing the
underlying material. Unexposed areas of the photoresist are insoluble to the photoresist
developer. Positive photoresist creates an identical copy of the pattern, which is exposed
as a mask on the wafer.

Negative photoresist:
The photoresist in areas exposed to the ultraviolet light polymerize (individual phorore-
sist molecules join to form long chain molecules). The polymerized photoresist molecules
are insoluble in phororesist developer solution. The photoresist in regions unexposed to
ultraviolet light are removed with photoresist developer solution.
The key transfer of the mask pattern to the photoresist treated wafer surface, requires
accurate alignment of the mask and the wafer. A photolithography mask, also called a
photomask, is a plate of opaque material, with transparent geometrical patterns—only the
transparent areas allow the incident light to pass through, transferring the mask pattern to
the photoresist coated semiconductor wafer surface.
Sophisticated computer programs generate the mask pattern. The computer generated
data is transferred to a chrome coated square quartz plate with electron beam lithography,
with the quartz plate coated with appropriate photoresist. A beam of electrons moves over
the mask in a vector|raster pattern. Only over those spots where the chrome needs to be
removed, the electron beam is switched on. When the photoresist on the mask is exposed,
the chrome can be etched away, leaving a clear path for the light in the stepper/scanner
systems to travel through.
Photomask alignment [8] is another very difficult task, involving sub-micron toler-
ances. Commercial semiconductor device fabrication facilities use high end computer
vision enabled equipment to eliminate all errors. Figure 11.2b shows how the process
works in a very simple case.
After the wafer and mask have been exposed to the ultraviolet light, the mask is
removed and the wafer is baked for a predefined duration. Then the wafer is treated with
the appropriate photoresist developer (depending on whether the photoresist used was
positive or negative). Deionized water wash removes traces of photoresist and developer
solution. The wafer is now ready for the next processing stage.
188 11 Semiconductor Device Manufacturing Technologies

Although photolithography is meant to transfer two dimensional images from the mask
to the wafer, it is a three dimensional image, because of the intermediate air. So the
expected sharp contrast between light intensity in the bright and dark areas of an image
is reduced because of light intensity gradient. The Normalized Image Log-Slope (NILS)
method is used to quantify the aerial image quality, and minimum acceptable NILS values
are calculated using empirically determined constants. The depth of focus (DOF) is the
vertical distance over which the image remains in focus. It is dependent on the wavelength
of light used, and the numerical aperture of the imaging system. A high DOF is essential
for the entire resist layer to be properly exposed during photolithography.
These key parameters need to be adjusted to transfer patterns with smaller and smaller
feature sizes, to the wafer. To reduce the feature size either the wavelength of the expos-
ing light must be decreased or numerical aperture of the projection optics must be
increased. The DOF must be sufficient to ensure accuracy and precision in the feature
size through the entire thickness of a resist.
The phase shift technique is used to enhance edge contrast in the image being patterned,
eliminating defects from diffraction limitations at sub-wavelength patterning. Phase shift
masks with different thicknesses at different sections of the pattern on the mask, which
change the phase of the transmitted light, are used to achieve this goal.
Initially, photolithography was a “dry” process. Immersion lithography bypasses the
feature size limitations of dry lithography by replacing air with water as the medium between
the optical system and the substrate. Water with a refractive index of 1.44 increases the
value of NA beyond 1.0, leading to a reduction in minimum single-exposure feature size
to about 40 nm when using 193 nm light. Immersion lithography techniques increase the
amount of light that can reach the resist (increasing the resolution) and change the phase
of the light so that it improves DOF. So single exposure immersion lithography is the
only patterning technique at design nodes down to 45 nm.

11.3 Deep and Extreme Ultraviolet Photolithography

Deep ultraviolet(DUV) technology for photolithography is based on projection optics

since the pattern on the photomask is much larger than the final pattern developed on
the photoresist. The optical system in a 193 nm photolithography machine is a catadiop-
tric system, using both refractive(lens) and reflective(mirrors) for directing and controlling
the light beam from the laser. A catadioptric optical system can handle a broad bandwidth
of the source laser light while limiting chromatic aberration. Refractive elements in the
optical system are fabricated from either synthetic fused silica|calcium fluoride, both with
low absorption coefficient of 193 nm light. Photomasks (or reticles) in these systems are
typically made from fused silica with chrome patterns. In a step-and-scan photolithogra-
phy process, a slit of light is scanned across one or more dies patterned on the reticle.
The light reproduces the part of the pattern on the reticle that is illuminated on the wafer,
11.4 Ion Implantation 189

at much reduced feature size because of passage through the reduction lens. Simultane-
ous (and highly precise, accurate, and repeatable) movement of both the reticle and the
wafer is used to produce the full image of the die on the wafer. After patterning a die,
the next die area is positioned for patterning. The alignment and positioning of masks is
fully automated using computer vision techniques.
With relentless trend in gate length reduction for microprocessor MOSFETs, the
Rayleigh and diffraction limit conditions dictate that light of smaller wavelength be used.
Extreme ultraviolet (wavelength 13.5 nm) lithography, although far more complicated than
deep ultraviolet lithography, addresses this issue.

• There is no material that allows radiation at 13.5 nm to pass through it, so lenses are
ruled out. The ultraviolet beam is controlled with mirrors.
• Ordinary mirrors do not work. Special mirrors constructed with alternating lay-
ers of materials with different dielectric constant(commonly molybdenum and sili-
con|beryllium) are used.
• These special mirrors reflect light via constructive interference, whose wavelength
exactly matches the spacing between the layers. So, constructing these mirrors is very
difficult and expensive.
• A 4X reduction system consisting entirely of these special mirrors, as used in standard
optical lithography systems is easily constructed, so that mask tolerances need not be
much better than in current systems.

An EUV machine uses an infrared laser to excite xenon atoms to plasma state, which upon
relaxation emits ultraviolet light at 13.5 nm. The rest of the machine consists of condenser
and beam size reduction mirrors to pattern the photoresist coated wafer (Fig. 11.3). Some
EUV machines use tin plasma to generate the EUV radiation. Such a machine is more
complicated, as the used tin vapor has to be extracted constantly.

11.4 Ion Implantation

A semiconductor material either has excess electrons(n type) or holes(p type). However
most base materials for semiconductor devices (e.g., silicon) are electrically neu-
tral|intrinsic semiconductor, so that appropriate impurity atoms must be inserted into the
crystal lattice to make, e.g., silicon n type. The common impurity atoms are boron, phos-
phorus (n type) or arsenic (p type). The semiconductor industry technique for introducing
these impurities is ion implantation [6, 7]. The advantages of ion implantation over the
now obsolete thermal diffusion process are:

• It produces isotropic doped regions with very tight impurity dosage tolerances.
• The physical dimensions of the doped regions can be tightly controlled.
190 11 Semiconductor Device Manufacturing Technologies

(a)

(b)

(c)

Fig. 11.3 a Extreme ultraviolet lithography system. b Ion implantation machine. c Collision sites
for ion implanted into wafer

• The ion beam impinging the semiconductor wafer can be moved very precisely over
the wafer surface. Ion implantation is a low temperature process.

The ion implanter machine is a particle accelerator (Fig. 11.4a), and the interior is
maintained at very high vacuum to prevent unwanted impurities from contaminating the
wafer.
Ions are extracted from the ion source using electromagnetic fields. The ion beam from
the ion source is directed into a mass analyzer where the beam is focused and bent through
a right angle. The radius of the bend is determined by a combination of electromagnetic
field characteristics and the mass to charge ratio of the ions. Consequently, only ions of
a particular mass to charge ratio is selected to exit the mass analyzer using a movable
aperture (or an electromagnetic lens), other different ions that may originate from the
11.4 Ion Implantation 191

(a)

(b)

Fig 11.4 a MOCVD reaction. b UHVCVD apparatus

ion source are blocked. The beam of selected ions is then accelerated to high energies,
ranging from sub-keV to MeV values (eV = electron Volt) and the high energy ion beam
is steered using electromagnetic fields to impinge the semiconductor surface.
When a dopant ion strikes the wafer surface, it penetrates into the substrate crystal
matrix to a depth proportional to its energy and angle of incidence. But the newly entered
ion does not immediately displace a crystal lattice atom and occupy the displaced atom’s
lattice site. The newly entered ion collides with and is scattered by lattice atoms and
a number of these collisions comes to a halt in an interstitial site. (Fig. 11.4b). So the
concentration profile for dopant atoms versus penetration into the substrate is Gaussian.
So, the ion implanted wafers need to be “activated”.
Implanted ion activation is achieved by annealing the ion implanted wafer. Annealing
also repairs any damage done to the wafer crystal matrix by collisions with the high-
energy dopant ions and flatten the dopant distribution profile—uniform doping. Once
substituted into the lattice, the dopant will act as either a donor or acceptor depending on
its electronic structure.
192 11 Semiconductor Device Manufacturing Technologies

11.4.1 Ion Implantation Masks and Photoresists

Ions are implanted only into specific regions of the wafer. To prevent the incident ions
from penetrating unwanted regions, those regions have to be covered with an appro-
priate resistive material, that can be removed after ion implantation is completed. In
addition, to demarcate the regions that need to be covered with the ion implant resist
material, a mask is necessary.
A n ionized atom of mass M, after being
/ accelerated over a potential U has velocity
v (using purely classical physics) V = 2nqU M , This expression implies that for a single
ionised heavy atom e.g., arsenic after an acceleration voltage of 10 keV which is com-
paratively low for ion implantation, has a speed of about 160 km/s, and for a boron ion
accelerated with 500 keV, the velocity is around 3000 km/s (approximately 1% of the
light speed), for which the above classical view is still a valid approximation.
The entering ions suffer collisions. Inelastic collisions of electrons result in excita-
tion|ionization of the wafer substrate atoms. In the case of ion energies of several 10 eV,
which are too low for these processes, i.e., about 1 per thousand of the original energy,
a charge exchange between the ion and the solid can take place during the short term
formation of “quasi-molecules” of the entering ions substrate atoms.
The collisions with the atomic nuclei of the solid are elastic with a scattering cross-
section increasing with decreasing ion velocity. Inelastic collisions can also occur in which
the atoms of the host matrix are displaced in the microstructure of the solid, producing
point defects in crystalline structure.
The material used as ion implantation mask must be sufficiently thick to block ions
from impinging the wafer surface areas covered by it. The lateral resolution and sidewall
steepness of this material must satisfy tight tolerances. As the substrate might heat up
during ion implantation, the mask material must not soften, i.e. have a high melting tem-
perature. The necessary ion implantation mask material film thickness increases with the
ionic energy. The higher the density ρ and average atomic number Z of the ion implanta-
tion mask material used, the lower its necessary film thickness to absorb the incident ions.
The ρ and Z parameters of common ion implantation mask materials as phenol, epoxy or
acrylic-resins differ only to a small extent.

11.5 Dry and Wet Etching—Anisotropic and Isotropic

The goal behind photolithography is to demarcate regions of the semiconductor wafer

surface for the next processing step—e.g., etching. Semiconductor wafer surfaces are
etched using either wet or dry etching [9]. As wet etching uses very corrosive chemicals,
the masking material, e,g., for silicon wafers is silicon dioxide or silicon nitride.
When a semiconductor wafer is treated with a corrosive liquid or vapor, the result-
ing wafer material removal may be anisotropic (uniform in one direction) or isotropic
11.5 Dry and Wet Etching—Anisotropic and Isotropic 193

(uniform in all three directions. The material removal occurs only from those regions not
protected by the ion implantation mask material. Material removal rate for wet etching is
faster than corresponding rates for many dry etching processes. Wet etching rates can be
changed by varying temperature or the concentration of the active etching species.
Liquid etching chemicals (etchants) etch away|remove crystalline materials at dif-
ferent rates depending upon which crystal face is exposed to the etchant. In silicon, this
results in very high anisotropy. Some of the common wet etching agents for silicon are
potassium hydroxide(KOH), ethylene diamine pyrocatechol(EDP), or tetramethylammo-
nium hydroxide(TMAH). Etching a (100) silicon wafer results in a pyramid shaped etch
pit, with flat and angled (54.7◦ ) etched walls.
To achieve isotropic wet etching, a mixture of hydrofluoric acid, nitric acid, and acetic
acid(HNA) is used for silicon. The concentrations of each etchant determines the etch rate.
Silicon dioxide|nitride is used as a masking material against HNA. During the reaction,
the material is removed laterally at the same rate as that for material being removed in
the downward direction—isotropic etching. Wet chemical etching is generally isotropic
even though a mask is present since the liquid etchant can penetrate underneath the mask.
Wet chemical etching is not used if directionality is very important for high-resolution
pattern transfer.
Dry etching can be of two types dry gas reaction or plasma based. In dry etching,
plasmas or etchant gasses remove the substrate material, using using high kinetic energy
of particle beams, chemical reaction or a combination.
Physical dry etching requires high kinetic energy(ion, electron, or photon) beams to
etch off the substrate atoms. When the high energy particles knock out the atoms from the
substrate surface, the material evaporates after leaving the substrate. There is no chemical
reaction and only unmasked material is removed.
Chemical dry etching(vapor phase etching) does not use liquid reactants or etchants.
Etching is achieved via a chemical reaction between etchant gases to corrode the silicon
surface. The chemical dry etching is isotropic and is highly selective. Anisotropic dry
etching has the ability to etch with finer resolution and higher aspect ratio than isotropic
etching. Directional nature of dry etching blocks undercutting. The ions that are used
in chemical dry etching are tetrafluoromethane, sulphur hexafluoride, nitrogen trifluoride,
chlorine gas, or fluorine.
Reactive ion etching(RIE) the semiconductor industry’s choice for fast, controlled high
resolution etching. It uses both physical and chemical mechanisms to achieve high levels
of resolution. The high energy collision between the high energy ions and the wafer
atoms helps to dissociate the etchant molecules into more reactive species. Cations are
produced from reactive gases which are accelerated with high energy to the substrate and
chemically react with the silicon. The typical RIE gasses for Si are carbon hexafluoride,
sulphur hexafluoride and boron chloride.
194 11 Semiconductor Device Manufacturing Technologies

11.6 Chemical Vapor Deposition—CVD, APCVD, LPCVD, PECVD,

MOCVD

Chemical vapor deposition [10] and its enhanced variants as Atmospheric Pressure
CVD(APCVD), Low Pressure CVD(LPCVD), Phase Enhanced CVD(PECVD), metal
oxide chemical vapor deposition(MOCVD) and ultra high vacuum chemical vapor depo-
sition(UHVCVD) are very widely used in semiconductor fabrication to deposit layers of
material with extremely tight tolerances on thickness. Before CVD can be used to deposit
a layer of some material on a wafer, photolithography is used to demarcate those areas
that need to get coated. Appropriate masking materials cover those wafer regions that do
not need to be coated.
CVD is a fundamental semiconductor device manufacturing technology, each form cus-
tomized for a different processing step. The different methods for CVD rely on differing
process parameters e.g., different chemistries, substrate materials, temperatures, pressures,
and deposition durations. However, all CVD processes utilize two main procedures:

• Decomposition reaction of a gaseous compound

• Combination reaction of one or more of those elemental parts on a substrate material.

For the decomposition and combination reactions to proceed (to generate the desired final
result), the parameters that control the chemical reactions must be adjusted as required
for the bonds to break and reform, similar to how water evaporates in hot or low-pressure
air.
The three common chemical vapor deposition techniques used in semiconductor pro-
cessing are: Atmospheric Pressure CVD(APCVD). Low Pressure CVD(LPCVD) and
Phase Enhanced CVD(PECVD). While APCVD requires high operating temperatures
(1000 °C). LPCVD requires a high vacuum chamber (10–1000 Pa) and moderately high
temperature (lower than the ~ 1000 °C of APCVD). The required chemical reactions occur
faster, and the vacuum chamber can be used to process a number of wafers at the same
time, reducing processing costs.
PECVD is used for low temperature (100–400 °C) low volume chemical vapor depo-
sition. During this process, cold plasmas are injected into the reaction chamber to boost
the electron temperature of the chemical that is being deposited on the wafer. By chang-
ing the pressure, the cold plasma uses the energy of these electrons to quickly dissociate
the molecules of the reactive gases. A layer of uniform thickness (of the material to be
deposited), is laid down on the exposed (not covered by mask) wafer surface. For exam-
ple, deposition of 3C and 6H silicon carbide(SiC) layers on silicon. A number of separate
but related processes exist to achieve this task, and some allow n, p type dopant atoms to
be included in the new layer to be deposited.
11.6 Chemical Vapor Deposition—CVD, APCVD, LPCVD, PECVD, MOCVD 195

11.6.1 Metal Organic Chemical Vapor Deposition

(MOCVD|OMVPE|MOVPE)

Metal organic vapor phase epitaxy (MOVPE), or organometallic vapor phase epitaxy
(OMVPE) or metalorganic chemical vapor deposition (MOCVD) [11], is a chemical
vapor deposition technique to deposit single or polycrystalline thin films on appropriate
substrates. Unlike MBE (Molecular Beam Epitaxy) which physically deposits layers
on a substrate, MOCVD involves chemical reactions between the reactant gases and
the substrate material to create the new layers. MOCVD does not require high vac-
uum conditions, and the reaction chamber is first purged to high vacuum and then the
reactant gases are pumped in to eliminate contaminants from polluting the layers to
be deposited. The working pressure inside the chamber is 10–760 Torr. MOCVD is
a preferred technique to fabricate devices which include thermodynamically metastable
alloys—optoelectronic devices.
MOVPE|MOCVD|OMVPE uses reactants in their gaseous form. Ultra pure reactant
gases in predetermined proportions are injected into the reaction chamber. The substrate
is heated to a precalculated high temperature. The gas molecules coming in contact with
the heated substrate react, depositing layer(s) of the reaction products on the substrate.
Crystal growth is favored by the surface reactions taking place on the substrate surface.
These reactions involve organic|metalorganics and hydrides which contain the required
chemical elements for producing the desired layer on the substrate surface. This technique
is used to deposit layers of compound semiconductor containing groups of the periodic
table II, III, V and VI. Figure 11.5 illustrates how indium phosphide(InP) is deposited on
a substrate, in three steps.

• Trimethyl indium and phosphine gases are injected into the purged reaction chamber
in predetermined proportions.
• As the chamber contains only the reactants and the substrate, heating the surface
triggers pyrolysis amongst the reactant gases, in contact with the wafer.
• The reaction product is deposited on the wafer.

Fig. 11.5 Atomic layer Deposition

196 11 Semiconductor Device Manufacturing Technologies

11.6.2 Ultra High Vacuum Chemical Vapor Deposition (UHVCVD)

Ultra-high vacuum chemical vapor deposition (UHVCVD) is used for epitaxial layer
growth of silicon and related materials as uniformly strained epitaxial layers. Several
implementations have been proposed, and of these the multi wafer UHVCVD technique
is widely used. The multi wafer UHVCVD is characterized by the absence of both hydro-
dynamic boundary layer effects and gas phase chemical reactions, as a result of the ultra
high vacuum conditions in the reaction chamber.
The key advantages of this material deposition technique are:

• Under ultra high vacuum conditions, the molecular mean free path comparable to the
chamber dimensions.
• With almost non-existent inter molecule collisions, gas phase reactions are almost
eliminated.
• Molecular flow transport eliminates hydrodynamic boundary layer issues.
• Deposited layer growth rate is determined by surface decomposition of the reactant
molecules.

Figure 11.5 shows the apparatus used in multi wafer UHVCVD. Wafers are arranged on a
wafer boat with inter wafer spacing of the order of a small fraction of the wafer diameter.
The wafer boat is placed inside a quartz tube which is heated along its length by a furnace.
Gases are injected into the quartz tube at one end and pumped out from the other end
using ultra high vacuum pumps. The pumps have load lock mechanisms so that low partial
pressures of important contaminants e.g., hydrocarbons, water vapor, and oxygen can be
maintained. This key feature is very important for low temperature growth because
important contaminants cannot be desorbed at the growth temperature. The reactants
used are hydrides (e.g., silane, germane, diborane, methylsilane, and phosphine diluted in
hydrogen or helium to obtain convenient flow rates. The chlorine containing reactants are
avoided as chlorine persists in the growth system: undesirable in multi wafer UHVCVD
as this results in non-uniform layer deposition. The operating temperatures are in the
500–600 °C range, with reaction chamber pressures in the micro Torr range.
As UHVCVD process is carried out at high temperatures, reducing the thermal budget
is very important. The wafer surfaces must be contaminant free, to quickly initiate the
epitaxial growth. A common method to create a hydrogen terminated surface is by dipping
wafers in dilute hydrofluoric acid with no following rinse (HF-last clean). Consequently,
all wafer surface dangling bonds are terminated by hydrogen. This treated surface does not
react with oxygen or water vapor under ambient conditions. Hydrogen terminated wafers
are loaded into the furnace and reactant gases are injected quickly to block hydrogen
desorption. The wafer is never exposed to any temperature greater than the epitaxial
growth temperature. Oxygen and water vapor cannot be allowed to adhere to the wafer
11.7 Molecular Beam Epitaxy (MBE) 197

surface that is to be processed with UNVCVD. Some other methods have also been
implemented to achieve the same goal [12].

11.6.3 Atomic Layer Deposition (ALD)

A variation of CVD is atomic layer deposition, which allows atomic layers of materials
to be deposited using chemical reactions. ALD exploits a binary sequence of self-limiting
surface chemical reactions which results in films of solid material with Angstrom(s) thick-
ness. It consists of cycles of alternating reactions with one ALD cycle depositing one
“atomic layer.” The number of deposition cycles provides a tight control on the thickness
of the resulting film. The sequence of steps is shown in Fig. 11.6.

11.7 Molecular Beam Epitaxy (MBE)

Molecular Beam Epitaxy(MBE) [13] is used to the deposit thin film compound semi-
conductors, metals or insulators. MBE enables a tight control of compositional profiles
by using a non-equilibrium thermodynamic process. “Epitaxy” is a combination of two
Greek roots “epi” and “taxis” which mean to arrange upon. So epitaxy is the arrangement
of one or more thermal particles on top of a heated and ordered crystalline substrate to form
a thin layer whose crystalline structure matches that of the substrate, despite their different
chemical compositions e.g. SiGe/Si, AlGaAs/GaAs, CdTe/GaAs etc., The evaporated atoms
and|or molecules do not interact with each other until they reach the substrate because of
their long mean free paths—possible only under ultra high vacuum conditions.
MBE is widely used to produce superlattice structures consisting of many alternate
thin (individual layer thickness ~ 10 Angstrom) layers. Single atom thickness layers (delta
doping) can also be fabricated, i.e., the chemical species above and below the single atom
thick impurity atom layer are different.

Fig. 11.6 a, b Critical (a) (b)

Dimension Scanning Electron
Microscopy and line profile
198 11 Semiconductor Device Manufacturing Technologies

(a)

(b)

Fig. 11.7 a Unpatterned wafer defect detection. b Patterned wafer defect detection

MBE enables materials (atoms etc.,) to be deposited at ultra low rates (few Angstrom
per second) by evaporating extremely pure solid elements heated in separate pyrolytic
boron nitride effusion (Knudsen) cells. Element heating is done either electrically, or
using electron beam (for high melting temperature elements).
As the evaporated elements reach the surface they have a probability of ’sticking’. An
element atom, after getting attached to the substrate can react with the substrate in three
ways.

• If it becomes adsorbed onto the surface through weak, physical, bonds e.g., Van der
Waals forces, then it is said to be physisorbed.
• If it exchanges electron(s) with the substrate and gets chemically bonded to the surface,
then it is said to be chemisorbed.
• If it does not desorb then the energy available from the heated substrate will cause it
to diffuse about on the surface, promoting growth.

To form a crystallographically oriented material, incoming elements must arrive or

diffuse to epitaxial sites and become chemisorbed at that site. Three (Frank van der
Merwe, Volmer-Weber and Stranski–Krastanov) layer growth modes can occur depend-
ing upon the substrate temperature, the deposition rate and available surface energy. The
Frank van der Merwe mode allows precision layer-by-layer growth. Volmer-Weber mode
11.7 Molecular Beam Epitaxy (MBE) 199

allows growth of three dimensional islands, and the Stranski–Krastanov is an combina-

tion|intermediate mode. Unwanted impurity elements in the growing layers are minimized
because of the ultra high vacuum < 10−10 Torr in the reaction chamber.
MBE is in the fabrication of ultra high frequency|power transistors(HBT, HEMT,
SiC etc.,), optoelectronic devices (phototransistors|light emitting diodes|semiconductor
lasers|thin film solar cells etc.,). The reaction chamber’s interior ultra high vacuum con-
ditions allow efficient diagnostic tools as RHEED (Reflection High Energy Electron
Diffraction) to monitor the properties of the deposited layers.
The main MBE high vacuum evaporation chamber is connected to other chambers by
gate valves, to avoid contamination of components and materials sources by both external
and process gases, and minimize pressure in the main growth chamber. State-of-art MBE
systems include a treatment chamber, and a load lock module to insert and remove wafers.
The key pumping system is a combination of Roots, ion, titanium sublimation and
liquid nitrogen pumps. The vacuum quality (inside the reaction chamber) metrics are:
the mean free path L and the partial pressure of the residual gas molecules. The highest
admissible residual gas pressure value depends on L being larger than the distance from
the outlet orifice of the beam source to the substrate surface (L > 0.2 m).
From the kinetic theory of ideal gases, numerical data for conventional MBE growth
of Si, the maximum value of the residual gas pressure is 10−5 Torr, i.e. much higher
than the typical ultra high vacuum conditions inside the MBE chamber. But the time
required for the deposition of 1 mono layer of residual contaminants is 105 times the
time needed to deposit 1 mono layer of film from the molecular beams. So very low
deposition rates should be used in an ultra high vacuum MBE chamber. However, the
partial pressure increases during deposition resulting from the increased heat load from the
effusion cells and the substrate. Then a titanium filament sublimation pump reduces the
residual gas pressure down to minimum permitted values. The vacuum chamber is baked
at approximately 250 °C for extended periods of time, to minimize outgassing from the
internal walls during the deposition process. A complete bake cycle, the vacuum chamber
and the components have an approximate vacuum level of 10−10 Torr, using only the main
ion pump. In addition, both carbon dioxide and water vapor pressure inside the chamber
can be reduced to 10−11 Torr with liquid nitrogen cryogenic cooling The substrate holder
is located a few centimeters from the effusion cell exit ports, along the center line of the
system. The temperature of the substrate can be set during the deposition, starting with
the room temperature, up to about 1400 °C, depending on the epitaxial process needed. It
can also be heated before deposition for cleaning|surface reconstruction, and afterwards
for various heat treatments. An included spectral mass analyzer detects the residual atoms
or molecules.
200 11 Semiconductor Device Manufacturing Technologies

11.8 Metrology in Semiconductor Device Manufacture

Metrology [14] and inspection of the wafers in-between successive processing steps of the
complete semiconductor device manufacturing process is essential because of the large
number of intermediate (approximately 400 to 600) steps in the overall manufacturing
process of semiconductor devices. Completing this entire process for a batch of wafers
takes 1- 2 months. If any defects occur early on in the process, these defects will propagate
through the subsequent processing steps. Metrology and inspection steps at critical points
of semiconductor manufacturing process ensure that a certain target yield can be confirmed
and maintained.
Some typical inspection|measurement|verification steps include:

• Determining the line width and hole diameter of a circuit pattern at a specified location
of a semiconductor wafer.
• Measurement of the thickness of the thin films on the surface of a semiconductor wafer.
• Verify the accuracy of the overlay. Measurement is performed to check the accuracy
of the shot overlay of the first and second layer patterns transferred onto a wafer.

Metrology is measurement performed by factoring in errors and accuracy, along with

the performance characteristics|tolerances of the measurement equipment. If pat-
tern measurements do not satisfy predefined tolerances, the manufactured device will
not operate as designed. Then re-work is essential. The two related concepts behind
designating semiconductor metrology equipment as high-performance are:

A: accuracy and precision

B: precision|trueness and repeatability

Accuracy is a measure of how close the measured quantity is to the “ideal|true value”, “pre-
cision|repeatability” is a measure of the variations of the measured values of a parameter
from multiple measurements.
These two key concepts can be summarized as:

• A small variation (from the ideal value) in a measurement indicates high precision.
• A mean value close to the ideal|true value means high (good) accuracy.

“Small variation” indicates tight tolerance, while “close” depends entirely on the
tolerance (e.g., 5%, 2.5%) set to denote the permissible variation from the ideal value.
11.8 Metrology in Semiconductor Device Manufacture 201

11.8.1 Critical Dimension Scanning Electron Microscopy

Exploiting the same physics as a scanning electron microscope, the critical dimension
scanning electron microscope (CD-SEM) is designed to measure separation of lines on
the sample wafer with high accuracy and precision. The special features of any of these
fully automated measurement machines are:

• Incident electron beam energy is restricted to a maximum value of 1 keV to minimize

damage to the wafer surface being inspected.
• Measurement accuracy and repeatability is guaranteed by having very precise high
magnification imaging system, such that the measurement repeatability is 1% 3σ of
measurement width.

The sequence of processing steps for a CD-SEM line profile measurement are simple.

• Using user input, the CD-SEM system positions the position indicator (often called
the cursor) at the required measurement location in the scanning electron microscope
(SEM) image.
• The line profile (signal that identifies the changes in the topological profile of
measurement feature) of the specified measurement position is measured.
• The line profile data is used to measure the dimensions of the specified location, by
counting the number of pixels in the measurement.

Figure 11.7a and b demonstrates these concepts. The two key semiconductor wafer
processing steps after which CD-SEM is performed are:

• Examination of photoresist pattern after deposition, before any other wafer processing
step.
• Measurement of contact hole and via hole diameters and metal wiring width after
etching.

11.8.2 Wafer Defect Detection

A wafer defect inspection system detects both physical and pattern defects (random
and systematic) on unprocessed and patterned wafers, as well as determining the x,y
coordinates of the defect locations.

• A random defect is a result of events beyond control—damage due to a foreign particle

landing on the wafer
202 11 Semiconductor Device Manufacturing Technologies

• A systematic defect results from events under control—e.g., defects in mask and expo-
sure process, and so will occur at the same position on each wafer of a given batch of
wafers being processed.

As a wafer defect detection system identifies faults by comparing the images of circuit
patterns on adjacent dies on a wafer under test, systematic defects sometimes cannot
be identified easily in conventional wafer defect detection systems. The unpatterned and
patterned defect detection schemes are shown in Fig. 11.7a and b. The three common
wafer defect detection systems are electron beam, bright and dark field, all using the
exploiting the basic physics.
In unpatterned wafer inspection, a finely collimated laser beam is moved back and
forth radially across a rotating wafer. When the laser beam is directly incident on a
defect|particle of a rotating wafer, the light will be scattered and detected by a detec-
tor. From the wafer rotation angle and the radius position of the laser beam, the position
coordinates of the particle/defect are calculated and registered. Defects on a mirror wafer
include crystal defects and particles. While the bright field inspection system is for
detailed examination of pattern defects, the dark-field inspection system is designed for
high speed defect inspection of a large number of wafers.
In the electron beam inspection system, electrons incident on the surface of the wafer,
and the emitted secondary electrons and backscattered electrons are detected. This defect
detection system detects the amount of the secondary electrons as an image contrast
(voltage contrast) according to the conductivity of the device’s internal wiring. If the
conductivity at the bottom of the contact hole of the high aspect ratio is detected, the
SiO2 residue of ultra-thin thickness can be detected.
Patterned wafer inspection systems can be electron beam irradiation, or bright|dark
field illumination types. A patterned semiconductor wafer consists of adjacent identical
integrated circuits, and the possibility of a random defect (e.g., impurity particle dropping
on a wafer surface) occurring at the same position in all wafers of a batch is negligible.
The pattern on the wafer is captured along the integrated circuit array by electron beam
or light. Defects are detected by comparing, (using highly accurate and reliable computer
vision systems) between image (1) of the wafer die under inspection and previously cap-
tured image (2) of the adjacent die. If there are no defects, the result of the subtraction of
Image 2 from Image 1 by digital processing will be zero and no defects are detected. If
the resulting image obtained from subtraction of the image of die 1 from the image of
die 2, contains anything, then a defect has been detected. The defect position coordinates
are registered.
11.9 Thin Film Thickness Measurement Techniques 203

11.8.3 Review Scanning Electron Microscopy

Defect Review Scanning Electron Microscopy is the immediate next wafer defect identi-
fication step after initial defect detection, using an inspection system, as examined earlier.
Using the output of the initial inspection (as discussed in previous sub-sections) which con-
sists of the identified defect position coordinates on the wafer, the review scanning electron
microscope obtains detailed images of these defect sites and classifies each defect.
The Review Scanning Electron Microscope, similar to the defect inspection system,
detects the defect by comparing the image of circuit pattern of a selected die with the
image of the circuit pattern of the adjacent dies and obtains the correct position of the
defect. The defect is then moved to the center of the field of view and an enlarged image
is created. The defect is then classified.
Automatic Defect Review (ADR) automatically obtains image of the identified defect
using the defect information (coordinates, etc.) obtained in defect inspection. The data
is stored and arranged into a database. The image information of the defect stored in
the image server is classified according to the cause of the defect by the classification
software based on the predetermined rules and is then restored in the classification server.
The classified information is sent to Yield Management System (YMS) and the central
database of the integrated circuit manufacturer so that it can be used in the failure and
defect analysis.

11.9 Thin Film Thickness Measurement Techniques

Common high performance semiconductor device consists of several layers of semi-

conducting materials each with different electrical properties and thickness. Since the
performance characteristics of the device are dependent on the thicknesses of these lay-
ers, it is essential that the thickness of each layer be monitored and measured accurately
during production. Selecting a method for a specific measurement is tricky, since while
one method may be ideal for measuring the thickness of one type of material, it might be
inappropriate for another material. So thin film thickness measurement technique for a
specific case depends on what methods are eligible for the material in question (taking
into account film properties as surface roughness, thickness range, properties of film and
substrate etc.,) what additional information other than the thickness of the film is to be
determined with the analysis, and what the budget is. The key constraints are:

• Thickness measurement must be non-contact and non-destructive.

204 11 Semiconductor Device Manufacturing Technologies

11.9.1 Oxide Layer Thickness Measurement

Oxide layers are transparent films. If light is irradiated onto the wafer and reflected,
various properties of the reflected light wave are changed—easily detected with sensitive
metering devices. Identification of vertically deposited multiple layers, each with different
optical properties can also be done using optical measurement techniques. To monitor the
film thickness across the wafer, several measuring points are quantified (e.g. 5 points on
150 mm, 9 points on 200 mm, 13 on 300 mm wafers). Multiple measurements, each
at different locations ensures absolute thickness as well as thickness uniformity across
the wafer. If the deposited layer is too thick or too thin material has to be removed
(e.g. by etching) or deposited again. The two common techniques are interferometry and
ellipsometry.
Interferometry is based on constructive and destructive interference of light—in phase
light waves reinforce, while out of phase light waves cancel eachother. This phenomenon
is used during semiconductor production for measuring translucent films. If light is irra-
diated onto a wafer some beams of light are reflected on top of it and some penetrate
into the film. The latter will be reflected from the bottom of this layer or penetrate into
another layer beneath and so on. A polychromatic light beam is shined on the wafer
and depending on the film thickness of the radiographed layer, the light waves interfere
either constructively or destructively, resulting in a characteristic interference pattern. A
photometer can analyze the reflected light and calculate the film’s thickness. Interferom-
etry can be used on films whose thicknesses are greater than at least one fourth of the
wavelength of incident light.
Ellipsometry is measurement of light polarization. Linearly polarized light is irradiated
on the test surface. During reflection of light on top of the wafer or on interfaces of two
layers, the light’s polarization is changed, easily detected with an analyzer. Combining
known optical properties of the film (e.g. angle of refraction, how much of the incident
light is absorbed etc.,), of the incident and reflected polarized light, the film thickness can
be calculated. Unlike interferometry, ellipsometry measurements can be used for films
with thicknesses less than one fourth of the wavelength of the incident light.

11.9.2 Ray Reflectometry, Scanning and Transmission Electron

Microscopy

Layered materials can be analyzed with X-ray reflectometry, enabling the estimation of
total film thickness, as well as thickness, density and surface roughness of individual
layers. The method is suitable for materials with a thickness less than 250 nm, optimally
under 100 nm. For accurate measurements, the thickness of the material must be at least
one order of magnitude greater than the surface roughness of the film. The results obtained
with this method are accurate and meaningful only if the estimated composition and structure
11.10 Maintaining Super Clean, Sanitized Semiconductor Fabrication … 205

of the sample under test are known beforehand. This is essential since the method relies on
fitting the experimental X-ray reflectometry data to corresponding simulated layer model
data. As expected, analysis can result in large errors if the composition of the sample is
completely unknown.
Cross-sectional Scanning Electron Moicroscopy (SEM) is ideal for measuring the
thickness of semiconductor thin films (single- and multi-layer materials). It also provides
information about the surface morphology and elemental composition of the sample. The
method is suitable for conductive and semiconductor materials with a thicknesses between
100 nm and 100 μm. Non-conductive materials can also be analyzed with a small modi-
fication, i.e., the non-conducting surface has a thin layer of conductive material deposited
on the surface. If in addition to thickness information, information on the elemental com-
position of the film is needed, an SEM equipped with an EDS detector (energy dispersive
spectroscopy) is required. The EDS detector measures the x-rays emitted from the sample
when the electrons interact with it. As the detector analyses the x-ray spectrum, it recog-
nizes the spectra of individual elements and compounds and allows for their identification
and quantification.
Cross-sectional Transmission Electron Beam Microscopy (TEM) is also commonly
used to measure thickness of and analyze properties of conductive and semiconductive
films (single and multilayer). The thickness range for accurate results varies between few
nanometers to 100 nm. In addition, sample thickness can be customized with focussed ion
beam. Just like cross-sectional SEM, an additional attached EDS detector enables extrac-
tion of information about the elemental composition of the sample. Unlike cross-sectional
SEM, the high voltage beam can burn|damage some materials, making it inappropriate
for polymeric and organic materials.

11.10 Maintaining Super Clean, Sanitized Semiconductor

Fabrication Facilities [15]

As expected, modern semiconductor devices are manufactured in cleanrooms. With semi-

conductor device internal physical dimensions getting scaled down low nanometers, it is
imperative that ultra clean and sanitized environments exist inside semiconductor device
manufacturing facilities to ensure that air particulate levels are within tight tolerances,
and de-ionized, distilled water is used for surface cleaning of wafers during intermediate
production steps. Wafer surface contamination has to be eliminated. Process engineers
and technicians wear head-to-toe body suits, with their mouth, nose and head completely
covered.
To address these issues, real time monitoring systems have been implemented to
monitor and eliminate semiconductor wafer contamination during each production step.
Key component of any real time cleanroom cleanliness monitoring system are airborne
and liquid particulate monitors. Portable and fixed airborne particle counters (for particle
206 11 Semiconductor Device Manufacturing Technologies

sizes 0.1–0.3 μm), for gas manifold systems are widely used for cleanroom certifica-
tion and routine monitoring. Equipped with communication network ports, these devices
enable real time data logging and eliminate paper use inside the cleanroom.
Wafer cleaning between successive processing steps uses large volumes of de-ionized
and distilled water. These water systems need to be monitored both inline and offline
using liquid particle counters. State-of-art liquid particulate monitors have resolution in
the 50 nm range.
The ISO 14644–1:2015 standard specifies the classification of air cleanliness in terms
of concentration of airborne particles in cleanrooms and clean zones. This standard applies
only to particle populations having cumulative distributions based on lower limit size
between 0.1 to 5 μm. Airborne particle concentration is estimated using light scattering
(discrete) airborne particle counters. The airborne particle sizes must be equal to and|or
greater than the specified sizes, at designated sampling locations.
The ISO 14698:2003 standard specifies the principles and basic methodology of a
formal system of biocontamination control for estimating, monitoring and controlling
biocontamination inside a cleanroom. It specifies the methods used for monitoring risk
zones in a consistent way and for applying control measures appropriate to the degree of
risk involved.
The physical task of removing airborne particulate contaminants is achieved with
HEPA filters [16]. HEPA (High Efficiency Particulate Air) filter is a type of pleated
mechanical air filter, which can theoretically remove at least 99.97% of dust, pollen,
mold, bacteria, and any airborne particles with a size of 0.3 microns (μm). The specified
0.3 microns diameter is the worst case—the most penetrating particle size (MPPS). Par-
ticles that are larger or smaller are trapped with even higher efficiency. Using the worst
case particle size results in the worst case efficiency rating (i.e. 99.97% or better for all
particle sizes). All air cleaners require periodic cleaning and filter replacement to function
as per specifications.
Minimum Efficiency Reporting Values, or MERVs, report a filter’s ability to cap-
ture larger particles between 0.3 and 10 microns (μm). This value, developed by by the
American Society of Heating, Refrigerating, and Air Conditioning Engineers is helpful in
comparing the performance of different filters. A high MERV [16] rating indicates that a
filter under test is the ideal one at trapping specific types of particles.

References

1. https://www.pfeiffer-vacuum.com/en/markets/semiconductor/ion-implantation/source-bea
mline-end-station/.
2. https://www.sciencedirect.com/science/article/abs/pii/0168583X91962083.
3. https://www.leybold.com/en-in/knowledge/vacuum-fundamentals/vacuum-generation/how-
does-a-roots-pump-work.
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4. https://www.vacuumscienceworld.com/blog/multistage-roots-vacuum-pumps-working-princi
ple.
5. https://sens4.com/vacuumunits.html.
6. https://www.mks.com/n/ion-implantation.
7. https://www.microchemicals.com/technical_information/ion_implantation_photoresist.pdf.
8. https://cleanroom.groups.et.byu.net/alignment.parts/Alignment_Tutorial.pdf.
9. https://www.ece.ucdavis.edu/~anayakpr/Papers/Wet%20and%20Dr%20Etching_submitted.
pdf.
10. https://www.arrow.com/en/research-and-events/articles/what-is-chemical-vapor-deposition.
11. https://www.azom.com/article.aspx?ArticleID=11585.
12. https://users.ece.cmu.edu/~dwg/research/UHVCVD.pdf.
13. https://www.researchgate.net/publication/256143230_Basics_of_Molecular_Beam_Epitaxy_
MBE_technique/link/57335adf08aea45ee838f482/download.
14. https://www.hitachi-hightech.com/global/en/knowledge/semiconductor/room/manufacturing/
metrology-inspection.html.
15. https://www.iso.org/obp/ui/en/#iso:std:iso:14698:-1:ed-1:v1:en.
16. https://www.epa.gov/indoor-air-quality-iaq/what-hepa-filter.
Designing Transistors for Specific
Applications
12

12.1 Transistor Capacitances

Transistor capacitors [1-5] arise because of built-in interfaces between the three regions—
base, collector, emitter for a bipolar transistor, and drain, gate, and source for a field effect
transistor. The generic structure of a transistor is in Fig. 12.1a Transistor capacitances are
defined in terms of current, and time rate of change of voltage as:
Q i i ∂t
C= = ∂V = (12.1a)
V ∂t
∂V

12.1.1 MOSFET Capacitances (SPICE Level 1 Model, Triode Region)

The built-in total(unlike per unit area) capacitances inside a

metal oxide semiconductor field effect transistor are classified
as extrinsic and intrinsic[6–22]. With reference to Fig. 12.1b
C D R AI N ,G AT E , C G AT E,S OU RC E , C D R AI N ,S OU RC E , C I N T R (transcapacitance) are
the intrinsic capacitances, while the rest.
C G AT E,D R AI N ,O V E R L A P , C G AT E,S OU RC E,O V E R L A P , C J D E AI N , C J S OU RC E are
labelled extrinsic capacitances.
Using the following definition of transcapacitance, the drain current is re-written as:
−CDRAIN , GATE ∂CGATE, DRAIN
CTRANSCAP = CGATE, DRAIN − CDRAIN,GATE i DRAIN =
∂t
(12.1b)

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 209
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_12
210 12 Designing Transistors for Specific Applications

Fig. 12.1 a Generic transistor (a)

structures. b Extrinsic and
intrinsic MOSFET
capacitances. c Electron, hole
movement and built-in
capacitances in a
heterogeneous bijunction (b)
transistor (HBT)

(c)

The drain source capacitance for a MOSFET in the linear region arises when the
drain source voltage increases widening the depletion zone, followed by accumulation
of negative substrate charge. Consequently, a positive charge develops in the channel.
Because the channel charge is related to both the drain and source charges, the changes
in these charges are positive. So the source drain capacitance is negative.
Analytically, it is difficult to derive expressions for the gate-source and gate-drain
intrinsic capacitances, but under the simplifying conditions of the triode region operation,
the approximate expressions for these two capacitances are:
  2 
2COXIDE L W VGATE, DRAIN − VTHRSH
CGATE ,SOURCE = 1−  2
3 VGATE,SOURCE + VGATE, DRAIN − 2VTHRSH
(12.1c)
  2 
2COXIDE L W VGATE, DRAIN − VTHRSH
CGATE, DRAIN = 1−  2
3 VGATE, SOURCE + VGATE, DRAIN − VTHRSH
(12.1d)
12.2 Heterogeneous|Homogeneous Junction Bipolar Transistor Capacitances 211

The extrinsic capacitances consist of overlap capacitances, junction capacitances and

the gate substrate overlap capacitance. For the gate drain overlap capacitance, the total
gate overlap charge, from Gauss’s law and the corresponding overlap capacitance is:
−ε O X I D E A O V E R L A P VD R AI N ,G AT E
Q G AT E,O V E R L A P = C O V E R L A P,G AT E,D R AI N
tO X I D E
−∂ Q G AT E,O V E R L A P εO X I D E A O V E R L A P
= = (12.1 e,f)
VD R AI N tO X I D E

12.2 Heterogeneous|Homogeneous Junction Bipolar Transistor

Capacitances

Due to the similar internal layered structure of both heterogeneous|homogeneous bipolar

transistors (Fig. 12.1c) the identical internal capacitances are present in both these tran-
sistors. As the base controls collector to emitter current flow, all voltages are referenced
with respect to the base, e.g., base–collector and base-emitter voltages(VBC , VB E ). The
cross-sectional areas of both the collector and emitter are larger than that of the gate of
FETs, so intrinsic capacitances are very important to the operation of bipolar transistors.
The focus is on Npn|npn transistors.
When the base voltage changes, the emitter base potential barrier is lowered, and the
depletion zone length region shrinks. The n side shrinks because electrons flow in from
the emitter lead and neutralize the charge of some of the ionized donors. The emitter base
junction capacitance is:
−∂ Q E M I T T E R,J U N C T I O N
C E M I T T E R,B AS E, J U N C T I O N = (12.2a)
∂ VB AS E,E M I T T E R, J U N C T I O N

where Q E M I T T E R,J U N C is the total charge of the electrons that have entered from the
emitter contact, and are present at the junction edge. Similarly, holes from the base contact
enter to reduce the width of the depletion region in the base side of the junction.
−∂ Q B AS E, J U N C T I O N
C B AS E,E M I T T E R, J U N C T I O N = (12.2b)
∂ VE M I T T E R,B AS E J U N C T I O N

As the base emitter junction is planar, the junction capacitance is:

ε S E M I C O N DU C T O R A E M I T T E R
C E M I T T E R,B AS E,J U N C T I O N = (12.2c)
W
The base storage capacitance is the sum total of the charges of the electrons in the base
injected from the emitter, in response to base-emitter voltage change, in order to establish
a new electron profile in the base, from which the new collector current is derived.
212 12 Designing Transistors for Specific Applications

−∂ Q E M I T T E R,ST O R AG E
C E M I T T E R,B AS E,ST O R AG E = (12.2d)
∂ VB AS E,E M I T T E R

With reference to the hole current, the same capacitance can be re-expressed as:
−∂ Q B AS E,ST O R AG E
C B AS E,E M I T T E R,ST O R AG E = (12.2e)
∂ VE M I T T E R,B AS E

Using the total charge stored in the quasi neutral base region, and using appropriate
boundary conditions, the base storage capacitance is:
V B AS E,E M I T T E R
n 0 p q 2 A E M I T T E R e VT H E R M AL
C E M I T T E R,B AS E,ST O R AG E = (12.2f)
VT H E R M AL
The emitter storage capacitance is unimportant in HBTs because injection of holes into
the quasi-neutral emitter from the base is blocked by the large potential resulting from
the valence band offset.
The capacitance related to the transit of electrons across the wide depletion layer at the
reverse biased base collector junction in the active mode of operation is very important.
The electrons come in from the emitter lead, but the holes these electrons draw in from
the base are smaller in number and this effect is very important in estimating the HBT’s
transition frequency, a key performance characteristic for ultra high frequency transistors.
This capacitance is the base emitter transit capacitance:
−∂ Q B AS E,hole
C B AS E,E M I T T E R, J U N C T I O N = (12.2g)
∂ VE M I T T E R,B AS E

The capacitance is in reference to base emitter, as the electrons that trigger its creation
are from the emitter. Assuming an uniform electric field in the base collector depletion
region of width w, it is maintained by a constant base collector voltage. Then image
charges +Q and −Q form at the edges of the depletion region, resulting from positive
charges flowing through the external collector base circuit, and building up at the edges of
the depletion zone. Using the fact that the collector voltage is constant along with Gauss’s
law, the image charges are expressed as:

qelectr on + q0 + qw = 0 (Q − q0 )x + (Q + qw )(w − x)
 x −qelectr on,x
= Qw q0 = −qelectr on 1 − qw = (12.2.h,i,j)
w w
As the base collector voltage is constant, the electrons have a constant drift velocity,
so that the base transit collector transit capacitance is:
∂ Q B AS E,hole gm w
C B AS E,E M I T T E R, J U N C T I O N = = (12.2k)
∂ VE M I T T E R,B AS E 2v D R I F T ,electr on
12.3 Transistors for Computer Memory 213

In the above equation, the term 2v D R I F T ,electr on in the denominator implies that the
signal velocity exceeds the drift velocity—a result of image charges at the collector before
the electrons reach the collector. Mobile electrons rearrange the electric field, creating
image charges. Image charges are not present in a field effect transistor at the drain—the
channel is two dimensional, and is close to the gate.
In active operation mode, the base collector junction is reverse biased and very few
minority carriers are injected across the junction—no charges are stored. The only collector
base capacitance is the junction capacitance:
−∂ Q C O L L EC T O R,J U N C T I O N
CC O L L EC T O R,B AS E =
∂ VB AS E,C O L L EC T O R
ε E M I C O N DU C T O R AC O L L EC T O R
= (12.2I)
w

12.3 Transistors for Computer Memory

All computer memory integrated circuits are made from MOSFETs [1, 3, 5–7]. The two
computer types dynamic ransom access(DRAM) and flash. While the DRAM uses the
standard n channel p substrate(NMOS) as the basic memory cell, flash memory uses the
floating gate MOSFET. All memory is organized in rectangular arrays (Fig. 12.1a).

12.3.1 Transistors for Dynamic Random Access Memory (DRAM)

The DRAM uses a n channel p substrate as the memory cell. The MOSFET acts as a
switch between the bit line and a parallel plate storage capacitor. The charge stored on
the capacitor determines the state (ONE or ZERO) of the cell (Fig. 12.2b). The storage
capacitor is connected to the source and has a much larger capacitance than that of the
source body np junction. The stored charge connects to the bit line via the inversion layer
in the channel when the FET is switched on. The bit line is floating during this part of
the operation, so its voltage could change in response to the new charged state of the bit
line capacitance. All voltage changes are detected by a sense amplifier attached to the bit
line. In this discussion no voltage change means stored logic value ONE, whereas a slight
decrease in bit line voltage is associated with a stored logic ZERO.
In Fig. 12.2b the plate electrode of the capacitor is held at VD2 D . Labelling the actual
source potential as VS RC , the basic charge-sharing equation is:

VD D
C ST O R E VS RC − + C B I T VB I T = (C B I T + C ST O R E )VBPI T (12.3a)
2
214 12 Designing Transistors for Specific Applications

(a) (b)

(c) (d) (e)

(f) (g)

Fig. 12.2 a Generic memory layout and memory cell details. The dark rectangles represent indi-
vidual memory cells. b DRAM memory cell. c Floating gate NMOS for flash memory. d, e Energy
band diagram for equilibrium and write operation of a floating gate flash memory cell. f, g Energy
band diagrams for store and delete|erase operations of single level floating gate flash memory cell

When writing a ONE, the bit line voltage is raised by internal, charge pumping circuitry
to.
(VD D + VT H RS H )—i.e., when the word line is enabled, turning on the n channel pass
transistor, the source node rises to VD D . Thus,
VD D
VST O R E = (12.3b)
2

To read this ONE, the bit line is precharged to VD2 D and left floating as the transistor
is turned on. Charge sharing occurs, and the new bit line voltage is:

VD D C ST O R E + C B I T VD D
VB I T =
P
= (12.3c)
2 C ST O R E + C B I T 2
12.3 Transistors for Computer Memory 215

The bit-line voltage is unchanged, and this is interpreted as a ONE.

To write a ZERO to the cell, VB I T is set to 0, the word line is enabled, turning on the
pass transistor, and the source node falls to 0, implying that:
−VD D
VST O R E = (12.3d)
2

To read this ZERO, again the bit line is precharged to VD2 D and left floating as the
transistor is turned on. Charge sharing results in the bit-line voltage changing to:

VD D C ST O R E − C B I T VD D
VB I T =
P
< (12.3e)
2 C ST O R E + C B I T 2

The physical layout of the DRAM transistors, the word and bit lines have evolved
rapidly over the years, especially with sub-micron gate length NMOS transistors replacing
the previous micron gate length NMOS transistors.

12.3.2 The Floating Gate NMOS Transistor and Flash Memory

Unlike the DRAM memory, flash memory can retain the logic level(ONE|ZERO) in the
memory cell even after the power is switched off, made possible by the floating gate
NMOS (Fig. 12.2c).
The MOSFET in a flash memory cell has two polysilicon gates, one of which is
completely surrounded by insulating oxide, floating electrically. Programming the cell
is achieved by applying an appropriate voltage to the top control gate, via the word line.
With an appropriate applied voltage, electrons from the channel region punch through the
oxide layer below the floating gate and come to rest near the floating gate. The memory
cell is now storing a logic ONE. With another appropriate applied voltage, the electrons
are pushed out of the oxide layer below the floating gate, and so at the end a logic ZERO
is stored on that memory cell. The state of charge on the floating gate determines the
threshold voltage of the transistor and the magnitude of the drain current that will pass
into the bit line when the cell is probed. A current sensor in the bit line circuitry detects
this current, and interprets from it the state of the memory cell.
The floating-gate charge density Q F L O AT controls the channel charge density
Q electr on . Applying Gauss’s Law, or equivalently directly from the conservation of charge:

Q F L O AT + Q electr on + Q C O N T R O LG AT E = 0 (12.3f)

Thus, to maintain a given Q electr on in the presence of a change in floating gate charge
∆Q F L O AT , the change in control gate charge density is −∆Q F L O AT . The associated
change in control gate voltage follows from Gauss’s Law, and is the change in threshold
voltage:
216 12 Designing Transistors for Specific Applications

∆Q F L O AT ,G AT E −∆Q F L O AT t O X I D,T O P
∆VT H RS H = = (12.3g)
C O X I D E,T O P εO X I D E

The word line voltage to address the cell is not sufficient to alter Q F L O AT , so reading
the memory cell contents is non-destructive. If the read voltage is less than ∆VT H RS H ,
then the presence of charge on the floating gate puts the transistor in the OFF state. That
is, electrons stored on the floating gate is interpreted as the storage of logic ZERO in the
memory cell. The read voltage is such that it is greater than the threshold voltage when
Q F L O AT = 0. The transistor is switched on(ON state) and drain current is received at
the bit line: this is interpreted as storage of a logic ONE. Each memory cell carries one
bit of information. This is single level cell operation. If the floating gate charge could be
precisely controlled, then a variable threshold voltage would be obtained. This means that
different values of read voltage would be required to turn-on the transistor, depending on
the amount of floating charge present. This leads to multi level cell operation and the option
of increasing the number of stored bits per cell. If the drain current has a maximum and
minimum value.
(i D,M AX , I D,M I N ), change that can be detected by the sensing circuitry is ∆I D , then
the number of possible bits is.

I M AX
n B I T = log2 1 + (12.3h)
∆I

Obviously, fabrication of a multi level flash memory cell is a challenging task.

The energy band diagrams corresponding to each of the four states(equilibrium, write,
store and delete) of a single level floating gate flash memory cell are in (Figs. 12.2d, e, f,
g).
Thus for DRAMs, NMOS transistors must be sized so that a very large number can fit on
a single die—else state-of-art 8GB etc., DRAM capacities would be impossible. For flash
memories each NMOS transistor must have at least one floating gate, in addition to be being
able to be densely packed on the same die.

12.4 Transistors for Ultra High Frequencies (RF|Microwave)

While the large signal equivalent circuit model is essential for analyzing the DC and
switching applications of a transistor, the small signal model is essential for analysing
the ultra high frequency performance characteristics [1, 8–16]. The two key ultra high
frequency performance metrics of a transistor are the maximum and transition frequen-
cies f M AX , f T . A RF|microwave transistor has unity current gain at the transition
frequency. At the maximum frequency the RF|microwave transistor has unity power
gain. The small signal model is the linearized version of the large signal model.
For a generic transistor, the total current at any of its three terminals has both a DC
and a AC component expressed as:
12.4 Transistors for Ultra High Frequencies (RF|Microwave) 217

i j (t) = i j,DC + i j, AC (t)

j = C O L L EC T O R ∨ D R AI N , B AS E ∨ G AT E, E M I T T E R ∨ S OU RC E
(12.4a)

For analysis purposes, j = 2 and the current to be analyzed is the collector current(BJT,
HBT) or drain current(FET, HEMT). All voltages are referenced with respect to the the
emitter(BJT, HBT) or source(FET, HEMT). Like the current, the voltage at any of the
three terminals(base,collector, emitter|gate, drain, source) has both a DC and AC com-
ponent. These currents are linearized by expanding the corresponding expression in a
Taylor’s series.
 
i 2 = I2 V21,DC v21, AC + V31,DC v AC,31
  ∂ I2 v21, AC ∂ I2 v31,AC
= I2 V21,DC , V31,DC + + (12.4b)
∂ V21,DC ∂ V31,DC

Identifying:
∂ I2 ∂ I2
g22 = g23 = i 2 = I2 + g22 v21 + g23 v31 (12.4c)
∂ V21,DC ∂ V31,DC

where I2 is the DC current. Using identical analysis,

∂ I3 ∂ I3
g33 = g32 =
∂ V31,DC ∂ V21,DC
i 3 = I3 + g33 v31 + g32 v21 (12.4d)

Restricting the Taylor series expansion to produce a linear relationship, means that
the second and higher order terms can be neglected. For FETs, this assumption is valid
as i 2 = i D which is already linear in v31 = vG AT E,S OU RC E in the saturation region of
operation, and v21 = v D R AI N ,S OU RC E in the linear|resistive region, and the exponent of
any relations in the saturation regime never exceeds 2. However, for bipolar devices,
i 2 = i C O L L EC T O R which depends exponentially on v31 , so the linearization is possible if
def
the magnitude of the small signal is v31 = v B E << 2kqB T which is 40 mV at 300 K.
The equivalent circuit representing the small-signal components is shown in Fig. 12.3a.
Often the two generator equivalent circuit is converted to a one generator circuit
Fig. 12.3b.
The conductor in the top branch of the circuit is real. g32 is called the reverse feedback
conductance. Its magnitude is much smaller than the other conductances, so it is common
practice to name the other conductances as follows:

input conductance g33 ≈ g33 + g32 transconductance g23 = g23 − g32 out put conductance g22 = g22 + g32
(12.4d)
218 12 Designing Transistors for Specific Applications

Fig. 12.3 a Generic small (a)

signal model of bipolar
transistor, e.g., HBT. b Hybrid
pi model of high frequency
bipolar transistor. c Simplified
hybrid pi model of high
frequency bipolar transistor,
ignoring collector emitter
resistances, as being small (b)
compared to base resistance

(c)

Previously introduced term transcapacitance(the effect of terminal 2 on terminal 3

during charging of the capacitor is different from the effect of terminal 3 on termi-
nal 2), has its parallel for transport currents—transconductance. Transport currents are
those currents that involve only conductive components. Transconductance is denoted and
defined as:
def ∂ I2
gm = g23 − g32 ≈ (12.4e)
∂ V31
where I2 is the DC collector-emitter|drain-source current and V31 is the DC base-
emitter|gate-source voltage. In practice, g23 >> [g32 ]. The generic small signal model
of a transistor is in Fig. 12.3c. The capacitors (parasitic and real) and resistors in a real
heterogeneous junction bipolar transistor are shown in Fig. 12.3d.
The resistors quasi neutral emitter and collector resistors and the path resistances fol-
lowed by the collector current to the actual collector contact; and the resistance of the
base. The base resistor consists of an access resistance (R B, ACC E SS ) due to the path
from the base contact to the edge of the base quasi neutral region and base spreading
resistance (R B,S P R E AD ) that controls the spreading nature of the resistance in the quasi
neutral base. Transferring the resistors and capacitors to the hybrid-π circuit generates
12.4 Transistors for Ultra High Frequencies (RF|Microwave) 219

(a) (b)

(c) (d)

(e)

(f) (g)

Fig. 12.4 a Energy band diagram for avalanche breakdown. Dark dots are electrons. db Abrupt np
junction charge density and electric field. c High frequency and power HBT layered structure. e High
power and frequency GaN field effect transistor. Charge carrier movement inside GaN field effect
transistor. Internal structure of two common high frequency and power MOSFETs. f, g For the IGBT,
the bipolar transistor with base connected to cathode conducts when the MOSFET switches on
220 12 Designing Transistors for Specific Applications

the HBT’s hybrid model—Fig. 12.3e, which shows a HBT biased in the active mode of
operation, So g32 ca be ignored.. The output conductance is omitted because it has a near-
infinite value in the active mode. Transcapacitance is not an issue in HBTs, for junction
and storage capacitances.
The input conductance is gπ , the base emitter capacitance is Cπ , and the base collector
junction capacitance is Cμ . The AC short-circuit at the output is the effective result of
holding VC O L L EC T O R,E M I T T E R constant. The transition frequency f T , is determined
under this condition.

12.4.1 Transition Frequency f T Definition and Expression

The transition frequency is the extrapolated unity current gain frequency. The exper-
imental data for the frequency dependency of the square of the magnitude of the current
| |2
gain iiCB of an HBT shows that. the measured data ends at a certain frequency that is the
upper bandwidth limit of the capabilities of the measuring equipment. But for a decade or so
before this frequency limit, the gain rolls off at − 20 dB/decade, implying a RC circuit with a
dominant single pole. The gain can be extrapolated at this slope to higher frequencies, and
the frequency at which the gain becomes unity (0 dB), is called the extrapolated transition
frequency or transition frequency. The transition frequency is one of two key performance
metrics of any high frequency transistor.
Current gain measurement is performed with the collector and emitter terminals held
at constant potentials—for the AC signal the emitter is shorted to the collector. Then.
 
i B = gπ + j ωC pi v B E + j ωC pi v BC i C = gm v B E − j ωCμ v BC (12.4f)

To eliminate v B R from (12.4f) it can be re-expressed as below, given that the current
gain must be much larger than unity:

v BC = v B E + v EC = v B E + i E R E + i C RC v BC
iC RE
= v B E + (i B + i C )R E + i C RC ≈ v B E + i C (RC + R E ) >> (12.4g)
iB RC + R E
Then the collector current can be re-expressed as follows and the conditions for its
validity are:
   2  2
gm − j ωCμ v B E gm + ω2 Cμ2 vbe
iC = |i C | =
2
1 + j ωCμ (RC + R E ) 1 + ω2 Cμ2 (RC + R E )2
2
gm 1
A : ω2 << B : ω2 << (12.4h)
Cμ2 Cμ2 (RC + R E )2
12.4 Transistors for Ultra High Frequencies (RF|Microwave) 221

Similarly, the square of the magnitude of the base current and the condition for its
validity is:
  2 
|i B |2 = gπ2 + ω2 Cπ + Cμ (1 + gm (RC + R E ))
gπ2
v 2B E C : ω2 >>  2 (12.4j)
Cπ + Cμ (RC + R E )

The current gain and consequently the transition frequency are:

I I
I iC I 2
gm
I I=  2 2π f TRANSTION
Ii I
B ω2 C x + Cμ (1 + gm (RC + R E ))
gm
= 2  (12.4k)
ω C x + Cμ (1 + gm (RC + R E ))

An ultra high frequency HBT is designed using simple expressions involving the analysis
for the transition frequency. The analysis starts with dividing the HBT into separate regions
and then estimating the time taken by the input signal to traverse each of the regions. The
reciprocal of the transition frequency is called signal delay time τ EC , defined as:

1 Cπ + Cμ (1 + gm (RC + R E ))
τ E M I T T E R,C O L L EC T O R = =
2π f T R AN S I T I O N gm
P P P 
C E,B, J C E,B, j C E,B,t 1
τ E M I T T E R,C O L L EC T O R = + + + CC,B R E,C +
P
gm gm gm gm
τ E M I T T E R,C O L L E T O R = τ B AS E + τC O L L EC T O R + τ E M I T T E R + τCC
(12.4m)

The signal delay from the quasi neutral base region is:

W B AS E W B AS E 1
τ B AS E = + (12.4n)
2 Delectr on vR

The signal delay from the change in field in the base—collector depletion region due
to the passage of the electrons carrying the signal current is:
w B AS E,C O L L EC T O R D E P L E T I O N
τC O L L EC T O R = (12.4p)
2v S AT U R AT I O N
Charging the base–collector junction capacitance via the dynamic and parasitic
resistances introduces delay:

ε A ACOLLECTOR 1 wEMITTER wCOLLECTOR
τCC = + +
w gm AEMITTER σEMITTER ACOLLECTOR σCOLLECTOR
(12.4q)
222 12 Designing Transistors for Specific Applications

Finally, the emitter signal delay is the time taken to charge the base-emitter junction
capacitance via the dynamic resistance ( g1m ) of the transistor is:

ε S E M I C O N DU C T O R A E M I T T E R
τE M I T T E R = (12.4r)
gm w E M I T T E R
Ultra high frequency performance depends on device dimension scaling. Lateral scal-
ing reduces collector, emitter areas. Vertical scaling reduces the base width and the
base–collector depletion region width w. In high performance InGaP/GaAs HBTs, for
example, the base width is so short (about 50 nm) that the major delay in the device is
shared by the two delays associated with the collector. Trade-offs must be made regard-
ing w as it affects τC , τCC differently. The delays must become very short, e.g., for
transition frequency of 800 GHz, the overall signal delay must be ≈ 2x10−12 s.

12.4.2 Unity Power Gain Frequency f M AX Definition and Expression

The expression for the transition frequency does not contain the base resistance, because
f T relates to the current gain, and any desired current can be forced through any resis-
tance, provided enough voltage can be applied. This is impossible in real world bipolar
transistors there are limits to the available input voltage. To account for this limitation,
an extrapolated frequency related to the power gain - f M AX is used, for the power gain
that rolls off with frequency at − 20 dB/decade. Extrapolating the gradient of power
gain, to a power gain of 0 dB yields f M AX .
The simplified hybrid π model of a HBT is in Fig. 12.2f. In this simplified model,
the collector and emitter resistances are much smaller than the base resistance, and thus
ignored. Also, the input conductance is ignored because the frequency at which the
extrapolation is to be made is so high that the following condition holds.

gπ2
ω2 >> (12.4s)
Cπ2

From the Thevenin equivalent circuit of the simplified hybrid π circuit, the input
impedance and voltages are:
   
R B + j ω Cμ + Cπ
1
v I N PU T j ωCμ − gm
vT H V N = ZT HV N =  
j ωCμ (1 + gm R B ) − ω2 Cμ Cπ R B j ωCμ gm + R1B − ω2 Cμ Cπ
(12.4t)

Using conjugate impedance matching conditions yields expressions that can only hold
if the corresponding conditions apply:

Z C I RC L = Z T H V N + Z L O AD ≈ 2Z T H V N (Z T H V N )
12.4 Transistors for Ultra High Frequencies (RF|Microwave) 223

Cμ + Cπ 1 gm + R1B
= Cπ ≈ Cπ + Cμ gm >> ω2 << (12.4u a,b)
Cμ gm RB Cπ

The RMS value of the Thevenin voltage holds only if the following conditions apply:

|vINPUT |2 2
gm 2
gm 1
|VT H V N |2 ≈  2 ω << 2 ω << 2 gm >>
2 2
(12.4v)
ωCμ R B Cμ Cs RB

Combining the above expressions, the maximum output power is:

|VT H V N |2 gm |vINPUT |2
POUT ,M AX = =   (12.1w.a)
4Z L O AD 4ω2 Cμ Cμ + C x R 2B

Using the previous assumption that C T ≈ Cπ the input impedance is.

j
Cμ << Cπ Z I N PU T ≈ R B − (12.4w b)
ωCπ
Thus the input power and maximum available gain(MAG) can be evaluated. The
frequency at which MAG = 1 is the extrapolated f M AX .

|vINPUT |2 POUTPUT, MAX

PINPUT, MAX ≈ M AG =
RB PINPUT, MAX
/
gm f T ,I N T R I N S I C
=   f MAX = (12.4w.c)
4ω2 Cμ Cπ + Cμ R B 8πCμ R B

where the intrinsic transition frequency is the transition frequency calculated by ignoring
parasitic resistances. So for ultra high frequency operation the transistor must have a good
very good intrinsic high frequency performance characteristics. Also, a low base resistance
1
to reduce absorption of the input power, and a high output impedance jωC μ
to reduce
feedback of power from the output. HBTs are perfectly suited to decreasing the base
resistance because the heterogeneous junction at the emitter–base interface can be specif-
ically designed to impede back injection of holes into the emitter. This allows the base
doping density to be increased, reducing the base resistance without compromising the
current gain. Reducing Cμ involves making the active part of the base–collector junction
as thin as possible. Base resistance is a sum of the intrinsic and spreading resistances.

12.4.3 fT , f M AX For Field Effect Transistors

The small signal, high frequency, equivalent circuit for field effect transistor follows
directly from the general hybrid π circuit (Fig. 12.3c, d), by noting that the bipolar tran-
sistor’s base, collector and emitter become gate, drain and source. Identical arguments
224 12 Designing Transistors for Specific Applications

hold for the parasitic capacitances. Similarly, the large signal models for the two tran-
sistor types can be correlated in a similar fashion. The input conductance is omitted,
indicating that there is no tunnelling or leakage through the oxide in the case of a MOS-
FET, nor any transport current in the Schottky diode of an heterogeneous junction FET.
Also, the reverse bias feedback conductance is ignored just like for the HBT. The output

conductance.
def
g22 = g D D has been retained because of the drain source channel resistance. There
are no circuit elements to represent the substrate, applicable to silicon-on-insulator(SOI)
field effect transistors. Using identical analysis as that used for HBTs, the extrapolated,
common-source, unity-current-gain frequency of FETs is.
gm
2π f T = (12.5a)
C G D (1 + g D D (R D + R S ) + C G D (1 + (gm + g D D )(R D + R S )))
A high transconductance is essential for high transistor frequency. Having a high mobility
helps—InP and GaAs HEMTs and MESFETs ideal for high frequency applications, specially
for HEMTs, where the high mobility o the starting semiconductor material is preserved by
the undoped channel material; confinement of the channel charge to a large extent, away
from the interface; undoped spacer layer of barrier material for electrons that do spread
into the barrier. The 2DEG is confined to a plane, and so there is no scattering in he third
direction.
d I2
Noting that gm ≈ dv , and that for a FET in the saturation mode is
31  n
I2 = I D R AI N ,S OU RC E,S AT U R AT I O N ∝ VG AT E,S OU RC E − VT H RS H 1 ≤ n ≤ 2. For a
V B AS E,E M I T T E R
HBT, IC ∝ e VT H E R M AL .
The corresponding tranconductances per unit current are.
gm n 1
= ( MOSFET ) = (H BT )VG S − VTHRSH = nVTHERMAL
I VG S − VTHRSH VTHFRMAI.
(12.5b)

At 300 K the operating voltage for the MOSFET is ≈ 50 mV, meaning that a very
low bias current. An even lower current could be tolerated if it is advantageous to operate
in the sub-threshold regime, in which an exponential drain source current vs. gate source
voltage holds. Then the transconductance per unit current ratio approximately equalling
that of HBTs is possible,
The FET unity gain power frequency is:
/
f T ,I N T R I N S I C
f M AX = 2π FT ,I N T R I N S I C (12.5c)
8πC DG R S

If the conditions required to derive this equation cannot be met, then it is still possible
to arrive at an expression for the power gain that rolls off at − 20 dB/decade, but the
12.5 Transistors for High Power (High Current and Voltage) and High Frequency 225

equation is much lengthier. The gate capacitance and resistance must be minimized. This
is achieved in modern MESFETs and HEMTs by using the ‘mushroom’ structure for the
gate. The small contact region between the gate metal and the underlying semiconductor
allows a short gate length to be achieved, and the wider top region keeps the access
resistance low.

12.5 Transistors for High Power (High Current and Voltage)

and High Frequency

Power amplifiers and switched mode power supplies need transistors [1, 17–21] to conduct
currents(10s of A or more), and to withstand high voltages(100s of V). So the struc-
tural details and properties of high power transistors are vastly different from those e.g.,
for computer memory etc., These types of high-power transistor include the GaAs HBT
and heterogeneous junction GaN FET for power amplification, and the Si MOSFET and
hybrid transistor for power supplies. High currents mean high carrier densities, which can
lead to a modification of the space charge region at the output junction (collector/base or
drain/body), with consequences for the frequency response and/or the breakdown voltage
(avalanche breakdown), and related high current, space charge modifying Kirk Effect.
Operating transistors at high VC O L L EC T O R,E M I T T E R , VD R AI N ,S OU RC E can lead to
electrical breakdown of the base collector or drain substrate junction, respectively, char-
acterized by sudden onset of a large current which, if not interrupted, can overheat the
junction and destroy it. The breakdown process in a reverse biased np junction is shown
in Fig. 12.4a. Electrons entering the high field of the junction rapidly gain kinetic energy.
If this energy is allowed to exceed the bandgap energy then after collision with a lattice
atom, an energy E ≥ E G A P can be transferred to another electron, thereby exciting it
into the conduction band. Thus, one electron creates another electron (and a hole). This
process is the generation equivalent of Auger recombination. The newly generated elec-
tron and hole are accelerated by the junction field, creating more electron hole pairs, and
a rapidly increasing current—a positive feedback system—avalanche breakdown. The
corresponding electric field at which avalanche breakdown is initiated, is termed as break
down field strength E B R . The break down electric field strength and the energy band gap
are correlated. The metrics for high power transistors are thermal conductivity, Johnson’s
figure of merit(JFOM) which characterizes devices for both high frequency and power
applications. The large bandgap semiconductor diamond comes out very well in both of
the above categories. In a np junction, the maximum electric field occurs at the interface
between the two differently doped regions. The left part of Fig. 12.4b shows the case
of an abrupt junction with uniform doping on each side of the junction, and under low-
current conditions. The right side shows a pn M n P where the M, P superscripts denote
‘minus’, ‘plus’. The left hand side diagrams are for a current density sufficiently low
for the space charge due to the mobile electrons to be negligible, and for the n M (“epi”)
226 12 Designing Transistors for Specific Applications

layer to be just fully depleted. The diagrams on the right are for the case when this mobile
charge is sufficient to reduce the electric field at the pn M interface to zero. The depletion
region penetrates the n P layer, the sub-collector. The applied bias is the same in both
sets of figures. The electric field and the break down voltage value(with the Depletion
Approximation) are:

2(VB I + V A P P ) εE 2B R 1 1
Ex = VB R = + (12.6a)
W 2q N ACC E P T O R NDO N O R

This pn M n P structure arises at the base–collector junction in Npn HBTs, and in the
drain-substrate region of lateral diffused MOSFETs. The lightly doped region is usually
deposited by vapor phase epitaxy—the “epi” layer. The electric field profile in|around the
epitaxial layer, and how it responds to an increasing electron current is very important,
and is analyzed as a one dimensional problem. A HBT in the forward active operation
mode has electrons injected from the emitter which pass through the p type base into
the lightly n doped epitaxial layer. Then these electrons are collected in the heavily n
doped sub-collector region. Ignoring holes in the epitaxial layer, Poisson’s equation in 1
dimension gives:
 
dE q Nn,epitaxial − v S AT UJRCAT I O N
= (12.6b)
dx ε E M I C O N DU C T O R
where the electrons are moving in the epitaxial layer at their saturation velocity. For low
def
collector current density JC the field gradient is positive for x > 0. At JC = JCRITICAL =
q Nepi v S AT the field becomes constant. At higher collector current densities the field gra-
dient in the epitaxial layer becomes negative for x > 0. Then the effect of the positive
space charge of the donor ions in the epitaxial layer is overcome by the negative space
charge of the electrons carrying the current. At a critical current density the field goes to
zero at the base|epitaxial layer boundary. The current density at which the field disappears
at the p—epitaxial layer junction is known as the Kirk current JK I R K . The onset of the Kirk
Effect can be delayed by using a semiconductor for which saturation velocity is high, and
by choosing a high doping density for the epitaxial layer. Kirk effect is unavoidable: if
the epitaxial layer thickness is reduced to zero, then the breakdown becomes very severe.
With ever increasing carrier frequencies for both wired and wireless telecommunica-
tion networks, power transistors must be able to handle both high current|voltages and
ultra high frequencies—e.g., transistors used in cellphone repeater amplifiers. InGaP/
GaAs HBTs, and AlGaN/GaN heterogeneous junction FETs are best. HBTs operating
at modest voltages and power, are used in the transmitter stage of cellphones, and final
stages of power amplifiers In radio base stations, where operation is at tens of volts and
hundreds of watts. GaN based heterogeneous junction FETs are also used for these appli-
cations. These FETs are used for electronic circuits operating in harsh environments due
to the high bandgap of the transistor material.
12.5 Transistors for High Power (High Current and Voltage) and High Frequency 227

The structure of a high power, high frequency HBT is shown in Fig. 12.4c. The semi-
conducting material are chosen for their high charge carrier mobility. Device fabrication
tricks as interdigitated emitter and base contacts facilitate a large current flow via the
large total emitter area. Simultaneously, reducing base access, controlling base spreading
resistance and a thick, lightly doped collector ensures a high breakdown voltage. Split-
ting the base current between three contacts reduces the power dissipation in the base
spreading resistance to 1/12 of its value in the single base case. A tall emitter separates
the emitter and base metallizations. The thick top part of the emitter reduces the parasitic
emitter resistance. The thick, lightly doped collector allows a high break down voltage to
be achieved to over a high JC R I T . At JC = JC R I T there is no field at the base–collec-
tor junction. There is no potential barrier to stop the holes from leaving the base. If the
collector current density increases more, holes flood into the epitaxial layer, widening the
quasi neutral base region. This increases the base transit time. The reduced width of the
base—collector space charge region could enhance the collector signal delay time, but this
is counter balanced by the increase in the collector charging time. So τ EC increases and
the transition frequency f T decreases at high currents. Before the onset of Kirk Effect,
the transition frequency increases as the transconductance improves.
∂ IC O L L EC T O R IC O L L EC T O R
gm ≈ = (12.6c)
∂ VB AS E,E M I T T E R γ (IC O L L EC T O R )VT H E R M AL

where γ is the junction ideality factor. At emitter current densities(that induce recom-
bination in the emitter–base space charge region) can be neglected, γ = 1, while low
level injection conditions apply. In high injection conditions, assuming that the injected
minority carrier concentration at the edge of the depletion region in the base of an Npn
 
transistor is such that n xd p = p p0 .

  VA P P   VA P P
n xd p p p0 = n i2 e VT H E R M AL n xd p = n i e 2VT H E R M AL (12.6d)

Minority carrier concentration increase is matched by a corresponding increase in

majority carrier concentration to maintain charge neutrality—conductivity modulation.
At the collector end of the base the minority carriers are extracted, so that there are large
concentration gradients of both electrons and holes. Thus both electrons and holes will
diffuse at different rates—ambipolar diffusion. As a result an induced electric field retards
the diffusion of the faster carrier. Diffusion dominates, with an high effective effectively
diffusivity—Webster Effect. Under appropriate operating conditions, a diffusive electron
current with the boundary condition of (12.6d) results in an ideality factor of γ = 2, and
reduces the transition frequency at high currents. As the channel ideality factor increases
the current the same channel decreases. This is a very interesting but complicated charge
carrier transport mechanism involving isothermal|non-isothermal drift diffusion and
isothermal|non-isothermal energy balance.
228 12 Designing Transistors for Specific Applications

Electrons injected into the high field region of the reverse biased base collector space
charge region are accelerated to velocities above the saturation velocity, before thermalizing
collisions occur—reducing the signal delay time in the collector space charge region and
consequently improving the transition frequency. The increased velocity also increases the
current.
Gallium nitride(GaN) based high power heterogeneous junction FETs have two
material properties that are superior to those of GaAs—breakdown field strength and
thermal conductivity. The high electron saturation velocity is also key to high frequency
applications in devices where the field is high enough for this velocity to be attained.
The layered structure of a sample GaN heterogeneous junction FET is in Fig. 12.4d.
The gate length and the separations between gate and source|drain electrodes are about
100–500 nm. The operating voltages are about 28 V for wireless base station applica-
tions, so velocity saturation is likely. An AlGaN surface is electrically active, so that
a passivation layer such as silicon nitride is essential. The gate electrode extends over
the passivation layer towards the drain, forming a field plate. This reduces the field in
the channel at the edge of the gate, thereby improving the breakdown voltage. But the
field plate adds capacitance to the device, undesirable for high frequency performance.
This can be curbed by recessing the gate, as a result of increasing the transconductance
through the closer coupling of the gate to the channel a two dimensional electron gas at
the AlGaN|GaN interface. A common substrate material is silicon carbide(SiC), which
has excellent thermal conductivity. A buffer layer of GaN is deposited before epitaxial
growth of the actual layers of the device, which crystallize in the wurtzite(hexagonal
close packed lattice) structure. Crystal growth is along the c-axis, from the {0001}
basal plane in the [0001] direction. The atoms are arranged in two, repeating, closely
packed bilayers, each layer of which is an hexagonal arrangement of either gallium or
nitrogen ions. The GaN bond is strongly ionic, with nitrogen more electronegative than
gallium. Thus the material is spontaneously polarized, with the polarization vector point-
ing towards the substrate. For the ternary material Al x Ga1−x N the lattice constant is
approximately a = (0.3189 − 0.0077x)nm. Therefore, AlGaN grown pseudomorphically
on GaN is under tensile strain, adding a piezoelectric polarization PP z to the spontaneous
polarization that is inherent to the material. The situation for AlGaN on Ga-face GaN
is in Fig. 12.4e. The surface polarization charge densities are negative on the top of the
AlGaN and positive on the bottom of the GaN. At the interface between the two materials
the surface polarization density is:
 
σ I N T E R F AC E = PS P O N T AN E OU S,2 + PP I E Z O E L EC T R I C,2 · n̂ 2
+ PS P O N T AN E OU S,1 · n̂ 1 (12.6e)

The sheet polarization charges are bound charges fixed in space. Th electrons are drawn
to the interface during the period of cooling after the growth of the layers or from the
ohmic contacts in the fabricated heterogeneous junction FET. So a two dimensional sheet
12.5 Transistors for High Power (High Current and Voltage) and High Frequency 229

of electrons is created at the interface without doping either of the layers. The two
dimensional gas consists of electrons confined in a potential notch, one side of which is
due to the electron affinity mismatch between the two materials. The relation expressed
in terms of the mole fraction x for Al, is χ (x) = 4.1 − 1.87 × eV. A typical value is
x = 0.15, gives a barrier of about 0.28 eV, while also maintaining the lattice constant
mismatch to be within appropriate tolerances. The spontaneous and piezoelectric polar-
izations in AlGaN are so large that the surface concentration of electrons at the interface
13
is approximately 10 cm 2
giving AlGaN|GaN heterogeneous junction FETs a high current
carrying capability. Also, the large bandgap and breakdown voltage allow operation at
typical base station voltage levels of 28 V. Thus additional voltage conversion circuitry is
unnecessary. These properties in combination with high electron velocity and high thermal
conductivity produce a transistor with for power amplifiers operating at high frequencies.
Power transistors used in high current|voltage DC-DC converters are used as a switch.
When the switch is closed the transistor needs to pass a large current. As this current is
derived from the input voltage source, the ON resistance of the transistor must be low,
to curb unwanted power dissipation within the transistor. When the switch is open, the
transistor must be able to withstand a voltage at least equal to that of the output voltage—
specified by the forward blocking voltage. The transistor must be able to switch quickly
between the ON and OFF states. As bipolar transistors are current controlled devices, the
pulse width modulated control circuitry for duty cycle adjustment becomes very complex.
Also, to get the required low ON resistance, bipolar transistors must be operated in the
saturation mode.
However MOSFETs, which are voltage controlled devices need simpler pulse width
modulation control circuitry and are unipolar, so switching times are not determined by
slow recombination processes. So field effect transistors are now the choice for power
supply designers.
The two MOSFETs specifically designed for high power and high frequency switching
applications are the Laterally Diffused MOSFET(LDMOS) and the Insulated Gate Bipolar
Transistor(IGBT)—Fig. 12.4f, g For the LDMOS, the source is embedded in a p well,
and these two regions are formed in a sequential diffusion process—hence ‘diffused’
in the transistor title. ‘Lateral’ comes from the lateral layout of the device, allowing
three terminal contacts on the top of the structure. The lateral arrangement enables the
integration of the power transistor with standard CMOS FETs, which can be used for the
control circuitry. The drain consists of the usual n + contact region, and a lightly doped
drain extension in the form of an n epitaxial layer grown on the p substrate. The junction
between the p well and the epitaxial layer forms a pn diode, and the junction between the
epitaxial layer and the p substrate forms a second diode.
The breakdown voltage of the first pn diode is given by 12.6a, with the carrier con-
centrations Nepi , N pwell . The low value for epitaxial layer doping concentration ensures
a low ON resistance. The ON resistance is determined by the lateral resistance of the epi-
taxial layer. A thin epitaxial layer is advantageous because of a two dimensional reduced
230 12 Designing Transistors for Specific Applications

surface field (RESURF) effect. At the second diode junction, the space charge region
extends into the n epitaxial layer by a distance approximately given as:
/  
2ε S E M I C O N DU C T O R N SU B ST R AT E VB R,J U N C T I O N 1 + VD R AI N ,S OU RC E
ysn =  
q Nepitaxial Nepitaxial + N SU B ST R AT E
(12.6f)

The key is to choose the thickness of the epitaxial layer to be less than ydn at the
desired forward blocking voltage. Then the depletion region from the second pn junction
reaches through to the surface of the FET and augments the depletion region surrounding
the first depletion region—effectively extending it in the x-direction. The voltage drop
across the first pn junction is spread over a longer region, and so reduces the electric field
E x below E B R E AK , shifting the region of likely breakdown to the second pn junction.
By making N SU B ST R AT E < Nepi , the breakdown voltage at the second pn junction
can extend the breakdown voltage of the first pn junction, increasing the forward blocking
voltage. But a parasitic n P LU S pn M I NU S BJT formed by the source-substrate-epitaxial
regions, and if the current is high enough, the Kirk Effect will come into play and influence
the voltage distribution in the structure. In the LDMOS the point of highest field moves
to the n P LU S n M I NU S junction between the drain and epitaxial layer regions, and this
determines the breakdown voltage. The LDMOS is an interesting design problem involving
the choice of epitaxial layer thickness and doping concentrations and the interaction between
blocking voltage and operating current.

12.6 Low Noise Transistors

The reader is requested to refer to a previous chapter dedicated to semiconductor device

noise mechanisms.

12.7 Figures of Merit for High Power and High Frequency

Transistors

As power diodes and transistors have to operate reliably with very high currents and
voltages, the power semiconductor device industry has adapted a set of figures of merit
to characterize the performance characteristics of these devices. These are:

• BFM: Baliga’s figure of merit—a measure of the specific on-resistance of the drift
region of a vertical field effect transistor. A related figure of merit is for high frequency
transistors
• BSFM: Bipolar transistor switching speed figure of merit
References 231

• BPFM: Bipolar transistor power handling capacity figure of merit

• BTFM: Bipolar power transistor switching product
• FPFM: Field effect transistor power handling capacity figure of merit
• FSFM: Field effect transistor switching speed figure of merit
• FTFM: Field effect transistor power switching product
• JFM: Johnson’s figure of merit denotes the power frequency product for low power
transistors
• KFOM: Keyes’ figure of merit denotes the thermal limitation to switching transistors
inside integrated circuits

The Baliga figure of merit identifies material parameters that minimize conduction losses
in low frequency unipolar transistors. The Baliga high frequency figure of merit indicates
that using silicon carbide(SiC) devices for high frequency applications can significantly
reduce power loss.
/
VG AT E
B F O M = εr μE G 3
A P B H F F O M = μE B R E AK
2
(12.7a)
4VB3 R E AK
 /
E B R E AK velectr on,saturation 2 cvelectr on,saturation
J FOM = K FOM = κ
2π 4π ε ST AT I C
(12.7b)

The other listed figures of merit are semiconductor device manufacturer specific, i.e.,
some figures of merit are quoted by some vendors, but not by others.

References

1. Sze, S. M. (2008, January). Physics of semiconductor devices, 3rd Edition. Retrieved form
https://www.amazon.in/Physics-Semiconductor-Devices-3ed-S-M/dp/8126517026/ref=sr_1_
1?qid=1670906380&refinements=p_27%3AS.M.+Sze&s=books&sr=1-1
2. Tsividis, Y. (1999). Operation and modeling of the MOS transistor, 2nd Edn., Sec. 9.2.1, Oxford
University Press.
3. Pulfrey, D. L., & Tarr, N. G. (1989). Introduction to Microelectronic Devices, Prentice-Hall.
4. John, D. L. (2008). Limits to the signal delay in ballistic nanoscale transistors. IEEE Transac-
tions on. Nanotechnolgy, 7, 48–55.
5. Streetman, B., & Banerjee, S. Solid State Electronic Devices 7th Edition https://www.amazon.
com/Solid-State-Electronic-Devices-7th/dp/0133356035/ref=sr_1_1?qid=1670906725&refine
ments=p_27%3ASanjay+Banerjee&s=books&sr=1-1
6. Trinh, C. et al. (2009). A 5.6MB/s 64Gb 4b/cell NAND flash memory in 43 nm CMOS. ISSCC
Digest Technology Papers, 246–248.
7. Schloesser, F. et al. (2008). A 6F 2 Buried Wordline DRAM Cell for 40 nm and beyond. IEEE
IEDM Technology Digest, p. 33.4.
232 12 Designing Transistors for Specific Applications

8. Hafez, W., Snodgrass, W., & Feng, M. (2005). 12.5 nm base pseudomorphic heterojunction
bipolar transistors achieving fT = 710 GHz and fmax = 340 GHz. Applied Physics Letters, 87,
252109.
9. Hafez, W., & Feng, M. (2005). Experimental demonstration of pseudomorphic heterojunction
bipolar transistors with cutoff frequencies above 600 GHz. Applied Physics Letters, 86, 152101.
10. Liu, W. (1999). Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs,
pp. 226–231, John Wiley & Sons Inc.
11. Vaidyanathan, M., Pulfrey, D. L. (1999). Extrapolated fmax for Heterojunction Bipolar Transis-
tors. IEEE Transactions on Electron Devices, 46, 301–309.
12. Lee, S., Wagner, L., Jagannathan, B., Csutak, S., Pekarik, J., Zamdmer, N., Breitwisch, M.,
Ramachandran, R., & Freeman, G. (2005). Record RF performance of Sub-46 nm L gate NFETs
in microprocessor SOI CMOS technologies. IEEE IEDM Technology Digest, 241–244.
13. Yamashita, Y., Endoh, A., Shinohara, K., Hikosaka, K., Matsui, T., Hiyamizu, S., Nimura, T.
(2002). In 0.52 Al 0.48 As/In 0.7 Ga 0.3 As HEMTs with an Ultrahigh f T of 562 GHz. IEEE
Electron Device Letters, 23, 573–575.
14. Castro, L. C., & Pulfrey, D. L. (2006) Extrapolated fmax for CNFETs. Nanotechnology, 17, 300–
304.
15. Gonzalez, G. (1984). Microwave transistor amplifiers: analysis and design, (2nd Edn.)
Chapter 1, Prentice-Hall.
16. Mason, S. J. (1954). Power gain in feedback amplifier. IRE Trans. Circuit Theory, 1, 20–25.
17. Ho, S. C. M., & Pulfrey, D. L. (1989). The effect of base grading on the gain and high-frequency
performance of AlGaAs/GaAs heterojunction bipolar transistors. IEEE Transactions on Electron
Devices, 36, 2173–2182.
18. Baliga, B. J. Fundamentals of Power Semiconductor Devices. Retrieved from https://www.ama
zon.in/Fundamentals-Semiconductor-Devices-Jayant-Baliga/dp/3319939874.
19. DiSanto, D. (2005). Aluminum Gallium Nitride/Gallium Nitride High Electron Mobility Tran-
sistor Fabrication and Characterization, Table 1-1, Ph.D. Thesis, Simon Fraser University.
20. Johnson, E. O. (1965). Physical limitations on frequency and power parameters of transistors.
RCA Review, 26, 163–177.
21. Apanovich, Y., Blakey, P., Cottle, R., Lyumkis, E., Polsky, B., Shur, M., & Tcherniaev, A.
(1995). Numerical simulation of submicrometer devices including coupled nonlocal transport
and nonisothermal effects. IEEE Transactions on Electron Devices, 42, 890–898, 298.
22. Ambacher, O., Smart, J., Shealy, J. R., Weimann, N. G., Chu, K., Murphy, M., Schaff, W. J.,
Eastman, L. F., Dimitrov, R., Wittmer, L., Stutzmann, M., Rieger, W., & Hilsenbeck, J. (1999).
Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges
in N- and Ga-face AlGaN/GaN heterostructures. Journal of Applied Physics, 85, 3222–3233.
23. Ludikhuize, A. (2000). A review of RESURF technology, proceedings of. 12th IEEE Interna-
tional Symposium on Power Semiconductor Devices and ICs, pp. 11–18.
Performance Characteristics of Selected
Commercial Heterogeneous Transistors
13
and TCAD (Technology Computer Aided
Design) Tools

13.1 Test Bench

The generic test bench used for the both AC|DC characteristic measurement of the high
performance transistors is in Fig. 13.1. All current measurements were done with a Keith-
ley 6485 picoammeter [5]. A Keithley 2230G-30–1 programmable triple output DC power
supply was used to provide the collector|drain and base|gate voltages [6, 7]. The col-
lector|drain and base|gate resistances were selected using the corresponding transistor’s
datasheet “Maximum Absolute Ratings” table information provided by the device manu-
facturer [1–4]. All DC sweep measurements(Ice|Ids vs Vbe|Vgs or Ice|Ids vs. Vce|Vds
were performed with continious and pulsed DC power modes. In the Ice vs. Vbe contin-
ious Vce mode, the Vbe voltage was swept over the specified range(as per device datasheet)
at different Vce levels(as per device datasheet). For the corresponding pulsed Vce, Ice vs.
Vbe measurement, the Vce was applied as pulses, with the pulse amplitudes the same as in
the continious DC measurement case. As each RF transistor has parasitic capacitors and
inductors, pulsed DC measurement allows these parasitic components to be discharged
when the applied DC pulse amplitude is zero.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 233
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_13
234 13 Performance Characteristics of Selected Commercial Heterogeneous …

Fig. 13.1 Generic test bench for RF|microwave transistors. The test bench components for RF
only(network analyzer, sampler, tuner, BTEE) are not essential for DC sweeps (Ids—Vgs @ constant
Vds and Ids – Vds @ constant Vgs

13.2 BFQ790 Heterogeneous Junction (SiGe) Medium Power NPN

RF Transistor

The BFQ790 SiGe transistor is a heterogeneous junction silicon germanium (SiGe)

medium power RF NPN device from Infinieon Technologies AG [1]. The results of the
DC sweep measurements are shown in Fig. 13.2a, b, c, d, e and f.

13.3 TP65H150G4LSG Heterogeneous Junction Gallium Nitride

(GaN) Power FET

The TP65H150G4LSG is a gallium nitride(GaN) heterogeneous junction power field

effect transistor[3] with an upper voltage limit of 650 V. The DC performance charac-
teristics are shown in Fig. 13.3a, b, c, d and e.

13.4 EPC2216 GaN Power FET DC Performance Characteristics

The EPC2216 is another GaN power FET whose DC performance characteristics are
shown in Fig. 13.4a, b, c, d and e.
13.4 EPC2216 GaN Power FET DC Performance Characteristics 235

(a)

(b)

(c)

Fig. 13.2 a Gummel plot(Ibe, Ice vs. Vbe) for BFQ790, b Collector current(Ice)—base emitter
voltage(Vbe) at continuous collector emitter voltage(Vce) for BFQ790. c Collector current(Ice)—
base emitter voltage(Vbe) at pulsed collector emitter voltage(Vce) for BFQ790. Current collapse,
compared to continuous collector emitter voltage case is evident. d Collector current(Ice)—col-
lector emitter voltage(Vce) at continuous base emitter voltage(Vbe) for BFQ790. e Collector cur-
rent(Ice)—collector emitter voltage(Vce) at pulsed base emitter voltage(Vbe) for BFQ790. Current
collapse compared to continuous base emitter voltage case is evident. f Transconductance -collector
current(Ice) for BFQ790
236 13 Performance Characteristics of Selected Commercial Heterogeneous …

Fig. 13.2 (continued) (d)

(e)

(f)

13.5 NE34018 Gallium Arsenide (GaAs) Field Effect Transistor

This GaAs FET operates in the RF|microwave frequency range [4], whose typical DC
performance characteristics are in Fig. 13.5a, b, c and d.
The transistors used in the author’s laboratory test bench for generating the DC sweep
curves were obtained as test samples from the respective manufacturers.
13.6 Technology Computer Aided Design (TCAD) Tools for Analyzing, … 237

13.6 Technology Computer Aided Design (TCAD) Tools

for Analyzing, Estimating and Visualizing Internal Electrical
Properties of Semiconductor Devices

In the recent past, a number of open source [8–10] and commercial [11, 12] Technology
Computer Aided Design (TCAD) tools have become sophisticated enough to analyze,
estimate and visualize key internal electrical properties of semiconductor devices
(e.g., charge carrier density, charge carrier energy, electrical potential, electric field (x,y
components), charge carrier velocity etc.,) Notable among the open source versions are

Fig. 13.3 a Drain (a)

current(Ids)—gate source
voltage(Vgs) continuous drain
source voltage(Vds) for
TP65H150G4LSG. b Drain
source current(Ids)—gate
source voltage(Vgs)—pulsed
drain source voltage(Vds) for
TP65H150G4LSG. Current
collapse compared to
continuous drain source
voltage case is evident. c Drain
current(Ids)—drain source
voltage(Vds) continuous gate (b)
source voltage(Vgs) for
TP65H150G4LSG. d Drain
current(Ids)—drain source
voltage(Vds) pulsed gate
source voltage(Vgs) for
TP65H150G4LSG. Current
collapse compared to
continuous gate source voltage
case is evident.
e Transconductance(gm)—
drain current(Ids) continuous
drain source voltage(Vds) for
(c)
TP65H150G4LSG
238 13 Performance Characteristics of Selected Commercial Heterogeneous …

Fig. 13.3 (continued) (d)

(e)

Archimedes [8], Charon [9] (from Sandia National Laboratories). The commercial vari-
eties [11, 12] even allow semiconductor device processing steps to be simulated and
analyzed to optimize semiconductor device manufacturing process flow.
TCAD is a software package|tool that models both semiconductor device fabrication
and semiconductor device operation. Semiconductor device fabrication modeling is Pro-
cess TCAD, semiconductor device internal electrical property analysis and estimation is
termed Device TCAD. Semiconductor device fabrication steps include ion implantation,
photolithography, molecular beam epitaxy, chemical vapor deposition, etc., Analysis and
estimation of key internal semiconductor device properties (e.g., charge carrier density,
charge carrier energy, electrical potential, electric field (x,y components), charge carrier
velocity etc.,) involves solving key underlying physics equations as Maxwell Boltzmann
Transport equation, drift–diffusion equation, hydrodynamic equation, Schrodinger’s Wave
equation etc., including real semiconductor device issues as charge carrier scattering from
acoustic|optical phonons, impurities, crystal lattice defects etc., Sophisticated numerical
analysis techniques as Monte Carlo [13] and two|three dimensional finite element [14]
analysis.
Device TCAD programs perform two|three dimensional analysis. For a typical two
dimensional TCAD program [8], the user supplied input must include:

● Physical dimensions in appropriate units

13.6 Technology Computer Aided Design (TCAD) Tools for Analyzing, … 239

(a)

(b)

(c)

Fig. 13.4 a Drain current(Ids)—gate source voltage(Vgs) continuous drain source voltage(Vds)
for EPC2216. b Drain current(Ids)—gate source voltage(Vgs) pulsed drain source voltage(Vds) for
EPC2216. Current collapse compared to continuous drain source voltage case is evident. c Drain
current(Ids)—drain source voltage(Vds) continuous gate source voltage(Vgs) for EPC2216. d Drain
current(Ids)—drain source voltage(Vds) pulsed gate source voltage(Vgs) for EPC2216. Current col-
lapse compared to continuous gate source voltage case is evident. e Transconductance(gm)—drain
current(Ids) for EPC2216
240 13 Performance Characteristics of Selected Commercial Heterogeneous …

(d)

(e)

Fig. 13.4 (continued)

● Type of semiconductor material (gallium arsenide|germanium|indium phos-

phide|silicon) used in the device
● Type of numerical analysis—Monte Carlo|finite element, including the option of
whether movement of both charges carriers (electron|holes) or one of the pair are to
be analyzed
● Type of internal charge carrier scattering process (acoustic phonon, optical phonon,
impurity,lattice imperfections scattering etc.,) to be included in the calculations
● Type(acceptor|donor) and concentration in different regions of the device
● Type(insulator|Ohmic|Schottky) of contacts to the various regions of the device
● Lattice temperature and result output format (popular Gnuplot [15] or ‘mesh’ [16])
format

The following three dimensional surface plots (Fig. 13.6a, b, c, d, e, f, g, h, I, j) show the
key internal electrical properties of an abrupt junction np rectifying|signal diode obtained
with the Archimedes 2.0.1 tool [8]. Both acoustic and optical scattering are included in the
calculations. Both charge carriers (electron, hole) properties (density, energy, velocity
etc.,) are measured. The three dimensional surface plots were generated with the excellent
13.6 Technology Computer Aided Design (TCAD) Tools for Analyzing, … 241

Fig. 13.5 a Drian (a)

current(Ids)—gate source
voltage(Vgs) at continuous
drain source voltage(Vds) for
NE34018. b Drain
current(Ids)—gate source
voltage(Vgs) pulsed drain
source voltage(Vds) for
NE34018. c Drain source
current(Ids)—drain source
voltage(Vds) continuous gate
source voltage(Vgs) for
(b)
NE34018. d Drain source
current(Ids) drain source
voltage(Vds) pulsed gate
source voltage(Vgs) for
NE34018

(c)

(d)
242 13 Performance Characteristics of Selected Commercial Heterogeneous …

(a) (b)

(c) (d)

(e) (f)

Fig. 13.6 a Forward bias abrupt junction np silicon diode electron density (unit n3 ), b Forward
m
bias abrupt junction np silicon diode hole density (unit n3 ), c Forward bias abrupt junction np
m
silicon junction potential (unit Volt), d Forward bias abrupt junction np silicon electric field x com-
ponent (unit m V ), e Forward bias abrupt junction np silicon diode electric field y component (unit
V ), f Reverse bias abrupt junction np silicon diode electron density (unit n ), g Reverse bias abrupt
m m3
junction np silicon diode hole density (unit n3 ), h Reverse bias abrupt junction np silicon junction
m
V ),
potential (unit Volt), i Reverse bias abrupt junction np silicon electric field x component (unit m
j Reverse bias abrupt junction np silicon diode electric field y component (unit m )V

freely available and downloadable graphics plotting software package Gnuplot [15] from
MIT.
References 243

(g) (h)

(i) (j)

Fig. 13.6 (continued)

References

1. https://www.infineon.com/dgdl/Infineon-BFQ790-DS-v02_00-EN.pdfiieId=5546d4624cb7f11
1014d237c2a8f54fc
2. https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2216_datasheet.pdf
3. https://www.transphormusa.com/en/document/datasheet-tp65h150g4lsg-650v-gan-fet/
4. https://pdf1.alldatasheet.com/datasheet-pdf/view/6373/NEC/NE34018.html
5. https://download.tek.com/manual/6487-900-01(C-Mar2011)(User).pdf
6. https://www.tek.com/en/products/keithley/dc-power-supplies/2220-2230-2231-series
7. https://download.tek.com/datasheet/2220_2230DataSheet_0.pdf
8. https://www.gnu.org/software/archimedes/
9. https://charon.sandia.gov/
10. https://devsim.org/
11. https://silvaco.com/tcad/
12. https://www.synopsys.com/silicon/tcad.html
13. https://www.ibm.com/topics/monte-carlo-simulation
14. https://www.simscale.com/docs/simwiki/fea-finite-element-analysis/what-is-fea-finite-ele
ment-analysis/
15. http://www.gnuplot.info/
16. https://mech.fsv.cvut.cz/~dr/software/T3d/guide/node13.html
Semiconductor Optoelectronic Devices
14

14.1 Basic Solar Cell Structure (Photo Diode)

A solar cell [1–16] is a large area np junction diode, that converts sunlight to electricity
via the photovoltaic effect. Absorbed photons generate electron–hole pairs, which are
separated within the diode resulting in photocurrent. This current flows into an external
load circuit, which converts the input current to a voltage. Thus optical energy|power is
converted to electrical energy|power—Fig. 14.1a.
In Fig. 14.1a the top metal contact covers a miniscule fraction of the front surface
area to allow maximum possible semiconductor surface area to be exposed to the incident
light. The conversion of incident light energy to electrical energy consists of four steps—
light absorption, electric current generation, internal transport of photo generated charges,
conversion of incoming photocurrent to photovoltaic power in an external circuit. This anal-
ysis uses a single junction diode made from a homogeneous single crystal semiconductor.
Real world solar cells are multi-crystalline silicon homogeneous junction cells, thin film
compound semiconductor heterogeneous junction cells or state-of-art multi junction, multi
semiconductor tandem cells.

14.1.1 Light Absorption by Solar Cells

Some of the incident solar light is reflected, and the remainder is transmitted into the
device. The spatial part of the electric field component of the incident sunlight’s transverse
electromagnetic wave is:
j2π x ωn COMP 2π (n R + jk R )
E y (x) = E 0 e λSEMICONDUCTOR k = = (14.1)
c c

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 245
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_14
246 14 Semiconductor Optoelectronic Devices

(a)

(b)

(c)

(d)

Fig. 14.1 a Layered solar cell structure. Light is incident on the top surface. b Energy band diagram
for a solar cell. B represents the blocking barrier that selectively allows one type of charge carrier
to pass through and blocks the other type. c Processes that do not generate any photocurrent in the
external circuit. d, e Structure and energy band diagram of heterogeneous junction solar cell where
a Si:H denotes hydrogenated amorphous silicon. C Si crystalline silicon
14.1 Basic Solar Cell Structure (Photo Diode) 247

where n R , k R are the real and imaginary parts of the complex refractive index of the
semiconductor material, and c, λ are the incident light’s velocity and wavelength in free
space. After substituting for the wave number in (14.1), the electric field is:
2π ( jn R −k R )x
E y (x) = E 0 e λ (14.2)

The Poynting vector corresponding to an electromagnetic wave embodies energy car-

ried by it and its optical power density. For an uniform plane wave, travelling in the x
direction, the magnitude of the power density (as related to its Poynting vector) is:
/ / /
ε II II2 ε ε 2 −αx 4π k R
S = E × H Sx = E x Hz =
p
Ey = Ey Ey = E0 e α=
μ μ μ λ
(14.3)

where a, ε, μ are respectively the absorption coefficient, the electric permittivity and
magnetic permeability of the semiconductor material.

14.1.2 Generation of Photovoltage and Photocurrent

The power density S at some free-space wavelength λ can be converted into the photon
flux φ(λ) (units photons
m2
second
) at that wavelength by dividing by the photon energy hc/λ.
The balance equation for monochromatic photons within the semiconductor is:

∂ P(λ)
+ ∇ · φ(λ) = RRAD (λ) − A(λ) (14.4)
∂t
where P is the volumetric photon density, RRAD is the generation rate of photons within
the semiconductor due to the radiative recombination of previously generated electron–
hole pairs, and A is the rate of loss of photons due to absorption of photons within the
volume. Ideally, for a solar cell all of the absorbed photons must create separable electron–
hole pairs, A(λ) = G O P (λ), the generation rate. But unwanted excitation of free carriers
G f c and bound electron–hole pairs (exciton) G ex do not contribute to the solar cell’s
output current—as it moves through the device as a neutral entity. So,

A = G O P + G f c + G ex = AηINTERNAL + G f c + G ex (14.5)

G O P = ηINTERNAL A is the internal quantum efficiency of the solar cell. In steady state,
for a sunlight beam, in one dimension, the internal quantum efficiency is:
/
η E 02 λ
G I O = ηINTERNAL (λ)α(λ)φ0 (λ)φ0 = (14.6)
μ c
248 14 Semiconductor Optoelectronic Devices

where φ0 is the photon flux at the solar cell surface. Most silicon solar cells have a high
generation rate near the surface of the cell. The roll-off is exponential for all wavelengths,
but is pronounced at shorter wavelengths where α is high. So, the peak photon density
occurs at approximately 500 nm.
Current generated by photon absorption is the photocurrent. It is created by separat-
ing the photo generated electron–hole pairs the electrons and holes to flow in opposite
directions. This is achieved by making the solar cell a np diode. The key considerations
to fabricate such a np junction are:

• How deep into the device should the metallurgical junction be placed
• The type (n, p) of the top section of the diode
• Appropriate acceptor|donor densities for the two regions (n,p)

As the generation rate decays exponentially with increasing depth into the solar cell,
the np junction should be placed very close to the front surface. Thus, the top part of
the semiconductor, which is called the emitter, is thin. Since the current must move in
a lateral path to the metallic contacts on the front surface, the emitter region must be
heavily doped to avoid unwanted, parasitic series resistance. The lower part of the diode
is called the base. The base must be thick (compared to the emitter layer) to collect the
long wavelength photons, and provide mechanical strength for the solar cell. Minority
carriers generated in this region would travel long distances to the junction, so the doping
type of the base must provide the more mobile minority carrier. For solar cell materials
as Si and GaAs, this means that the base should be p type. So a solar cell is a shallow
junction, np diode, with a heavily n doped emitter.
The energy band diagram for a standard solar cell is in Fig. 14.1b. As the generation
rate decreases with distance into the cell, both electrons and holes in both of the quasi-
neutral regions diffuse to the right. In the emitter, charge carrier separation occurs at the
junction, where the electrons are reflected by the built-in potential barrier. To achieve the
same effect for carriers generated in the base, a back-surface field is created by heavily
doping the end of the p type region. There is also a field at the front surface of the cell
due to the donor density gradient, which occurs during the diffusion doping process. In
the remaining region of the cell, the space-charge region, carriers generated (in the space
charge region) are separated by the built-in junction field.
The expression for the component of the total photocurrent due to generation in the
emitter quasi neutral region is obtained by analyzing the diffusion of minority carrier
holes, under the assumption that no large gradients in the kinetic energy per carrier exist
Then at steady state,

−d Jhole
E
p0 − p
+ + GOP = 0
qd x τhole
−k B μhole Tlattice d P def −q Dhole d P
E
Jhole (x) = = 0 < x < xjunction (14.7)
dx dx
14.1 Basic Solar Cell Structure (Photo Diode) 249

with the boundary conditions:

(14.8)

where S F is the front surface recombination velocity. The second boundary condition
implies that all excess minority-carrier holes reaching the edge of the space charge region
are swept across the junction by the built-in field. Using (14.6) for G O P and assuming an
extremely idealized internal quantum efficiency of 100%, the solution for monochromatic
light of wavelength λ is:
  αqφ(0)L hole
E
Jhole λ, xjunction = 2 2 (14.9)
α L hole − 1

Similar expression for the base generated minority carrier electron photocurrent can be
derived using similar technique as for the hole current in the emitter.
In the space charge layer all carriers generated in that region are separated by the built-
in field, and the expression for the photo generation current in this region is obtained by
analyzing the photocurrent due to either electrons or holes. Assuming no recombination
occurs as the carriers are swept out of the space-charge region very fast, and consider-
ing the photocurrent for electrons in combination with the Depletion Approximation (to
calculate the width W of the space charge region) gives:
DEPLETION
d Jelectron
+ GOP = 0 (14.10)
qd x
Integrating over x junc ≤ x ≤ x junc + W and assuming perfect internal quantum effi-
ciency, gives:
 
DEPLETION
jelectron = qe−αxjunction 1 − e−αW xjunction  x xjunction + W (14.11)

Then the total photocurrent is the sum of the above three components:
   
JPHOTO (λ) = Jhole
E
λ, xjunction + Jelectron λ, xjunction + W + Jelectron
DEPLETION
(14.12)

The effect of surface fields on minority carriers is controlled by surface recombination

velocity. The rate of recombination of electrons at the surface is the same as if a flux of
electrons of density (n − n 0 ) were drifting with an average velocity S into the surface and
being removed. Thus, in the quasi neutral base at x = B, the electron current is diffusive:

−Delectron d(n − n 0 ) −Delectron dn

=
dx dx
def
= S(n − n 0 )S = ∞ n(B) = n 0 Jelectron finite Ohmic
S = 0 n(B) > n 0 Jelectron = 0 Blocking (14.13)
250 14 Semiconductor Optoelectronic Devices

The electrons and holes constituting the photocurrent flow in the direction of a reverse
bias current. When this current flows through an external load, it generates a voltage
across that load to forward bias the diode. A current that opposes the photocurrent is
developed, so some net current loss occurs. The above expressions for the photocurrent
are valid only if the illumination is not so intense so that:

• there are very small deviations in quasi-Fermi levels in the space-charge region from
constant values.
• minority carrier lifetime does not change from its value ‘in the dark’.

The diode dark current is computed using the boundary conditions at the edges of the
space charge region, and a boundary condition at the contact ends of the quasi neutral
regions. For electrons injected into the base:

  Vlattice,junction
−Delectron dn
n xjunction + W = n 0 p e VTHERMAL = S B (n(B) − n 0 ) (14.14)
dx x=B

where S B is the back-surface recombination velocity, i.e., at x = B, and VL, junc is that
part of the load voltage that is dropped across the junction. In absence of series resistance
this is the load voltage. Neglecting any current change from recombination in the space
charge region, the hole dark current (injected across the forward biased junction into the
emitter), the total dark current is the sum of the two injected currents. The load current is
the difference of the photo and dark currents:
 V
lattice
JDARK = J0 e VTHERMAL − 1 JLOAD = JPHOTO − JDARK (14.15)

When the dark current exactly negates the photocurrent, an open circuit exists, and
the load voltage is the open circuit voltage. J0 can be re-written in terms of the minority
carrier properties of diffusion length and surface recombination velocity for the emitter
and base, the appropriate acceptor, donor concentrations N A , N D . The intrinsic carrier
concentration depends exponentially on the bandgap so that J0 can be re-written in terms
of the bandgap, the minority carrier properties of diffusion length and surface recombina-
tion velocity for the emitter and base and the acceptor, donor concentrations (constant C
in 14.16)

JPHOTO + J0
VOPEN CIRCUIT = VTHERMAL ln
J0
 (14.16)
E GAP C
JOPEN CIRCUIT = − VTHERMAL ln
q JPHOTO

For a typical solar cell, when 0 < VLOAD < VOPEN CIRCUIT , the solar cell’s I-V curve is
in the 4th quadrant, where the current is negative and the voltage is positive—the power
14.1 Basic Solar Cell Structure (Photo Diode) 251

is negative, indicating generation, not dissipation. The power at the point of maximum
power generation is expressed as a density in Watts
m2
, given by:

PMAX POWER = JMAX POWER VMAX POWER

= FILLFACTOR JSHORT CIRCUIT VOPEN CIRCUIT (14.17)

The presence of parasitic resistances in the solar cell forces

|JSHORT CIRCUIT | < |JPHOTO |. Series resistance arises as the vertical path through
the p doped base region is much larger than the corresponding vertical path through the
very thin highly n doped region. As a low voltage device, a solar cell is sensitive to series
resistance. Shunt resistance arises mainly from internal imperfections at the junction, as
well as any conductivity along the vertical edges of the device.
The FILLFACTOR is typically less than unity because the exponential form of the solar
cell’s I-V characteristic is an approximation to the perfect characteristic that would have
JLOAD = JSHORT CIRCUIT = JPHOTO VLOAD < VO P R N C I RCU I T . The FILLFACTOR ensures
that a real cell makes the transition from JLOAD = JSHORT CIRCUIT to JLOAD = 0 in a
smooth manner. This ‘softness’ of the diode characteristic becomes less important as the
bounding area JPHOTO VOPEN CIRCUIT is increased. Using a high bandgap material does not
improve the VOPEN CIRCUIT , as the photocurrent density is reduced by the increased trans-
parency of the material to sunlight. Consequently, the photovoltaic conversion efficiency
ηPHOTOVOLTAIC peaks at some value of the bandgap energy.
Thin film solar cells have been designed and built to fulfil the need for solar cells
be deposited in situ onto large-area surfaces. A candidate is copper indium gallium
diselenide, CIGS. Depending on the ratio of indium to gallium in the material, the
bandgap lies 1.04 eV (gallium free) < E GAP < 1.7 eV (selenium free). Inserting dopants
in this ternary compound crystal is difficult, so excess carriers are created by deliber-
ately creating vacancies in the deposited film. For example, if the growth conditions are
adjusted so that there is a deficiency of copper in the CIGS layer, then the selenium
atoms surrounding the copper vacancies will lack electrons. Selenium atoms accept elec-
trons from elsewhere, and the material becomes p-type. CIGS solar cells have a p type
base and use another semiconductor for the n type emitter—heterogeneous junction
diode. In CIGS solar cells the n-type semiconductor has a large bandgap and does not
absorb much sunlight—incident solar energy penetrates the absorbing CIGS film quickly.

14.1.3 Heterogeneous Junction Solar Cell

The structure and energy band diagram of a common silicon based heterogeneous(np junc-
tion is between amorphous and crystalline silicon) junction solar cell [16] is in Fig. 14.1
d, e.
252 14 Semiconductor Optoelectronic Devices

Silicon based heterogeneous junction solar cells exploit the fact that the high
recombination active contacts are moved away from the crystalline surface by
insertion of a film with wide bandgap. To reach the full device potential, the hetero-
geneous|homogeneous interface state density should be minimum—achieved by having a
nanometer thick hydrogenated amorphous silicon (a-Si:H) film, whose bandgap is wider
than that of crystalline silicon (c-Si). Amorphous silicon films reduce the crystalline sil-
icon (c-Si) surface state density by hydrogenation. Such films can be doped easily (n|p)
type, without lithography fabrication of contacts with very low values for the satura-
tion current density. The outcome is impressive large-area (>100 cm2 ) energy-conversion
efficiencies (~25%).
The basic device features on the illumination side are successively an intrinsic hydro-
genated amorphous silicon (a-Si:H) passivation layer and a p doped amorphous silicon
emitter both deposited by plasma enhanced chemical vapor deposition (PECVD). On top
of the silicon layers, an antireflective transparent conductive oxide (TCO) is deposited by
physical vapor deposition (PVD) and the charge collection is made by a screen-printed
metallic contacting grid. On the back side, an electron collecting stack is used, and it is
composed of an intrinsic hydrogenated amorphous silicon (a-Si:H) passivation layer, a
doped n type amorphous silicon (both deposited by PECVD), a TCO layer and a metallic
contacting layer (deposited by PVD).
Low defect density in high purity silicon wafers enables heterogeneous junction silicon
based solar cells to have efficiencies over 25%. To achieve this high efficiency device, the
surface of the wafer must be free of electronically active defects. High quality surface
passivation is achieved by using plasma deposited hydrogenated amorphous silicon (a-
Si:H), resulting in large carrier lifetimes and high efficiencies.
A key challenge in fabricating a high efficiency solar cell from a high quality silicon
wafer is to ensure that the electrons and holes are collected at two spatially separated
terminals. Selective collection exploits properties of semi-permeable electronic membranes.
Such membranes provide a low-resistance electrical connection for one type of charge (e.g.
electrons) while blocking with minimal leakage the other type (holes). Doped amorphous
silicon layers (n|p type a-Si:H) is the ideal way to provide the desired charge carrier
selectivity. However, a-Si:H films introduce limitations as parasitic absorption of light
and non-ideal selectivity (non-negligible resistance to charge extraction and low lateral
conduction).
A number of interesting solar cell structure are being actively investigated at present.
Dopant-free solar cells: Although it was believed for long that an efficient photovoltaic
device needs doped contacts of opposite polarities, recent understanding of the physics of
solar cells does not support this. Experimental demonstration of a high-efficiency entirely
dopant-free crystalline silicon cell, using slightly sub-stoichiometric molybdenum trioxide
(MoO3) and lithium fluoride (LiF) as hole|electron selective contacts—promises entirely
new device architecture, with much simplified processes and extremely simple designs.
14.2 Light Emitting Diodes (LEDs) 253

Fig. 14.2 Layered structure of

a NPN phototransistor

Interdigitated back contact (IBC) solar cells: Metal contacts extract the electrical
charges from a silicon solar cell. In the traditional architecture solar cells negative (elec-
trons) and positive (holes) charges are collected on each side of the wafer, the IDC design
collects both charge types on the rear of the wafer. All metal contacts are placed at the
rear of the wafer, preventing shadowing and allowing a higher current to be generated.
Conceptually simple but difficult to implement in a real world solar cell.
Small-area devices: So long photovoltaic cells were small area devices (1 cm2 or less).
Recent record efficiencies for wafer based silicon devices were obtained with areas >100
cm2 . The large diffusion length of photogenerated carriers in silicon (typically of mil-
limeter scale) makes edge recombination a particular issue, and the fabrication of small
devices challenging.
A phototransistor is a simple extension of a photodiode. Figure 14.2 shows a NPN
phototransistor.

14.2 Light Emitting Diodes (LEDs)

14.2.1 Heterogeneous Junction Light Emitting Diodes

A light emitting diode (LED) is a pn-junction diode in which generates light (in a selected
frequency band of the electromagnetic spectrum, e.g., infra red, visible etc.,) based on
radiative recombination, under forward bias operating conditions. There is conversion of
electrical energy to optical energy, opposite to what happens in a solar cell. In most LED
designs, the internally generated photons escape through the top surface which cannot be
covered by a top metallic contact. A number of performance metrics are associated with
a LED as listed below [17].

• Voltage efficiency. This relates the applied voltage to the bandgap of the semiconductor.
The bandgap determines the desired color of emitted light.
• Current efficiency. This relates the current due to recombination in the desired part of
the device to the current due to recombination elsewhere. Estimating this efficiency is
very important for heterogeneous junction LED design. Modern high intensity LEDs
are heterogeneous junction devices.
254 14 Semiconductor Optoelectronic Devices

• Radiative efficiency. Correlates amounts of radiative recombination and unwanted, non-

radiative radiation. Estimating this efficiency is key to selecting the LED material
(direct bandgap), and its properties as doping level and purity.
• Extraction efficiency. Quantifies hiw efficiently the photons can come out of the
semiconductor, and determines the substrate, contacts, and device shape.
• Wall-plug efficiency. Measures the overall efficiency of the electrical to optical
conversion process.

Voltage Efficiency: At equilibrium, electrons occupy states near the bottom of the con-
duction band, and holes reside near the top of the valence band. An applied forward
bias perturbs the distribution of both electrons and holes, but the energy of any photons
resulting from radiative recombination will be close to that of the bandgap. The voltage
efficiency is defined as:

def ω E GAP
ηVOLTAGE = ≈ (14.18)
q VAPP q VAPP
This equation defines the applied voltage required to get a voltage efficiency of unity
when using the semiconductor that has been chosen for a particular frequency of light out-
put—VAPP < ω q would lead to higher voltage efficiencies. As the carrier concentrations
depend exponentially on potential, low biases do not result in a high overall efficiency.
Current efficiency: The rate of radiative recombination is proportional to the local
electron hole concentration product. In a forward biased diode, the minority carrier con-
centrations are elevated above their equilibrium values over distances that extend from the
space charge layer by several minority carrier diffusion lengths. Photon generation will
occur over a length of the order of microns.
To obtain intense photon generation, the minority carriers must be concentrated into
a smaller region. Modern high brightness LEDs use dissimilar materials for the p- and
n-regions of the diode (Fig. 14.3). This structure uses a low bandgap material sandwiched
between two higher bandgap materials to form a potential well in which the minority carriers
are trapped, thereby increasing their concentrations and the intensity of the generated light.
The region of carrier confinement is called the active layer.

Fig. 14.3 a, b Passive mode organic light emitting diode (PMOLED - a) and active mode organic
light emitting diode (AMOLED - b)
14.2 Light Emitting Diodes (LEDs) 255

In a heterogeneous junction, the current due to electrons injected from the n region
recombine in the active region with holes that are injected from the p region. The electron
current density, in steady state and with no non thermal generation of electron hole pairs,
is:
d Jelectron n
− =0 (14.19a)
qdx τelectron
Integrating over the active region bounded by x = 0 and x = H, while noting that the
minority carrier lifetime is uniform over the active region,
 
nd x τelectron d Jelectron
=
τRADIATION qτ R AD A AI O N dx
τelectron
= (Jelectron (H ) − Jelectron (0)) 0  x  H (14.19b)
qτ R AD I AT O N
where τRADIATION the radiative recombination lifetime. Now the current efficiency can be
defined as:
Jelectron (H ) − jelectron (0)
ηCURRENT = (14.20)
JTOTAL
under the assumption that the electron current density is zero in the p region.
Jelectron (0) is reduced to prevent electrons from escaping into the p region, achieved by
making a large energy barrier for electrons at the interface between the active region and
the p region. Likewise, a barrier at the active—n region junction prevents the holes from
escaping from the active region. These properties are included in the LED by implement-
ing Type I heterogeneous junctions. LEDs are p-on-n diodes, unlike solar cells, which are
n-on-p diodes. The junction region in the LED does not have to be close to the surface,
as the photons are all of energy very close to the bandgap, and so the relevant absorption
coefficient is low. To provide mechanical rigidity the bottom layer of the LED is thick,
and n type material is used to minimize series resistance. ‘Vertical’ resistance dominates
in this device because there is little lateral current, and the LED has a much smaller
cross-sectional area than a solar cell. As a LED operates in forward bias, the current is
large and series resistance is avoided to obtain the desired junction.

14.2.2 Radiative Recombination Efficiency

A LED operates if recombination is confined to a well-defined active region, and to ensure

that maximum light is generated, the recombination is radiative. So the active material
should be a direct bandgap semiconductor. For a high rate of radiative recombination, high
concentrations of both types of carrier are needed. As a high level of electron and hole
injection into the active layer must be established,—the LED must be forward biased.
256 14 Semiconductor Optoelectronic Devices

The background doping density of the active layer is usually chosen to make the region
p type. So electrons are the minority carriers, and their superior minority carrier mobility
ensures a more uniform carrier distribution in the active layer. Therefore a more spatially
uniform generation of photons is ensured. The net rate of recombination for electrons is
n τelectron
. The radiative recombination efficiency is: ηRADIATION = (14.21a)
τelectron τradiation
The principal non-radiative contributors to τelectron are generation-recombination cen-
ter recombination and Auger recombination. Recombination generation recombination in
the active layer is reduced by ensuring that the active region material is of high crys-
talline purity|perfection. The active-layer material must be lattice matched to the substrate
material on which it is epitaxially grown.

14.2.3 Extraction and Wall Plug Efficiency

The extraction efficiency is the ratio of the optical power that actually escapes from the
structure to the optical power that is generated within the diode.
SOUT
ηEXTRACTED = (14.21b)
SGEN
Extracting the light is inherently difficult because the relatively large value of refractive
index for most semiconductors means that the critical angle beyond which total internal
reflection occurs, is small. For example, GaAs has a refractive index of about 3.5, so, at
the semiconductor/air interface, from Snell’s Law:

1
θCRITICAL = arcsin ≈ 1.7o (14.21c)
3.5

The spontaneous light emission from an LED is omnidirectional, and if the light is
assumed to emanate from a point source, it is easy to estimate the optical power that exits
through a segment of a spherical surface defined by a polar angle equal to the critical
angle. Then the corresponding output optical power is approximately given by:

SOUT 1 − cos(θCRITICAL )
ηEXTRACTION = = (14.21d)
SGEN 2
For a point source in GaAs, this means that only about 2% of the optical power would
escape into the surrounding air. However, semiconductor layers in an LED are usually
deposited epitaxially onto a substrate, and the resulting structure is planar. Thus, the light
source is planar rather than a point, so a significant fraction of light generated inside
the LED can escape. The semiconductor die can be sawed and wedge-shaped diodes, in
which total internal reflection is reduced by effectively increasing the critical angle.
14.2 Light Emitting Diodes (LEDs) 257

Wall plug Efficiency: The output power density of a LED is:

SOUT = ηCURRENT ηVOLTAGE ηEXTRACTION ηRADIATION JDIODE VDIODE (14.21e)

where VDIODE , JDIODE are the applied bias and diode current density, respectively. Rear-
rangement of this equation leads to an expression for the overall efficiency of the electrical
to optical conversion process, LED wall-plug efficiency:
SOUT
= ηCURRENT ηVOLTAGE ηEXTRACTION ηRADIATION (14.21f)
PI N PU T
The wall-plug efficiency is a radiometric measurement based on measurable physical
properties of power, that can be measured by a calibrated photodetector and a wattmeter.
Common figures-of-merit for LED optical performance are based on photometric units,
i.e., optical power that is perceived by the human eye. The eye is most sensitive to the
color green. So, the optical power perceived by the eye can be expressed in watts as
γ SOUT
P (λ)dλ where the prime signifies power, not power density, and S
OUT (λ) is the
spectral power density in W/m. The perceived optical power is expressed in units of
lumens (lm), by applying a conversion factor of 683 lm/W. This factor is based on the
old light intensity unit of candle power, originally defined in terms of the light output of
a standard candle. Thus, S watts of optical power are perceived by the eye as lumens of
luminous flux according to:

 = 683.0 γ SOUT
P
(λ)dλ. (14.21g)

14.2.4 Luminous Efficiency and Efficacy

The luminous efficacy measures the effectiveness of the eye in perceiving optical power:

 lumens
Luminous Efficacy = P
(14.21h)
SOUT Watt

The luminous efficiency is also expressed in lumens per Watt and relates the perceived
optical power to the electrical power supplied to the LED:

 lumens
Luminous Efficacy = (14.21i)
IDIODE VDIODE Watt
Luminous efficiency is the product of the wall plug efficiency and the luminous
efficacy.
The light from blue green InGaN LED, mixed with output with red light from AlGaInP
LED generates white light. The human eye senses color through rod and cone cells in the
258 14 Semiconductor Optoelectronic Devices

retina that are specifically sensitive to red, green, or blue light. Combinations of certain
intensities of these colors are perceived by the eye as white light. For standardization
and colorimetric reasons, three color matching functions have been developed. Each is
centered on a particular wavelength (red, green, or blue) and has some spectral content
such that specific combinations of the intensities of the three sources can produce any
desired color. The chromaticity coordinates corresponding to the red, green, and blue
color-matching functions are labeled x, y, z, respectively. The x-coordinate, e.g., measures
the ratio of the stimulus of the red cells in the eye to the total stimulus of all the color cells
to the entire visible spectrum. Thus, x + y + z = 1, and it is only necessary to stipulate
two chromaticity coordinates when specifying a particular color. This is the basis of the
chromaticity diagram.

14.2.5 Organic Light Emitting Diodes (OLED)

An Organic Light Emitting Diode (OLED) [21] has an emissive electroluminescent layer
of film made up of organic (carbon based) molecules. Light is emitted when electrical
current travels through the organic molecules. The advantages of an OLED is that it is
thinner than a conventional LED, and generates brighter, higher contrast display with
faster response times, wider viewing angles, and less power consumption (all properties
in reference to a conventional LED).
The OLED has a simple planar layered structure going from top to bottom.

• Topmost glass shielding layer.

• Cathode: a negatively charged cation attracting layer.
• Emissive layer: consisting of organic molecules or polymers that performs the key task
of transporting electrons from the cathode to the anode.
• Conductive layer: also consisting of organic molecules or polymers that transport holes
from the anode layer
• Anode: Positively charged electron or anion attracting layer
• Substrate: Bottom glass shielding layer.

Light generation mechanism of an OLED is straightforward. Electrical current is applied

to both the anode and cathode. Current traverses both the organic material emissive
and conductive cathode and anode layers, to the anode layer. The current provides
electrons to the emissive layer and removes electrons from the conductive layer. So holes
are generated in the conductive layer. The generated holes in the conductive layer need to be
re-filled with electrons. To recombine with electrons, the holes jump from the conductive
layer to the electron filled emissive layer. Electron hole recombination generates energy
in the visible part of the electromagnetic spectrum—the bright, electroluminescent
light that is visible through the outermost layer of glass (substrate and seal). Instead
14.3 Phototransistor Structure and Performance Characteristics 259

of having a backlight, like in LEDs, the OLED’s display is self-illuminating because of

its organic material. Consequently, OLEDs are significantly thinner than standard liquid
crystal displays.
OLED displays are of three varieties, passive mode (PMOLED), active mode
(AMOLED) and transparent OLEDS.
The physical structure of the passive mode (PMOLED) is simple. The anode and cath-
ode layers consist of nanometer wide strips at tight angles to eachother, with the emissive
and conductive layers sandwiched in between. Light is generated at the intersection points
of the cathode and anode layers (Fig. 14.3a).
The active mode OLED (AMOLED) Active-matrix OLEDs (AMOLED) have a thin
film transistor layer (TFT) beneath the anode layer which forms a matrix (Fig. 14.3b).
The TFT array determines which pixels get switched on in order to form an image. The
TFT arrays require less power than external circuitry, so AMOLEDs are more energy
efficient than PMOLEDs. With faster refresh rates than PMOLEDs, AMOLEDs are ideal
for large displays.
Transparent OLEDs are used specifically for head up displays in military aircraft.
When the OLED is switched off it is almost 85% transparent. When powered on, light
can pass through in both directions. Transparent OLEDs can also be either a passive- or
active-matrix. The military aircraft pilot can look straight ahead, without having to move
his|her head up|down|sideways to check key aircraft performance parameters.

14.3 Phototransistor Structure and Performance Characteristics

A phototransistor is an extension of the photodiode, whose equivalent electrical circuit

consists of a photodiode whose output photocurrent drives the base of a small signal tran-
sistor. Phototransistors performance characteristics are a combination of the performance
characteristics of both these devices, as listed below.

14.3.1 Spectral Response

The output of a phototransistor is dependent upon the wavelength of incident light: start-
ing from near UV wavelengths, through the visible and into the near infra red part of
the spectrum. Without optical filters, the peak spectral response is in the near infra red at
approximately 840 nm. The peak response is at a shorter wavelength than that of a typ-
ical photodiode, since the diffused junctions of a phototransistor are formed in epitaxial
rather than crystal grown silicon wafers. Phototransistors will respond to fluorescent or
incandescent light sources but display better optical coupling efficiencies when matched
with infra red LEDs as GaAs (940 nm) and GaAlAs (880 nm).
260 14 Semiconductor Optoelectronic Devices

14.3.2 Sensitivity

For a given light source illumination level, the output of a phototransistor is defined by
the area of the exposed collector base junction and the DC current gain of the transistor.
The collector base junction of the phototransistor functions as a photodiode generating
a photocurrent which is fed into the base of the transistor section. Thus, just like the
standard photodiode, doubling the size of the base region doubles the amount of generated
base photocurrent (IP), which then gets amplified by the DC current gain of the transistor.
Similarly, like signal transistors, hFE (forward DC current gain) varies with base drive,
bias voltage and temperature. At low light levels the gain starts out small but increases
with increasing light (or base drive) until a peak is reached. As the light level is further
increased the gain of the phototransistor starts to decrease. The DC current gain also
increases with increasing the collector emitter voltage.

14.3.3 Linearity

Unlike a photodiode whose output is linear with respect to incident light over 7–9 decades
of light intensity, the collector current (IC) of a phototransistor is linear for only 3–4
decades of illumination, because the DC gain (hFE) of the phototransistor is a function of
collector current (IC) which in turn is determined by the base drive. The base drive may be
in the form of a base drive current of incident light. While photodiodes operate best when
linear output versus light intensity is extremely important, as in light intensity measuring
equipment, the phototransistor in contrast performs best as a switch. When light is present,
a phototransistor or photodarlington can be considered “on”, a condition during which
they are capable of sinking a large amount of current. When the light is removed these
photodetectors enter an “off” state and function electrically as open switches.

14.3.4 Collector-Emitter Saturation Voltage—VC E,S AT U R AT I O N

Saturation condition is when both the emitter base and the collector base junctions of a
phototransistor become forward biased. From a practical standpoint the collector emit-
ter saturation voltage, V CE(SAT ) indicates how closely the photodetector approximates a
closed switch. This is because V CE(SAT ) is the voltage dropped across the detector when it
is in its “on” state. V CE(SAT ) is specified as the maximum collector emitter voltage allowed
at a given light intensity and for a specified value of collector current.
14.3 Phototransistor Structure and Performance Characteristics 261

14.3.5 Dark Current—I D AR K

When the phototransistor is placed in the dark and a voltage is applied from collector to
emitter, a certain amount of photocurrent will flow—the dark current (ID). This current
consists of the leakage current of the collector base junction multiplied by the DC current
gain of the transistor. Therefore the phototransistor is never completely “off”, i.e., it is
not and ideal switch with “close-open” transitions. The dark current is specified as the
maximum collector current permitted to flow at a given collector emitter test voltage. The
dark current is a function of the value of the applied collector emitter voltage and ambient
temperature.

14.3.6 Speed of Response

The speed of response of a phototransistor is controlled totally by the capacitance of the

collector base junction and the value of the load resistance. These dominate due to the
Miller Effect which multiplies the value of the RC time constant by the current gain of
the phototransistor. Consequently, for devices with the same active area, the higher the
gain of the photodetector, the slower will be its speed of response. A phototransistor takes
a certain amount of time to respond to sudden changes in light intensity. This response
time is usually expressed by the rise time (tR) and fall time (tF) of the detector where:

tR−The time required for the output to rise

from 10 to 90% of its on state value.
tF−The time required for the output to fall
from 90 to 10% of its on state value.

As long as the light source driving the phototransistor is not intense enough to cause
optical saturation (characterized by the storage of excessive amounts of charge carriers in
the base region), risetime equals falltime. If optical saturation occurs, tF can become much
larger than tR. Phototransistors must be properly biased in order to operate. Specifically,
applied voltages must not exceed the collector emitter breakdown voltage (VBRCEO)
or the emitter–collector breakdown voltage (VBRECO ). Else permanent damage to the
phototransistor results.
The generic layered structure of a phototransistor is in Fig. 14.3. Although at start pho-
totransistors were fabricated with germanium and silicon, currently gallium arsenide is a
popular choice for phototransistor fabrication. Although phototransistor normally implies
a bipolar transistor, photo field effect transistors are also available, but less commonly
used. Also, phototransistors are not as widely used as photodiodes, as they have nar-
rower operating wavelength ranges, lower quantum efficiency, smaller active detection
area and detection bandwidth. Although the phototransistor has higher responsivity than
262 14 Semiconductor Optoelectronic Devices

a photodiode, it does not translate to reduced noise equivalent power, as photocurrent

and dark current are both amplified by the device. Moreover the large base collector
capacitance reduces detection bandwidth, so that rise-fall times are in the microsecond
range. Although avalanche phototransistors have higher responsivity than ordinary photo-
transistors, the collector emitter current generation mechanism is different, i.e., avalanche
breakdown.
Field effect phototransistors (photoFET) are voltage controlled devices. Light incident
on the gate region generates a voltage that switches the transistor on. Also, the incident
electromagnetic radiation does not have to be in the visible wavelength range—infra red
radiation can also trigger a photoFET.

14.4 Charge Coupled Devices

An optical instrument, e.g., a telescope integrates the incident photons, over long time
exposures, enabling the user can see faraway objects. The human eye responds to the rate
at which photons reach the retina. At optical frequencies|wavelengths, photoelectric effect
ejects electrons from the surface the photons are incident on—the charge coupled device
(CCD).
The quantum efficiency of a light detector is the ratio of the number of photons detected
to the number of incident photons. Charge coupled devices (CCDs) have quantum efficien-
cies of 10–90% over the entire optical frequency range, and this can be extended using
clever techniques. A CCD consists of a thin (approximately 10μ) n type silicon layer, on
top of a thick (about 250–300μ) p type silicon layer. The n doped region creates fixed
positive charges, and the p doped region contains fixed negative charges. Before a CCD
is exposed to radiation, the n type substrate is purged of electrons. Consequently, the
positive free charges in the p-type silicon, repelled by the overlying positively charged
n type substrate, move to the bottom of the p type substrate and form an “undepleted
region” (Fig. 14.4a). Conduction is possible because of free holes. However, above this
undepleted region, and in both the n type and p type silicon layers, the lack of free charges
prevents conduction. In the p depleted layer an electric field in the downward direction
(motion of a positive test charge) occurs as a result of the high positive charge in the n
type region, which has a greater concentration of fixed positive charges than in the p type
region. The device is now ready for operation—capturing the photoelectrons, which
are forced upward into the upper n layer, whose positive charge traps them.
Incident photons generate photoelectrons and for standard CCDs, one electron is pro-
duced for each detected photon. Silicon with band gap energy of 1.14 eV, absorbs photons
of energies of 1.1–1.4 eV, energizing valence electrons to gain enough energy to move
into the conduction band. The wavelength sensitivity|quantum efficiency of CCDs can be
deduced from the path length of light as a function of wavelength in silicon. The quan-
tum efficiency also depends on the width of the CCD. Photons of incident light with
14.4 Charge Coupled Devices 263

Fig. 14.4 Generic

phototransistor physical
layered structure. Individual
devices could be
heterogeneous|homogeneous
junction type

wavelength >0.35μ and <0.8μ are absorbed by the backside illuminated CCDs, which
are only ∼15μ thick, as well as by the front side illuminated CCDs of ∼300μ width. At
wavelengths shorter than ∼0.35μ, 70% of the incident light is reflected. An anti-reflection
coating can partly remedy this and extend the sensitivity to 0.3 μm, but at wavelengths
larger than 1μ, the CCD is transparent.
The photoelectrons released into the conduction band do not recombine with the sil-
icon, which they would normally do. These generated photoelectrons are quickly forced
into the n type layer as a result of the electric field, where they are trapped in the poten-
tial well. At the end of the observation, the number of stored electrons depends on the
integrated intensity of light. The amount of charge that a pixel can hold after normal
integration is its well capacity. Integration times must be set so as not to exceed the well
capacity of the detector.
Picture elements, or pixels are generated by applying potential across the top n type
layer. Each pixel generally has 3 electrodes of different positive voltages, so that the
electrons gather at the spots within the array (and within the pixel) where the potential is
highest. In Fig. 14.4a, electrode “1” induces the highest potential, ∼+5 V, and the photons
gather at this place. CCDs consist of an array of ∼15μ wide pixels.
The electrodes’ (generally 3), applied voltage can be increased|reduced within a upper
and a lower threshold value. To read out the CCD, the potentials are sequenced simul-
taneously, to move the charges, along a column, which is connected in parallel, towards
an “output register”—an unexposed row of pixels at the end of the exposed chip. This
shifting of electrons to the output registrar is achieved by altering the voltages in the 3
gates, simultaneously in all pixels. The voltage of electrode “1” is dropped to ∼2.5 V,
while”2” is raised to a higher voltage. In the next step “1” is dropped to zero, and 2 raised
to 5 V so that the electrons migrate to electrode “2”. In the next two steps, the electrons
migrate to electrode “3”. In the final 2 steps the electrons move to electrode “1” in the
adjacent pixel, which has been vacated by the same process, conducted simultaneously.
Therefore, in 6 voltage adjustment steps, the electrons migrate to the adjacent pixel. Once
an entire row is shifted into this output register row, the charges on the “output register”
row pixels are shifted, similarly using variable voltages, towards the output electronics.
The sequence of operations are partially shown in Fig. 14.4b. The number of photons that
can be detected depends on: well capacity, digitization rate at which raw pixel data is
264 14 Semiconductor Optoelectronic Devices

converted to usable data and the electron capacity beyond which the output of the CCD
becomes non-linear (readout noise). It is very difficult to detect the onset of readout noise.
The readout time is typically kept to 50 microsecond/pixel, to prevent amplifier heating
(with the higher current). This minimizes readout noise—approximately 10 electrons/
pixel/readout. Read noise occurs in part during the analog to digital conversion, as well as
semiconductor device specific noise currents, as thermal, shot noise(s) etc., Readout noise
can be controlled by binning the pixels before readout. Then if four pixels are binned, the
signal is affected by only one read out noise, rather that four times the value. The output
register pixels (non-illuminated) are normally 5–10 times the number of illuminated pixels
so that binning is possible even for high signals.
When CCD images are converted from analog to digital, a DC bias is added to prevent
the signal from being negative at any point—analog to digital converters have unable to
tackle negative numbers. The signal is kept positive to use all the bits in the A/D converter
on the signal rather than the minus sign. The value of the bias varies with position across
the CCD and with the read out time. The bias can be measured with overscan strips or
the measurement of a bias frame. Overscan strips are added columns to the CCD, which
are recorded and read out with no signal, after the entire CCD image is read out. They are
averaged for each row, thereby giving a measure of the zero signal point, and subtracted
from each image pixel in that row. Another scheme is to eliminate the bias is to record
bias frames, i.e. images taken with no integration time and a closed shutter. These images
represent the zero point in the data.
A very fast and efficient analog to digital conversion scheme is delta sigma conversion.
This scheme trades amplitude for temporal accuracy—a zero crossing resulting from input
signal amplitude transition from positive to negative results in zero value in the output
signal amplitude. During the interval when the input signal amplitude is negative, the
output signal amplitude is zero.

14.5 Semiconductor Lasers

14.5.1 Laser Fundamentals [18]

For any material immersed in electromagnetic radiation, two things can happen.
An atom with an initial energy E i absorbs a photon of energy hν and transitions to a
new state with energy E f E f > E i —stimulated absorption. Albert Einstein proposed that
the probability per unit time that this happens is proportional, through a constant, to the
energy density of the radiation, at the frequency ν, that is f (ν) (14.22a). The frequency of
the stimulated events with transition i → f referred to the unit of volume of the material
is (14.22a).

Ri f = Bi f f (v) Ni = n i Ri f N f = n i Bi f f (v) (14.22a)

14.5 Semiconductor Lasers 265

where n i is the number of atoms per unit volume, in the initial energy state and B is
Einstein’s B coefficient. From the higher energy state (excited), the atom can return to its
initial energy state (ground) via spontaneous and stimulated emission.
In spontaneous emission, each excited atom can return to the ground state any time
it wants to, so that the emission of radiation is out of phase. Upon reaching the ground
state, the relaxed atom emits the extra energy as radiation—basis for non laser light. In
contrast, for stimulated emission, all the excited atoms return to the ground state at the
same time, emitting the extra energy at the same time—in phase. This is light emission
by stimulated emission of radiation, LASER.
The probability R f i per unit time that the atom returns to its ground state is (14.22b),
where A f i is Einstein’s A coefficient, and represents the spontaneous emission term, while
B f i f (ν) is the stimulated emission term. Spontaneous emission does not depend on the
radiation f (ν), while the stimulated emission does, and is proportional to the stimulating
radiation density, that is, f (ν). The emission frequency with transition f → i, just like in
the i → f case is (14.22b):
 
Rβ = Aβ + Bβ f (v) Ni = N f = n f Rβ = n f Aβ + Bβ f (v) (14.22b)

where n f is the population of the final state.

At equilibrium, the number of photons emitted per time must be equal to the number of
absorbed photons, and this expression after some manipulation gives the radiation density
as:
Aβ Aβ
−E i −E f
Bβ Bβ
f (v) = n i Bi f
ni = n0 e k B Tlattice
n f = n0e k B Tlattice
f (v) = ν
n f Bfi −1 e k B Tlattice
Bi f
−1
Bfi
(14.22c)

From Planck’s blackbody radiation law (14.22c), the expressions for the ratios of
Einstein’s A, B coefficients are (14.22d):

8π ν 3 Afi 8π ν 3
f (v) =  Bi f = B f i = (14.22d)
ν Bfi c3
c3 e k B Tlattice − 1

The B coefficient for the stimulated emission is equal to coefficient of stimulated

absorption. Also, higher ν implies higher level of spontaneous emission. At thermal equi-
librium the ratio of the probability of a spontaneous decay and that of a stimulated decay
is:
Afi ν
= e k B Tlattice − 1. (14.22e)
B f i f (v)
266 14 Semiconductor Optoelectronic Devices

A laser is a device in which, through external methods, the populations of the initial
and final states are brought to values different from the thermal equilibrium values.
In a typical laser, the atoms in the excited state are allowed to fall back to a state
which has an energy value intermediate between the excited state energy and the final
ground state energy. The key property of the intermediate state is that the atoms in this state
have long mean life times, e.g., of the order of milliseconds. Therefore, a large number of
atoms collect in this intermediate (metastable) state and after that they all return to
the ground state at the same time—i.e., in phase emitting stimulated emission.

14.5.2 Semiconductor Lasers

Semiconductor lasers [19–22] are direct bandgap semiconductor material based solid state
lasers to exploit stimulated emission from interband transitions. These transitions result
from high carrier density in the conduction band. Figure 14.5a illustrates how gain is
achieved in an optically pumped semiconductor material. In absence of an external stimu-
lus (the optical pump) all the electrons are in the valence band. An external optical pump
beam with photon energy slightly above the semiconductor’s band gap energy can push
some of these electrons high into the conduction band. From these high energy excited
states, the electrons fall back to energy levels at the bottom of the conduction band—
metastable state. Simultaneously, the holes generated in the valence band move to the top
of the valence band. Electrons near the bottom of the conduction band can then recom-
bine with these holes, emitting photons with an energy near the bandgap energy. This
process is enhanced by external pump providing photons with appropriate energy values.
In indirect band gap semiconductors (e.g. silicon), the conduction band electrons in the holes
acquire substantially different wavenumbers. Consequently, optical transitions cannot take
place as momentum is not conserved.
Although most semiconductor lasers are optical diode lasers, optically pumped semi-
conductor lasers and quantum cascade lasers are also available. Diode lasers are pumped
with electrical pulses at the np junction. Optically pumped lasers use an external opti-
cal pump and quantum cascade lasers exploit intraband transitions. Direct bandgap
semiconductor laser materials include:

• Aluminum arsenide (AlAs)

• Aluminum gallium arsenide (AlGaAs)
• Gallium phosphide (GaP)
• Indium gallium phosphide (InGaP)
• Gallium nitride (GaN)
• Indium gallium arsenide (InGaAs)
• Indium gallium nirtride arsenide (InGaNAs)
• Indium phosphide (inP)
14.5 Semiconductor Lasers 267

(a)

(b)

Fig. 14.5 a General charge coupled device structure. Black dots are ejected photoelectrons. b Key
signalling steps to read out data from a charge coupled device

• Indium gallium phosphide (InGaP)

As the photon energy of a laser diode is close to the bandgap energy, compositions with
different bandgap energies allow for different emission wavelengths. For the ternary and
quaternary semiconductor compounds, the bandgap energy can be continuously varied in
some substantial range. In AlGaAs (equivalently AlxGa1 − xAs) an increased aluminum
content (increased x) causes an increase in the bandgap energy. Most common semicon-
ductor lasers operate in the near infra red spectral region, some others generate red light
(e.g. laser pointers using GaInP) or blue or violet light (with gallium nitrides). For mid
infra red emission, there are e.g. lead selenide (PbSe) lasers and quantum cascade lasers.
Organic semiconductor compounds are being researched upon for use in semiconductor
lasers. Only optically pumped organic semiconductor lasers have been demonstrated so
far—for various reasons it is difficult to achieve a high efficiency with electrical pumping.
A wide variety of semiconductor lasers, each for a specific end application are
available.

• Small edge emitting laser diodes generate high quality low milliwatt (approximately
0.5 W), used in laser pointers, in CD players and for optical fiber communications.
268 14 Semiconductor Optoelectronic Devices

(a)

(b)

Fig. 14.6 a, b Optical pumping in a semiconductor laser and electrically pumped semiconductor
laser. c, d Optically pumped VECSEL

• External cavity diode lasers contain a laser diode as the gain medium of a longer laser
cavity. They are often wavelength tunable and exhibit a small emission linewidth.
• Both monolithic and external-cavity low-power levels can also be mode locked for
ultra short pulse generation. Broad area laser diodes generate low beam quality low
output power beams.
• High power diode bars are an array of broad area emitters, generating high power (tens
of watts) poor quality output.
• High power stacked diode bars can generate extremely high power (hundreds or thou-
sands of watts). Surface emitting lasers (VCSELs) emit low power, very high beam
quality laser radiation perpendicularly to the wafer.
• Optically pumped vertical cavity surface emitting lasers (VECSELs) generate high
beam quality multi -watt output, even in mode locked operation. Electrically pumped
photonic crystal surface emitting lasers promise to reach similar performance. Quantum
cascade lasers operate on intraband transitions (as compared to interband transitions)
and usually emit teraHertz frequency mid infra red beams.
14.5 Semiconductor Lasers 269

When electrons acquire sufficient energy that they are raised to the conduction band
through external pumping (electrical|optical), the empty states left behind in the valence
band are holes. Light is produced when an electron near the bottom of the conduction band
recombines with a hole in the valence band. The photon emitted during this recombination
process carries an energy f h = E GAP . As f = λc , a semiconductor laser can operate only
in a specified wavelength band near λ = Ech GAP
.
Semiconductor lasers operating in the wavelength range 1.3–1.6 microns are used for
optical fiber communications. These use the quaternary compound In1−xGaxAsyP1−y
that is grown in a layer form on InP substrates using molecular beam epitaxy. The lattice
constant of each layer must match the lattice constant of InP to maintain a well defined
lattice structure so that defects are not formed at the interfaces between any two layers
with different bandgaps. The fraction x and y cannot be chosen arbitrarily but are related
as x/y = 0.45 to ensure matching of the lattice constant. The bandgap of the quaternary
compound can be expressed in terms of y only by the empirical relation:

E GAP (y) = 0.12y 2 − 0.72y + 1.35 (14.23a)

where 0 < = y < = 1. The smallest bandgap occurs for y = 1. The corresponding ternary
compound I nd0.55 Ga0.45 As emits light near 1.65μ. By a suitable choice of the mix-
ing fractions x and y, In1−xGaxAsyP1−y lasers can be designed to operate in the wide
wavelength range 1.0–1.65μ that includes the region 1.3–1.6μ important for optical fiber
communication systems.
Electrically pumped semiconductor lasers use a pn junction [19]. The three dimen-
sional physical layered structure of such a laser is in Fig. 14.5b. The central core
layer(“active layer”) is sandwiched between the p type and n type cladding layers, both
of which are doped so heavily that the Fermi-level separation Efc − Efv exceeds the
bandgap energy Eg under forward biasing of the p–n junction.
The central core layer(“active layer”) is the light emitting semiconductor material. The
cladding layers have bandgaps much larger than that of the active layer. The bandgap
difference between the two semiconductors confines the electrons and holes to the
active layer. The active layer has a slightly larger refractive index than the surrounding
cladding layers that acts a planar waveguide whose number of modes can be controlled
by changing the active-layer thickness. This heterostructure design confines both the
injected carriers (electrons and holes) and the light generated within the active layer
through electron–hole recombination. Also the two cladding layers are transparent to the
emitted light owing to their higher bandgap, resulting in a low-loss structure. These features
enable semiconductor lasers to be used for a wide variety of applications.
When the injected carrier density in the active layer exceeds a threshold, population
inversion occurs and the active region exhibits optical gain. An input signal propagating
inside the active layer is then amplified by a factor of e gL , where g is the gain coeffi-
cient and L is the active-layer length. g is calculated numerically based on the rates at
270 14 Semiconductor Optoelectronic Devices

which photons are absorbed and emitted through stimulated emission and these parame-
ters depend on details of the band structure of the active material. The plot of optical gain
(g) versus carrier density (N) for a 1.3μ wavelength InGaAsP has an interesting struc-
ture. Initially when population inversion has not yet occurred, g < 0. As N increases, g
becomes positive over a spectral range that increases with N. The peak value of the gain,
gp, also increases with N, together with a shift of the peak toward higher photon energies,
varying almost linearly for carrier densities above a threshold value. The optical gain in
a semiconductor laser increases rapidly after population inversion.
Based on empirical data, the nearly linear dependence of gp on N is approximated by

gp(N) = σ g(N − N T)

where NT is the transparency value of the carrier density and σ g is the gain cross section
or differential gain. Typical values of NT and σ g for InGaAsP lasers are in the range
1.0–1.5 × 1018 cm−3 and 2–3 × 10–16 cm−2 , respectively. This approximation is valid in
the high gain region where gp > 100 cm−1 .
Semiconductor lasers with a larger value of σ g perform better, since the same amount of
gain can be realized at a lower carrier density or, equivalently, at a lower injected current.
In quantum-well semiconductor lasers, σ g is typically larger by about a factor of 2. The
linear approximation in the equation above for the peak gain can still be used in a limited
range. A better approximation replaces it with gp(N) = g0[1 + ln(N/N0)], where gp =
g0 at N = N 0 and N0 = eNT ≈ 2.718 NT since gp = 0 at N = NT.
A laser can work only when optical gain is combined with optical feedback, which con-
verts any amplifier into an oscillator. In most lasers the feedback is provided by placing
the gain medium inside a Fabry–Perot (FP) cavity formed by using two mirrors. Semi-
conductor lasers do not require external mirrors since the two cleaved facets act as mirrors
owing to the large refractive index difference across the air semiconductor interface. The
facet reflectivity normal to this interface is:
n−1
Rm = (14.23b)
n+1
where n is the refractive index of the gain medium. Typically, n = 3.5, resulting in 30%
facet reflectivity. Even though FP cavity formed by two cleaved facets is lossy, the gain
in a semiconductor laser is large enough that high losses can be tolerated.
The threshold condition that triggers the laser operation is obtained by analysis of
how the amplitude of an optical mode changes during one round trip inside the FP cavity.
Assume that the mode has initially an amplitude A0, frequency f , and propagation constant
β = 2πcf n̄ where n is the mode index. After one round trip, its amplitude increases
by exp[2(g/2)L] because of gain (g is the power gain) and its phase changes by 2βL,
where L is the length of the laser cavity. Simultaneously, its amplitude decreases by
√
R1 R2 e−α I N T L L cause of reflection at the laser facets and because of internal losses
resulting from free carrier absorption and interface scattering. The facet reflectivities R1
14.5 Semiconductor Lasers 271

and R2 can be different if facets are coated to change their natural reflectivity. In the
steady state, the mode should remain unchanged after one round trip:
√
A0 R1 R2 e((g−αINTERNAL )+2 j β)L = A0

1 1
g = αINTERNAL + ln = αINTERNAL + αMIRROR = αCAVITY (14.23c)
2L R1 R2
mc
β L = mπ f = f m =
2n L
where m is an integer. The first equation shows that the gain g equals total cavity loss
αCAVITY at the threshold and beyond. g is not the same as the material gain gm. The optical
mode extends beyond the active layer while the gain exists only inside it. So g = Γgm ,
where Γ is the confinement factor of the active region with typical values <0.4.
From the phase condition above, it is clear that the laser frequency f must match one
of the frequencies in the set f m , where m is an integer. These frequencies correspond
to the longitudinal modes and are determined by the optical length n L. The spacing
f L between the longitudinal modes is the free spectral range associated with any FP
resonator and is given by f L = 2n GROUPc
L which includes material dispersion. Typically,
f L = 150 GHz for L = 250μ.
A semiconductor laser generally emits light in several longitudinal modes of the cav-
ity simultaneously. The gain spectrum g(ω) of semiconductor lasers is wide enough
(bandwidth ~10 THz) so that many longitudinal modes of the FP cavity experience gain
simultaneously. The mode closest to the gain peak becomes the dominant mode. Under
ideal conditions, the other modes should not reach threshold since their gain always
remains less than that of the main mode. In reality, the difference is so small (~0.1 cm−1 )
such that one|two neighboring modes on each side of the main mode share a sizeable
fraction of the laser power together with the main mode. Since each mode propagates
inside the fiber at a slightly different speed because of group velocity dispersion, the
multimode nature of a semiconductor laser often limits the bit rate of lightwave systems
operating near 1.55μ. To circumvent this issue, lasers can be designed to oscillate in a
single longitudinal mode.
The vertical cavity surface emitting laser (VECSEL) [20] is another semiconductor
laser consisting of a surface light emitting semiconductor integrated circuit and a laser
resonator. Unlike other types of semiconductor lasers, a VECSEL can generate high
beam quality, very high power, diffraction limited optical output. Compared to both doped
insulator solid sate and gas lasers, the output wavelength of a VECSEL is tunable.
Physically, a VECSEL (Fig. 14.5c, d) consists of one|more Bragg mirrors and the
active light generation region with several quantum wells, with a total thickness of a few
microns. The laser is fabricated on a semiconductor substrate and the whole structure
is mounted on a heat sink. The laser resonator is created with an external mirror at a
distance varying between a few millimeters and a few centimeters. The constraint is that
for high beam quality output, the length of the resonator should not be much smaller than
272 14 Semiconductor Optoelectronic Devices

the Rayleigh length of the intracavity beam. This external resonator arrangement controls
the laser mode. The external resonator may be folded with additional flat|curved mirrors
and may contain additional optical elements. These additional optical elements include:

• An optical filter for single frequency operation, i.e., wavelength tuning

• A nonlinear crystal for crystal for intracavity frequency tuning
• A saturable absorber for passive mode locking

A VECSEL may be pumped either electrically or optically. For electrically pumped VEC-
SEL, a ring electrode is used to contact the active area. This technique limits the usable
active area and thus the output power, since it is difficult to pump large areas uniformly,
avoiding a weakly pumped region at the center of the active area. Thus electrically pumped
VECSELs can generate a maximum of 1 W of output power.
The optical pumping method circumvents the shortcomings of electrical pumping.
Optical pumping enables large active areas to be illuminated uniformly. No specially
doped regions|structures for carrying current is needed. The pump light is provided by
a high brightness broad area laser diode or diode bar. Due to the very short absorption
length of the semiconductor gain structure (at least for spacer pumping), the beam qual-
ity of the pump light is unimportant, a poor beam quality only requires working with a
strongly converging pump beam, which requires more space and may make it more dif-
ficult to arrange the intracavity elements. A diode bar addresses this problem, enabling
tens of watts of output power. An external resonator is necessary for diffraction limited
output, when the mode area is large. Therefore, VCSELs (having a monolithic resonator)
are not suitable for high powers with perfect beam quality, even with optical pumping.
As the quantum wells are very thin, input optical power absorption is low, if only the
quantum wells are present. To circumvent this issue, a gain structure consisting of spacer
layers between the quantum wells are added to absorb input optical pump radiation. The
carriers generated in these layers can be efficiently transferred to the quantum wells, as
these have a smaller band gap than the spacer layers. Efficient carrier transfer means
that the bandgaps of the spacer and quantum well materials must be widely separated,
and this means that the pump wavelength be much shorter than the laser wavelength.
This increases the quantum defect and thus the dissipated power.
Although in well pumping, i.e. directly pumping the quantum wells is a proposed
alternative. Efficient input pump power absorption can be achieved by using a multipass
pumping scheme, as in a solid state thin disk laser. However, fabricating this VECSEL is
difficult and the optical spectrum the pump radiation must satisfy tight tolerances.
The quantum wells in a VECSEL are fabricated in resonant periodic gain config-
uration—i.e., each well is in an anti node of the electric field distribution for the lasing
wavelength. As different wavelengths have a different standing wave periods, their field
distributions will overlap less perfectly with the quantum wells. This results in lower
confinement factor and consequently reduced effective gain.
References 273

The number of quantum wells used in a VECSEL can vary. A larger number of quan-
tum wells result in a higher gain, but the gain structure becomes thicker with a higher
sensitivity to fabrication errors, strain and temperature effects. Also inhomogeneous gain
saturation can occur as a result of internal temperature gradients and different excitation
levels of the quantum wells. This can be a problem in narrow linewidth or mode locked
VECSELs.
Temperature changes affect both the wavelength of maximum intrinsic gain of the
quantum wells and the field distribution. Heating is unavoidable, so gain structures are
designed so that an optimum match of all parameters is achieved at the expected oper-
ating temperature (not room temperature)—non ideal designs result in significant power
reduction (roll-over) for high pump powers.
Lattice constant mismatch between quantum well material and the material used for
the Bragg mirrors introduces physical strain. Lattice strain induced issues crop up in
the VECSEL output e.g., dark lines from photoluminesence quenching. The problem is
complicated by lattice strain propagating along certain crystal lattice directions. Lattice
strain issues are curbed with additional layers with a intermediate lattice constant and
appropriate thickness. This strain compensation balances compressive and tensile strain.
This similar to the graded doping in metamorphic HEMT examined previously.

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15. International Energy Agency, World Energy Outlook (2006). ISBN: 92 64 10989 7
16. Weber, K.J., Blakers, A.W., Deenapanray, P.N.K., Everett, V., & Franklin, E. (2013). Sliver cells.
In Proceedings IEEE 31st Photovoltaic Specialists Conference (pp. 991–994), 2005.17,16. Pull-
frey, D. Understanding modern transistors and diodes. Cambridge University Press, 2013. ISBN
13 978-0521514606.
17. https://www.epfl.ch/labs/pvlab/research/heterojunction_solar_cells/.
18. https://johnloomis.org/ece445/topics/egginc/pt_char.html.
19. https://www.rp-photonics.com/semiconductor_lasers.html.
20. https://www.fiberoptics4sale.com/blogs/wave-optics/semiconductor-laser-physics.
21. https://www.rp-photonics.com/vertical_external_cavity_surface_emitting_lasers.html.
22. https://www.jameco.com/Jameco/workshop/Howitworks/how-organic-light-emitting-diodes-
work.html.
Gallium Nitride—The Reigning King of Ultra
High Frequency|Power Transistors
15

15.1 Face Centered Cubic Crystal (Zinc Blende) Gallium Nitride

Gallium Nitride appears in two basic crystalline forms (phases)—the face centered cubic
(FCC–Zinc Blende structure) [1–16] (Fig. 15.1a) and the hexagonal close packed (HCP—
Wurtzite structure). The unit cell (for any crystal—e.g., GaN) consists of that unique
combination of constituent atoms (e.g., gallium and nitrogen for GaN) in the three
dimensional space, which translated in appropriate directions, can re-create the entire
crystal. The properties of the face centered cubic (FCC) and hexagonal close packed
(HCP) crystal structures are different. So while FCC GaN is ideal for some applica-
tions, it is inappropriate for others for which HCP is ideal. FCC crystalline structure is a
metastable, β- phase (space group F 43 m) form of gallium nitride, which can be stabi-
lized in epitaxial films. The stacking sequence for the (111) close-packed planes in this
structure is ABCABC. Since the α-(hexagonal close packed) and β-(face centered cubic)
phases of group III-nitrides only differ in the stacking sequence of nitrogen and metal
atom planes, these hexagonal and cubic phases can coexist in epitaxial layers, e.g., due
to stacking faults. Both α, β phases of GaN lack inversion symmetry.
Although the HCP lattice structure GaN is the material of choice for semiconductor
device industry, as it can be deposited without lattice constant mismatch on sapphire
substrates, the FCC crystalline structured GaN is also used in special applications. FCC
lattice structure GaN has higher saturated electron drift velocity and a slightly lower
bandgap than HCP lattice structure GaN. The key crystalline and electronic electronic
properties essential for semiconductor device design and fabrication with both FCC and
HCP crystal structures gallium nitride (GaN) are:

• Energy gap
• Electron affinity

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 275
A. Banerjee, Semiconductor Devices, Synthesis Lectures on Engineering, Science,
and Technology, https://doi.org/10.1007/978-3-031-45750-0_15
276 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

Fig. 15.1 Three dimensional

face centered cubic lattice
structure of GaN. The nitrogen
atoms are located at the center
of each square face, while the
gallium atoms are at the
vertices of the cube

• Conduction band Γ, X valley separation

• Conduction band Γ, L valley separation
• Conduction band effective density of states
• Valence band spin orbital splitting
• Valence band effective density of states
• Effective electron mass
• Effective mass of density of states
• Effective heavy hole mass
• Effective light hole mass
• Effective hole mass split-off band

The numerical values for these properties for both crystal structures are freely available
and downloadable [1–16].
The intrinsic, conduction and valence band carrier concentrations are:
√ −E G A P 3
n i = NC O N D N V AL e k B Tlattice NC O N D = 2.3x1014 T 2 cm −3
3
N V AL =8.0x1015 T 2 cm −3 (15.1)

15.2 Hexagonal Close Packed Structure (HCP Wurtzite) Gallium

Nitride [1–33]

Unlike FCC III-V semiconductors (e.g., GaAs, InP etc.,), the thermodynamically stable
phase of InN, GaN and AlN (i.e., indium nitride, gallium nitride and aluminium nitride) is
the hexagonal close packed (wurtzite) structure [17]. The wurtzite structure (Fig. 15.2a)
consists of alternating biatomic close packed (0001) planes of gallium and nitrogen atom
pairs stacked in an ABABAB sequence. Atoms in the first and third layers are directly
aligned with each other. In this phase III-nitride materials form a continuous alloy system
indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum gallium
15.2 Hexagonal Close Packed Structure (HCP Wurtzite) Gallium Nitride [1–33] 277

nitride (AlGaN) whose direct optical bandgaps range from 0.7 eV for α- InN 1 and 3.4
for α-GaN to 6.2 eV for α- AlN.
The hexagonal crystal structure of group III-nitrides is characterized by three
length parameters a0 (hexagonbaselength), c0 (hexagonalprismheight) and an inter-
nal parameter u defined as the anion cation bond length along the (0001) axis. Owing to
the different cation and ionic radii (Al 3 + : 0.39 Å, Ga 3 + : 0.47 Å, In 3 + : 0.79 Å)
InN, GaN and AlN have different lattice constants, bandgaps and binding energies. The
bonds in the 0001 direction for wurtzite and 111 direction for zincblende are all faced by
nitrogen in the same direction and by the cation in the opposite.
As the basis material for heterostructure growth, GaN is the most investigated nitride
compound. The most common growth direction of hexagonal GaN is normal to the {0001}
basal plane, where the atoms are arranged in bilayers consisting of two closely spaced
hexagonal layers, one with cations and the other with anions. Bilayers have polar faces.
Lack of inversion symmetry means that group III-nitrides do not have any inversion plane
perpendicular to the c-axis. So crystal surfaces have either a group III element (Al, Ga,
or In) polarity (designated 0001) or a N-polarity. Gallium faced means gallium on the
top position of the {0001} bilayer, corresponding to [0001] polarity. Gallium faced does
not mean gallium terminated. As termination describes a surface property, gallium faced
material can be gallium terminated or nitrogen terminated. The gallium, nitrogen (0001)
surfaces of GaN are not equivalent (by convention, the [0001] direction is given by a
vector pointing from a Ga to a nearest neighbor N-atom) along the longitudinal bond. The
properties of GaN that make it very attractive for device applications are:

(a)

(b)

Fig. 15.2 a The hexagonal close packed (HCP wurtzite) lattice structure. b The closed surface
enclosing a volume V, used to measure polarization charge density at the interface
278 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

• High thermal conductivity (4 × that of GaAs) and high breakdown field allow this
material to withstand high power levels.
• A high electron saturation velocity enables GaN to operate at high frequencies.
The peak drift velocity for AlGaN/GaN is 2.7x107 cm/s as compared to AlGaAs/
InGaAs.with 2.1x107 cm/s since an electric field is able to accelerate the electrons up
to higher field values before optical phonon scattering—the optical phonon energy—is
much higher in GaN (91.2 meV) than in GaAs (33.2 meV).

AlGaAs/GaAs Based Devices Are Doped, AlGaN/GaN Are not.

15.3 Piezoelectric and Spontaneous Polarization and Symmetry

No AlGaN|GaN based device is doped because of two crystalline properties—piezo-

electric and spontaneous polarization [17–32]. Certain crystals exhibit an electrical
polarization spontaneous polarization [17–32], characterized by a non-zero value in
absence of an external electric field. This polarization is quantified by the spontaneous
polarization vector, PS P . Spontaneous polarization is different from induced polarization
which occurs only when a dielectric is placed in an electric field.
If a stress σ is applied to certain crystals they develop an electric dipole moment
whose magnitude is proportional to the applied stress—direct piezoelectric effect. The
general relationship between the piezoelectric polarization, the vector PP E , and the second
rank stress tensor, σi j , is given by P jk
i = d σ , where d
i jk jk i jk are elements of the the third
rank piezoelectric moduli tensor. Polarization, as a physical property of a crystal, is related
to the symmetry properties of the semiconductor crystal structures examined here.
Unlike most III-V semiconductor compounds with FCC(zincblende) crystal structure,
the nitride equilibrium crystal structure is the hexagonal wurtzite type. Neumann’s prin-
ciple states that the symmetry elements of any physical property of a crystal must include
the symmetry elements of the point group of the crystal.
Spontaneous polarization, is described by a vector with a fixed orientation in the crystal.
This form of polarization can occur only in those crystals (also called pyroelectric crystals)
for which there is at least one direction (a vector) that remains invariant under all the
symmetry operations of the crystal. This is the case only for rotation through any angle
about the vector and mirrored in any plane containing the vector. Any kind of inversion,
through a centre of symmetry or through the presence of a n-fold inversion axis (rotation
followed by inversion through a given point on the axis) as well as multiple rotation axis
are symmetric elements not compatible with a spontaneous polarization in the crystal. The
key facts about pyroelectric crystals are:

• Pyroelectric crystals do not have a center of symmetry

15.3 Piezoelectric and Spontaneous Polarization and Symmetry 279

• Pyroelectric crystals either have no rotation axis, or have a single rotation axis that is
not an inversion axis.

Point group symmetry rules dictate that both zincblende and wurtzite are non-
centrosymmetrical. The wurtzite lattice, with its unique sixfold symmetry axis and
mirror planes satisfies both requirements and can therefore have a spontaneous polar-
ization which is parallel to the polar axis (c-axis). This is strictly not true for the
FCC(zincblende) lattice, which has both four polar three fold rotation axis (the [111]
equivalent direction) and four fold inversion axis (the [001] equivalent directions). Thus
spontaneous polarization is absent in FCC(zincblende) crystals.
The piezoelectric effect is described by a third rank tensor and is restricted to
non-centrosymmetric classes. From the form of the non-zero components of piezoelec-
tric moduli, FCC(zincblende) symmetry crystals can develop piezoelectric polarization.
Therefore, all pyroelectric substances are also piezoelectric, but not vice-versa.
The macroscopic electric polarization of a crystal is defined as the dipole of a unit cell.
In the lack of a no clear scheme to select the unit cell, taking into account contributions
that result from charge transfer between unit cells across individual cell boundaries. For
example by referring to the two possible choices of zincblende unit cell combined with
the rudimentary approximation of assigning equal positive and negative point charges to
the cation and anion lattice sites, it is seen that the calculated dipoles of the two unit cells
are different.
The spontaneous polarization PS P of a pyroelectric material can not be measured as
an intrinsic equilibrium property, as the physical observables are only the variations of
the polarization ΔP, measured as bulk material properties. In the wurtzite lattice atoms
of opposite electronegativity lie above each other along the symmetry axis and the
charge displacement generates a dipole along the same axis. An atomic relaxation in the
wurtzite structure (non ideal wurtzite) due to Coulomb forces acting differently along c-axis
on the different tetrahedral bonds enhances spontaneous polarization. On the other hand,
the symmetry of the zincblende lattice cancels these contributions along the four [111]
equivalent directions.
The HCP lattice (wurtzite) has the highest symmetry needed for the existence of spon-
taneous polarization. Also, the piezoelectric tensor of wurtzite has three independent
non-vanishing components. So polarization in a III-nitride system will have both a
spontaneous and a piezoelectric component. In the absence of external electric fields,
the total macroscopic polarization P of a solid is the sum of the spontaneous polariza-
tion PS P in the equilibrium lattice and the strain-induced or piezoelectric polarization
PP E .
The spontaneous polarization in the hexagonal close packed (HCP|wurtzite) GaN lat-
tice occurs along the [0001] axis. All subsequent analysis will be with reference to this axis.
The sign of the spontaneous polarization is determined by the polarity and is opposite to
the [0001] direction. The piezoelectric polarization along the c axis is calculated using the
280 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

piezoelectric coefficients e13 , e33 , equilibrium lattice parameters a0 , c0 , in-plane strain

parameters ε1 = ε2 = a−a a0 and out of plane (along c axis) strain parameter ε3 = c0 :
0 c−c0

   
c − c0 a − a0
PP E 3 = e33 ε3 + e31 (ε1 + ε3 ) = e33 + 2e31 (15.2)
c0 a0

The third independent component of the piezoelectric tensor is related to the polar-
ization induced by shear strain and is ignored for heterogeneous epitaxial layers grown
in the [0001] direction, in absence of external applied forces. For the HCP lattice, the
lattice parameters are related via the elastic constants (C13 , C33 ) and then (15.2) can be
re-written as:
   
c − c0 −2C13 a − a0 a − a0 e33 C13
= PP E 3 = 2 e31 − (15.3)
c0 C33 a0 a0 C33

This equation is valid in the linear regime for small strain values. It defines the piezo-
electric tensor through the change in polarization induced by variations of lattice constants
a, c only. Inside the HCP lattice, a strain parallel or perpendicular to the c axis produces
an internal displacement of the metal sub-lattice with respect to the nitrogen ones, i.e.,
a variation of the parameter u of the wurtzite structure. Therefore the spatial distri-
bution of the polarization charges changes in comparison with the unstrained state.
The piezoelectric contribution PP E to the total polarization P becomes large enough so
that it cannot be ignored any more. The calculated values of the piezoelectric constants
in GaN, InN, and AlN are up to ten times larger than in GaAs based crystals and the sign
is opposite to other III-V compounds. The value of the piezoelectric polarization increases
with the strain and, for crystals or epitaxial layers under the same strain, piezoelectric
polarization increases from GaN - > InN - > AlN.
Experimentally measured spontaneous polarization is negative for each of aluminum
nitride (AlN), gallium nitride (GaN) and indium nitride (InN): meaning that for alloys
like Al x Ga1−x N 0 < x < 1 e31 − e33CC3313 < 0.
Therefore piezoelectric polarization is negative for tensile and positive for compressive
strained films, Al x Ga1−x N . So the orientation of the piezoelectric polarization is parallel
to the spontaneous polarization in the case of tensile strain and antiparallel in the case
of compressively strained layers of Al x Ga1−x N . The remainder of the analysis is based
on both the piezoelectric and spontaneous polarizations parallel to the c-axis.
Inside GaN bulk, for homogeneous top|bottom pairs layer the total polarization is con-
stant in the bulk and has a discontinuity at the interface with fixed polarization charge
density σ (Fig. 15.2b). The polarization induced charge density and the fixed polarization
charge density(using theorem of divergence) is:
 
ρ p = −∇ · P σ ΔS = − ρ p d P = − P · n̂ds = (|PT O P | − |PB O T T O M |)d S
(15.4)
15.4 Two Degree Electron Gas (2DEG) GaN-AlGaN–GaN Pseudomorphic … 281

where the cylindrical surface enclosing the volume V, is formed by two surfaces ΔS just
above and below the interface—‘x’ represents the mole fraction.
To estimate the polarization induced sheet charge located at Al x Ga1−x N /Ga N inter-
face, the linearized versions of piezoelectric constants, lattice constants, elastic constants
and spontaneous polarization respectively used:

ei j (x) =xei j (Al N ) + (1 − x)ei j (Ga N ) a0 (x) = 3.189 − 0.077x

c0 (x) =5.189 − 0.203x C13 (x) = 103.0 + 5.0x G Pa
C33 (x) =405.0 − 32.0x G Pa PSpontaneous Polari zation (x) = −(0.052 + 0.029)
(15.5 a,b,c,d,e,f)

where Gpa is GigaPascals and the units of the spontaneous polarization are Coulomb
m2
.
The piezoelectric polarization for partially relaxed barriers can be determined either
by using the measured lattice constants or from the measured degree of relaxation:
  
a0 (x) − a(Ga N ) e33 (x)C13 (x)
PP E (x) = 2(r (x) − 1) e31 (x) − (15.6)
a0 (x) C33 (x)

where r(x) is the degree of polarization relaxation as a function of the mole fraction x.

15.4 Two Degree Electron Gas (2DEG) GaN-AlGaN–GaN

Pseudomorphic Heterogeneous Junction Properties

A junction between two different semiconductor materials on the two sides of the junction
is a heterogeneous semiconductor junction. Moreover, the material on one side has a nar-
row bandgap (type I e.g., Al x Ga1−x As, Al x Ga1−x N ) and as expected, the material on the
other side is wide bandgap (type II GaAs, GaN). Therefore at the junction there are differ-
ences in the conduction and valence bands of the two sides [17]. When equilibrium is
achieved following band bending and corresponding equilibrium Fermi level creation,
a potential well is created at the narrow and wide bandgap material interface junction.
For electrons to collect inside the potential well, the equilibrium Fermi level must lie
inside the potential well. When these conditions are satisfied, a two dimensional electron
gas(2DEG) is produced inside the potential well—key to the operation of a high electron
mobility transistor (HEMT). Figure. 15.3a, b show the band structure of a lightly doped
n type narrow bandgap semiconductor (I) and a heavily n doped wide bandgap semicon-
ductor (II) before and after contact. In thermal equilibrium, the electrons are confined in
the triangular quantum well of the narrow bandgap semiconductor (I) and form a two
dimensional electron gas (2DEG). E C O N D , E V AL , E F , φ S , χ S , VB I are respectively the
conduction band minimum, the valence band maximum, the equilibrium Fermi level, the
semiconductor work function, the electron affinity and the built-in voltage.
282 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

(a) (b)

Fig. 15.3 a, b Energy band diagram and band bending for lightly n doped Type I semiconductor in
contact with heavily doped n type Type II semiconductor to form a heterogeneous junction before
and after contact

The band discontinuity is determined by high electrostatic potential gradients acting

on the carriers on the length scale of some atomic interplanar spacing. The electric fields
V
are are of the order of the atomic fields 108 cm . Since semiconductor (I) has a smaller
gap than semiconductor (II), there are regions in the gap of (II) where the continuum of
bulk valence and conduction band states of (I) leak into the gap of semiconductor (II).
Thus, in limited energy range in the upper and lower parts of the gap of semiconductor
(II) there exist a number of Virtual Induced Gap States (VIGS) derived from the bands
(wave functions) of both semiconductors (I) and (II)—Fig. 15.4a, b. These two diagrams
explain how a semiconductor heterostructure is formed, using the Virtual Induced Gap
States (VIGS) model. The band schemes of two semiconductors are plotted with conduction
and valence band band edges. T he matching of the two band schemes (band offsets), are
controlled by charge neutrality within the VIGS—i.e., equilibrium is achieved only when
the branching energies on the two sides E BI R , E BI IR coincide.
Any electronic state in the gap of a semiconductor, including VIGS, is a mixture of
conduction and valence band states—the corresponding wavefunction is a superposition

Fig. 15.4 a, b Creation of (a) (b)

virtual induced gap states
15.4 Two Degree Electron Gas (2DEG) GaN-AlGaN–GaN Pseudomorphic … 283

of conduction and valence band wavefunctions. The wavefunction of the state closer to the
valence band edge will have a larger contribution from valence band only wavefunctions, as
compared to contribution from conduction band wavefunctions. The crossover point (also
branching point or neutrality point) E B occurs when there is an equal contribution
from both conduction band only and valence band only wavefunctions.
When the Fermi level is close to the branching point of the VIGS, overall charge com-
pensation occurs. When the branching points (E BI , E BI I ) of the two semiconductors do not
match, the negative charge carried by the VIGS below E BI I exceeds (small conduction band
wavefunction contribution) the tiny positive charge in the interface states in the upper half
of the gap. This positive charge is a result of these predominantly acceptor type states hav-
ing a small contribution from valence band only wavefunctions. Both the positive and the
negative interface charges in the VIGS are compensated when the branching points in the
two materials are aligned. From energy balance arguments, the condition of zero interface
dipole therefore requires alignment of the branching energies. For an ideal semiconductor
heterostructure the alignment of the branching points in the two semiconductors yields the
valence-band offset:
   
E BI − E VI IAL − E BI I − E VI IAL = ΔE V AL (15.7)

Built-in potential in a material are from free charges, which accumulate in the lowest
energetic states. Free charges, in combination with the ionized dopants create a space
charge zone. The built-in potential overlaps the effective crystal potential. Its value is
determined by the interface position of the Fermi level and extends on a length scale that
depends on the bulk doping of the two semiconductors, i.e., of the order of the Debye
length. It could be as long as thousand Å for doping of the order of 1016 /cm 3 , or as
short as 10 − 100 Å for doping up to 1020 /cm 3 . The electric fields are similar to the
those which are spread over space charge in a np junction (105 V/cm). Figure 15.5 shows
a depletion region of fixed ionized donor atoms spread in the wide gap semiconductor
near the interface due to the accumulation of donor dopant electrons in the narrow-gap
semiconductor, which form a two dimensional electron gas (2DEG).
The pseudomorphic Ga N − Al x Ga1−x N − Ga N structure (Fig. 15.6) illustrates how
the concepts presented above apply to real world GaN based semiconductor devices. This
semiconductor heterostructure consists of a thick GaN layer deposited on a thin aluminum
gallium nitride (Al x Ga1−x N ) layer, which itself is grown on a GaN buffer layer. The
middle thin AlGaN layer is under tensile strain—the piezoelectric and spontaneous
polarizations point in the same direction. Since the values of the piezoelectric con-
stants and spontaneous polarization increase from GaN to AlN, the total polarization
of a strained (or even unstrained) Al x Ga1−x N layer is larger than that of a relaxed
GaN buffer layer. Consequently, a positive polarization charge is present both at the
lower AlGaN|GaN interface for the gallium face structure and at the upper GaN|AlGaN
interface for the nitrogen face structure. Electrons neutralize this positive polarization
284 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

Fig. 15.5 Spontaneous,

piezoelectric polarizations, two
dimensional electron
gas(2DEG) and tensile strain at
pseudomorphic
GaN|AlGaN|GaN
heterogeneous junction

Fig. 15.6 Energy band

diagram for GaN-AlGaN-GaN
heterogeneous junction

charge resulting in the formation of a two dimensional electron gas(2DEG), when the trian-
gular quantum well at the AlGaN|GaN interface is deeper than the Fermi level. Analogously,
negative polarization sheet charge density results in accumulation of holes at the inter-
face, if the valence band edge of the AlGaN|GaN heterostructure crosses the Fermi level.
For AlGaN|GaN interfaces, the spontaneous and piezoelectric polarization are large
enough to generate 2DEGs with high electron concentration without doping the bar-
rier. In contrast, the 2DEG in AlGaAs|GaAs modulation doped heterogeneous junction is
due to remote doping (Fig. 15.5).

15.4.1 Surface Charge Concentration AlGaN|GaN Interface 2DEG

Exploiting and extending Eqs. 15.2–15.6, the surface (sheet) carrier (charge) concentra-
tion at a AlGaN|GaN interface 2DEG can be estimated [18]. Free electrons compensate a
positive polarization induced sheet charge which is bound at the lower AlGaN|GaN inter-
face for Ga(Al) face or at the upper GaN|AlGaN interface for N-face GaN|AlGaN|GaN
structures. The value of the total polarization induced sheet charge is the same in hetero-
geneous structures of different polarities for a given Al concentration and strain of the
barrier. For undoped Ga-face AlGaN|GaN or GaN|AlGaN|GaN heterogeneous structures,
the sheet electron concentration n SU R F AC E (x) can be calculated by using the total bound
sheet charge σ (x). Equation 15.6 expresses the piezoelectric polarization and Eq. 15.5f
expresses the spontaneous polarization, both as functions of the aluminum mole fraction
15.4 Two Degree Electron Gas (2DEG) GaN-AlGaN–GaN Pseudomorphic … 285

x. The total bound sheet charge density is:

qσ (x) = PS P O N T AN E OU S + PP I E Z O E L EC T R I C E F F EC T (15.8a)

The sheet carrier concentration and carrier distribution profile in doped and undoped
GaN|AlGaN|GaN and AlGaN|GaN heterogeneous junctions are computed numerically
using a Poisson-Schrodinger solver. Contributions from both spontaneous and piezoelec-
tric polarizations are included in the solver using thin layers (few Angstroms thick) of
charge at the heterogeneous structure interface equivalent to the bound sheet charge den-
sity σq . Appropriate boundary conditions at the correct surface and substrate interfaces
need to be added. The aluminum mole fraction based linearized equations for the various
intermediate parameters as bandgap (AlGaN), dielectric constant, Schottky barrier height
(metal contact at the surface), conduction band offset (for the two dissimilar materials at
the heterogeneous junction) are:

ΔE C O N D =10.4 − 0.3x qφ B = 1.3x + 0.84 N ickelContact

ΔE C O N D =0.7(E G A P (x) − E G A P (0))
E G A P (x) =6.13 + 3.42(1.0 − x) − x(1 − x) (15.8 b,c,d,e)

Then the interface sheet electron concentration is:

σ (x) ε0 ε(x)
n SU R F AC E (x) = − (qε B (x) + E F − ΔE C O N D (x)) (15.8e)
q d AlGa N
where a AlGa N is the thickness of the AlGaN layer.

15.4.2 Surface Charge Concentration GaN-AlGaN–GaN Interface 2DEG

The 2DEG in AlGaN|GaN HEMTs is due to the presence of the surface donor states at the
AlGaN top. It is assumed that the donor states are present at the top of the GaN cap layer,
once deposited. Both the GaN cap thickness dcap,Ga N and AlGaN thickness d AlGa N in
combination with the aluminum mole fraction x influence the 2DEG. This analysis uses
the following parameters:

• AlGaN piezoelectric charge density (qσ )

• Dielectric permittivity (ε)
• 2DEG electron concentration (n SU R F AC E )
• Fermi level and conduction band minimum at the GaN heterogeneous junction interface
(E F ).
• Conduction band offset between the AlGaN and GaN at the junction (ΔE C O N D )
• Surface donor level at the top (E d )
• Constant surface donor density (n 0 )
286 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

• Surface barrier height (qφ B A R R I E R )

Both AlGaN, GaN with Wurtzite crystal structure, and asymmetric bonding generates
strong spontaneous polarization charges. The lattice mismatch between the GaN sub-
strate and the AlGaN barrier layer, generates strong piezoelectric polarization charge,
depending on the value of the Al mole fraction x. Denoting the electric fields in the GaN
cap layer and the AlGaN layer as E 1 , E 2 and ignoring E F (of the order of a few multiples
of k B T ) the electric field in the AlGaN layer is:
qφ B A R R I E R + dcap,Ga N E 1
E2 = (15.9a)
d AlGa N
To maintain the continuity of displacement at the GaN cap—AlGaN interface, E 1 , E 2
must satisfy:

q(σ − n SU R F AC E )
εE 2 = qσ − εE 1 E 2 = (15.9b)
ε
Combining Eqs. 15.9a, 15.9b gives the expression for the surface free electron charge
density of the 2DEG:
 
n 0 σ − εqεqdBAlGa
ARRI E R
N
n SU R F AC E = dcap,Ga N
(15.9c)
1 + d AlGa N

The surface barrier height is:

n 0 E d dcap,Ga N + d AlGa N (σ + n 0 E d )
qε B A R R I E R = ε
 (15.9d)
q + n 0 dcap,Ga N + dalGa N

The 2DEG density must monotonically decrease with increasing GaN cap layer thick-
ness. Experimentally it is observed that the 2DEG charge value saturates at higher values
of the GaN cap layer thickness. It has been postulated that this might be because the
valence band and any trapped charge effect are ignored in this analysis. The free electron
2DEG charge density increases with the height of the AlGaN layer even in the presence
of the GaN cap layer. Then the expression for the surface charge density can be re-written
as:
 
n 0 σ d AlGa
ε
N
− Ed
q
n SU R F AC E = (15.9e)
n 0 (dcap,Ga N +d ALGa N )
q +
1
ε

The energy band diagram for this stacked GaN|AlGaN|GaN system is in Fig. 15.6.
15.5 High Electron Mobility Transistor Properties 287

15.5 High Electron Mobility Transistor Properties

State-of-art molecular beam epitaxy (MBE) and chemical vapor deposition (CVD) tech-
niques enable the fabrication of ultra high purity semiconductor layers essential for
constructing High Electron Mobility Transistors (HEMTs). These transistors are essen-
tial for ultra high frequency (10 s of GHz) and power (10 s of Amperes—100 s of Volts)
applications as wireless communication.
The epitaxial growth of wide bandgap AlGaN semiconductor on a thick GaN
undoped buffer layer creates a heterostructure essential for HEMTs. Figure 15.6
shows the schematic structure and electronic band scheme perpendicular to the wafer
surface underneath the gate electrode of an AlGaN|GaN normally on (depletion
mode) HEMT device. The conductive channel is formed by the 2DEG. The band
schemes are under zero gate voltage, in thermal equilibrium, under negative gate
bias. E C O N D , E V AL , E F,metal , E F,semi , qφ SC H O T T K Y B A R R I E R , VG AT E are respec-
tively the conduction band minimum, the valence band maximum, the Fermi level in
metal, the Fermi level in the semiconductor, the Schottky barrier height and applied the
gate voltage. The n channel is built by a 2DEG at the AlGaN|GaN interface with typical
electron concentrations of 1013 cm −2 . Similar transistors based on AlGaAs|GaAs layer
structure have an electron concentration in the 2DEG of 2x1012 cm −2 . Ultra high elec-
tron mobility and low noise operation is a result of high electron concentration (separated
from the ionized donors). Drain and source contacts under the metal overlayers must
make a good ohmic contact to the 2DEG at the interface. In thermal equilibrium, the
conduction, valence band structure along an intersection normal to the layers below the
gate electrode appears in Fig. 15.7. When positive drain voltage is applied, the potential
drop along the source-drain connection perturbs the equilibrium band structure, parallel to
the AlGaN|GaN interface. Depending on the local potential, the accumulation layer does
not contain any more electrons—the position of the Fermi level with respect to the band
edges varies along the current channel.

Fig. 15.7 Layered structure

and energy band diagrams in
equilibrium (“normally on”)
and switched off conditions
288 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

Externally applied gate voltage shifts the Fermi level in the gate metal with respect to
its value deep in the undoped GaN layer. Then due to the Schottky depletion layer just
below the metal gate electrode (donors in the AlGaN layer having been emptied), most
of the voltage drop occurs across this AlGaN layer, thus establishing a quasi-insulating
barrier between gate electrode and 2DEG. Depending on the gate voltage, the triangu-
lar potential well at the interface is raised or lowered in energy and the accumulation
layer is emptied or filled. This changes the carrier density of the 2DEG and switches
the drain source current. For large enough gate bias, the depletion region penetrates
into the 2DEG region, the electron concentration is negligible and the current channel
is pinched off. The corresponding relative gate voltage is called the threshold voltage.
As a depletion mode (normally on) field effect transistor, the amplification is based on
a low voltage gate bias that cuts off the drain source current. A simplified model with the
gate length, width L, W respectively enables the gate capacitance to be estimated:
ε S E M I C O N DU C T O R ε0 L W
C G AT E = (15.10a)
d AlGa N
where εs , ε0 , d AlGa N are respectively the dielectric constant of the semiconductor the
dielectric constant of the vacuum and the thickness of the AlGaN layer below the gate
electrode. The charge density qn SU R F AC E in the 2DEG is induced by the gate voltage
VG AT E , and so the gate capacitance can be re-written as:
dQ qn SU R F AC E L W
C G AT E = ≈ (15.10b)
d VG AT E VG AT E − VB I
where VB I is the built-in voltage at zero external gate bias. For normal operation the drain
source voltage is so high that the electrons in the channel move with saturation velocity
v S AT (v S AT ≈ 107 cm
s ) independent of drain voltage. The drain source current can then be
written as:
C G AT E v S AT U R AT I O N (VG AT E − VB I )
I DS ≈ qn SU R F AC E v S AT U R AT I O N W ≈
L
(15.10c)

The key HEMT parameter describing the performance of HEMT is the transconduc-
tance which defines the change of drain source current with the change of the gate voltage
at constant drain source voltage:
 
∂ I DS qv S AT U R AT I O N W dn SU R F AC E
gm = ≈ (15.10d)
∂ VG AT E,S OU RC E VDS d VG AT E

The transconductance depends on the influence of electron concentration on the gate

voltage. The relation between the transconductance and the gate capacitance defines the
the transit time τ for an electron to pass under the gate.
15.6 Scattering Processes in GaN HEMTs [33–52] 289

1 v S AT U R AT I O N gm
f M AX = = = (15.10e)
τ L C G AT E
where f M AX is the maximum frequency. For gate lengths in the order of 1 μm and
saturation velocities around 107 cm
s transit times of about 10 picosecond are reached. This
makes the GaN HEMT ideal for circuits operating at the microwave frequency range.
To improve the high frequency properties, gate capacitance should be minimized and the
transconductance maximized.

15.6 Scattering Processes in GaN HEMTs [33–52]

The quantum well at the AlGaN|GaN interface results from a large conduction band
discontinuity (as high as 2.4 eV for AlN/GaN), in combination with band bending induced
by charge transfer across the junction leads (a growth in the [0001] direction). As long as
the equilibrium Fermi level lies within the quantum well, free electrons are confined
to the quantum well—2DEG.
The eigenvalues of electrons along the normal to the surface are quantized due to their
confinement in the quantum well. Parallel to the interface the assumption of a free electron
gas, controlled by Bloch waves holds. The eigenvalues of the electrons in a 2DEG are:

2 k x2 2 k 2y
E i2D = + + El (15.11a)
2m xP 2m yP

The 2DEG controls the electronic transport along the interface. In a 3 dimensional non
degenerate semiconductor the transport properties are calculated by solving the Boltz-
mann equation for elastic scattering under the assumption that the relaxation time τm is
averaged through the temperature dependent energy distribution. A 2DEG can be treated
as a degenerate semiconductor: only the electrons near the Fermi edge contribute to the
transport and so the relaxation time is valid only for E = E F . This different energy depen-
dency leads to a different temperature behavior in the 3 dimensional case. The Fermi
√
impulse is dependent on the carrier concentration k F = 2π n SU R F AC E , that determines
the quantity of initial and final states, which are available for scattering processes.
The different scattering mechanisms limit the electron mobility in different ways,
but their effects can be treated as independent of each other. The effective mobility is
expressed in first approximation by the Matthiensen rule:
 
1 1
= (15.11b)
μT O T AL μi
290 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

15.6.1 Polar Optical Phonon Scattering

For the optical phonon the atoms in the elementary cell move in opposite directions. In a
polar crystal this behavior is similar to that of an oscillating dipole moment. Since polar
optical phonons in GaN have large energy (E 0 ≈ 91meV ) compared to the energy sep-
aration between sub-bands, the effect of a large number of sub-bands must be included
when calculating their effects, and the problem changes from two-dimensional to a three
dimensional one. That is electrons absorbing optical photon(s) gain so much energy
that they can be scattered completely out of the confining potential and into the bulk.
Thus an analytical solution to the optical phonon limited mobility uses a variational prin-
ciple method. This scattering mechanism is dominant in degrading electron mobility for
temperatures above 200 K.

15.6.2 Acoustic Phonon Scattering

Acoustic phonons are generated when the crystal lattice atoms move in the same direc-
tion, all together. In modulation doped heterogeneous junction structures, although the
movement of the electrons is confined to a thin layer (~100 Å) near the interface, it is
assumed that acoustic phonons can propagate freely in all three dimensions. The electrons
in a polar crystal can interact either electrostatically through the piezoelectric inter-
action or through the deformation potential. The temperature dependency of mobility of
confined electrons with three-dimensional acoustic phonons due to screened deformation
potential scattering has inverse power law dependency on temperature, just as mobility in
the screened piezoelectric mode. The acoustic phonon scattering rates are linear functions
of temperature. This approximation is true at temperatures at which the thermal energy
is greater than the acoustic phonon energy, but is not true for lower temperatures. Since
temperature independent processes (e.g., Coulomb scattering) dominate the low temper-
ature mobility, the deviations of the acoustic phonon scattering rate from linearity will
have little effect on the total mobility.

15.6.3 Ionized Impurity Scattering

Variations in the perfect crystal lattice structure result in potential variations, and so scat-
ter electrons. For example, the interaction with the Coulomb potential of the ionized
impurities is very strong at low temperatures. In an AlGaN|GaN modulation doped het-
erogeneous junction structure, there are two types of ionized impurity scattering. The
first is scattering by residual ionized impurities in the GaN. In bulk semiconductors, the
ionized impurities occupy the same region of space as the conduction electrons, making
a Coulomb scattering a very efficient process. The electrostatic interaction between an
15.6 Scattering Processes in GaN HEMTs [33–52] 291

ionized donor and a conduction electron is screened by other conduction electrons. How-
ever to achieve the high electron concentrations needed for efficient screening, the crystal
must be highly doped, leading to higher concentrations of ionized impurity centers and
counteracts any beneficial screening effects. The second type is scattering by the ionized
donors in the AlGaN barrier left behind the conduction electrons. Since the electric field
of ionized centers drop off as the distance squared, this type of scattering is much less
effective in limiting the electron mobility, and can be neglected for concentrations up
15
to 10
cm 3
for spacers in the AlGaN barrier less than few hundred Å. Assuming the impu-
rities screening (Thomas–Fermi screening) both two and three dimensional mobilities are
inversely proportional to the impurity concentration. Three dimensional mobility is power
law dependent on the temperature, and two dimensional mobility is power law dependent
on the surface charge concentration. Coulomb scattering rates are often estimated using
a temperature independent approximation for 2DEGs, assuming that all scattering events
involve electrons at the Fermi level. At temperatures above 100 K, as the Fermi level
starts to shift upward, the approximation is invalid, and the mobility is limited by phonon
scattering.

15.6.4 Alloy Disorder Scattering

AlGaN is an alloy of aluminum and GaN. In the alloys the statistical distribution of the
elements leads to local potential fluctuations. The height of the scattering potential can
be assumed as the difference of the energy gaps of the two different binary compounds.
The effect of this scattering mechanism depends on the degree of disorder in the crystal, i.e.
on the frequency of the appearance of the single constituents. This is taken in consideration
through the parameter x(1-x) where x is the mole fraction of the alloy material. The three
dimensional mobility is inversely proportional to both this parameter and the temperature,
while the two dimensional mobility is inversely proportional to this parameter and the
surface charge concentration.

15.6.5 Dislocation Scattering

Common defects in GaN(0001) include stacking disorder|faults, Shockley|Frank partial

dislocations, inversion domains and threading dislocations (TDs). The stacking disorder
and partial dislocations occur in regions immediately adjacent to the substrate and are
associated with the growth of a disordered low temperature nucleation layer. Inversion
domains occur in nitrogen polar domains that have grown either through the free surface
of a Ga polar film or are overgrown by Ga polar material. The TDs have typical total
8 −1010
densities in the range 10 cm 2 as a result of the substantial GaN film substrate chemical
and lattice mismatch. There are two different predominantly observed TDs:
292 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

• pure edge, with Burgers vectors in the family 13 < 2110 > and [0001] line directions
• mixed character, with Burgers vectors in the family 31 < 2113 > and line directions
inclined ∼10o from [0001] towards the Burger vector.

Pure screw TDs, with line direction [0001], represent a small fraction (∼0.1 − 1%) of
the total density of TDs. TDs in the group III-nitrides behave as nonradiative recombina-
tion centers, with energy levels in the forbidden energy gap. These TDs act as charged
scattering centers in doped materials, providing leakage current pathways. The highly
dislocated wurtzite crystal can be considered as consisting of hexagonal columns rotated rel-
atively to each other by a small angle, with inserted atomic planes to fill the space between the
columns—resulting from coalescence of slightly disoriented GaN high temperature islands.
Grain boundaries between prisms as in poly crystalline material would require arrays of
dislocations along the interface between two prisms.
Pure screw and mixed dislocations decrease with distance from the substrate buffer
interface. Edge dislocations with mainly vertical orientation thread to the epitaxial layer
surface. The charged vertical dislocation lines form space charge regions scattering
electrons and reducing mobility.
Mobility reduction also occurs in the buffer region due to scattering at screw disloca-
tions, point defects and stacking faults. Empty traps are electrically neutral, but each filled
trap carries one electronic charge—negatively charged dislocation lines act as Coulomb
scattering centers. The effect of scattering at charged dislocation lines on mobility, as com-
pared to effect of lattice and ionized impurity scattering on mobility, becomes significant
109
at threading dislocation densities above cm 2.
At low growth temperatures “V-defect”s are formed, consisting of six {1011} family
planes and form an inverted hexagonal pyramid. They form mostly at mixed character
TDs. V-defects are speculated to be due to a kinetically limited growth process such that
the surface depression associated with a TD assists in the formation of {1011} facets. For
HEMTs the V-defects form during the last grown AlGaN layer and concentrate electric
fields at ohmic source drain and Schottky gate contacts. The two dimensional electron
mobility is inversely proportional to the number of dislocations and directly power law
proportional to the surface charge density.

15.6.6 Interface Scattering

In a quasi two dimensional electron gas the charge transport takes place along the interface
between two semiconductors. As expected, interface roughness produces an additional
deviation from the periodical lattice and can substantially reduce the mobility of a 2DEG.
Theoretical calculations performed on AlGaN|GaN wurtzite and zincblende heterogeneous
junction structures(to determine the scattering processes that limit the electron mobility)
indicate that:
15.7 Basic and Advanced Physical Structures of HV, RF HEMTs 293

• At room temperature, the mobility is dominated by polar optical phonon scattering.

• For higher sheet electron densities in the 2DEG the remote donor (impurity) and
piezoacoustic scattering processes (which dominate at lower sheet densities) are
screened and the electrons are pushed closer to the interface.

For poor interface quality, the mobility is significantly reduced due to increase in interface
2
roughness scattering. For ideal defect free interfaces, the mobility is 2000cm Vs at room
temperature, which does not agree with either theoretically estimated or experimentally
measured values. Depleting the electrons from the 2DEG channel by applying negative
gate voltage the electron screening is less effective and Coulomb scattering dominates.
Increasing the negative gate bias, the maximum mobility shifts towards higher temperatures
along with decrease of the maximum mobility.

15.6.7 Dipole Scattering

Dipole scattering is dominant scattering mechanism at low temperatures. The 2DEGs

in III-V nitride modulation doped heterogeneous junction structures are polarization
induced, compared to the 2DEG in modulation doped heterogeneous junction structures
in AlGaAs|GaAs and gate induced inversion in Si-MOSFETs. Spontaneous and piezo-
electric polarization in III-V nitride modulation doped heterogeneous junctions is large
enough to produce 2DEGs without doping the barrier. Strong polarization along the c-
axis of the wurtzite nitride compounds and fluctuations of a perfectly periodic structure
in the AlGaN alloy, a random distribution of microscopic dipoles in AlN and GaN regions
of the alloy scatters the electrons in 2DEG.

15.7 Basic and Advanced Physical Structures of HV, RF HEMTs

While semiconductor device research groups and semiconductor device manufacturers

have improvised a variety of physical structures for the GaN based HEMTs, the common
property shared by each of them is that the power HEMTs are less complicated than the
ultra high frequency counterparts. Typical layered structure of these two devices is shown
in Fig. 15.8.
To satisfy the ever increasing stringent performance characteristics being placed on
GaN HEMTs for wireless communications (e.g., K-, W-band wireless communications)
and high power switching (e.g., electric vehicle battery charging) a number of innovative
features have been added to GaN HEMTs.
294 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

Fig. 15.8 Typical layered structure of power and RF GaN HEMTs. Dashed lines indicate 2DEG

15.7.1 Gate and Source Connected Field Plates [53]

The cross sections of a gate and a source connected field plate structures in GaN HEMTs
are in Fig. 15.9a, b respectively. The field plate (FP) lowers the electric field peak value,
thereby changing the electric field profile. Unwanted trapping effects are minimized and
breakdown voltages are increased. Initial FPs were either constructed as part of the gate or
tied to the gate externally. This improves large signal|power performance as well as high
voltage operation. Up to a critical value for the FP length, increasing its physical length
increases output power. But in this configuration the capacitance between the FP and drain
becomes gate to drain capacitance C G D , causing negative Miller feedback, which in turn
reduces both current gain and power gain cutoff frequencies( f T , f M AX ).
As the voltage swing across the gate and source is only 4–8 V for a typical GaN
HEMT, much less than the dynamic output swing up to 230 V, terminating the FP to
the source also satisfies the electrostatics for it to be functional. With the source tied FP,
the FP-to-channel capacitance becomes the drain-source capacitance, which is absorbed
in the output tuning network. The key drawback of the gate tied FP, i.e., additional gate
drain capacitance, is eliminated. Depending on the implementation, the source connected
field plate can add parasitic capacitance to the device input. This parasitic capacitance is
absorbed into the input impedance tuning circuit, for narrow band signals.

15.7.2 Deep Recessed Gate HEMTs [53]

Silicon nitride(Si N x ) passivation is used to reduce the dispersion, but reproducibility of

breakdown voltage, gate leakage, and effectiveness of dispersion elimination is strongly
fabrication|process related. A solution, based on molecular beam exitaxy (MBE) is the
deep recessed GaN HEMT with a thick cap layer to eliminate dispersion (Fig. 15.9c, d).
The effect of the surface on the channel is inversely proportional to the distance between
surface and channel. The thick AlGaN or GaN cap layers in the deep recessed HEMTs
15.7 Basic and Advanced Physical Structures of HV, RF HEMTs 295

(a)

(b)

(c)

(d)

Fig. 15.9 a, b Gate, source connected field plate structures for GaN HEMTs c, d Deep recessed gate
structures with AlGaN and GaN caps. e, f MOSHEMT and ion implanted drain source AlGaN|GaN
HEMT. g Conduction band of back InGaN plane HEMT
296 15 Gallium Nitride—The Reigning King of Ultra High Frequency|Power …

increase the surface-to-channel distance, minimizing surface trap induced dispersion. Sur-
face passivation is not necessary, as only a smaller portion of the channel charge is affected
compared to the original AlGaN|GaN HEMT structure. The graded AlGaN layer is Si-doped
to compensate the negative polarization charge and prevent hole accumulation.
The device fabrication processing flow is similar to that of the standard HEMT except
that to create the deep ohmic and gate recess. A processing trick that reduces gate leakage
by two orders of magnitude and also increases the breakdown voltage is to treat the
recessed surface with fluorine plasma before gate metallization.
Accurate control of recess depth is achieved with a selective dry etch using a mixture
of boron trichloride and silicon hexafluoride (BCl3 S F6 ). Fluorine decreases the etch rate
of AlGaN due to the formation of a non-volatile aluminum trifluoride (Al F3 ) residue on
the AlGaN surface. The deep-recessed structure has a GaN cap(>200 nm) and an abrupt
GaN|AlGaN interface to clearly define the etch-stop position.

15.7.3 Metal Oxide Semiconductor(MOS) HEMT [53]

The MOSHEMT (Fig. 15.9e) exploits the best features of both the MOSFET and the GaN
HEMT. Specifically, the MOS structure minimizes gate leakage current and the AlGaN/
GaN heterogeneous junction provides high density high mobility 2DEG channel.
Just like in a regular AlGaN|GaN HEMT, the MOSHEMT’s built-in channel is formed
by the high density 2DEG at the AlGaN|GaN heterogeneous junction. The key difference
between a AlGaN|GaN based MOSHEMT and the corresponding regular HEMT, is that the
gate metal is isolated from the AlGaN barrier layer by a thin dielectric film (e.g., silicon
dioxide, aluminum nitride|oxide, zirconium oxide, niobium oxide, hafnium dioxide). So,
the MOSHEMT gate behaves like the gate in a regular MOSFET. Because a properly
designed AlGaN barrier layer is fully depleted by electron transfer to the adjacent GaN
layer, the gate insulator in the MOSHEMT consists of two sequential layers: dielectric
film (e.g., silicon dioxide) and AlGaN epitaxial layer. The advantages of the double layer
are:

• Extremely low gate leakage current–density.

• Large positive to negative gate voltage swing.

The maximum DC saturation drain current at positive gate voltages is a key parameter
controlling maximum output RF power. For standard AlGaN|GaN HEMTs, gate voltages
above 1.2 V result in excessive forward current. In contrast, for a MOSHEMT, the gate
voltages as high as 10 V cause no problems, resulting in significant increase in maximum
channel current.
The gate-to-source spacing of a RF (e.g., millimeter wave) HEMT must be minimized,
to keep the source access resistance low. Conventional alloyed ohmic contacts have rough
References 297

edges, which prevents the source gate spacing from being reduced below a limit. Therefore,
a non-alloyed ohmic contact is preferred for the high frequency devices. Ion implanta-
tion has been used in the GaN device fabrication to form non-alloyed ohmic contacts
(Fig. 15.9f).
To boost the performance of GaN HEMTs beyond the Ka-band, the standard HEMT
features as shorter gate length, multiple fingers to reduce gate resistance and Γ-shaped.
gate to decrease gate-to-drain capacitance, are being augmented with the back barrier
structure, whose energy band diagram is shown in Fig. 15.9g.

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