AND8S001/D Odd Number Divide By Counters With 50% Outputs and Synchronous Clocks Propared by: Cleon Petty and Paul Shockman Product Applications, ‘ON Semiconductor The application inquiries handled by the Product Applications gives opportunities to solve customer needs ‘with new ideas and learn of ways the customer has used our devices in new applications. A. couple of these calls lead to techniques of designing odd number counters with synchronous clocks and 50% outputs. The first technique requires a differential clock, that has 250% duty cycle, a extra Flip Flop, and a gate to allow Odd Integers, such as 3,5, 7, 9, to have 50% duty cycle outputs and a synchronous clock. The frequency of operations is, Limited by Tpdof the driving FF, Setup, and Hold ofthe extra FF, and the times cannot exceed one half on the incoming, clock cycle time. The design begins with producing a odd number counter (Divide By 3 for this discussion) by any means one wishes ON Semiconductor omeiy a Division of Motor http:/onsemi.com APPLICATION NOTE and add a flip flop, and a couple of gates to produce the desired function. Karnaugh maps usually produce counters that are lockup immune. Exampl Specify, Divide By 3, 450% duty cycle on the output ‘Synchronous clocking 150% duty cycle clock in Using D type Flop flips and Karaugh maps we find: Ad= A*B® and Bd =A (Note: * indicates BAR function) Figure 1 shows schematic and timing of such a design, Divide By 3 JUL LLL J LF LE a es ee Figure 1. October, 1999 Rev. 0 Publication Order Number "ANDGO1/DAND8001/D Using the technique, we add a gate on the clock to get differential Clock and Clock bar, a flip flop that triggers on the Clock Bar rising edge (Clock Neg.) to shift the output of “B” by 90 degrees and a gate to ANDIOR two FF output 10 produce the 50% output. We get Figure 2, a Divide By 3that clocks synchronously with 50% output duty cycle. | L{ jp p Pp > so% out A 8 c a a a c c c chkin Divide By 8 WI50% out om FT LELE LAL LL ag _J LF Ba ca or Figure 2. The Max frequency of the configuration (figure 2) is calculated as Clock input freq /2 = Tpd of FF "B” + Setup of °C" + Hold of "C Example: ‘pd = INs, Setup = INS and Hold time = ONs. with these numbers the Max Frequency the configuration ‘can expect is: Cycle time =2* (1 + 1)Ns or 4 Ns that converts to 250MHZ. The Method is usable on other divide by "N” counters as ‘well by using the same methodology. The use of different types of Flip Flops (J.K. S.R, Toggle, ETC.) may produce fewer components, The type logic used may also dictate ‘configuration. The configuration should always be checked for lockup conditions before the design is committed to a production, Exampl ADivideBy 3 design hasall possiblestates shown in chart 1 but uses only the states shown in chart 2 leaving the states 2.3.4.5, & 7 for possible lockup. char 1 Chart 2 A BC A BC 0 0 0 0 o 0 0 0 1 410 0 4 4 0 0 2 0 1 0 eo 1 4 3 1 1 0 40 0 1 5 1 0 4 6 oo 1 4 7444 htp:/onsemi.com 2AND8001/D We need to know that the counter will go into the flow, shown in chart 2, if i happens to come up in one of the unused states at powerup or for any other reason, Figure 3 shows the resulting flow chart of the analysis of the Divide By 3 counter of Figure 2. There is no state thatthe counter can begin in that doesn’t lead to the desired flow after one clock cycle. Figure 3. Observation shows that FF "C” follows FF "B” by a half ‘a clock cycle and will never be able to lockup making the analysis of the Divide By 3 sufficient to assure the whole configuration will have no lockup flow. So; only the 11 state of the divide by three needed to be confirmed. ‘The method is extendible o other odd larger divide by "N’ numbers by following the same design flow: a) Design a stable UP or Down divide by "N” counter b) Make the Clock input a 50% duty cycle differential signal Add a FF to follow one of the FF’s in the counter by 1/2 clock cycle 4d) ORVAND the shifted FF with the one tha is driving it 10 obvain the desired 50% output Exampl Design a 50% Divide By 9 Use "D” type FF's, other types may give smaller component count Karnaugh maps yield: Ad= AB? Bd=A"B+AB* Cd = ABC* + CBP + A°C Da=ABC htp:/onsemi.com