SRM VALLIAMMAI ENGINEERINGCOLLEGE

(An Autonomous Institution)

SRM Nagar, Kattankulathur–603203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

VI SEMESTER
1906008 - EMBEDDED AND REAL TIME SYSTEMS

Regulation–2019

Academic Year 2022–2023

(Even Semester)

Prepared by
Dr. V. Suresh Kumar, Assistant Professor
D. Murugesan, Assistant Professor
J. Charles Vinoth, Assistant Professor
 SRM VALLIAMMAI ENGINEERING COLLEGE
(An Autonomous Institution)
SRM Nagar, Kattankulathur–603203.

DEPARTMENTOF ELECTRONICS AND COMMUNICATION

ENGINEERING

Question Bank
SUBJECT : 1906008–EMBEDDEDAND REAL TIME SYSTEMS
SEM / YEAR : VI / III-Year B.E.

UNIT I - INTRODUCTION TO EMBEDDED SYSTEM DESIGN

Complex systems and microprocessors– Embedded system design process –Design example:
Model train controller- Design methodologies- Design flows - Requirement Analysis –
Specifications-System analysis and architecture design – Quality Assurance techniques -
Designing with computing platforms – consumer electronics architecture – platform-level
performance analysis.
PART -A
Q. No Questions BT level Domain
1. Define Embedded system. BTL 1 Remembering
2. What are the applications of an embedded system? BTL 1 Remembering
3. What are the typical characteristics of an embedded system? BTL 1 Remembering
4. List the important considerations when selecting a processor. BTL 2 Understanding
5. Classify the processors in embedded system BTL 4 Analyzing
6. List the steps in embedded system design process. BTL 2 Understanding
7. Mention the challenges in the design of embedded computing BTL 3 Applying
system.
8. List the non-functional requirements of an Embedded BTL 1 Remembering
Architecture.
9. Give the major levels of abstraction in the Embedded system BTL 3 Applying
design.
10. What are the services to be provided by consumer electronics? BTL 1 Remembering
11. What you mean by real time computing? BTL 2 Understanding
12. Identify the various issues in real time computing. BTL 2 Understanding
13. Mention the observations of quality management of ISO 9000. BTL 2 Understanding
14. Draw the functional architecture diagram of multimedia player. BTL 3 Applying
15. Interpret the importance of DCC in train controller. BTL 3 Applying
16. Illustrate the need of flash file systems in consumer electronics. BTL 3 Applying
17. Assess the characteristics of embedded computing. BTL 4 Analyzing
18. Categorize the steps involved in system analysis using CRC BTL 4 Analyzing
card.
19. Write the requirements chart for GPS moving map system. BTL 1 Remembering
20. Justify the need of UML language for Embedded system
BTL 4 Analyzing
design.
21. Depict the UML notation for display class. BTL 4 Analyzing
22. Summarize the five levels of maturity in CMM model. BTL 2 Understanding
23. Sketch the block diagram of moving map GPS system BTL 2 Understanding
24. What software factors might be considered when choosing a
BTL 4 Analyzing
computing platform?
PART-B
1. Discuss in detail about the characteristics features of
(13) BTL 2 Understanding
Embedded computing applications
2. Write in detail about the challenges in embedded computing
(13) BTL 4 Analyzing
system design.
3. Briefly Illustrate the performance of embedded computing
(13) BTL 2 Understanding
systems.
4. Explain in detail about various levels of abstraction in the
(13) BTL 3 Applying
embedded system design process with necessary diagrams
5. Analyze the requirements and write the requirement chart
needed for designing a GPS moving map in embedded system (13) BTL 4 Analyzing
design process.
6. Write down the major operations and data flows of a GPS
moving map and draw its hardware and software architecture (13) BTL 3 Applying
diagrams.
7. (i). Explain a Model Train Controller with suitable diagrams.
(5)
(ii). Outline the design steps of Model Train Controller in BTL 2 Understanding
(8)
detail.
8. Describe the goal of design methodology in detail. (13) BTL 1 Remembering
9. Illustrate with diagrams the system design methods using
(13) BTL 2 Understanding
waterfall, spiral and successive refinement model.
10. Explain briefly about hardware/software design system,
hierarchical design flows and concurrent engineering models (13) BTL 4 Analyzing
with necessary diagrams.
11. Describe in detail about Control-Oriented Specification
Languages used in design of embedded system with necessary (13) BTL 3 Applying
diagrams.
12. What is CRC and explain the system analysis and architecture
(13) BTL 1 Remembering
design using CRC card Layout.
13. What is Quality assurance? and explain briefly about the
(13) BTL 1 Remembering
quality assurance techniques
14. Write short note on the following in terms of consumer
electronics system architecture. (6)
BTL 1 Remembering
i. Use cases and requirements. (7)
ii. Platforms and Operating Systems.
 15. Examine in detail the about the main components of designing
(13) BTL 4 Analyzing
with computing platforms.
16. With necessary diagram explain the need of platform level
(13) BTL 3 Applying
performance analysis.
17. (i). What are the factors to be considered while designing an (6)
Embedded System Process?
BTL 4 Analyzing
(ii). State the importance of Structural and Behavioral (7)
description in detail.
PART -C
1. Summarize the different factors involved in embedded system
design process of GPS moving map with necessary (15) BTL 1 Remembering
illustrations.
2. Justify the need of Quality Assurance techniques in
(15) BTL 2 Understanding
Embedded design and explain.
3. Develop the requirement, specification, and state diagram of a
(15) BTL 3 Applying
model train controller with necessary illustrations.
4. Analyze the steps involved in complex embedded system
design with an example of consumer electronics architecture in (15) BTL 4 Analyzing
detail.
5. Design an Alarm clock and explain the various steps involved
(15) BTL 4 Analyzing
in the design of computing system.

UNIT II - ARM PROCESSOR AND PERIPHERALS

ARM Architecture Versions – ARM Architecture – Instruction Set – Stacks and Subroutines – Features of the
LPC 214X Family – Peripherals – The Timer Unit – Pulse Width Modulation Unit – UART – Block Diagram
of ARM9 and ARM Cortex M3 MCUhavard.
PART A
Q. No Questions BT Level Competence

1. List the functions of ARM processor in Supervisory mode. BTL 1 Remembering

Write down the main differences between Von Neumann and BTL 3 Applying
2.
Harvard architecture.
3. Differentiate CISC and RISC architectures. BTL 3 Applying
4. What is "Thumb" in ARM processor? BTL 1 Remembering
5. List the three different profiles of ARM cortex Processor. BTL 1 Remembering
6. Differentiate between assembler and compiler. BTL 3 Applying
7. Name the registers set of ARM processor. BTL 1 Remembering
8. What is the use of CPSR Register? BTL 4 Analyzing
9. What is instruction pupelining? BTL 1 Remembering
10. Write down the significance of TST instruction. BTL 2 Understanding
11. State the usage of EQU directive in programming. BTL 2 Understanding
12. Draw the sequence of actions needed for a nested procedure. BTL 4 Analyzing
13. What is meant by idle mode in processors? BTL 3 Applying
14. Outline the significance of SWI instruction. BTL 2 Understanding
15. Compare the differences between MULS and MULSEQ. BTL 3 Applying
16. Find the methods to terminate the power down mode. BTL 3 Applying
Give the maximum size of the constant that can be used in the BTL 3 Applying
17.
immediate mode?
18. Distinguish between PCLK and CCLK. BTL 4 Analyzing
For a GPIO pin to be made to act as an ON/OFF switch, what are BTL 4 Analyzing
19.
the registers to be used?
20. Write the difference between single and double edged PWM. BTL 4 Analyzing
Mention the important features that make ARM ideal for BTL 2 Understanding
21.
embedded applications.
22. What will be the output of the instruction MOV R11, R2? BTL 4 Analyzing
23. How does the prescalar in a timer unit function? BTL 2 Understanding
24. What is interrupt Latency? BTL 1 Remembering
PART – B
1. With necessary diagrams briefly explain about the register set of (13)
BTL 1 Remembering
ARM processor.
2. Describe briefly about the operating modes of ARM and also (13)
explain about mode switching. BTL 2 Understanding

Illustrate in detail about the interrupt vector table by providing the (13)
3. BTL 4 Analyzing
vector address of each interrupt supported by ARM.
(i) Classify the ARM instruction set. (3)
4. (10) BTL 4 Analyzing
(ii) Explain any one type of instruction set with example.
Write the general structure of an Assembly language line and (13)
5. explain briefly about directives used in ARM with examples for BTL 1 Remembering
each directive.
What are the types of stacks and subroutines supported by ARM (13)
6. BTL 2 Understanding
processor? Explain with the instruction sets.
Explain the following indexed addressing mode with a sample
instruction.
7. (7) BTL 4 Analyzing
i) Pre indexed Addressing mode.
(6)
ii) Post indexed Addressing mode.
Discuss in detail about Arithmetic and logical instructions of (13)
8. BTL 4 Analyzing
ARM with examples for each.
Explain in detail about Compare and branch instructions of ARM (13)
9. BTL 3 Applying
with examples for each.
With neat block diagram explain the architecture of LPC2148 (13)
10. BTL 3 Applying
ARM7 MCU and its features.
Illustrate briefly about Rotate and Shift instructions of ARM with (13)
11. BTL 3 Applying
examples for each.
Explain in detail about the working of timer unit of LPC2148 with (13)
12. BTL 4 Analyzing
its associated registers.
13. With neat block diagram illustrate the working of a UART in (13)
BTL 3 Applying
LPC214x ARM.
 14. Draw the architecture of ARM Cortex M3 MCU processor and (13)
BTL 6 Creating
describe its functional units.
15. Describe briefly about the concepts behind single edge controlled (13)
BTL 2 Understanding
PWM.
16. (i) Calculate the value of the clock to be given in PWMMR0 (7)
andPWMMR3 to get a pulse train of period 5 ms and duty
BTL 5 Evaluating
cycle of 25%.
(6)
(ii) List the features of LPC 214x processor.
17. With necessary illustrations explain the features of the ARM 9 (13)
BTL 1 Remembering
processor Core.
PART – C
1 Write a program to find the sum of 3X + 4Y + 9Z, where X = 2, (15)
BTL 3 Applying
Y = 3 and Z = 4 using ARM Processor instruction set.
2 Find the output of the program using ARM instructions for 3X2 + (15)
BTL 4 Analyzing
5Y2, where X = 8 and Y = 5.
3 Summarize the procedure to generate the square wave from Timer (15)
BTL 2 Understanding
unit in LPC214x chip with an example code.
4 (i). With necessary illustrations, explain the control registers of (6)
PWM unit.
(ii) Determine the values to be entered in the PWMPCR register (9)
for the following situations?
BTL 1 Remembering
i) Single edge control for PWM3.
ii) Double edge control for PWM3.
iii) Single edge control for PWM1, 2 and 3.

5. The content of registers is given as below

R1 = 0xEF00DE12,
R2 = 0x0456123F,
R5 = 4, R6 = 28.
What is the output result in the destination register when the
BTL 4 Analyzing
following instructions are executed? (4)
i) LSL R1, #8 (4)
ii) ASR R1,R5 (4)
iii) ROR R2,R6 (3)
iv) LSR R2,#5

UNIT III EMBEDDED PROGRAMMING

Components for embedded programs- Models of programs- Assembly, linking and loading – compilation
techniques- Program level performance analysis – Software performance optimization – Program level energy
and power analysis and optimization – Analysis and optimization of program size- Program validation and
testing.
PART A
Q. No Questions BT Level Competence

1 Mention the different components for embedded programs. BTL 1 Remembering

2 State the basic principle of compilation technique. BTL 1 Remembering
Name any two techniques used to optimize execution time of
3 BTL 1 Remembering
program.
4 Mention the various compilation techniques. BTL 1 Remembering
5 What does a linker do? BTL 1 Remembering
State the difference between program location counter and
6 BTL 1 Remembering
program counter.
7 Illustrate the need of symbol table in Assemblers. BTL 2 Understanding
8 Outline the significance of CDFG. BTL 2 Understanding
Summarize the two ways used for performing input and output
9 BTL 2 Understanding
operations
10 Describe about the elements of program performance. BTL 2 Understanding
Draw a Data Flow Graph and Control/ Data Flow Graph (CDFG)
11 BTL 3 Applying
with an example.
12 Interpret the differences between loop fusion and loop tiling BTL 3 Applying
13 Find the limitation of polling techniques. BTL 3 Applying
14 Compare enqueueing and dequeueing BTL 4 Analyzing
15 State the importance of Boot-block flash. BTL 4 Analyzing
16 Differentiate compiler and cross compiler. BTL 4 Analyzing
17 Write the importance of circular buffer. BTL 1 Remembering
18 Draw the diagram of software state machine. BTL 4 Analyzing
Draw a Data Flow Graph for the block shown below:
19 BTL 4 Analyzing
r = a+b-c; s = a*r ; t = b-d; r = d+e;
20 How power can be optimized at the program level? BTL 3 Applying
21 What is program optimization in embedded system? BTL 1 Remembering
How power can be optimized at the program level in embedded BTL 3 Applying
22
system?
23 What are the basic compilation techniques in embedded systems? BTL 1 Remembering
24 List out the challenges facing in embedded software testing. BTL 1 Remembering
PART – B
1 Summarize the components of embedded program and discuss in (13)
detail about each component. BTL 2 Understanding
2 Describe about stream-oriented programming and circular buffer (13)
BTL4 Analyzing
with example.
3 (i) List the different models of Program.
(3)
(ii) Briefly explain with neat diagrams on various models of BTL 1 Remembering
(10)
program.
4 Examine the Data flow graph with the help of an example. (13) BTL 2 Understanding
Illustrate the Control /Data flow graph for a While loop with (13)
5 BTL 1 Remembering
necessary diagrams and explain.
6 In compilation process, explain the role of
i) Assemblers (7) BTL 2 Understanding
ii) Linkers (6)
7 With the help of a flow chart describe the basic compilation (13)
process and explain. BTL 3 Applying
 8 Determine the code generated for the given conditional code (13)
snippet, explain with necessary CDFG.
if (a + b > 0)
x = 5; BTL 4 Analyzing
else
x = 7;
9 Outline about the Procedure and Data structure with respect to (13)
BTL 1 Remembering
compilers.
10 Interpret the need of dead code elimination to optimize the (13)
program with a code snippet. BTL 3 Applying

11 Write about the Loop transformation techniques for optimization (13)

of code. BTL 1 Remembering
12 Outline the Program level energy and power analysis and (13)
optimization. BTL 4 Analyzing
13 Write about
i) Black box Testing (7) BTL 1 Remembering
ii) White box Testing (6)
14 (i) With necessary diagrams about the program level (7)
performance analysis. BTL 3 Applying
(ii) Mention the key features of cache optimizations. (6)
15 Outline the verification techniques involves in Embedded Systems (13)
BTL 4 Analyzing
16 Describe in detail about the assembly linking and loading in (13)
BTL 2 Understanding
Embedded system programming?
17 Interpret the Program level performance analysis in embedded (15)
BTL 3 Applying
system.
PART C
1 Write a symbol table for the following code snippet and explain in (15)
detail.
ORG 100
label1 ADR r4,c
BTL 1 Remembering
LDR r0,[r4]
label2 ADR r4,d
LDR r1,[r4]
label3 SUB r0,r0,r1
2 Describe he statement translation into ARM instruction for the (15)
expression a*b + 5*(c-d) with necessary illustrations. BTL 2 Understanding

3 Interpret the various methods for Program optimization with (15)

necessary examples. BTL 3 Applying
4 Outline the different techniques used in software performance (15)
BTL 4 Analyzing
optimization.
5 Why the person generating clear-box program tests should not be (15)
BTL 4 Analyzing
the person who wrote the code being tested.

UNIT IV REAL TIME SYSTEMS

Structure of a Real Time System –– Estimating program run times – Task Assignment and Scheduling –
Fault Tolerance Techniques – Reliability, Evaluation – Clock Synchronization.
PART A
Q.No. Questions BT Competence
Level
1 List out the two Rate Monotonic scheduling conditions. BTL 1 Remembering
2 Outline the uniprocessor scheduling algorithms. BTL 1 Remembering
3 Define Performance measures for real time systems. BTL 1 Remembering
4 What is mean by hardware and software fault? BTL 1 Remembering
5 State the limitation of Rate Monotonic algorithm. BTL 1 Remembering
6 Define hardware redundancy. BTL 1 Remembering
7 Summarize the two steps of tasks for developing a multiprocessor BTL 2 Understanding
schedule.
8 Draw the performance degradation graph of a fault tolerant system BTL 2 Understanding
9 Explain the forward and backward error recovery. BTL 2 Understanding
10 Classify the partitioning of the inter-vote interval. BTL 2 Understanding
11 Illustrate the role of static priority algorithm. BTL 3 Applying
12 Sketch the frequency response of an ideal VCO. BTL 3 Applying
13 How will you distinguish static priority algorithm & dynamic priority BTL 3 Applying
algorithm?
14 Outline the features of preemptive and non-preemptive schedule. BTL 4 Analyzing
15 Compare the difference between release time and deadline. BTL 4 Analyzing
16 Identify the fault types based on temporal behavior classification. BTL 4 Analyzing
17 Write the ways of assigning priorities in scheduling. BTL 2 Understanding
18 What are the features of offline and online scheduling? BTL 1 Remembering
19 Write about malicious or byzantine failures. BTL 2 Understanding
20 Compare the difference between periodic, sporadic and aperiodic tasks. BTL 4 Analyzing
21 Compare between the Rate-Monotonic and Deadline-Monotonic BTL 4 Analyzing
Algorithms.
22 What are the various scheduling criteria for CPU scheduling? BTL 1 Remembering
23 Draw the state diagram of task? BTL 2 Understanding
24 Mention some task scheduling algorithms. BTL 1 Remembering

PART B
1 Write a short notes on transient faults and the use of state aggregation
BTL 2 Understanding
(13)
2 i) List out the sequence of events resulting in triad failure. (6)
ii)Explain the methodology to choose the best distribution for obtaining BTL 1 Remembering
parameter values in model. (7)
3 Describe the typical designs for voter reliability with the example of
Poisson failures. (13) BTL 1 Remembering
4 Mention the classification of faults according to their temporal behavior
and output behavior and explain. (13) BTL 1 Remembering
5 Write a detailed note on mathematical understanding of the priority
BTL 2 Understanding
ceiling algorithm using a series of results. (13)
6 Summarize the important features on :
a) Software Redundancy in Fault tolerance techniques. (6)
BTL 2 Understanding
b) Measuring error propagation times in Fault tolerance
synchronization. (7)
7 Describe about Rate Monotonic Scheduling Algorithm with examples.
BTL 2 Understanding
(13)
8 (i) Explain the permanent faults in series parallel system. (7)
BTL 3 Applying
(ii) Summarize the performance measures for real time systems? (6)
9 Outline the features of information redundancy and its principle to obtain
BTL 3 Applying
a code that will correct multiple bit errors. (13)
10 (i). Write about the limited usefulness of software error models? (5)
(ii). Explain how the clocks are synchronized if the times are close to BTL 4 Analyzing
each other. (8)
11 (i) Compare independent failure and correlated failure. (3)
(ii) Examine the process of completely connected zero propagation BTL 4 Analyzing
system. (10)
12 Summarize the concepts of impact of faults and Loss of synchrony in
fault tolerant systems. (13) BTL 4 Analyzing
13 Write about reliability models for hardware redundancy.
BTL 4 Analyzing
(13)
14 Outline the More general model assuming that the failure process and
fault latency are exponential and Poisson distributed. (13) BTL 3 Applying
15 Describe the real time system and discuss the structure of real time
systems. (13) BTL 2 Understanding
16 Write in detail about System reliability and Mean Time To
Failure(MTTF) (13) BTL 4 Analyzing
17 List the characteristics of task assignment /scheduling and
Multiprocessor schedule. (13) BTL1 Remembering
PART – C

1 Explain the mathematical concepts of Identical Linear Reward functions

in Uniprocessor scheduling. (15) BTL 4 Analyzing

2 Describe the completely connected zero propagation time system in

BTL 2 Understanding
hardware fault tolerant synchronization. (15)
3 Outline the utilization bound for the RM algorithm and explain in detail.
BTL 3 Applying
(15)
4 Summarize with necessary illustrations explain the following
redundancy in fault tolerant systems.
(i) Hardware Redundancy (5) BTL 2 Understanding
(ii) Software Redundancy (5)
(iii) Information Redundancy (5)
5 Write about system reliability preliminaries in detail.
BTL1 Remembering
(15)

UNIT V PROCESSES AND OPERATING SYSTEMS

Introduction – Multiple tasks and multiple processes – Multirate systems- Preemptive real-time operating
systems- Priority based scheduling- Interprocess communication mechanisms – Evaluating operating system
performance- power optimization strategies for processes – Example Real time operating systems-POSIX-
Windows CE. - Distributed embedded systems – MPSoCs and shared memory multiprocessors. – Design
Example - Audio player, Engine control unit – Video accelerator.
PART – A
Q.No Questions BT Competence
Level
1. Mention the networks for distributed embedded systems. BTL1 Remembering
2. Define the term time quantum. BTL1 Remembering
3. List the major function of POSIX RTOS. BTL1 Remembering
4. What is Semaphore? BTL1 Remembering
5. State the needs of CPU accelerator in embedded systems. BTL1 Remembering
6. Outline the advantages and limitations of Priority based process
BTL1 Remembering
scheduling.
7. Summarize the essential criteria’s of rate monolithic scheduling. BTL2 Understanding
8. Explain priority inversion briefly. BTL2 Understanding
9. Enumerate the various scheduling states of a process. BTL2 Understanding
10. Write examples of blocking and Non-blocking inter process
BTL2 Understanding
Communication
11. Draw the block diagram of Distributed embedded systems BTL3 Applying
12. Identify the principle of multi rate embedded system by quoting three
BTL3 Applying
Examples
13. Mention the two different styles used for inter process communication. BTL3 Applying
14. Compare between a process and thread. BTL4 Analyzing
15. Differentiate between initiation time and completion time BTL4 Analyzing
16. Explain the multi-processing systems. BTL4 Analyzing
17. Determine the communication among processes which runs at
BTL3 Applying
different rates.
18. Summarize the important characteristics of Multitasking. BTL2 Understanding
19. Write about hard-real-time operating system with an example. BTL1 Remembering
20. Compile the organization of scheduling policy. BTL3 Applying
21. Write short notes on Distributed embedded systems. BTL1 Remembering
22. What are the advantages of Shared memory multiprocessors? BTL3 Applying
23. Why Power optimization strategies are required? BTL4 Analyzing
24. What is MPSoC in embedded system? BTL2 Understanding
PART – B
1. Enumerate the context switch mechanism for moving the CPU from
one executing process to another. (13) BTL1 Remembering
2. State how the Kernel determines the order of the processes which has
BTL2 Understanding
to be executed. (13)
3. (i). Enumerate why an automobile engine requires multi rate control.(4)
(ii) Describe the performance of the Earliest – Deadline – First BTL1 Remembering
scheduling with suitable example. (9)

4. Describe the real time operating system called POSIX in detail. (13)
BTL1 Remembering
5. Explain about Power optimization strategies in embedded system. (13) BTL2 Understanding
6. (i) Mention in detail about Shared Resources. (7)
BTL1 Remembering
(ii) Explain about Windows CE with a neat diagram. (6)
7. (i) Write in detail about multitasking and multiprocessing. (4)
BTL2 Understanding
(ii) Illustrate process state and scheduling. (9)
8. Infer in detail about the Characteristics of distributed embedded
BTL2 Understanding
System. (13)
9. Explain the architecture of Distributed Embedded System with neat
BTL3 Applying
sketch. (13)
10. (i) Outline the services of operating system in handling multiple tasks
and multiple processes. (7)
BTL2 Understanding
(ii) Identify the features of preemptive execution with the help of a
Sequence diagram. (6)
11. (i) Explain in detail about power optimization strategies for CPU
operation. (7)
BTL3 Applying
(ii) Identify how the Predictive shut down technique proved itself as
more sophisticated. (6)
12. With necessary diagrams explain about Audio Player design. (13) BTL3 Applying
13. (i) Outline about priority-based scheduling in detail. (7)
(ii) With the help of an example, explain how the knowledge of data BTL4 Analyzing
dependencies can help to use the CPU more efficiently. (6)
14. (i) Summarize the preemptive real time operating systems in detail. (7)
(ii) Analyze the special characteristics of Processes and Internet with the BTL4 Analyzing
help of a suitable diagram. (6)
15. Explain the concepts of Multiprocessor System-On-Chip (MPSoC) and
BTL4 Analyzing
Shared memory multiprocessor are used in embedded applications. (13)
16. Explain the principle, merits and its limitations of inter-process
communication mechanisms. (13)
17. (i) Justify this statement with the help of an example. ‘The timing
requirements on a set of process can strongly influence the type of
appropriate scheduling’. (7)
(ii) Write about a critical section using semaphores in operating system.
(6)
PART C
1 Explain about Multiple tasks and multiple processes with suitable
examples. (15) BTL3 Applying
2 Explain the working of Engine control unit in detail.
i). Theory of operations and requirements (4)
ii). Specification (4)
iii). System Architecture (3) BTL2 Understanding
iv). Component designing and testing (2)
v). System integration and testing. (2)
3 Outline in detail how shared memory and message passing
mechanisms are used for interprocess communication. (15) BTL1 Remembering

4 With necessary illustrations explain about EDF algorithm for

BTL4 Analyzing
scheduling three process with hyper period 60. (15)
5 What is the purpose of Priority based scheduling. Discuss in detail
BTL2 Understanding
with appropriate diagrams.