NCP1207

PWM Current−Mode
Controller for Free Running
Quasi−Resonant Operation
The NCP1207 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/critical
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Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent skip
cycle capability, the controller enters burst mode as soon as the power MARKING
demand falls below a predetermined level. As this happens at low peak DIAGRAMS
current, no audible noise can be heard. An internal 8.0 s timer prevents 8
the free−run frequency to exceed 100 kHz (therefore below the 150 kHz SOIC−8
1207
CISPR−22 EMI starting limit), while the skip adjustment capability lets 8 D1, D2 SUFFIX
ALYW
the user select the frequency at which the burst foldback takes place. CASE 751
1
The Dynamic Self−Supply (DSS) drastically simplifies the 1
transformer design in avoiding the use of an auxiliary winding to supply
the NCP1207. This feature is particularly useful in applications where 8
the output voltage varies during operation (e.g. battery chargers). Due to PDIP−8 1207P
its high−voltage technology, the IC is directly connected to the N SUFFIX AWL
high−voltage DC rail. As a result, the short−circuit trip point is not 8 CASE 626 YYWW
dependent upon any VCC auxiliary level. 1 1
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast
Overvoltage Protection (OVP). Once an OVP has been detected, the IC 1207/P = Device Code
permanently latches off. A = Assembly Location
WL, L = Wafer Lot
Finally, the continuous feedback signal monitoring implemented with
YY, Y = Year
an Overcurrent Fault Protection (OCP) circuitry makes the final design WW, W = Work Week
rugged and reliable.
Features
PIN CONNECTIONS
• Pb−Free Packages are Available*
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation DMG 1 8 HV
• Current−Mode with Adjustable Skip−Cycle Capability FB 2 7 NC
• No Auxiliary Winding VCC Operation
3 6 VCC
CS
• Auto−Recovery Overcurrent Protection
GND 4 5 Drv
• Latching Overvoltage Protection
• External Latch Triggering, e.g. Via Overtemperature Signal (Top View)
• 500 mA Peak Current Source/Sink Capability
• Internal 1.0 ms Soft−Start ORDERING INFORMATION
• Internal 8.0 s Minimum TOFF
Device Package Shipping†
• Adjustable Skip Level
NCP1207DR2 SOIC−8 2500/Tape & Reel
• Internal Temperature Shutdown
• Direct Optocoupler Connection
NCP1207DR2G SOIC−8
(Pb−Free)
2500/Tape & Reel

• SPICE Models Available for TRANsient Analysis

NCP1207P PDIP−8 50 Units/Tube
Typical Applications
• AC−DC Adapters for Notebooks, etc. NCP1207PG PDIP−8
(Pb−Free)
50 Units/Tube

• Offline Battery Chargers

†For information on tape and reel specifications,
• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.) including part orientation and tape sizes, please
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.) refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

October, 2004 − Rev. 8 NCP1207/D
 NCP1207

Vout

+ OVP and NCP1207

Demag
1 8
*
GND
2 7
3 6
4 5
Universal Network

*Please refer to the application information section

Figure 1. Typical Application

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PIN FUNCTION DESCRIPTION

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Pin No. Pin Name Function Description
1 Demag Core reset detection and OVP The auxiliary FLYBACK signal ensures discontinuous operation and
offers a fixed overvoltage detection level of 7.2 V.

2 FB Sets the peak current setpoint By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.
3 CS Current sense input and This pin senses the primary current and routes it to the internal
skip cycle level selection comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.
4 GND The IC ground −
5 Drv Driving pulses The driver’s output to an external MOSFET.
6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 10 F.
7 NC − This unconnected pin ensures adequate creepage distance.
8 HV High−voltage pin Connected to the high−voltage rail, this pin injects a constant current into
the VCC bulk capacitor.

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 NCP1207

4.5 s
Delay

Resd
HV Demag − Demag
OVP +
7.0 8.0 s Rint
PON 10 V
mA + /1.44 +
Blanking
5.0 V 50 mV
+ − S Q
+ VCC Driver: src = 20
− + S*
sink = 10
R* R Q
VCC 12 V, 10 V, Drv
5.3 V (fault)
4.2 V

To Internal Fault
Soft−Start = 1 ms
Supply Mngt. + /3 FB
GND −
1.0 V 200 A
when Drv
Overload? is OFF

380 ns
Timeout L.E.B. CS
5.0 s Reset
Timeout Demag
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.

Figure 2. Internal Circuit Architecture

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MAXIMUM RATINGS

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Rating Symbol Value Units
Power Supply Voltage VCC, Drv 16 V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) Pin 5 (Drv) and − −0.3 to 10 V
Pin 1 (Demag)

Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V − 5.0 mA
ESD diodes are activated

Maximum Current in Pin 1 Idem +3.0/−2.0 mA

Thermal Resistance, Junction−to−Case RJC 57 °C/W
Thermal Resistance, Junction−to−Air, SOIC version RJA 178 °C/W

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Thermal Resistance, Junction−to−Air, PDIP version RJA 100 °C/W

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Maximum Junction TemperatureÁÁÁÁ
Operating Junction Temperature TJ
TJMAX
−40 to +125
150
°C
°C
Temperature Shutdown − 155 °C
Hysteresis in Shutdown − 30 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, HBM Model (All pins except HV) − 2.0 kV
ESD Capability, Machine Model − 200 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F VHVMAX 500 V
Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F VHVMIN 40 V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

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 NCP1207

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted)

Rating Pin Symbol Min Typ Max Unit

DYNAMIC SELF−SUPPLY
VCC Increasing Level at which the Current Source Turns−off 6 VCCOFF 10.8 12 12.9 V
VCC Decreasing Level at which the Current Source Turns−on 6 VCCON 9.1 10 10.6 V
VCC Decreasing Level at which the Latchoff Phase Ends 6 VCClatch − 5.3 − V
Internal IC Consumption, No Output Load on Pin 5, 6 ICC1 − 1.0 1.3 mA
FSW = 60 kHz (Note 1)

Internal IC Consumption, 1.0 nF Output Load on Pin 5, 6 ICC2 − 1.6 2.0 mA

FSW = 60 kHz (Note 1)

Internal IC Consumption in Latchoff Phase 6 ICC3 − 330 − A

INTERNAL STARTUP CURRENT SOURCE (TJ  0°C)
High−voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA
High−voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA
DRIVE OUTPUT
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output 5 Tr − 40 − ns
Signal
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output 5 Tf − 20 − ns
Signal
Source Resistance 5 ROH 12 20 36 
Sink Resistance 5 ROL 5.0 10 19 
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB − 0.02 − A
Maximum Internal Current Setpoint 3 ILimit 0.92 1.0 1.12 V
Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 100 160 ns
Leading Edge Blanking Duration 3 TLEB − 380 − ns
Internal Current Offset Injected on the CS Pin during OFF Time 3 Iskip − 200 − A
OVERVOLTAGE SECTION (VCC = 11 V)
Sampling Delay after ON Time 1 Tsample − 4.5 − s
OVP Internal Reference Level 1 Vref 6.4 7.2 8.0 V
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k)
Internal Pullup Resistor 2 Rup − 20 − k
Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − −
Internal Soft−Start − Tss − 1.0 − ms
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (Vpin1 Decreasing) 1 VTH 35 50 90 mV
Hysteresis (Vpin1 Decreasing) 1 VH − 20 − mV
Input Clamp Voltage
High State (Ipin 1 = 3.0 mA) 1 VCH 8.0 10 12 V
Low State (Ipin 1 = −2.0 mA) 1 VCL −0.9 −0.7 −0.5 V
Demag Propagation Delay 1 Tdem − 210 − ns
Internal Input Capacitance at Vpin1 = 1.0 V 1 Cpar − 10 − pF
Minimum TOFF (Internal Blanking Delay after TON) 1 Tblank − 8.0 − s
Timeout After Last Demag Transition 1 Tout − 5.0 − s
Pin 1 Internal Impedance 1 Rint − 28 − k
1. Max value at TJ = 0°C.

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 NCP1207

TYPICAL CHARACTERISTICS
(TJ = −40°C to 125°C)

13.2 11.2
7
12.8
10.8
12.4
10.4
VCCOFF (V)

VCCON (V)
12.0
10.0
11.6
9.6
11.2

10.8 9.2

10.4 8.8
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 3. VCC Increasing Level at which the Figure 4. VCC Decreasing Level at which the
Current Source Turns−off versus Temperature Current Source Turns−on versus Temperature
2.30
1.60

1.40 2.10

1.20 1.90
ICC2 (mA)
ICC1 (mA)

1.00 1.70

0.80 1.50

0.60 1.30

0.40 1.10
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. Internal IC Consumption, No Output Figure 6. Internal IC Consumption, Output
Load on Pin 5 versus Temperature Load on Pin 5 versus Temperature
12 1.20
11
1.15
10
9
1.10
8
IC1 (mA)

Ilimit (V)

7 1.05
6
1.00
5
4
0.95
3
2 0.90
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 7. Internal Startup Current Source, Figure 8. Maximum Internal Current Setpoint
VCC = 10 V versus Temperature versus Temperature

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 NCP1207

TYPICAL CHARACTERISTICS
(TJ = −40°C to 125°C)

40 20
18
35
16
30
14
25 12
ROH ()

ROL ()
20 10
8
15
6
10
4
5 2
0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. Source Resistance versus Figure 10. Sink Resistance versus
Temperature Temperature
120 8.0

100
7.5
80
VTH (mV)

Vref (V)

60 7.0

40
6.5
20

0 6.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 11. Input Voltage (Vpin1 Decreasing) Figure 12. OVP Internal Reference Level
versus Temperature versus Temperature

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 NCP1207

TYPICAL CHARACTERISTICS
(TJ = −50°C to 125°C)

10 1.5

9.5 1.4

9.0 1.3

Tss (ms)
8.5
Toff (s)

1.2

8.0 1.1

7.5 1

7.0 0.9

6.5 0.8
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 13. Minimum Toff versus Temperature Figure 14. Internal Soft−Start versus
Temperature

50

40

30
Rint (k)

20

10

0
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 15. DMG Pin Internal Resistance versus
Temperature

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 NCP1207

Application Information
Introduction occurs at low peak current. This point guarantees a
The NCP1207 implements a standard current mode noise−free operation with cheap transformer. This
architecture where the switch−off time is dictated by the option also offers the ability to fix the maximum
peak current setpoint whereas the core reset detection switching frequency when entering light load
triggers the turn−on event. This component represents the conditions.
ideal candidate where low part−count is the key parameter, • Overcurrent Protection (OCP): by continuously
particularly in low−cost AC−DC adapters, consumer monitoring the FB line activity, NCP1207 enters burst
electronics, auxiliary supplies, etc. Thanks to its mode as soon as the power supply undergoes an
high−performance High−Voltage technology, the NCP1207 overload. The device enters a safe low power operation
incorporates all the necessary components / features needed which prevents from any lethal thermal runaway. As
to build a rugged and reliable Switchmode Power Supply soon as the default disappears, the power supply
(SMPS): resumes operation. Unlike other controllers, overload
• Transformer core reset detection: borderline / critical detection is performed independently of any auxiliary
operation is ensured whatever the operating conditions winding level. In presence of a bad coupling between
are. As a result, there are virtually no primary switch both power and auxiliary windings, the short circuit
turn−on losses and no secondary diode recovery losses. detection can be severely affected. The DSS naturally
The converter also stays a first−order system and shields you against these troubles.
accordingly eases the feedback loop design. Dynamic Self−Supply
• Quasi−resonant operation: by delaying the turn−on The DSS principle is based on the charge/discharge of the
event, it is possible to restart the MOSFET in the VCC bulk capacitor from a low level up to a higher level. We
minimum of the drain−source wave, ensuring reduced can easily describe the current source operation with some
EMI / video noise perturbations. In nominal power simple logical equations:
conditions, the NCP1207 operates in Borderline POWER−ON: IF VCC < VCCOFF THEN Current Source
Conduction Mode (BCM) also called Critical is ON, no output pulses
Conduction Mode.
IF VCC decreasing > VCCON THEN Current Source is
• Dynamic Self−Supply (DSS): due to its Very High
OFF, output is pulsing
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1207 allows for a direct pin IF VCC increasing < VCCOFF THEN Current Source is
connection to the high−voltage DC rail. A dynamic ON, output is pulsing
current source charges up a capacitor and thus provides Typical values are: VCCOFF = 12 V, VCCON = 10 V
a fully independent VCC level to the NCP1207. As a To better understand the operational principle, Figure 16’s
result, there is no need for an auxiliary winding whose sketch offers the necessary light.
management is always a problem in variable output
voltage designs (e.g. battery chargers).
• Overvoltage Protection (OVP): by sampling the plateau VRIPPLE = 2 V
VCCOFF = 12 V
voltage on the demagnetization winding, the NCP1207
VCC

goes into latched fault condition whenever an

overvoltage condition is detected. The controller stays VCCON = 10 V
fully latched in this position until the VCC is cycled
down 4.0 V, e.g. when the user un−plugs the power ON
CURRENT
SOURCE

supply from the mains outlet and re−plugs it.

• External latch trip point: by externally forcing a level
OFF
on the OVP greater than the internal setpoint, it is
possible to latchoff the IC, e.g. with a signal coming
Output Pulses
from a temperature sensor.
• Adjustable skip cycle level: by offering the ability to Figure 16. The Charge/Discharge Cycle Over a 10
F
tailor the level at which the skip cycle takes place, the VCC Capacitor
designer can make sure that the skip operation only

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 NCP1207

The DSS behavior actually depends on the internal IC When using Figure 17 option, it is important to check
consumption and the MOSFET’s gate charge Qg. If we the absence of any negative ringing that could occur
select a MOSFET like the MTP2N60E, Qg equals 22 nC on pin 8. The resistor in series should help to damp
(max). With a maximum switching frequency selected at any parasitic LC network that would ring when
75 kHz, the average power necessary to drive the MOSFET suddenly applying the power to the IC. Also, since
(excluding the driver efficiency and neglecting various the power disappears during 10 ms (half−wave
voltage drops) is: rectification), CVCC should be calculated to supply
Fsw ⋅ Qg ⋅ VCC with: the IC during these holes in the supply
3. Permanently force the VCC level above VCCH with
Fsw = maximum switching frequency
an auxiliary winding. It will automatically
Qg = MOSFET’s gate charge disconnect the internal startup source and the IC will
VCC = VGS level applied to the gate be fully self−supplied from this winding. Again, the
To obtain the output current, simply divide this result by total power drawn from the mains will significantly
VCC: Idriver = FSW ⋅ Qg = 1.6 mA. The total standby power decrease. Make sure the auxiliary voltage never
consumption at no−load will therefore heavily rely on the exceeds the 16 V limit.
internal IC consumption plus the above driving current
Skipping Cycle Mode
(altered by the driver’s efficiency). Suppose that the IC is
The NCP1207 automatically skips switching cycles when
supplied from a 350 VDC line. The current flowing through
the output power demand drops below a given level. This is
pin 8 is a direct image of the NCP1207 consumption
accomplished by monitoring the FB pin. In normal
(neglecting the switching losses of the HV current source).
operation, pin 2 imposes a peak current accordingly to the
If ICC2 equals 2.3 mA @ TJ = 60°C, then the power
load value. If the load demand decreases, the internal loop
dissipated (lost) by the IC is simply: 350 V x 2.3 mA =
asks for less peak current. When this setpoint reaches a
805 mW. For design and reliability reasons, it would be
determined level, the IC prevents the current from
interested to reduce this source of wasted power that
decreasing further down and starts to blank the output
increase the die temperature. This can be achieved by using
pulses: the IC enters the so−called skip cycle mode, also
different methods:
named controlled burst operation. The power transfer now
1. Use a MOSFET with lower gate charge Qg.
depends upon the width of the pulse bunches (Figure 18) and
2. Connect pin 8 through a diode (1N4007 typically) to
follows the following formula:
one of the mains input. The average value on pin 8
1  Lp  Ip 2  Fsw  D
V
becomes mainsPEAK  2. Our power contribution burst with:
 2
example drops to: 223 V x 2.3 mA = 512 mW. If a Lp = primary inductance
resistor is installed between the mains and the diode, Fsw = switching frequency within the burst
you further force the dissipation to migrate from the
Ip = peak current at which skip cycle occurs
package to the resistor. The resistor value should
account for low−line startups. Dburst = burst width / burst recurrence

HV 1N4007
MAX PEAK NORMAL CURRENT
CURRENT SENSE SIGNAL (mV)

300
5 CURRENT MODE OPERATION
1 2 Cbulk
MAINS 1 8 6 200 SKIP CYCLE
2 7 CURRENT LIMIT
3 6
100
4 5

0
Figure 17. A simple diode naturally reduces the WIDTH
average voltage on pin 8
RECURRENCE

Figure 18. The skip cycle takes place at low peak

currents which guaranties noise free operation

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 NCP1207

DRIVER current sense comparator permanently resets the latch and the
next clock cycle (given by the demagnetization detection) is
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 A
ignored: we are skipping cycles as shown by Figure 20. As
soon as the feedback voltage goes up again, there can be two
Rskip situations: the recurrent period is small and a new
− 3
RESET + demagnetization detection (next wave) signal triggers the
Rsense NCP1207. To the opposite, in low output power conditions, no
2 more ringing waves are present on the drain and the toggling
of the current sense comparator together with the internal 5 s
timeout initiates a new cycle start. In normal operating
+ conditions, e.g. when the drain oscillations are generous, the
demagnetization comparator can detect the 50 mV crossing
and gives the “green light”, alone, to re−active the power
switch. However, when skip cycle takes place (e.g. at low
Figure 19. A patented method allows for skip level
selection via a series resistor inserted in series output power demands), the restart event slides along the drain
with the current ringing waveforms (actually the valley locations) which
decays more or less quickly, depending on the
The skip level selection is done through a simple resistor Lprimary−Cparasitic network damping factor. The situation can
inserted between the current sense input and the sense element. thus quickly occur where the ringing becomes too weak to be
Every time the NCP1207 output driver goes low, a 200 A detected by the demagnetization comparator: it then
source forces a current to flow through the sense pin permanently stays locked in a given position and can no longer
(Figure 19): when the driver is high, the current source is off deliver the “green light” to the controller. To help in this
and the current sense information is normally processed. As situation, the NCP1207 implements a 5 s timeout generator:
soon as the driver goes low, the current source delivers 200 A each time the 50 mV crossing occurs, the timeout is reset. So,
and develops a ground referenced voltage across Rskip. If this as long as the ringing becomes too low, the timeout generator
voltage is below the feedback voltage, the current sense starts to count and after 5 s, it delivers its “green light”. If the
comparator stays in the high state and the internal latch can be skip signal is already present then the controller restarts;
triggered by the next clock cycle. Now, if because of a low load otherwise the logic waits for it to set the drive output high.
mode the feedback voltage is below Rskip level, then the Figure 20 depicts these two different situations:

Drain
Signal

Timeout
Signal

Demag Restart
Current Sense and Timeout Restart

Drain
Signal

Timeout 5 s 5 s
Signal

Figure 20. When the primary natural ringing becomes too low, the internal timeout together with the sense
comparator initiates a new cycle when FB passes the skip level.

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 NCP1207

Demagnetization Detection
The core reset detection is done by monitoring the voltage 400
activity on the auxiliary winding. This voltage features a

DRAIN VOLTAGE (V)

FLYBACK polarity. The typical detection level is fixed at 300
50 mV as exemplified by Figure 21.

200
7.0
DEMAG SIGNAL (V)

POSSIBLE 100
5.0
RESTARTS

0
3.0

1.0
Figure 23. The NCP1207 Operates in
50 mV Borderline / Critical Operation
0V
−1.0
Overvoltage Protection
The overvoltage protection works by sampling the plateau
Figure 21. Core reset detection is done through a voltage 4.5 s after the turn−off sequence. This delay
dedicated auxiliary winding monitoring
guarantees a clean plateau, providing that the leakage
TO INTERNAL inductance ringing has been fully damped. If this would not
COMPARATOR Resd Rdem be the case, the designer should install a small RC damper
1 across the transformer primary inductance connections.
2 1 5 4
Figure 24 shows where the sampling occurs on the auxiliary
Rint ESD2 ESD1 Aux winding.
3
4 SAMPLING HERE
Resd + Rint = 28 k 8.0

Figure 22. Internal Pad Implementation

DEMAG SIGNAL (V)

6.0
An internal timer prevents any restart within 8.0 s further
to the driver going−low transition. This prevents the
switching frequency to exceed (1 / (TON + 8.0 s)) but also 4.0
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a 2.0
slight filtering is necessary. 4.5 s
The 1207 demagnetization detection pad features a
0
specific component arrangement as detailed by Figure 22. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins. Figure 24. A voltage sample is taken 4.5
s after
The first ESD diode connected to the pad, exhibits a parasitic the turn−off sequence
capacitance. When this parasitic capacitance (10 pF
typically) is combined with Rdem, a restart delay is created When an OVP condition has been detected, the NCP1207
and the possibility to switch right in the drain−source wave enters a latchoff phase and stops all switching operations.
exists. This guarantees QR operation with all the associated The controller stays fully latched in this position and the
benefits (low EMI, no turn−on losses etc.). Rdem should be DSS is still active, keeping the VCC between 5.3 V/12 V as
calculated to limit the maximum current flowing through in normal operations. This state lasts until the VCC is cycled
pin 1 to less than +3 mA/−2 mA. If during turn−on, the down 4 V, e.g. when the user unplugs the power supply from
auxiliary winding delivers 30 V (at the highest line level), the mains outlet.
then the minimum Rdem value is defined by: By default, the OVP comparator is biased to a 5 V
(30 V + 0.7 V) / 2 mA = 14.6 k. reference level and pin 1 is routed via a divide by 1.44
This value will be further increased to introduce a restart network. As a result, when Vpin1 reaches 7.2 V, the OVP
delay and also a slight filtering in case of high leakage comparator is triggered. The threshold can thus be adjusted
energy. by either modifying the power winding to auxiliary winding
Figure 23 portrays a typical VDS shot at nominal output turn ratios to match this 7.2 V level, or insert a resistor from
power. pin1 to ground to cope with your design requirement.

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 NCP1207

Latching Off the NCP1207 Power Dissipation

In certain cases, it can be very convenient to externally The NCP1207 is directly supplied from the DC rail
shut down permanently the NCP1207 via a dedicated signal, through the internal DSS circuitry. The DSS being an
e.g. coming from a temperature sensor. The reset occurs auto−adaptive circuit (e.g. the ON/OFF Duty Cycle adjusts
when the user unplugs the power supply from the mains itself depending on the current demand), the current flowing
outlet. To trigger the latchoff, a CTN (Figure 25) or a simple through the DSS is therefore the direct image of the
NPN transistor (Figure 26) can do the work. NCP1207 current consumption. The total power dissipation
CTN
can be evaluated using: (VHVDC  11 V)  ICC2. If we
operate the device on a 250 Vac rail, the maximum rectified
voltage can go up to 350 Vdc. As a result, the worse case
dissipation occurs at the maximum switching frequency and
the highest line. The dissipation is actually given by the
internal consumption of the NCP1207 when driving the
NCP1207 Aux selected MOSFET. The best method to evaluate this total
1 8 consumption is probably to run the final circuit from a
50 Vdc source applied to pin 8 and measure the average
2 7
current flowing into this pin. Suppose that we find 2.0 mA,
3 6
meaning that the DSS Duty Cycle will be 2.0/7.0 = 28.6%.
4 5 From the 350 Vdc rail, the part will dissipate:
350 V  2.0 mA  700 mW (however this 2.0 mA number
Figure 25. A simple CTN triggers the latchoff as will drop at higher operating junction temperatures).
soon as the temperature exceeds a given setpoint A DIP8 package offers a junction−to−ambient thermal
resistance RJA of 100°C/W. The maximum power
dissipation can thus be computed knowing the maximum
NCP1207 Aux operating ambient temperature (e.g. 70°C) together with
the maximum allowable junction temperature (125°C):
1 8
T  TAmax
2 7 P max  Jmax  550 mW. As we can see, we
RJA
ON/OFF 3 6 do not reach the worse consumption budget imposed by the
4 5 operating conditions. Several solutions exist to cure this
trouble:
• The first one consists in adding some copper area around
the NCP1207 DIP8 footprint. By adding a min pad area
Figure 26. A simple transistor arrangement allows
of 80 mm2 of 35 m copper (1 oz.) RJA drops to about
to trigger the latchoff by an external signal
75°C/W. Maximum power then grows up to 730 mW.
Shutting Off the NCP1207 • A resistor Rdrop needs to be inserted with pin 8 to
Shutdown can easily be implemented through a simple a) avoid negative spikes at turn−off (see below)
NPN bipolar transistor as depicted by Figure 27. When OFF, b) split the power budget between this resistor and the
Q1 is transparent to the operation. When forward biased, the package. The resistor is calculated by leaving at least 50 V
transistor pulls the FB pin to ground (VCE(sat) ≈ 200 mV) and on pin 8 at minimum input voltage (suppose 100 Vdc in
V  50 V
permanently disables the IC. A small time constant on the our case): Rdrop  bulkmin  7.1 k. The
transistor base will avoid false triggering (Figure 27). 7.0 mA
power dissipated by the resistor is thus:
NCP1207
Pdrop  VdropRMS 2Rdrop
2
1 8
IDSS  Rdrop  DSSduty  cycle
10 k 2 7 
ON/OFF Q1
1 Rdrop
3 6 2
3 2
4 5 7.0 mA  7.1 k  0.286
10 nF   99.5 mW
7.1 k
Please refer to the application note AND8069 available
from www.onsemi.com/pub/ncp1200.
Figure 27. A simple bipolar transistor totally
disables the IC

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 NCP1207

• If the power consumption budget is really too high for the feedback loop takes over. This period of time depends on
DSS alone, connect a diode between the auxiliary normal output load conditions and the maximum peak
winding and the VCC pin which will disable the DSS current allowed by the system. The time−out used by this IC
operation (VCC  10 V). works with the VCC decoupling capacitor: as soon as the
The SOIC package offers a 178°C/W thermal resistor. VCC decreases from the VCCOFF level (typically 12 V) the
Again, adding some copper area around the PCB footprint device internally watches for an overload current situation.
will help decrease this number: 12 mm
12 mm to drop If this condition is still present when the VCCON level is
RJA down to 100°C/W with 35 m copper thickness (1 oz.) reached, the controller stops the driving pulses, prevents the
or 6.5 mm
6.5 mm with 70 m copper thickness (2 oz.). self−supply current source to restart and puts all the circuitry
As one can see, we do not recommend using the SO−8 in standby, consuming as little as 330 A typical (ICC3
package and the DSS if the part operates at high switching parameter). As a result, the VCC level slowly discharges
frequencies. In that case, an auxiliary winding is the best toward 0. When this level crosses 5.3 V typical, the
solution. controller enters a new startup phase by turning the current
source on: VCC rises toward 12 V and again delivers output
Overload Operation pulses at the VCCOFF crossing point. If the fault condition
In applications where the output current is purposely not has been removed before VCCON approaches, then the IC
controlled (e.g. wall adapters delivering raw DC level), it is continues its normal operation. Otherwise, a new fault cycle
interesting to implement a true short−circuit protection. A takes place. Figure 28 shows the evolution of the signals in
short−circuit actually forces the output voltage to be at a low presence of a fault.
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up Soft−Start
to 4.2 V, as internally imposed by the IC. The peak current The NCP1207 features an internal 1 ms Soft−Start to
setpoint goes to the maximum and the supply delivers a soften the constraints occurring in the power supply during
rather high power with all the associated effects. Please note startup. It is activated during the power on sequence. As
that this can also happen in case of feedback loss, e.g. a soon as VCC reaches VCCOFF , the peak current is gradually
broken Optocoupler. To account for this situation, NCP1207 increased from nearly zero up to the maximum clamping
hosts a dedicated overload detection circuitry. Once level (e.g. 1.0 V). The Soft−Start is also activated during the
activated, this circuitry imposes to deliver pulses in a burst overcurrent burst (OCP) sequence. Every restart attempt is
manner with a low Duty Cycle. The system recovers when followed by a Soft−Start activation. Generally speaking, the
the fault condition disappears. Soft−Start will be activated when VCC ramps up either from
During the startup phase, the peak current is pushed to the zero (fresh power−on sequence) or 5.3 V, the latchoff
maximum until the output voltage reaches its target and the voltage occurring during OCP.
VCC
REGULATION
OCCURS HERE

12 V
LATCHOFF
10 V PHASE
5.3 V

TIME
If the fault is relaxed during the VCC
DRV
natural fall down sequence, the IC
automatically resumes.
DRIVER If the fault still persists when VCC
PULSES reached VCCON, then the controller
cuts everything off until recovery.
TIME
INTERNAL
FAULT FLAG

FAULT IS
RELAXED
TIME
STARTUP PHASE FAULT OCCURS HERE

Figure 28.

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 NCP1207

Calculating the VCC Capacitor HV

As the above section describes, the fall down sequence
NCP1207
depends upon the VCC level: how long does it take for the
VCC line to go from 12 V to 10 V? The required time depends 1 8 D1
+
on the startup sequence of your system, i.e. when you first Cbulk 2 7 1N4007
apply the power to the IC. The corresponding transient fault 3 6
duration due to the output capacitor charging must be less
4 5
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists +
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6.0 ms. Therefore a
VCC fall time of 10 ms could be well appropriated in order
Figure 29.
to not trigger the overload detection circuitry. If the
corresponding IC consumption, including the MOSFET
drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET), Operation Shots
we can calculate the required capacitor using the following Below are some oscilloscope shots captured at
formula: t  V  C, with V = 2.0 V. Then for a wanted Vin = 120 VDC with a transformer featuring a 800 H
i
t of 10 ms, C equals 9.0
F or 22
F for a standard value. primary inductance.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330 A
typical. This happens at VCC = 10 V and it remains stuck
until VCC reaches 5.3 V: we are in latchoff phase. Again,
using the calculated 22 F and 330 A current consumption,
this latchoff phase lasts: 313 ms.

HV Pin Recommended Protection

When the user unplugs a power supply built with a QR
controller such as the NCP1207, two phenomena can
appear:
1. A negative ringing can take place on pin8 due to a
resonance between the primary inductance and
the bulk capacitor. As any CMOS device, the
NCP1207 is sensitive to negative voltages that
could appear on it’s pins and could create an
Figure 30.
internal latchup condition.
2. When the bulk capacitor discharges, the internal
This plot gathers waveforms captured at three different
latch is reset by the voltage developed over the
operating points:
sense resistor and the ON time expands as less
voltage is available. When the high−voltage rail 1st upper plot: free run, valley switching operation,
becomes too low, the gate drives permanently Pout = 26 W
stays high since no reset occurs. This situation is 2nd middle plot: min Toff clamps the switching frequency
not desirable in many applications. and selects the second valley
For the above reasons, we strongly recommend to add a 3rd lowest plot: the skip slices the second valley pattern
high−voltage diode like a 1N4007 between the bulk and will further expand the burst as Pout goes low
capacitor and the VCC pin. When the bulk level collapses, it
naturally shuts the controller down and eradicates the two
above problems.

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 NCP1207

VGATE (5 V/div) VRsense (200 mV/div) VCC (5 V/div)

200 A X RSKIP
VGATE (5 V/div)

Current Sense Pin (200 mV/div)

Figure 31. Figure 32.

This picture explains how the 200 A internal offset The short−circuit protection forces the IC to enter burst in
current creates the skip cycle level. presence of a secondary overload.

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 NCP1207

PACKAGE DIMENSIONS

SOIC−8
D1, D2 SUFFIX
CASE 751−07
ISSUE AC

−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
−Z− C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0
8
0
8

0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050
mm
SCALE 6:1
inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NCP1207

PACKAGE DIMENSIONS

PDIP−8
N SUFFIX
CASE 626−05
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
8 5 FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10
−−− 10

−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M

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 NCP1207

The product described herein (NCP1207), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,385,061, 6,429,709,
6,587,357, 6,633,193. There may be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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18