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IPC-7093
Design and Assembly Process
Implementation for Bottom
Termination Components
March 2011

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IPC-7093
®

Design and Assembly

Process Implementation
for Bottom Termination
SMT Components

Developed by the IPC Bottom Termination Components (BTC) Task

Group (5-21h) of the Assembly & Joining Processes Committee (5-20)
of IPC

Users of this publication are encouraged to participate in the

development of future revisions.

Contact:

IPC
3000 Lakeside Drive, Suite 309S
Bannockburn, Illinois
60015-1249
Tel 847 615.7100
Fax 847 615.7105
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March 2011 IPC-7093

Acknowledgment
Any document involving a complex technology draws material from a vast number of sources. While the principal members
of the IPC Bottom Termination Components (BTC) Task Group (5-21h) of the Assembly & Joining Processes Committee
(5-20) are shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them,
the members of IPC extend their gratitude.

Assembly & Joining Bottom Termination Components Technical Liaisons of the

Processes Committee (BTC) Task Group IPC Board of Directors
Chair Co-Chairs
Leo P. Lambert Ray Prasad Peter Bigelow
EPTAC Corporation Ray Prasad Consultancy Group IMI Inc.
Vern Solberg Sammy Yi
Solberg Technical Consulting Aptina Imaging Corporation

Bottom Termination Components (BTC) Task Group

Dudi Amir, Intel Corporation Michael Green, Lockheed Martin Ray Prasad, Ray Prasad Consultancy
Richard Arnold, Continental Space Systems Company Group
Automotive Systems Hue Green, Lockheed Martin Space Eric Radza, SiTIme Corporation
Raiyomand Aspandiar, Intel Corporation Systems Company Stanton Rak, Continental Automotive
Elizabeth Benedetto, Hewlett-Packard Bill Hanna, Agilent Technologies Systems
Company Gaston Hidalgo, Samsung Robert Rowland, RadiSys Corporation
David Bernard, Nordson DAGE X-ray Telecommunications America Greg Ruiz, Flextronics
Systems Craig Hillman, DfR Solutions Jeff Shubrooks, Raytheon Company
Scott Buttars, Intel Corporation David Hillman, Rockwell Collins Jerry Smith, Foxconn PCE
Fritz Byle, Astronautics Corp. of Constantin Hudon, Varitron Technology Inc.
America Technologies Inc. Vern Solberg, Solberg Technical
Beverley Christian, Research In Motion Bruce Hughes, U.S. Army Aviation & Consulting
Limited Missile Command Richard Stadem, General Dynamics
Michael Davisson, Agilent Technologies Greg Hurst, BAE Systems Info. Sys., Inc
C. Don Dupriest, Lockheed Martin Jennie Hwang, H-Technologies Group Becky Travelstead, TechSearch
Missiles and Fire Control Clyde Ishikawa, Trimble Navigation International Inc.
Harold Ellison, Quantum Corporation Glenn Koscal, Carsem Cheryl Tulkoff, DfR Solutions
Werner Engelmaier, Engelmaier William Kunkle, MET Associates Inc. E. Jan Vardaman, TechSearch
Associates, L.C. Murad Kurwa, Flextronics International International Inc.
Rei Fang, Cypress Semiconductor Paul Lotosky, Cookson Electronics Teresita Villavert, Flextronics
Zhen Feng, Flextronics Todd MacFadden, Bose Corporation Bill Werner, Trimble Navigation
Joe Fjelstad, Verdant Electronics Brian Madsen, Continental Automotive Robert Wettermann, BEST Inc.
Mark Fulcher, Continental Automotive Systems Dewey Whittaker, Honeywell Inc.
Systems Kelly Miller, SigmaPoint Air Transport Systems
Lionel Fullwood, WKK Distribution Technologies Inc. Ian Williams, Intel Corporation
Ltd. David Nelson, Adtran Inc. Bob Willis, The SMART Group
Ava Fung, Trimble Navigation Jack Olson, Caterpillar Inc. Linda Woody, Lockheed Martin
Thomas Gardeski, Gemini Sciences Richard Otte, PROMEX Missile & Fire Control
David Geiger, Flextronics International Industries, Inc. Dongji Xie, Flextronics International

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IPC-7093 March 2011

A special note of thanks goes to the following individuals for their dedication to bringing this project to fruition. We
would like to highlight those individuals who made major contributions to the development of this standard.
Dudi Amir, Intel Corporation Bruce Hughes, U.S. Army Aviation & Jeff Shubrooks, Raytheon Company
Richard Arnold, Continental Missile Command Vern Solberg, Solberg Technical
Automotive Systems David Nelson, Adtran Consulting
Raiyomand Aspandiar, Intel Corporation Dick Otte, Promex Kris Troxel, Hewlett Packard
Scott Buttars, Intel Corporation Ray Prasad, Ray Prasad Consultancy Bill Werner, Trimble Navigation
Beverley Christian, Research In Motion Group Robert Wettermann, BEST Inc.
Limited Stan Rak, Continental Automotive Bob Willis, The SMART Group
Werner Engelmaier, Engelmaier Systems Linda Woody, Lockheed Martin
Associates Robert Rowland, RadiSys Missile & Fire Control
David Hillman, Rockwell Collins

Illustrations courtesy of the following:

Amkor Technologies: Figures, 3-5, 3-6, 3-7, 4-28, 4-29, 4-35, 6-8, 6-16, 6-17, 6-21, 6-22, 6-23, 8-1, 8-2, 8-3, 8-5, Table 4-7
Analog Devices: Figures 4-40, 4-42,6-4, 6-8, 6-11, 6-14, 7-24, 7-27, 7-28, Table 4-9
BEST Inc.: Figures 7-28, 7-33, 7-34, 7-35
Continental Automotive Systems: Figures 7-19, 7-20, 7-21, 7-22
Fairchild Semiconductor: Figure 4-36
Intersil: Figure 4-37
Intel Corporation: Figures 9-3, 9-4, 9-10, 9-11, 9-12, 9-19, 9-20, 9-21, 9-27, 9-28
JEDEC: Figures 4-6, 4-7, 4-8, 4-12, 4-13, 4-17, 4-18, 4-20, 4-21, 4-38, 4-39, 4-43
Martin GmbH: Figure 7-32
Mini Micro Stencil: Figure 7-29
National Semiconductor: Figures 4-41, 6-3, 6-9, 7-1, 7-2, 7-3, 7-10, 7-11, 7-15
QPL Group: Figure 6-2
Raytheon Co.: Figure 7-14, 7-18

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March 2011 IPC-7093

Table of Contents
1 SCOPE ......................................................................1 4.5.3 Marking Alternatives ...........................................24
1.1 Purpose ................................................................1 4.5.4 Materials Used ....................................................24
1.2 Intent ....................................................................1 4.6 Description of Commercial Variations ..................24
4.6.1 Detailed Description of MLF®, MLP, and
2 APPLICABLE DOCUMENTS ....................................1
MLFP™ Components ..........................................25
2.1 IPC ......................................................................1
4.6.2 Detailed Description of LLC™ and LFCSP™
2.2 JEDEC .................................................................2 Components ........................................................27
4.7 Packaging and Handling ......................................30
3 SELECTION CRITERIA AND MANAGING BTC
IMPLEMENTATION ...................................................2
5 MOUNTING STRUCTURES ....................................31
3.1 Terms and Definitions ...........................................2
5.1 Types of Mounting Structures ..............................31
3.1.1 Bottom Termination Components (BTC) ................2
5.1.1 Organic Resin Systems ........................................31
3.1.2 Component Mounting Site .....................................2
5.1.2 Inorganic Structures ............................................31
3.1.3 Conductive Pattern* ..............................................2
5.1.3 Layering (Multilayer, Sequential or Build-Up
3.1.4 Land Pattern* .......................................................2 and HDI) ............................................................31
3.1.5 Mixed Component-Mounting Technology* .............2 5.2 Properties of Mounting Structures ........................31
3.1.6 Printed Board Assembly ........................................2 5.2.1 Resin Systems .....................................................32
3.1.7 Surface Mounting Technology (SMT)* ...................2 5.2.2 Reinforcements ...................................................32
3.2 BTC Executive Summary ......................................2 5.2.3 Reliability Concerns with High Temperature
3.3 Description of Different Component Lead-Free Soldering ............................................32
Structures ...........................................................3 5.2.4 Thermal Expansion .............................................33
3.4 Total Cost of Ownership ........................................6 5.2.5 Moisture Absorption ............................................33
3.5 Design and Assembly Process Considerations 5.2.6 Flatness (Bow and Twist) ....................................34
for QFN Type BTC Packages ................................6
5.3 Surface Finishes ..................................................34
3.6 Future Needs and Expectations ..............................8
5.3.1 Hot Air Solder Leveling (HASL) .........................35
4 COMPONENT CONSIDERATIONS ..........................8 5.3.2 Organic Surface Protection (Organic Solder-
4.1 General Description of Different BTC ability Preservative) Coatings ...............................36
Packages ...............................................................8 5.3.3 Noble Metal Platings/Coatings .............................36
4.2 Detailed Description and Standards for 5.4 Solder Mask .......................................................38
BTCs ...................................................................9
5.4.1 Wet and Dry Film Solder Masks ..........................38
4.2.1 Single Row Molded Lead-Frame Based
Packaging ............................................................9 5.4.2 Photoimageable Solder Masks ..............................40
4.2.2 Multiple Row Molded Lead-Frame Based 5.4.3 Registration ........................................................41
Packaging .............................................................9 5.4.4 Via Protection .....................................................41
4.2.3 JEDEC Publication 95 Design Guide 4.8 ..............10 5.5 Thermal Spreader Structure Incorporation (e.g.,
4.2.4 JEDEC Publication 95 Design Guide 4.23 ............12 Metal Core Boards) .............................................44

4.2.5 JEDEC Publication 95 Design Guide 4.19 ............15 5.5.1 Lamination Sequences .........................................44
4.3 Detailed Description of QFN and SON 5.5.2 Heat Transfer Pathway ........................................44
(DFN) Packages ..................................................17 5.5.3 Thermal Pad Attachment .....................................44
4.3.1 Manufacturing Methods .......................................17 5.5.4 Thermal Vias ......................................................45
4.3.2 Types of Defects .................................................21 5.6 Solderless Interconnections Systems .....................45
4.3.3 Marking Alternatives ...........................................21
6 PRINTED CIRCUIT ASSEMBLY DESIGN
4.3.4 Materials Used ....................................................21 CONSIDERATIONS .................................................46
4.3.5 Solderability Testing ............................................21 6.1 BTC Part Description ..........................................46
4.4 Custom QFN and SON (DFN) .............................21 6.1.1 BTC Package Variations ......................................46
4.5 Detailed Description of LGA, QFN and
6.1.2 Termination Formats ...........................................48
SON (DFN) Substrate-Based Packages .................23
6.1.3 Mounting Conditions ...........................................48
4.5.1 Manufacturing Methods for Substrate-
Based Packages ...................................................23 6.1.4 Package Tolerances .............................................54
4.5.2 Types of Defects .................................................24 6.1.5 Attachment Techniques ........................................57

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IPC-7093 March 2011

7 ASSEMBLY OF BTCs ON PRINTED 8.2.3 Mold Compound Material ....................................85

BOARDS ..................................................................60 8.2.4 Die Size .............................................................85
7.1 PCB Surface Finish Requirements ........................60 8.2.5 Full vs. Half Etched Leadframe ...........................85
7.2 PCB Design ........................................................61 8.2.6 Gold/Silver/Palladium Embrittlement ....................85
7.2.1 Consideration for Soldering Process .....................61 8.2.7 Stand-Off Height .................................................85
7.2.2 Component Preconditioning Bake ........................62 8.3 PCB Design Considerations .................................85
7.2.3 Component Preparation for Assembly ...................62 8.3.1 Land Size ...........................................................85
7.2.4 Solder Paste and its Application ...........................62 8.3.2 Fillet Formation ..................................................86
7.2.5 Component Placement Impact ..............................65 8.3.3 Board Thickness .................................................87
7.2.6 Reflow Soldering and Profiling ............................66 8.4 Voids in Thermal Pad ..........................................87
7.2.7 Reflow Process Impact on Material ......................68 8.5 Design for Reliability (DfR) Process ....................87
7.2.8 Vapor Phase ........................................................69 8.5.1 Wear-Out Mechanisms ........................................88
7.2.9 Cleaning vs. No-Clean ........................................70 8.5.2 Creep-Fatigue Interaction .....................................88
7.2.10 Package Standoff .................................................70 8.5.3 Solder Thickness Mechanical Reliability ..............89
7.3 Post-SMT Processes ............................................71 8.6 Wear-Out Mechanisms Review ............................90
7.3.1 Conformal Coatings ............................................71 8.6.1 Reliability Factors ...............................................90
7.3.2 Use of Underfills and Adhesives ..........................71 8.6.2 Benefits of Reinforcement ...................................90
7.3.3 Depaneling of Boards and Modules ......................71 8.6.3 Event Related Failures .........................................91
7.4 Inspection Techniques .........................................71 8.7 Design for Reliability Issues and Concerns ...........91
7.4.1 X-Ray Usage ......................................................72 8.7.1 Damage Mechanisms and Failure of Solder
7.4.2 Scanning Acoustic Microscopy ............................72 Attachments ........................................................91
7.4.3 BTC Standoff Measurement .................................72 8.7.2 Solder Joints and Attachment Types .....................91
7.4.4 Optical Inspection ...............................................73 8.7.3 Solder Interface Grain Structure Effects ................92
7.4.5 Destructive Analysis Methods ..............................73 8.7.4 Global Expansion Mismatch ................................92
7.5 Testing and Product Verification ...........................74 8.7.5 Local Expansion Mismatch ..................................92
7.5.1 Electrical Testing ................................................74 8.7.6 Internal Expansion Mismatch ...............................93
7.5.2 Test Coverage .....................................................75 8.8 Solder Attachment Failure ...................................93
7.5.3 Burn-In Testing ...................................................75 8.9 Validation and Qualification Tests ........................93
7.5.4 Product Screening Tests .......................................75 8.10 Screening Procedures ..........................................93
7.6 Assembly Process Control Criteria for 8.10.1 Solder Joint Defects ............................................93
Plastic BTCs ......................................................75 8.10.2 Screening Recommendations ................................93
7.6.1 Voids in BTC Solder Joints .................................75
7.6.2 Solder Bridging ...................................................76 9 DEFECT AND FAILURE ANALYSIS
CASE STUDIES ......................................................94
7.6.3 Opens .................................................................77
9.1 Solder Attachment Failures ..................................94
7.6.4 Cold Solder ........................................................78
9.1.1 Solder Attachment Failure Conditions ..................94
7.6.5 Defect Correlation/Process Improvement ..............78
9.1.2 Insufficient Solder Failures ..................................94
7.6.6 Effect of Insufficient and/or Uneven Heating ........78
9.1.3 Land, Nonsolderable ...........................................95
7.6.7 BTC Component Solderability Testing .................78
9.1.4 Termination, Nonsolderable .................................95
7.6.8 Solder Ball Defects .............................................78
9.2 Package Failures .................................................95
7.7 Repair Processes .................................................78
7.7.1 Rework/Repair Philosophy ...................................78 9.2.1 Package Warpage ................................................95

7.7.2 Removal of BTC .................................................79 9.3 Dewetting Failures ..............................................96

7.7.3 BTC Assembly Defect Repair ..............................79 9.3.1 Dewetting on QFN ..............................................96
9.4 Cracked Solder Joint Failure ................................96
8 RELIABILITY ...........................................................83 9.4.1 Cracks in Solder Joints ........................................96
8.1 Accelerated Reliability Testing .............................83 9.5 Component Failures ............................................97
8.2 Damage Mechanisms and Failure of 9.5.1 Tilted Component ...............................................97
Solder Attachments .............................................83
9.5.2 Lead Configuration Conditions .............................97
8.2.1 Differences in Accelerated Testing of
SAC vs. Tin/Lead ...............................................84 9.5.3 Joint Configuration Condition ..............................98
8.2.2 Mixed Alloy Soldering ........................................85 9.5.4 Solder Joint Volume ............................................98

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9.6 Voids ..................................................................99 Figure 4–16 Two and Three Row QFN Package Examples ..16
9.6.1 Voids in Solder Joint Through Xray .....................99 Figure 4–17 Basic Two Row Terminal Layout Variations .....16
9.6.2 Voids in Solder Joints Microsection Figure 4–18 Basic Three Row Terminal Layout Variations ...17
and X-Ray ..........................................................99 Figure 4–19 Contact Geometry Variations ...........................17
9.6.3 Voids in Thermal Pad ........................................100 Figure 4–20 Basic QFN Package Outline Drawing ..............17
10 GLOSSARY AND ACRONYMS ............................101 Figure 4–21 Pin 1 Location Option .....................................18
Figure 4–22 BTC Multiple Package Configurations .............18
11 BIBLIOGRAPHY AND REFERENCES .................101
Figure 4–23 Typical Die Attach Side Leadframe with Ni-
APPENDIX A ................................................................102 PdAu Finish for QFNs ....................................18
Figure 4–24 Typical Solder Pad Side of QFN Panel for
APPENDIX B ................................................................105 with Tape over the Leadframe .........................18
Figure 4–25 QFN Fabrication with Saw Singulation ............19
Figures Figure 4–26 Overmolded Leadframe Configuration ..............19
Figure 3-1 Discrete General Types of Bottom-Only Figure 4–27 QFN Fabrication with Punch Singulation .........20
Terminations .....................................................3
Figure 4–28 Comparing Punch-Press and Saw-Cut
Figure 3-2 Quad Flat No Lead Type Bottom-Only Singulation and Illustrating Wire Bond
Terminations .....................................................4 Options ..........................................................20
Figure 3-3 Small Outline No Lead Type Bottom-Only Figure 4–29 Example of Half Etch Pullback Contact
Terminations .....................................................4 and Full Etch No-Pullback Perimeter
Figure 3-4 Land Grid Array Type Bottom-Only Contact Configurations ....................................21
Terminations .....................................................4 Figure 4–30 Plating Layer Construction Comparison ...........23
Figure 3-5 Typical QFN Cross-Section ...............................5 Figure 4–31 Detailed View of a Custom Site for a QFN ......23
Figure 3-6 Saw Singulated (a, b) BTC Package ..................6 Figure 4–32 Bottom View of Land Grid Array
Figure 3-7 MLF Package Thickness When Compared to Printed Board .................................................24
Other Types of Packages ...................................6 Figure 4–33 Top View of Land Grid Array Printed Board ....24
Figure 3-8 Solder Mask Clearance Guideline for BTCs .......7 Figure 4–34 BTC Fabrication on a Substrate with Saw
Figure 3-9 Example of Segmented Stencil Pattern Design Singulation .....................................................25
on Thermal Land ..............................................7 Figure 4–35 Amkor’s 28 I/O MicroLeadFrame® Package .....27
Figure 3-10 Recommended Stencil Design to Provide Figure 4-36 Fairchild’s MLP is a Thermally Enhanced
50–60% Paste Coverage to Ground Lands SON Developed for Power Switch
(but 100% on I/O lands) ...................................8 Technology .....................................................27
Figure 4-1 Various Forms of BTC Parts .............................9 Figure 4–37 Intersil’s Quad No-lead Micro Leadframe
Figure 4-2 Singulated LGA Showing Bottom of Part .........10 Plastic Package (MLFP) ..................................27
Figure 4-3 Basic Single Row Lead-Frame Based SON- Figure 4–38 JEDEC MO-220 Package Outline ....................28
QFN Package Assembly Model .......................10 Figure 4–39 QFN Contact Design .......................................28
Figure 4-4 Basic Multiple Row QFN Package Assembly Figure 4–40 Analog Devices LFCSP™ (Leadframe
Model ............................................................10 Chip-Scale Package) .......................................29
Figure 4-5 Terminal Configuration for Single Row SON Figure 4–41 National Semiconductor LLP™ (Leadless
and QFN Packaging ........................................10 Package) ........................................................29
Figure 4-6 JEDEC Defined Package Outlines for Single Figure 4–42 Typical LLC and LFCSP Outline Detail ...........30
Row SON and QFN Packaging .......................11
Figure 4–43 JEDEC Tray Carrier Format ............................30
Figure 4-7 Terminal Design Variations for Single Row
SON and QFN Packaging ...............................12 Figure 5-1 Typical Build-Up HDI Platform, 2[4]2
Layer Configuration ........................................31
Figure 4-8 Odd and Even Terminal Contact Layout ..........12
Figure 5-2 Material Thermal Expansion Comparison .........34
Figure 4-9 Depopulation Schemes for Single Row
QFN Packaging ..............................................13 Figure 5–3 SSD Application Basic Fabrication Steps .........39
Figure 4–10 Corner Terminals and Exposed Heat Spreader ..13 Figure 5-4 SSD Process Steps ..........................................40
Figure 4–11 Fine-Pitch Two Row QFN (No lead) Figure 5-5 Comparing Solder Mask off Via Land with
Packaging .......................................................13 a Solder Mask Encroached Via Land ...............41
Figure 4–12 QFN Dual Row Package (top and side views) ..14 Figure 5-6 Planarized and Capped Via Protection
Example .........................................................42
Figure 4–13 Outer and Inner Terminal Layout Variations .....15
Figure 5-7 Via Protection Methods ...................................43
Figure 4–14 Two Row Terminal Layout ..............................15
Figure 4–15 The Notch Feature on the Exposed Die Figure 5-8 Metal Core Board Construction Examples ........44
Attach Pad Confirms Package Orientation Figure 5–9 Examples of Type VII Filled
with Reference to the A1 and B1 Terminals .....15 and Capped Vias .............................................. 45
...

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Figure 5-10 Example of Circuit Development of Solderless Figure 7-9 Metal Defined Land Solder Joint .....................66
Connection Technology .............................. 45
. Figure 7-10 Profile for Tin/Lead Solder Reflow ..................68
Figure 6-1 Family of Bottom Termination Components Figure 7-11 Profile for SAC Alloy Solder Reflow ...............68
(BTC) ............................................................47
Figure 7-12 SAC Alloy Flow Characteristics ......................71
Figure 6-2 QFN Bottom Termination Component
Lead-Frame Array ...........................................47 Figure 7-13 Post Assembly Contact and DAP Solder
Joint Profile ....................................................71
Figure 6-3 Comparing Pullback and No-Pullback
Configurations ................................................48 Figure 7-14 X-Ray Images Using Various Techniques to
Detect Missing Solder .....................................72
Figure 6-4 Land Pattern and DAP Land Layout Guide ......49
Figure 7-15 Typical X-Ray After Process ...........................73
Figure 6-5 Basic Outline Drawing for the 6 I/O SON .......49
Figure 7-16 Wire-bond X-Ray to Leadframe Illustration .....73
Figure 6-6 Recommended Land Pattern for JEDEC 6
I/O SON Package ...........................................50 Figure 7–17 Scanning Acoustic Microscopy ........................74
Figure 6-7 QFN Component and Land Pattern Figure 7-18 Typical Thermal Plane Voiding ........................75
Composite ......................................................50 Figure 7-19 Solder Paste Segments vs. Solder Paste Dots
Figure 6-8 Definition of Toe, Heel and Side Fillets ...........50 Printed over Plugged Thermal Vias ..................76
Figure 6-9 Comparing Pull Back to no-Pull Back Figure 7-20 X-Ray Images Showing Solder Segment and
Package Outline and Land Pattern Thermal Solder Dot Voiding Results .............................77
Land Layout ...................................................53 Figure 7-21 Solder Paste Printing Strategy: Segments
Figure 6–10 SON 0.5 mm Pitch, 6 Pin with Thermal Tab ....54 (left) vs. Solder Dots (right) ............................77
Figure 6-11 DAP to PCB Interface Example ......................54 Figure 7-22 Solder Segments vs. Solder Dots – Void
Potential .........................................................77
Figure 6–12 The Affect of θJA vs. Number, Distribution and
Diameter of Thermal Vias and Die Sizes for Figure 7-23 Dip and Look Test ..........................................78
a 36 I/O QFN with a 9 x 9 mm Body and Figure 7-24 Process Simulation Test ..................................78
7x7 mm Thermal Land ...................................55
Figure 7–25 Solder is Heated to Liquidus State and
Figure 6–13 Comparing Optional Solder Mask Variations ....55
the BTC is Withdrawn Before Solder
Figure 6–14 Solder Mask for (A) Perimeter Lands for Re-Solidification .............................................80
0.5 mm and Higher Pitch Parts, and (B)
for 0.4 mm Pitch Parts ....................................55 Figure 7–26 Desoldering of the BTC Mounting Site ............80

Figure 6–15 Representative BTC Outline Detail ..................56 Figure 7-27 Typical Laser Ablated Stencil Aperture
Geometry .......................................................81
Figure 6–16 Effect of Number of Thermal Via on Package
Thermal Performance ......................................56 Figure 7-28 Example of Window Pane Pattern on Stencil ....81
Figure 6–17 PCB Thermal Pad and Via Array for 7x7 mm, Figure 7-29 Typical Metal Stencil for Printing onto
48 lead and 10x10 mm, 68 Lead Packages .......57 Component .....................................................81
Figure 6–18 Comparison of the 80% Rule with Standard Figure 7-30 BTC Device is Clamped into Stencil Fixture ....82
Grid Systems for Routing Improvement ..........57 Figure 7-31 Solder Paste is Transferred Through Stencil
Figure 6–19 Effect of Voids on Thermal Performance ..........58 Apertures onto the Undersurface Features
of the BTC .....................................................82
Figure 6–20 X-Ray Example Showing Voids in the
Thermal Pad ...................................................59 Figure 7-32 Typical Dispensing System ..............................82
Figure 6–21 Solder Protrusion from the Bottom Side of Figure 7-33 Solder Bumping Method Using a Stencil .........82
PCB for Encroached Vias ................................60 Figure 7–34 Alignment Stencil on PCB ..............................83
Figure 7-1 Example of Good Land Patterns for Bottom Figure 7–35 “Bumped” Part Placed and Reflowed ...............83
Termination Components .................................61
Figure 8-1 Plate-Up Bumped Option ................................85
Figure 7-2 Example of Poor Land Patterns for Bottom
Termination Components .................................61 Figure 8-2 Cracks in QFN Solder Joints after
Temperature Shock .........................................86
Figure 7-3 Comparison of Solder Dipped and a Non
Solder-Dipped BTC and Resultant No Solder Figure 8-3 Land Size Impact on Fatigue Life of 7 mm
Condition .......................................................62 BTC Package .................................................86
Figure 7-4 Undersized PCB Pads Resulting in Potential Figure 8-4 QFN with Wettable Flanks ..............................86
Areas Where Pure Tin Finish Has Not Mixed
Figure 8-5 Weibull Plot Showing Thinner Board Results
with SnPb Solder Paste ...................................63
in Higher Fatigue Life ....................................87
Figure 7-5 Recommended Aperture Dimensions for Figure 8-6 The Crack Formation is the Result of the
Commonly Used Stencil Thicknesses ...............64 CTE Mismatch ...............................................89
Figure 7-6 Thermal Pad Stencil Designs for 7x7 mm and Figure 8-7 Depiction of the Effects of Accumulating
10x10 mm BTC Devices .................................65 Fatigue Damage in the Solder Joint
Figure 7-7 Solder Stencil Aperture Wall Area ...................65 Structure ........................................................92
Figure 7-8 Assessing Maximum Pre-Reflow Off-Land Figure 8-8 Solder Crack Due to Cte Mismatch after
Acceptance .....................................................65 1000 Cycles ...................................................92

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Figure 9–1 Optical image of acceptable QFN edge Figure 9–26 16-pin QFN with voids in the joint and the
terminations. Solder fillets should exist if thermal pad but well within action level. .........99
the design incorporates pads that extend Figure 9–27 QFN component with increase level of
beyond the package width. ..............................94 voiding to above 30%. Could be a reliability
Figure 9–2 Optical image of acceptable QFN edge concern. .......................................................100
terminations. Solder fillets should be Figure 9–28 Acceptable Condition of QFN edge joints
visible to a minimum of 75% of the showing an increased level of voiding within
width of the termination. .................................94 the joints but well within any action level. .....100
Figure 9–3 Cross section of BTC open joint due to Figure B1-1 BTC Component (left) and PCB (right)
insufficient solder paste volume during after Part Removal ........................................106
printing. .........................................................94
Figure 9–4 Cross section of BTC reliability failure after
Tables
1000 cycles due to insufficient solder paste
volume during printing. ...................................94 Table 3-1 Total Cost of Ownership of Bottom
Figure 9–5 Nonsolderable land on LGA package. ..............95 Terminated Components (BTC) ..........................7
Figure 9–6 3-D X-ray shows non-wet joints on a QFN. .....95 Table 4-1 QFN and DFN Configurations ............................9
Figure 9–7 Optical image of unacceptable QFN edge Table 4-2 Terminal width variations for SON and QFN ....13
terminations. The solder rise is limited and Table 4-3 Body Outline and Maximum Terminal Count ....14
an open joint can be seen. The package is
Table 4-4 Leadframe Package Defects and Failure
also ‘floating’ above the surface of the pads. ....95
Modes .............................................................22
Figure 9–8 Cross section image of QFN with an open Table 4-5 Plating Systems Used on Metal Leadframes ......23
joint caused by nonwetting of the solder to
the bottom land of the QFN. ...........................95 Table 4-6 Substrate Based Package Defects and Failure
Modes .............................................................26
Figure 9–9 Cross section of LGA with a corner joint
failure. The paste wicked to the package. .........95 Table 4-7 Typical Package Outline and I/O for QFN ........29
Figure 9–10 Concave warpage on 15x15 mm BTC. .............95 Table 4-8 Contact Pitch and Width Variations ..................30
Figure 9–11 Good wetting on QFN thermal pad after Table 4-9 Basic Material Elements for the LLC and
printing and reflow. .........................................96 LFCSP Devices ...............................................30
Figure 9–12 Dewetting on QFN thermal pad after printing Table 5-1 Environmental Properties of Common
and reflow. .....................................................96 Dielectric Materials .........................................33

Figure 9–13 Defect Condition of QFN edge joints Table 5-2 Key Attributes for Various Board Surface
showing insufficient solder in a joint. ...............96 Finishes ..........................................................35
Table 5-3 Via filling/encroachment to surface finish
Figure 9–14 Cracks in QFN solder joints after process evaluation ...........................................42
temperature shock. ..........................................96
Table 6-1 Quad Flat No Lead Tolerance Goals for
Figure 9–15 Tilted BTC causing high joint height Solder Joint Formation .....................................51
open on the left. .............................................97
Table 6-2 Package and Land Pattern (Pullback and No-
Figure 9–16 Tilted BTC causing good height on the right. ...97 Pullback) Dimensions ......................................52
Figure 9–17 Full lead option on BTS component. ...............97 Table 6-3 Legend for Basic Mechanical Attributes ............54
Figure 9–18 Half etched option on BTS component. ...........97 Table 6-4 Contact Pitch and Width Variations ..................56
Figure 9–19 Small fillet due to nonwetting of the side Table 7-1 Particle Size Comparisons ................................63
copper. ...........................................................98 Table 7-2 Typical Reflow Profile for Eutectic
Figure 9–20 Side fillet on bottom termination component (63Sn/37Pb) Solder Paste .................................67
good wetting to copper lead. ...........................98 Table 7-3 Profile Comparison Between SnPb and
Figure 9–21 Large fillet due to increase of solder volume. ...98 SAC Alloys .....................................................67
Figure 9–22 No Side fillet on bottom termination Table 7-4 Typical Reflow Profile for Lead-Free
component. .....................................................98 (SAC305 or SAC405) Solder Paste ..................69

Figure 9–23 Target Condition of QFN edge joints where Table 7-5 Guidelines for Void Criteria in Thermal/
showing a moderate level of voiding within Ground Planes of BTCs ...................................76
joints is acceptable. All joints have reflowed. ...99 Table 8-1 Accelerated Testing for End Use
Environments ..................................................84
Figure 9–24 Acceptable Condition of QFN edge joints
showing an increased level of voiding within Table 8-2 Coefficients of Thermal Expansion for
the joints but well within any action level. .......99 Typical Materials .............................................89
Figure 9–25 BTC component with a large edge joint. Table 8-3 Typical Heights (Joined) ..................................89
The joint did not have any cracking after Table A1-1 Etchants used to highlight Intermetallic
shock test. ......................................................99 compounds .....................................................104

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March 2011 IPC-7093

Design and Assembly Process Implementation

for Bottom Termination Components

1 SCOPE IPC-A-610 Acceptability of Electronic Assemblies

This document describes the design and assembly chal-
IPC-SM-785 Guidelines for Accelerated Reliability Test-
lenges for implementing Bottom Termination surface mount
ing of Surface Mount Solder Attachments
Components (BTCs) whose external connections consist of
metallized terminations that are an integral part of the
component body. Throughout this document the word IPC-1756 Manufacturing Process Data Management
“BTC” can mean all types and forms of bottom only
termination components intended for surface-mounting. IPC-2226 Sectional Design Standard for High Density
This includes such industry descriptive nomenclature as Interconnect (HDI) Printed Boards
QFN, DFN, SON, LGA, MLP, and MLF, which utilize
surface to surface interconnections. The focus of the infor- IPC-4101 Specification for Base Materials for Rigid and
mation contained herein is on critical design, assembly, Multilayer Printed Boards
inspection, repair, and reliability issues associated with
BTCs. IPC-4761 Design Guide for Protection of Printed Board
Via Structures
1.1 Purpose The target audiences for this document are
managers, design and process engineers, and operators and IPC-6012 Qualification and Performance Specification
technicians who deal with the electronic design, assembly, for Rigid Printed Boards
inspection, and repair processes. The intent is to provide
useful and practical information to those companies who are IPC-7351 Generic Requirements for Surface Mount De-
using or considering tin/lead, lead-free, adhesives or other sign and Land Pattern Standard
forms of interconnection processes for assembly of BTC
type components. IPC-7525 Stencil Design Guidelines
1.2 Intent This document, although not a complete
recipe, identifies many of the characteristics that influence IPC-7526 Stencil and Misprinted Board Cleaning Hand-
the successful implementation of robust and reliable assem- book
bly processes and provides guidance information to compo-
nent suppliers regarding the issues being faced in the IPC-9201 Surface Insulation Resistance Handbook
assembly process. The exchange of information between the
component supplier, product designer, and assembly per- IPC-9701 Performance Test Methods and Qualification
sonnel about those parameters that influence good assembly Requirements for Surface Mount Solder Attachments
practices are more critical with BTC implementation than
with many other surface mount parts. J-STD-001 Requirements for Soldered Electrical and
Electronic Assemblies
2 APPLICABLE DOCUMENTS
J-STD-002 Solderability Tests for Component Leads, Ter-
2.1 IPC1 minations, Lugs, Terminals and Wires
IPC-T-50 Terms and Definitions for Interconnecting and
Packaging Electronic Circuits J-STD-005 Requirements for Soldering Pastes

IPC-CH-65 Guidelines for Cleaning of Printed Boards J-STD-020 Moisture/Reflow Sensitivity Classification for
and Assemblies Nonhermetic Solid State Surface Mount Devices

IPC-D-279 Design Guidelines for Reliable Surface J-STD-033 Handling, Packing, Shipping and Use of
Mount Technology Printed Board Assemblies Moisture/Reflow Sensitive Surface Mount Devices

1. www.ipc.org

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IPC-7093 March 2011

2.2 JEDEC2 3.1.3 Conductive Pattern* The configuration or design

JEDEC Publication 95 JEDEC Design Standard, Design of the conductive material on a base material. (This includes
Requirements for Outlines of Solid State and Related traces, lands, vias, planes, and passive components when
Products Design Guide: 4.8, Plastic Quad and Dual Inline these are an integral part of the printed board manufacturing
Square and Rectangular No Lead Packages (With Optional process.)
Thermal Enhancements) (QFN/SON) Date: September
2006, Issue: C 3.1.4 Land Pattern* A combination of lands that is used
for the mounting, interconnection and testing of a particular
JEDEC Publication 95 JEDEC Design Standard, Design component.
Requirements for Outlines of Solid State and Related
Products Design Guide: 4.19, Quad No-Lead Staggered and
3.1.5 Mixed Component-Mounting Technology* A com-
Inline Multi-Row Packages (With Optional Thermal En-
ponent mounting technology that uses both through-hole
hancements) (QFN) Date: May 2007, Issue: D
and surface-mounting technologies on the same packaging
JEDEC Publication 95 JEDEC Design Standard, Design and interconnecting structure.
Requirements for Outlines of Solid State and Related
Products Design Guide: 4.20, Small Scale Plastic Quad and 3.1.6 Printed Board Assembly The generic term for an
Dual InLine Square and Rectangular No-Lead Packages assembly that uses a printed board for component mounting
(With Optional Thermal Enhancements) (QFN/SON) Date: and interconnecting purposes.
September 2009, Issue: D.01
JEDEC Publication 95 JEDEC Design Standard, Design 3.1.7 Surface Mounting Technology (SMT)* The electri-
Requirements For Outlines of Solid State and Related cal connection of components to the surface of a conductive
Products Design Guide: 4.23, Punch-Singulated Fine Pitch pattern that does not utilize component holes.
Square Very Thin and Very-Very Thin Profile, Leadframe-
Based Quad No-Lead Staggered Dual-Row Packages (with 3.2 BTC Executive Summary The term BTC represents
Optional Thermal Enhancements) Date: November 2005 industry descriptive package names such as DFN (Dual Flat
No-lead), QFN (Quad Flat No-Lead package), LGA (Land
3 SELECTION CRITERIA AND MANAGING BTC IMPLE-
Grid Array), SON (Small Outline No-Lead – leads on two
MENTATION
sides), PQFN (Plastic Quad Flat No-Lead), MLFP (Micro
This section provides a high level overview of the entire Leadframe Plastic Package), and MLP (Micro Leadframe
document. It is the executive summary of the usage and Package) etc. They are in some ways similar to BGAs which
implementation of BTC parts in the electronic assembly. For also have hidden terminations, but they are also very
technical details on BTC design, assembly and reliability different. They do not have spheres but rather metallized
issues, refer to the sections related to those topics. terminations or pads underneath the package.
When implementing BTCs into an electronic assembly, one
3.1 Terms and Definitions Terms and definitions used
must keep in mind that these parts are not the only
herein are in accordance with IPC-T-50 except as otherwise
components that must be mounted on the interconnection
specified. Any definition denoted with an asterisk (*) is a
product board. The board will have other packages such as
reprint of the term defined in IPC-T-50.
BGAs, fine pitch and even some through-hole components,
and those components may have their own unique design
3.1.1 Bottom Termination Components (BTC) Surface
and assembly implementation requirements.
mountable electronic components whose external connec-
tions consist of metallized terminations that are an integral There are two key issues in BTCs: providing the appropriate
part of the component body. The terminology BTC includes amount of solder paste and ensuring solder joint reliability.
such industry descriptive nomenclature as QFN, DFN, This entire document is essentially dealing with these two
SON, LGA, MLP, and MLF, which utilize surface to surface issues in various design and assembly sections. Other
interconnections. variables such as surface finish, stencil selection, thermal
profile are also discussed and may not be different because
3.1.2 Component Mounting Site The location on a of BTCs. Since there is no protruding lead on the package,
printed board or mounting structure that consists of a land reliability of the solder joint is essentially controlled by
pattern and conductor fan-out to additional circuit features solder joint area and height. Lower paste volume can reduce
such as lands for testing or vias that are associated with the floating and voids but increases the risk of solder opens so
mounting of a single component. a balance is required to ensure overall solder joint reliability.

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March 2011 IPC-7093

Most, but not all, BTC packages have an exposed Die Because there are no protruding leads, BTCs have proved to
Attach Pad (DAP) feature on the package bottom to provide exhibit minimal parasitic losses due to their very low
a thermal interface with the mating circuit board surface. electrical resistance and capacitance, and heat transfer from
When it comes to inspection, they pose even more challenge the package to the PCBs is excellent due to their large
than Ball Grid Arrays (BGAs) which allow inspection by thermal pad in direct contact with PCB.
endoscopes. One may not be able to see side solder fillets
In order to ensure a robust package-to-PCB interface, solder
and even when they are seen on BTCs with cut metal
paste deposition must be tightly controlled. Excessive or
leadframes, they may look non-wetted or dewetted. If
unevenly deposited solder paste volume may cause the
plating is on the side metal, dewetted and non-wetted side
package to float, resulting in poor land pattern alignment,
fillets on BTCs may indicate solder bonding problems.
random solder bridging, voiding and opens.
Examples of BTC components covered in this section are
shown in Figures 3–1 to 3–4. Too little solder volume may compromise product reliabil-
ity. Even minimal warping in the package or PCB can result
a) General types: Discrete components (diodes, transistors, in solder joint opens. Because the terminal features may not
inductors etc.) – some DFNs as shown in Figure 3–1. protrude beyond the package body, visual inspection and
b) Quad Flat No Lead (QFN): Component part with I/O uncompromised verification of the solder interface will be
(input/output) on four sides as shown in Figure 3–2. difficult.
c) Small Outline No Lead (SON): Component part with I/O 3.3 Description of Different Component Structures
on two sides (includes some DFNs) as shown in Figure Surface mount components with bottom only terminations
3–3. are becoming more and more prevalent and there are many
d) Land Grid Array (LGA): Component part with I/O in types of bottom only termination components that go by
rows and columns [structured or random] as shown in various names. Unlike the more traditional leadframe pack-
Figure 3–4. aged semiconductors with protruding leads, the BTC de-
vices are furnished with flat pads or terminations on the
The basic driver for BTCs is the cost. It is a package with bottom of the package. Those terminations are provided on
the lowest per pin cost, as low as half a cent per pin. To put only two sides or on all four sides of the package in single
this in a proper perspective, if a package costs less than one or multiple rows. The Bottom Termination Component task
cent per pin, it is considered a very low cost package. So group has decided to use a common name for all these
BTCs become an ideal package especially in high volume package types since they require a common approach of
applications such as cell phones or other mobile products design and assembly. That common name is BTC or Bottom
Termination surface mount Component to represent all of
Although many select BTC packaging for its favorable cost
these packages in this document.
factor, the package family has become widely used for
semiconductors requiring electrical performance and im- The BTC packages are leadless, near Chip Scale Package
proved thermal management. Assembly processing, how- (CSP) size with low profile (1.0 mm and less), excellent
ever, will require a careful attention to process control from thermal dissipation and good electrical performance. Typi-
solder material selection, deposition, package placement cal BTCs have solderable terminations that are flush with
and solder reflow profile. In regard to the mounting struc- the bottom of the device. These devices can also have
ture, the PCB must exhibit minimal warp and the land smaller solderable termination areas located along the
patterns for BTC attachment must provide a uniform surface perimeter sides or flanks of the package near the bottom of
finish. the device.

IPC-7093-3-1

Figure 3-1 Discrete General Types of Bottom-Only Terminations

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IPC-7093 March 2011

Includes QFN and PQFN with Pull back

leads and multiple rows
IPC-7093-3-2

Figure 3-2 Quad Flat No Lead Type Bottom-Only Terminations

Includes SON and PSON with Pull

back leads and some complex
DFN general components
IPC-7093-3-3

Figure 3-3 Small Outline No Lead Type Bottom-Only Terminations

IPC-7093-3-4

Figure 3-4 Land Grid Array Type Bottom-Only Terminations

One of the primary benefits provided by the BTC package is Traditional gull-wing leaded packages have very good long
a very low profile. This is a key requirement for newer solder joint reliability life compared to leadless components
generations of portable, wireless and handheld electronic of the same size, since they have very flexible leads. The
products where both weight and package thickness must be BTC packages, on the other hand, are not compliant and
minimized. This trend reduces the semiconductor package may exhibit a relatively shorter solder joint life when
outlines and profile for portable handheld devices. subjected to operation in harsh environments. This is
because they do not have leads that can take up stresses and
The contact pitch for BTC packages is generally 1.0 mm or
strains introduced by differing coefficients of thermal ex-
less and the packages tend to be smaller in size. The body
pansion between the package and the substrate.
outline dimensions can be as small as 2.0 mm x 2.0 mm or
as large as 12.0 mm x 12.0 mm. Due to finer contact pitch Many of the BTC packages are furnished with a copper
variations this package is able to accommodate a die leadframe substrate and offer a thermal enhancement by
element that is nearly the same size as the package exposing the die attach pad on the bottom of the package

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March 2011 IPC-7093

surface. The die-attach pad provides an efficient heat path the top half of the lead thickness exposed to the sides of the
when soldered directly to the board. This enhancement also package. Figure 3–6 shows the differences in these package
enables stable ground interface by use of down bonds or by configurations.
electrical connection through a conductive die attach mate-
rial. But such thermal pads have the potential for large voids One of the biggest benefits of the BTC packages is their
and may even lead to the package floating if solder paste thickness. In mobile applications such as the cell phone,
volume is not tightly controlled. palm top and laptop, weight and thickness of the device
becomes even more important. BTC packages allow much
The BTC package comes in two formats: punch singulated thinner devices than possible when using other types of
and saw singulated. While punch singulated packages are surface mount components. Figure 3–7 shows relative
individually punched from molded strip during final assem- package thickness of various component packages. The
bly, saw singulated packages are assembled in array format MLF package is much thinner than traditional SMT pack-
and separated into individual components during the final ages.
sawing operation. See Figure 3–5. Both singulation methods
can leave the terminal edges without a wettable surface While the lack of traditional leads or balls allows lower
finish. package thickness and better electrical and thermal perfor-
mance, the low standoff height makes it difficult to remove
The saw singulated package is further divided into two any trapped flux residues that remain in and around the
options: Full Lead package, and Lead Pullback package. solder joints. And if the flux is active, the corrosion potential
While the full lead package has the whole thickness of the is increased. Also, it is necessary that the package and PCB
lead exposed on the package sides, the lead pullback be very flat to achieve good interconnection; otherwise, the
package has a bottom half etch leadframe, resulting in only potential for opens in solder joints is increased. And since

IPC-7093-3-5

Figure 3-5 Typical QFN Cross-Section

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IPC-7093 March 2011

IPC-7093-3-6

Figure 3-6 Saw Singulated (a, b) BTC Package

Package Height Comparison

SOIC
MQFP
3.93 mm CABGA
SO/8C
MLF
MQFP LQFP
2.33 mm TSOP
1.6 mm TSOP
TQFP TSSOP
1.2 mm 1.1 mm 0.9 mm
0.8 mm 0.6 mm

IPC-7093-3-7

Figure 3-7 MLF Package Thickness When Compared to Other Types of Packages

the standoff height is very low, solder joint reliability may 3.5 Design and Assembly Process Considerations for
be a concern in harsher environments. QFN Type BTC Packages Land pattern design and stencil
designs are the key tools to prevent potentials for opens and
shorts in the same package. Since some BTCs require wide
3.4 Total Cost of Ownership Low package cost is a key
lands for power/ground pins and narrow lands for signals, it
driver for widespread use of BTCs. However, the low
may be necessary to increase the stencil aperture for signal
package cost may not immediately translate into overall low
pins to prevent opens but at the same time make the stencil
assembly cost since this package presents many challenges
apertures much smaller than the power and ground pads to
in assembly, inspection, and rework.
prevent squeeze balls and shorts.
In practical reality, the total cost of the final assembly is
often greatly impacted by decisions made early in the design Figure 3–8 shows guidelines for land pattern design. The
process. Too often accounting systems track “cost in the lands are larger than the lead footprint. The land pattern
door” but fail to track “cost out the door”. Purchasing is should extend beyond the package footprint especially
measured and rewarded by identifying and procuring at the underneath the package. The stencil aperture may have to be
lowest price, without understanding and fully appreciating the same size as the land pattern. When the spacing becomes
the impact on the manufacturing process and long term very close, solder mask is used in order to retain the solder
reliability of the product and the implied cost of failures. in the land pattern area as shown in Figure 3–8.
Thus it is incumbent on management to prudently consider Stencil aperture design is not only critical to preventing
and decide on the amount of effort to devote to “up front” opens and shorts in BTC package, it is also important to
engineering, including component selection or package prevent floating of BTC packages, a very common phenom-
design, solder joint design, board design, and design veri- enon.
fication. Management must also understand and appreciate
the true piece part cost which is comprised of several The reality is that BTC packages will be used with all other
elements including the cost of components, incoming in- types of surface mount components, including BGAs,
spection, assembly, test, and final inspection. The decisions PQFPs, etc. So the selection of solder powder size will have
made will directly impact product reliability. Table 3–1 to be done based on the lowest pitch component on the
below lists the key components of Total Cost of Ownership. board. That particular package may or may not be a BTC

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March 2011 IPC-7093

Table 3-1 Total Cost of Ownership of Bottom Terminated Components (BTC)

Cost Contributor Impact

Incoming inspection The incoming component inspection level is a function of the confidence the buyer has in the sup-
plier considered in view of the cost of the different potential defects which might be encountered
and how they might be resolved. Rework is an expensive process but product returns can ruin a
business.
Component or package To meet cost and reliability targets, a reasonable rule of thumb is to select or design the lowest
design cost package that meets the lead count requirement and power dissipation with the largest pitch
tolerable within design constraints. Consideration of the potential change to product specifications
to improve product cost and reliability may be desirable under certain circumstances.
Solder joint quality The solder joint is the most critical factor in product reliability today. Solder volume and solder
placement is critical to yield and reliability of BTC assembly. The die attach pad (DAP) has been
identified as an item that may be of high importance as some data show that reliability is reduced
when it is not soldered in place.
Board design The board materials choice, layout and land pattern design are all vital and directly impacts board
cost, assembly yield and reliability.
Assembly method The assembly process has several steps including solder paste deposition, component place-
ment, reflow and cleaning. The method chosen can represent a relatively minor % of overall cost
when done with a well controlled process but costly otherwise. In some cases with BTCs, supple-
mentary process equipment may be needed. While this will add some cost, overall cost will be
reduced by improving yield.
Test & inspection While it is impossible to inspect quality into a product, test and inspection are commonly used to
assure process control. Thus some level of visual, X-ray and electrical test is used to verify the
quality of assemblies. Assembling BTC devices with solderable flanks has been shown to promote
improved post-reflow inspection capability. Current BTC device processing steps do not guarantee
solderable flanks. Requiring device suppliers to produce BTCs with solderable flanks may require
adding additional processing. Post-reflow inspection that allows bad or marginal solder joint es-
capes leads to lower end user confidence and higher total cost.
Reliability Rigorous design control reduces cost by ensuring reliability. Demonstrating the reliability of a de-
sign can be an expensive process and represent a major up front cost. A failure, however, espe-
cially a field failure, has arguably even greater cost impact.

Solder Mask
BTC footprint Thermal pad
outline
Land Pattern

BTC footprint
Solder paste
apertures
IPC-7093-3-8

Figure 3-8 Solder Mask Clearance Guideline for BTCs

IPC-7093-3-9

package. Also the thickness of the paste for BTC is critical Figure 3-9 Example of Segmented Stencil Pattern Design
since too little paste will create insufficient or, most likely, on Thermal Land
open solder joints. But excessive paste may cause floating of
BTC. To prevent package float during the solder process, The land pattern design should allow extension of the land
paste deposit thickness (especially on the center located beyond the package footprint outside of the package to
thermal pad) should not be on the excessive side. Figure 3–9 facilitate AOI or visual inspection. It is important to keep in
shows a stencil design approach to achieve 50 to 60% of the mind that a toe fillet is not required since it is not possible
thermal pad area. to achieve a toe fillet on a consistent basis since the
packages are sawed and have an exposed unplated surface.
It is recommended that the stencil design provide 50 to 60%
A land pattern extension should provide visual evidence of
solder paste coverage on the thermal pad area and 100%
reflowed solder at the toe of the BTCs even though the edge
solder paste coverage on the I/O lands. Figure 3–10 shows
of the metallization is not wetted.
a stencil design for both a ground plane with reduced paste
coverage and outer I/O pad with stencil apertures with It is difficult to inspect BTC solder joints from the top of the
100% paste coverage. package. So it may be necessary to tilt the PCB to inspect

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IPC-7093 March 2011

remove and replace faulty components. Tools such as hot air

and laser systems are used for rework of assemblies by
removing the component in question, redressing the lands
and adding the appropriate solder paste or perform and
positioning the component before applying heat.

3.6 Future Needs and Expectations BTC packages are

becoming more and more popular because of their lower
cost. But the lower package cost has not necessarily
translated into lower cost overall when you take into
account the total cost of the package, assembly, inspection,
repair and potentially increased field failures. The root cause
often attributed to this increased failure is the lack of
protruding leads which, on the positive side, is the founda-
tion of increased thermal and electrical benefits of the BTC
package family.
IPC-7093-3-10 As the industry has been constantly focused on cost reduc-
Figure 3-10 Recommended Stencil Design to Provide
tion, the package suppliers have carved out a niche to reduce
50–60% Paste Coverage to Ground Lands (but 100% on I/O package cost. There remains a lot to be done about reducing
lands) PCB and manufacturing cost.

BTC solder joints to see solder underneath the package even 4 COMPONENT CONSIDERATIONS
though no toe or end fillet is expected. See 7.4 for more
This section provides the details of various BTC from the
detail for post assembly inspection techniques of BTC
point of view of the component manufacturer. The common
devices.
fabrication methods using both leadframes and substrates
X-ray inspection is one way to detect solder shorts under- are described as well as common defects from each of these
neath the BTC package. The X-ray image is also a good way processes. The section also describes the manufacturing
to view solder voids in the solder joints. The acceptance process flow for producing the different packages as well as
limit of percentage of voiding in BTCs should be less than the geometries, materials and many standard variations.
acceptable limits of 25% voids allowed in BGAs since there
Although a number of small outline semiconductor package
are no balls in BTCs and hence the potential for void
innovations have been available (e.g., BGA and FBGA), an
is much less than in BGAs. However the void limits in
effective method to significantly reduce the package area
the BTC thermal solder joints will have to be much
and cost was not available until the introduction of the SON
higher because of much higher solder paste volume used
and QFN package technology. The most significant feature
on thermal pads. It is recommended that producers/
of all of these small outline leadframe package families is
manufacturers determine the voids allowable in volume and
their power dissipation capability and minimal electrical
distribution for respective application requirements.
parasitics. The improved thermal dissipation performance
The micro-sectioning and die penetration techniques are comes from the exposed leadframe that is used to help pull
other methods of inspecting solder joints. These methods heat out of the die to a mating thermal pad on the circuit
are not meant for production inspection, but should be used board. Electrical parasitics are inherently low due to the
for process development. small size and short wire bonds.
BTC components removed during PCB rework should not
4.1 General Description of Different BTC Packages A
be reused for final assemblies. A package that has been
large variety of bottom termination component packages are
attached to a PCB and then removed has seen two solder
in the market. A few of the options are:
reflows and if the PCB is double sided, the package has seen
three solder reflows. Thus the package is at or near the end 1) package configuration
of the tested and qualified range of known survivability. 2) pitch (1.0–0.4 mm)
These removed BTC components should be properly dis-
3) termination geometry
posed of so they will not be mixed in with fresh equivalent
BTC components. See 7.7 for more detail for rework and 4) land pattern geometry
repair of BTC devices. 5) package thickness
The rework station for BTCs should be similar to many 6) thermal pad geometry
other type rework systems and have available the tools to 7) plating

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March 2011 IPC-7093

Figure 4–1 shows some of the BTC parts as shipped by the built on a multilayer substrate. Many of the laminate based
manufacturer to the board assembly plant. LGA components include multiple die elements and a
number of passive devices. These configurations may con-
These parts are available in a variety of configuration. Table
sist of several different, but complementary, functions that
4–1 shows the configurations of QFN and SON (DFN) that
together create a product that can be classified as a system-
are available from one packaging foundry. Other foundries
in-package (SiP). See Figure 4–2.
are likely to have many of these as well as some that do not
appear here. The JEDEC Standards list many other size, 4.2 Detailed Description and Standards for BTCs
lead and thickness combinations that result from a general
approach. Most of those listed, however, are not in common 4.2.1 Single Row Molded Lead-Frame Based Packaging
use. The Die Attach Pad (DAP), when exposed outside the mold
compound, also serves as a heat spreader. The die element
Table 4-1 QFN and DFN Configurations
is first bonded to the DAP surface followed by wire-bond
Typical QFN/SON (DFN) termination from the die bond pads to the contact features at
Plastic Packages that are Commercially Available
All dimensions in millimeters
its perimeter (see Figure 4–3). The package is completed
when the plastic casing is molded around the die and
Lead Nominal
Size QFN DFN Pitch Thickness wire-bond area leaving only the bottom area of terminals
and heat spreader exposed for solder attachment.
2x2 6, 8 0.50 0.9
3x3 8 0.65 0.9 To control the effects of the large surface area of the die
attach pad feature during the reflow soldering process, it
3x3 12, 16, 8, 10 0.50 0.9
will be necessary to tailor the solder stencil pattern or alter
3x3 20 0.40 0.9
the mating thermal plane on the PC board.
4x3 12 0.50 0.9
4x4 16 0.65 0.9 4.2.2 Multiple Row Molded Lead-Frame Based Pack-
4x4 20,24 0.5 0.9 aging Plastic quad configured multiple row no-Lead pack-
5x5 20 0.65 0.9 ages (QFN) are plastic semiconductor packages with met-
5x5 28, 32 0.50 0.9 allized terminals. Terminal contacts are located along the
6x6 40 0.50 0.9
edges of the bottom surface of the package body arranged in
1, 2 or 3 rows. Typical of the single row QFN, the multiple
7x7 48 0.50 0.9
row QFN package is a lead-frame based product. Before
7x7 56 0.40 0.9
wire-bond, the die is bonded to the DAP surface followed
8x8 52, 56 0.50 0.9 by wire-bond termination from the die bond pads to the
9x9 64 0.50 0.9 contact features at its perimeter (see Figure 4–4).
12x12 100 0.40 0.9
The package is completed when the plastic casing is molded
around the die and wire-bond area leaving only the bottom
Land Grid Arrays are built in comparable sizes to those in area of terminals and heat spreader exposed for solder
the JEDEC standards and those in the table above. LGAs are attachment. The die attach ‘paddle’, when exposed, also
typically larger than 5 mm x 5 mm and are almost always serves as a heat spreader.

IPC-7093-4-1

Figure 4-1 Various Forms of BTC Parts

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IPC-7093 March 2011

of the plastic package body outline. The industry also uses

the term DFN (dual flat no-lead) to describe SONs.

4.2.3.2 QFN Plastic Quad Flat No-Lead Packages have

terminals on all four edges of the bottom surface of the
package. The QFN can have either a square or rectangular
body outline as well as either symmetric or asymmetric
terminal patterns.
The single row small outline no-lead (SON) and quad
flatpack no-lead (QFN) package technology has become a
viable low cost methodology furnishing a package outline
only slightly greater than the die. JEDEC defines the
QFN/SON as a plastic semiconductor package with metal-
lized terminals located on the bottom of the package body
along its periphery as detailed in Figure 4–5.
IPC-7093-4-2

Figure 4-2 Singulated LGA Showing Bottom of Part

Wire-bond interface
Die element attached to DAP feature

IPC-7093-4-5

Figure 4-5 Terminal Configuration for Single Row SON and

QFN Packaging
Bottom exposed die attach pad (DAP)
Bottom exposed contact pads
IPC-7093-4-3 As noted in earlier sections, because the terminal features
are flush with the bottom surface of the plastic body and do
Figure 4-3 Basic Single Row Lead-Frame Based SON-QFN
not protrude beyond the body outline, these packages are
Package Assembly Model
categorized as “bottom termination components” or “no-
lead”. In addition, the supplier has the option of supplying
Wire-bond interface an exposed heat spreader element on the bottom surface to
Die element attached to DAP feature assist in transferring thermal rise generated by the die
element into the host circuit structure using solder or
thermally conductive compounds.
The JEDEC design guide defines the symbology, algo-
Bottom exposed die attach pad (DAP) rithms, and recommended dimensions and tolerances for a
family of QFN and SON Packages. The guidelines are based
Bottom exposed contact pads
IPC-7093-4-4 on hard metric dimensions and adhere to the geometric
dimensioning and tolerancing principles defined in ASME
Figure 4-4 Basic Multiple Row QFN Package Assembly
Y14.5M.
Model
In regard to the contact numbering method for the SON
4.2.3 JEDEC Publication 95 Design Guide 4.8 The fol- package positions terminal #1 (viewed from the top surface)
lowing excerpts are for Plastic Quad and Dual Inline, at the lower left corner. Dimension ‘D’ should then be
Square and Rectangular, No-Lead Packages (With Optional measured in the horizontal direction. Similarly, measure
Thermal Enhancements). They include JEDEC definitions dimension ‘E’ in the vertical direction for both package
for SON and QFN packaging. types. For QFN, the position of terminal #1 is perpendicular
to the body edge in the upper left corner as compared in
Figure 4–6.
4.2.3.1 SON (DFN) Plastic Dual Inline Flat No-Lead
Package is a semiconductor package with metallized termi- Terminal #1 identifier and terminal numbering convention
nals located on the bottom of the package. The SON has will conform to JEDEC Pub.95, Sec 4.3, SPP-002. Terminal
terminals on only two opposite sides of the bottom surface. #1 identifier will be located within the zone indicated on the
By design, these terminals are flush with the bottom surface outline drawing. Topside terminal #1 indicator may be a

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March 2011 IPC-7093

IPC-7093-4-6

Figure 4-6 JEDEC Defined Package Outlines for Single Row SON and QFN Packaging
molded or marked feature. Optional indicator marking or An example of two terminal design variations is detailed in
features may also be furnished on the bottom surface as Figure 4–7.
well.
There are three terminal variations:
Basic dimension for D and E dimensions suggested in the
1. Pullback – The terminals are located completely under
JEDEC design guide to be in increments of 0.50 mm
the package body outline.
ranging from 1.00 mm through 12.00 mm. Outlines with
‘D’ and ‘E’ increments less than 0.50 mm should be 2. No Pullback – The terminals extend all the way to the
Registered as ‘standalone’ outlines. These outlines should edge of the package outline.
use as many of the algorithms and dimensions (stated in this 3. Extended – Terminals extend beyond the body outline
guide) as possible to ensure predictability in manufacturing. (flange type molded version) but the overall measure-
ments do not exceed the ‘D’ and ‘E’ dimensions defined
The JEDEC members acknowledge that differing manufac-
in the guideline.
turing processes by supplier companies will require some
flexibility in the package configuration. Although the pri- The terminal contacts may be furnished in ‘odd ‘or ‘even’
mary controlling dimensions will remain common, the numbers as illustrated in Figure 4–8. Inner edge of corner
terminal geometry may vary from one supplier to another. terminals may be chamfered or rounded in order to achieve

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IPC-7093 March 2011

Standard (Saw Cut) Flange Type (Molded)

IPC-7093-4-7

Figure 4-7 Terminal Design Variations for Single Row SON and QFN Packaging

Even Terminal Variation Odd Terminal Variation

( DATUM A OR B )
( DATUM A OR B )
TERMINAL TIPS
MAY BE ROUNDED

(L) L1 L3

e/2 L2 e
e
TERMINAL TIP
IPC-7093-4-8

Figure 4-8 Odd and Even Terminal Contact Layout

minimum gap ‘k’. This feature should not affect the terminal The length (L) of the terminal as measured from the edge of
width ‘b’ which is measured from the edge of the package the plastic body. The JEDEC 4.8 guideline document allows
body. two optional length dimensions defined as ‘short foot’ and
‘long foot’. The terminal is classified as ‘short foot’ when
Suppliers will generally furnish components with a bal-
‘L’ nominal is 0.35–0.45 mm. If the package terminal
anced depopulation to reduce unequal surface tension forces
dimension ‘L’ nominal is 0.50–0.60 mm, it is classified as a
that may occur during reflow solder assembly processing.
‘long foot’ variation.
Non-symmetric package configurations should be separate
mechanical outline variations including depopulation graph- In regard to contact pitch, although six variations are
ics. See Figure 4–9. Corner population of terminal features included in the guideline standard, a majority of products
is also an option on the QFN package and both SON and actually reaching the market have been supplied with either
QFN, as noted, may be furnished with an exposed portion of 0.65 mm or 0.50 mm pitch. The 0.40 mm pitch devices are
the die attach pad on the bottom surface as shown in Figure also being offered for limited applications, however, second
4–10. The bottom exposed die attach pad may be a solid or level assembly processing requires very strict control.
segmented, arranged in a matrix format, and may have
optional corner radii on each segment. 4.2.4 JEDEC Publication 95 Design Guide 4.23 The
JEDEC Design Guide applies to Punch-Singulated, Fine
4.2.3.3 SON/QFN Terminal Spacing and Dimensions Pitch, Square, Very Thin and Ultra Thin Profile, Lead-frame
The ‘b’ dimension represents the width of the metallized Based, Quad No-Lead Staggered Dual-Row Packages (with
terminals (including lead finish) exposed at the bottom optional Thermal Enhancements). The examples shown in
surface of the package. The terminal width (b) will vary as Figure 4–11 represent dual and triple row QFN with and
the pitch dimension narrows as shown in Table 4–2. without optional exposed die attach pad features.

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March 2011 IPC-7093

Example A Example B Example C

IPC-7093-4-9

Figure 4-9 Depopulation Schemes for Single Row QFN Packaging

6 18

1 23 IPC-7093-4-11

Figure 4–11 Fine-Pitch Two Row QFN (No lead) Packaging

IPC-7093-4-10

In regard to the description of the package as ‘very thin’ and

Figure 4–10 Corner Terminals and Exposed Heat Spreader
‘very-very thin’, the overall component height is measured
The QFN is described as a plastic semiconductor package from the seating plane (surface of the host substrate). The
with metallized terminals located along the peripheral edges very thin (V) version will have a maximum dimension of
of the bottom surface of the package. As noted, the package 1.0 mm while the package defined as very-very thin (W)
terminals are flush with the bottom surface of the plastic configuration has a 0.8 mm height limitation. The uniform
package body, so the packages are considered to be “BTC” square body dimensions are established in 1.0 mm incre-
or “no-lead”. This package has 2 rows of terminals on all ments from 5.0 mm through 12.0 mm and, depending on
four peripheral edges of the bottom surface of the package contact pitch (0.50 mm or 0.65 mm), an established maxi-
(see Figure 4–12). mum terminal count possible in the two row configuration
(see Table 4–3).
The dual row QFN package may have either symmetric or
asymmetric terminal patterns. Terminal A1 identifier must Outlines with “D” and “E” increments less than 1.00 mm
be located within the zone indicated on the outline drawing. will likely be registered as “stand-alone” outlines. These
Topside terminal A1 indicator may be a molded or marked outlines should use as many of the algorithms and dimen-
feature and an optional indicator on bottom surface may be sions (stated in this guide) as possible to ensure predictabil-
furnished as a molded, marked, or metallized feature. ity in manufacturing.
Table 4-2 Terminal width variations for SON and QFN
Contact b
Pitch Terminal Width (b)
1.27 0.30 0.40 0.50
1.00 0.30 0.40 0.45
0.80 0.25 0.30 0.35
L
0.65 0.25 0.30 0.35
0.50 0.18 0.25 0.30
0.40 0.15 0.20 0.25

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IPC-7093 March 2011

IPC-7093-4-12

Figure 4–12 QFN Dual Row Package (top and side views)

Table 4-3 Body Outline and Maximum Terminal Count In regard to terminal layout variations, terminals are defined
Terminal Count by Pitch as even row spacing or odd row spacing as illustrated in
Body Outline 0.65 mm 0.50 mm Figure 4–13.
5.00 x 5.00 36 52 The JEDEC design guide document explains that the
6.00 x 6.00 44 68 tolerance that controls the position of the entire terminal
7.00 x 7.00 60 84 pattern (bbb) with respect to Datum’s A and B cannot
8.00 x 8.00 76 100 exceed 0.10 mm. The center of the tolerance zone for each
9.00 x 9.00 84 116 terminal is defined by the basic dimension “eT” as related to
10.00 x 10.00 100 132
Datum’s A and B.
11.00 x 11.00 108 148 The bilateral profile tolerance (aaa) that controls the posi-
12.00 x 12.00 124 164 tion of the plastic body sides cannot exceed 0.10 mm. The
Maximum terminal counts are centers of the profile zones are defined by the basic
calculated using established formulas. dimensions D and E. Centerline-to-centerline spacing be-
tween two adjacent rows of terminals (eR) is 0.65 mm for
the 0.50 mm pitch terminals and for the 0.65 mm pitch
Depopulation of terminal features is allowed, but only under variation the spacing is specified at 0.75 mm. The nominal
the following conditions: length (L) specified for the metallized terminals (including
lead finish) exposed at the bottom surface of the package
1. Depopulation scheme must be consistent in each quad- is 0.40 mm with a min./max. tolerance of 0.10 mm as
rant of the package. illustrated in Figure 4–14. The minimum separation be-
2. Non-symmetric variations should be broken out as sepa- tween the inner terminal tip and the heat spreader feature
rate mechanical outline variations, including depopula- and or between the terminals at the package corners is
tion graphics. 0.20 mm.

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March 2011 IPC-7093

IPC-7093-4-13

Figure 4–13 Outer and Inner Terminal Layout Variations

Full R (optional)
Symbol Dimensions (mm.)

eT 0.65 Basic or 0.50 Basic

L eR 0.75 Basic or 0.65 Basic
L 0.30 min. — 0.40 max.
eR
b 0.18 min. — 0.30 max.

eT
IPC-7093-4-14

Figure 4–14 Two Row Terminal Layout

The tolerance that controls the position of the optional

exposed metal heat spreader feature is positioned so that the
center of the tolerance zone will be the datums defined by
the centerlines of the package body. Because the die element
is mounted to the inside surface of the heat spreader,
thermal transfer of any heat generated by the die can be
effectively transferred onto the surface of the host circuit
structure. Although the dimple detail on the top surface of
the mold compound clearly identifies the orientation of the
device, the addition of a small chamfer or notch feature on
the exposed die attach pad (illustrated in Figure 4–15)
further assists in confirming the location of the A1 and B1
IPC-7093-4-15
terminal.
Figure 4–15 The Notch Feature on the Exposed Die Attach
4.2.5 JEDEC Publication 95 Design Guide 4.19 JEDEC Pad Confirms Package Orientation with Reference to the A1
defines this package family as a ‘Plastic Quad No-Lead and B1 Terminals
(QFN)’ having staggered or inline multi-row terminals.
Typical of the preceding package configurations, this QFN be laminate based or plastic molded leadframe-based. The
family is classified as a plastic semiconductor package with primary difference of this variation from the two previous
metallized terminals located along the edges of the bottom guidelines is that this guideline details the requirements for
surface of the package body. This design guide furnishes the square or rectangular contact terminal features arranged in 2
primary outline features of the family of packaging that may or 3 rows typical of those shown in Figure 4–16.

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IPC-7093 March 2011

tolerance that controls the position of the entire terminal

pattern with respect to Datum’s A and B is 0.10 mm for
the 0.65 mm and 0.50 mm pitch package and is reduced to
0.07 mm for the 0.40 mm pitch package variation. The
center of the tolerance zone for each terminal is defined by
the basic dimension ‘e’ as related to Datum’s A and B.

The overall package outline dimensions are defined as ‘D’

for package width and ‘E’ for package length. The current
document specifies that the ‘D and E’ dimensions be in
increments of 0.50 mm ranging from 4 mm to 19 mm.
Outlines with ‘D’ and ‘E’ increments less than 0.50 mm
should be registered as “stand-alone’’ outlines. These out-
lines should use as many of the algorithms and dimensions
(stated in this guide) as possible to ensure predictability in
IPC-7093-4-16
manufacturing. The overall package height is not specifi-
Figure 4–16 Two and Three Row QFN Package Examples cally defined but the guideline recommends a profile no
higher than 1.0 mm where the overall component height is
By design the package terminals are flush with the bottom measured from the seating plane (surface of the host
surface of the plastic package body, so the packages are
substrate). The unilateral tolerance located above the seating
considered to be “BTC” or “no-lead” and, as noted, the
plane wherein the bottom surface of all terminals must be
package has 2 rows or 3 rows of terminals on all four edges
located is 0.08 mm. This tolerance is commonly known as
of the bottom surface of the package.
the “coplanarity” of the package terminals. The tolerance
The package can have a square or a rectangular body as well which controls the top surface of the package is nominally
as symmetric or asymmetric terminal patterns as detailed in 0.10 mm. The basic QFN package outline shown in Figure
Figure 4–17 and Figure 4–18. 4–20 defines the basic outline features referenced above for
Three contact pitch (e) variations are specified; 0.65 mm, ‘D’ (package width) and ‘E’ (package length) and ‘A’,
0.50 mm and 0.40 mm. The dimensions defined for the overall package height.
terminals are adjusted to allow clearance at various pitch
Terminal A1 identifier must be located within the zone
conditions and the supplier has the option of selecting
indicated on the outline drawing. Topside terminal A1
uniform or non-uniform ‘b’ and ‘L’ dimensions to provide a
indicator may be a molded or marked feature. Optional
square or rectangular geometry. (See Figure 4–19).
indicator on bottom surface may be a molded, marked, or
The tolerance that controls the position of the terminals to metallized feature. See Figure 4–21 for examples of pin 1
each other (e) is nominally defined at 0.05 mm. The indicator.

Even Terminal Format Odd Terminal Format

IPC-7093-4-17

Figure 4–17 Basic Two Row Terminal Layout Variations

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March 2011 IPC-7093

Even Terminal Format Odd Terminal Format

IPC-7093-4-18

Figure 4–18 Basic Three Row Terminal Layout Variations

e Contact Dimensions (mm.)

Pitch (e) b L
min. nom. max. min. nom. max.
L 0.65 0.35 0.40 0.45 0.35 0.40 0.45
0.50 0.25 0.30 0.35 0.25 0.30 0.35
1
0.50 0.20 0.25 0.30 0.25 0.30 0.35
0.40 0.15 0.20 0.25 0.20 0.25 0.30
b
1 Optional variation to expand the clearance
between terminal features
IPC-7093-4-19

Figure 4–19 Contact Geometry Variations

4.3 Detailed Description of QFN and SON (DFN) Pack-

ages

4.3.1 Manufacturing Methods BTC package configura-

tions are frequently used for individual semiconductor chips
and less frequently to package multiple components. See
Figure 4–22.
The outline dimensions of the BTC package family ranges
between 2.0 mm x 2.0 mm having only four terminals to
12 mm x 12 mm outline with as many as 108 terminals. The
package height may vary between 0.4 mm to 1.5 mm,
however, a 0.8 mm to 1.0 mm package height are more
common. There are a number of terminal spacing (pitch)
variations allowed on the BTC packages with 0.4 mm,
0.5 mm and 0.65 mm being the most common.
QFNs and SONs (DFN) are most commonly assembled on
IPC-7093-4-20
an etched or stamped metal leadframe that is 0.150 mm to
0.200 mm thick. The die attach side of a multiple site
Figure 4–20 Basic QFN Package Outline Drawing leadframe panel is shown in Figure 4–23 and the bottom
side of the panel is shown in Figure 4–24.

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IPC-7093 March 2011

IPC-7093-4-21

Figure 4–21 Pin 1 Location Option

IPC-7093-4-23

Figure 4–23 Typical Die Attach Side Leadframe with Ni-

PdAu Finish for QFNs

IPC-7093-4-24
IPC-7093-4-22
Figure 4–24 Typical Solder Pad Side of QFN Panel for with
Figure 4–22 BTC Multiple Package Configurations Tape over the Leadframe

The leadframe panel shown in Figure 4–23 and Figure 4–24

drawings and sketches in section 4. The major purpose of
measures 75 mm x 300 mm and includes four sections each
the undercuts is to provide mechanical interlocking of the
having 42, 7.0 mm x 7.0 mm QFN sites. The bottom, or
terminal side of the leadframe panel will be covered with a mold compound and leads to increase the mechanical
protective film that prevents mold compound from en- strength.
croaching onto the terminals surface during the overmold
In preparation for package assembly and to accommodate
process.
the eventual mounting of the BTC package, the leadframes
Leadframes are usually made from rolled sheet copper are electroplated with alloys compatible with both wire-
etched from both sides with slightly different patterns. The bond processing and reflow solder soldering (a NiPdAu
difference in etch pattern gives the undercut evident in the alloy composition is most common).

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March 2011 IPC-7093

Another option is to spot plate the wire-bond sites with a

silver alloy leaving the remaining area of the copper based
leadframe without plating until after the overmold process.
The remaining exposed contact and thermal pad features on
the panel are plated with a tin-alloy finish for solder
attachment.
The BTC package assembly process may vary somewhat
from one supplier to another, but, the basic sequence of
assembly for the product described above will follow the IPC-7093-4-26
flow of the diagram detailed in Figure 4–25.
Figure 4–26 Overmolded Leadframe Configuration
An overmolded version of the leadframe in Figure 4–23 is
shown in Figure 4–26. The example is a four section equipment required for punch singulation, the technique is
overmolded array right after it was removed from the mold. typically reserved for very high volume production.
The dark colored areas are the molding compound that form
The process flow for Punch Singulated QFNs is illustrated
the 4 arrays, each of which measures approximately 45 mm
in Figure 4–27.
x 55 mm. The dark areas around the periphery and between
the molded arrays are mold compound that fill slots in the The mold design for the punch singulation method is more
leadframe. complex and expensive than those used for saw singulation.
Punch singulation requires a mold with a cavity for each
Following the overmold process the individual devices will
part so that the web of the leadframe remains exposed
be marked and singulated from the panel format. The most
between individual parts. This web is punched out in a
common method for singulation of BTC devices is a
single stroke with a die that matches the part.
precision saw. An alternate method uses a punch press
operation. For this method the mold design will be pre- Both saw singulation and punch singulation leave bare
segmented at each device site to provide access for the copper edges on the leads where they are cut from the
die-punch. Due to the high cost of tooling and additional leadframe. These bare edges can serve as a surface for a

Color Key
Die Attach
Material Parts &
Die Materials

Assembly
Dispense Process
Place Cure Die Attach at 200 ºC
Leadframe Die Attach
Die Material 150 ºC
Material Assembly
Process
at 150 ºC

Molding Compound Finished

Part

Gold Wire Place Transfer Remove

Ball Bond Leadframe Mold 150 ºC Array from
150 ºC In Mold Leadframe Mold

Saw Package Finished

Mark Singulate Test & Bin
Part for Shipment
IPC-7093-4-25

Figure 4–25 QFN Fabrication with Saw Singulation

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IPC-7093 March 2011

Color Key
Die Attach
Material Parts &
Die Materials

Assembly
Dispense Process
Place Cure Die Attach at 200 ºC
Leadframe Die Attach
Die Material 150 ºC
Material Assembly
Process
at 150 ºC

Molding Compound Finished

Part

Gold Wire Place Transfer Remove

Ball Bond Leadframe Mold 150 ºC Array from
150 ºC In Cavity Mold Leadframe Mold

Punch Package Finished

Mark Singulate Test & Bin
Part for Shipment
IPC-7093-4-27

Figure 4–27 QFN Fabrication with Punch Singulation

solder fillet if the solder system will wet the bare copper. A second characteristic of punch singulated devices evident
Some users may also require BTC suppliers to take in the image on the left of Figure 4–28 is the small
additional measures, after singulation, to preserve flank leadframe extension beyond the edge of the molding com-
solderability. These measures are intended to allow users to pound to provide space to prevent the die from cutting the
rely on toe fillets formed along the BTC flanks as an aid to mold compound.
reliable assembly inspection.
The sketch on the right of Figure 4–28 shows the saw
The illustrations in Figure 4–28 show the detailed differ- singulated cross section that lacks both draft and the
ences that result using punch singulation and saw singula- extended lead.
tion.
Figure 4–28 also shows the 3 common wire bond options:
While punch singulated packages are individually punched
from molded strip during final assembly, the saw singulated • bonds between the die and the finger leads
package are assembled in array format and separated into • bonds between the die and the die attach pad (so called
individual components during the final sawing operation.
“down bonds”)
The image on the left of Figure 4–28 is punch singulated • bonds from the die pad to the finger leads
from an array of individually molded sites. The mold cavity
walls have some draft shown in the sketch to facilitate These wire bond options are used to make the required
removing the molded parts from the cavities. electrical connections.

Die Die

Punch-press Singulation Saw-cut Singulation

IPC-7093-4-28

Figure 4–28 Comparing Punch-Press and Saw-Cut Singulation and Illustrating Wire Bond Options

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March 2011 IPC-7093

Saw singulated packages are further divided into two of the package, sometimes severe enough to result in
options as illustrated in Figure 4–29: the no-pullback (full) shorting, especially during SMT solder reflow
lead package, and the pullback lead package. While the full • burrs from the sawing or punching process interfering
lead package has the whole thickness of the lead exposed on with the planarity of the part or the geometry of the
the package sides, the lead pullback package has a bottom solder joint
half etch leadframe, resulting in only the top half of the lead • inadequate tolerance control of the part dimensions,
thickness exposed to the sides of the package. especially the width and length, resulting in a poor fit to
test sockets
• incorrect marking of pin 1
Table 4–4 shows some examples of common leadframe
package defects. The table provides three levels of defects
and highlights the possible causes.
The plating characteristics are an important part of the
leadframe BTC construction. Attachment both within the
component package as well as the external terminations
must be carefully addressed for the most robust joint
structure. Table 4–5 provides some examples of the poten-
Pullback No-Pullback tial defects.
IPC-7093-4-29

Figure 4–29 Example of Half Etch Pullback Contact and 4.3.3 Marking Alternatives Common methods of mark-
Full Etch No-Pullback Perimeter Contact Configurations ing BTC packages are:
• Pad printing with a high contrast ink, usually white
The pullback approach is only viable when the package is • Laser marking to give finer features that often has low
built into an etched leadframe. The pullback approach contrast
provides better capture of the lead and thus makes the • Laser marking using an ink that provides good contrast
package stronger. One disadvantage is that some test sockets as well as fine features
may not be designed to make contact in this area.
4.3.4 Materials Used Leadframes are most commonly
A more important disadvantage of the pullback configura- made of copper. A variety of molding compounds are used.
tion is that the solder joint is not visible making inspection Which is used depends not only on the part and components
more difficult. The mold compound blocking access to the within the QFN-SON, but the mold design and molding
‘pullback’ terminal makes it impossible to form a solder machine. These molding compounds are formulated to have
fillet on the outer edge of the device. While the unplated excellent flow characteristics to ensure fill while minimizing
surface of these edges that result from both the punching wire sweep.
and sawing processes makes solder wetting difficult, the pull
A variety of lead finishes are used. The most common are
back configuration virtually guarantees that a fillet cannot
NiPdAu, and Tin. SnBi is also sometimes used as a plating
form with any soldering process.
finish as is plated solder using other alloys. Table 4–5 shows
some of the plating variations while Figure 4–30 shows the
4.3.2 Types of Defects Common defects that result from thickness relationships of some of the plating combinations.
the fabrication methods described are:
4.3.5 Solderability Testing The solderability testing of
• delamination of the mold compound from the leadframe BTC components should be conducted in accordance with
that sometimes results in wire bonds pulling loose from the IPC-J-STD-002 specification. A number of individual
the leadframe test methods are applicable to the BTC components. Test
• mold compound flash on the leads or die pad that Method S (for tin/lead solder processes) and S1 (for
interferes with soldering, die attach or wire bonding lead-free solder processes) are the most applicable for BTC
surface mount components.
• voids resulting from incomplete mold compound fill
• bond wire sweep in the molding process resulting in 4.4 Custom QFN and SON (DFN) One of the attractive
shorted wires or, less frequently, broken wires features of the leadframe based QFN family of BTC
packages is the relative low cost and minimal time required
• smear of copper during the sawing process along the side
to design and fabricate a custom version. All of the

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IPC-7093 March 2011

Table 4-4 Leadframe Package Defects and Failure Modes

Common Leadframe-Based Package Defects and Failure Modes
Defect/Failure Mode Potential Failure Detection Method Cause
Level 1, within package
Excess water content due to Pop corning, delamina- Hard to detect. Water uptake from environment when
inadequate storage or drying tion during solder re- parts are not stored or dried properly
flow.
Detrimental package com- Corrosion, delamination Ultrasonic Poor molding control or poor handling
pound voids
Cracked package Mechanical and/or Visual examination, die Excess mechanical bending of pack-
electrical failure penetrant age, mold compound knit line
Lead to compound failure Lead falling off or Visual examination Molding, sawing or punching process
potentially resulting in lead breaking wire bond defect
fall out
Paddle to die delamination Overheating, wire Ultrasonic, decapsulation Poor wetting, incorrect cure
break, die cracking
Broken wires Electrical open X-ray Wire bonding process control error,
mold compound sweep
Lifted stitch/broken heel to Electrical open X-ray, electrical test Wire bond process control error, sur-
leadframe face contamination, inadequate plating
Lifted wire bond balls from die Electrical open X-ray, electrical test Wire bond process control error, sur-
face contamination, die metallization
error
Shorted wire Electrical short X-ray, electrical test Mold wire sweep, or wire bond pro-
cess control
Level 2, outside of package
Non-wetting lead surfaces Open connection Visual, X-ray Oxidized surfaces, plating contamina-
tion or incorrect thickness
Out of dimensional spec Poor contact in test Measurement Molding (thickness) or singulation
socket
Lead smear of copper Shorting of leads Visual Sawing conditions
Inadequate flatness Open joints Visual Molding or singulation method
Burrs Electrical shorts Visual Singulation process
Dimples on pads cause by test Void in solder joint and Visual Aggressive probing breaks through
socket contact potential open connec- plating resulting in non-wetting spot
tion and void in final joint
Marking defects Wrong part or unknown Visual Poor marking, handling damage
part
Level 3 package to board
Voiding in joints Long term electrical X-ray Solder paste or reflow process
open
Non-wetting of pads Electrical open X-ray, electrical test Part contamination or solder process
Bridging under package Electrical short X-ray, electrical test Part or board contamination, solder
process
Liftoff of package from PCB Electrical open, less Visual Too much solder paste
due to floating on the solder shock resistance
Sinking of package into solder Electrical short X-ray Part too heavy for reflow conditions,
due to its weight causing detri- paste or solder rheology at tempera-
mental solder displacement ture
resulting in bridges and/or
poor joints.

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March 2011 IPC-7093

Table 4-5 Plating Systems Used on Metal Leadframes

Plating types Characteristic Descriptions

Tin plate 10 µm min. Most common

NiPdAu 0.508 µm, 0.013 µm and 0.005 µm Often called the Samsung finish 0.4 mm pitch are all NiPdAu. Larger are other
systems
Tin finish with Ag on bond sites Post mold tin plate of bare copper
NiPdAu 1.02 µm, 0.08 µm and 0.010 µm Often called the Shinko finish 0.4 mm pitch are all NiPdAu. Larger are other
systems

IPC-7093-4-30

Figure 4–30 Plating Layer Construction Comparison

processes, materials, etc., are described above for QFNs. This leadframe is not square but measures 5 mm x 7 mm
The major method of customizing is modifying the lead- with 7 leads on one side and 9 on the other. In addition,
frame. Figure 4–31 shows several modifications built into leads on two sides are tied directly to the die paddle.
one leadframe.
Another alternative is to split the thermal die pad. That
option allows some thermal isolation of individual die.

4.5 Detailed Description of LGA, QFN and SON (DFN)

Substrate-Based Packages

4.5.1 Manufacturing Methods for Substrate-Based

Packages Substrate-based packages are similar to lead-
frame-based packages in many ways. Many devices that can
be packaged using the leadframe approach could also be
packaged using a substrate. For reasons having to do with
cost and reliability, substrates are used as an alternative to
leadframes in only small volume.
Substrates are sometimes used for individual die but more
commonly to interconnect and package multiple active and
passive components. Many of these assemblies are SiPs
(system in a package) per the ITRS definition implying at
IPC-7093-4-31
least 2 different active components. Others that do not
Figure 4–31 Detailed View of a Custom Site for a QFN comply with the strict SiP definition are simply high density

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IPC-7093 March 2011

electronic assemblies. The density is increased by using • voids resulting from complex internal geometry that is
direct die attach, stacking die, flip chip assembly, 0201 and hard to fill or from mold compound that does not flow for
01005 SMT parts. some reason
The substrates used for BTC devices are essentially multi- • wire sweep in the molding process resulting in shorted
layer circuit boards, often built with BT dielectric and wires or, less frequently, broken wires
frequently implemented utilizing HDI technology. Figures • sawing induced defects such as delamination of the mold
4–32 and 4–33 show both sides of a typical substrate for a compound from the substrate
BTC part. • warpage from the molding process or inherent in the
substrate that interferes with the planarity of the part or
the geometry of the solder joint
• movement or sweeping off of SMT parts due to excessive
temperature rise during the molding process
• excess water uptake by the part during storage resulting
in delamination during solder reflow
Table 4–6 shows some examples of common substrate
IPC-7093-4-32
based package defects. The table provides three levels of
Figure 4–32 Bottom View of Land Grid Array Printed Board defect potential and highlights the possible causes.

4.5.3 Marking Alternatives Common methods of mark-

ing these packages are the same as those used with QFNs
and SONs (DFN):
1. Pad printing with a high contrast ink, usually white
2. Laser marking to give finer features but often furnish a
IPC-7093-4-33
low contrast image
3. Laser marking onto a printed ink background provides
Figure 4–33 Top View of Land Grid Array Printed Board
good contrast as well as fine features

The substrate measures ~75 mm x 300 mm. This bottom

4.5.4 Materials Used Substrates are commonly built us-
surface of the substrate is eventually soldered to the circuit
ing standard circuit board fabrication methods. Many of the
board. Those sites with an “X” were found to be defective
substrates incorporate HDI technology to increase density.
during board test and will not be populated. This particular
Four-layer boards are common.
substrate does not have a large pad in the center as many
QFNs do because the final package does not dissipate a lot The most common dielectrics are BT and FR-4.
of heat so a good thermal connection to the circuit board on A variety of board finishes are used depending on choice of
which the BTC device is attached is not required. the designers working with both the substrate fabricator and
Figure 4–33 shows the top surface of the substrate where the assembly house. Since most BTC substrate based
parts are placed. 0402 down to 01005 size SMT parts are packages incorporate some wire bonded die, gold finish on
commonly used. Die interconnect is either wire bond or flip at least the component surface of the substrate is common.
chip, often with multiple die. 25 parts in a 7 mm x 7 mm A typical system is NiPd with an Au flash that is wire
size is common. Many of these assemblies are Systems in a bondable, solderable and avoids the risk of solder embrittle-
Package (SiP). ment.
A typical process flow to assemble a BTC using a substrate A variety of molding compounds are used. The choice
like that above is shown in Figure 4–34. depends not only on the part and components within the
QFN-SON, but the mold design and molding machine.
4.5.2 Types of Defects Some common defects that result These molding compounds are formulated to have excellent
from the BTC on substrate fabrication methods described flow characteristics to ensure fill while minimizing wire
are: sweep. They are also formulated to have a TCE that is close
to copper and to comply with environmental requirements.
• delamination of the mold compound from the substrate
that results in pulling parts off of the substrate 4.6 Description of Commercial Variations Many de-
• mold compound flash on the leads that interferes with tailed variations of the QFN and SON (DFN) type of BTC
soldering have been developed. These are now marketed under a

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March 2011 IPC-7093

Color Key
Parts &
Solder SMT
Materials
Paste Parts
Assembly
Process
Stencil Deposit Place SMT Reflow Water at 200 ºC
Circuit Board
Solder Paste Parts Solder Wash
Assembly
Process
at 150 ºC
Wire Bond Flip Chip Flux Place Reflow
Solder Assembly
Die Die Die Die
Process
at 260 ºC
Dispense Gold Wire Place
Place Cure Die Attach Finished
Die Attach Ball Bond Leadframe
Die Material 150 ºC Part
Material 150 ºC In Mold

Molding Compound

Transfer Remove
Saw Test & Package Finished
Mold 150 ºC Array from Mark
Singulate Bin Part for Shipment
Leadframe Mold

IPC-7093-4-34

Figure 4–34 BTC Fabrication on a Substrate with Saw Singulation

broad number of trademarks and acronyms by various enhanced performance, MLPs have the bottom exposed
companies, a few of which are described below. thermal feature visible in Figure 4–36.

4.6.1 Detailed Description of MLF®, MLP, and MLFP™

Carsem’s MLP (Micro Leadframe Package) is a family of
Components JEDEC compliant QFN plastic packages. This near CSP
package is available in three versions. The Quad (MLPQ™)
4.6.1.1 Part Descriptions The microleadframe (MLF®), has 4 sides of I/Os with a body size range of 3 x 3 mm with
micro leadframe package (MLP) and micro leadframe 8 I/Os to 9 x 9 mm with 64 I/Os and body thickness options
plastic package (MLFP™) are all near CSP size plastic of 0.9 mm, 0.75 mm, plus the Ultra-Thin that is only 0.5 mm
encapsulated quad contact configured no-lead (QFN) pack- thick. The Micro (MLPM™) has 2 sides of I/Os with a body
ages with a copper lead-frame substrate. This package size range of 2 x 2 mm with 3 I/Os to 3 x 3 mm with 10 I/Os
family uses perimeter lands on the bottom of the package to and a thickness of 0.9 mm. The Dual (MLPD™) versions
provide electrical contact to the PCB. Typical of all QFN are designed to provide a footprint compatible replacement
packaging, these variations offer a thermal enhancement by for SOIC, SSOP, TSSOP and MSOP packages. Typical of
having the die attach paddle exposed on the bottom of the most QFN and SON devices, MLPs have an exposed die
package surface to provide an efficient heat path when attach pad for improved thermal performance. However, the
soldered directly to the PCB as exhibited in Figure 4–35. company also offers a non-exposed pad option they refer to
as COL™ (Chip On Lead), FCOL™ and other special
Fairchild and Carsem’s MLP (Micro Leadframe Package) applications.
are near chip-size plastic encased packages that are JEDEC
MO-220 and MO-229 compliant QFN and SON (DFN) The Micro Leadframe Plastic Package (MLFP) from Intersil
plastic packages. The high-density lead-frame package de- is also a JEDEC standard package outline (EIA/JEDEC
sign is furnished with RoHS compliant lead-free plating and Publication 95, MO-220). Figure 4–37 illustrates a section
meets the most stringent moisture sensitivity level (MSL)1. view of a 16-Lead MLFP package. The die pad and
To provide even greater utilization of package space and perimeter I/O pads are fabricated from a planar copper

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IPC-7093 March 2011

Table 4-6 Substrate Based Package Defects and Failure Modes

Substrate Based Package Defects and Failure Modes
Defect/Failure Mode Potential Failure Detection method Cause

Level 1, within package

Excess water content due to Pop corning, delamination Hard to detect Water uptake from environment
inadequate storage or drying during solder reflow when parts are not stored or dried
properly
Detrimental package com- Corrosion, delamination Ultrasonic Poor molding control
pound voids
Cracked package Mechanical and/or electrical Ultrasonic Poor molding control or poor han-
failure dling
Substrate to compound failure Broken connection, corrosion Visual examination, die Molding or sawing process defect
from water ingress penetrant
Part to substrate delamination Open circuit, die overheating, Ultrasonic, decapsula- Inadequate mold compound flow,
bond wire break, part cracking tion, cross sectioning poor wetting of parts and sub-
strate, surface contamination
Broken wire bonds Electrical open X-ray Wire bonding process control
error, mold compound sweep
Lifted wire bond stitch/broken Electrical open X-ray, electrical test Wire bond process control error,
heel to substrate surface contamination, inad-
equate plating
Lifted wire bond ball from die Electrical open X-ray, electrical test Wire bond process control error,
surface contamination, die metalli-
zation error
Shorted wire Electrical short X-ray, electrical test Mold wire sweep, or wire bond
process control
Level 2, outside of package
Non-wetting lead surfaces Open connection Visual, X-ray Oxidized surfaces, plating con-
tamination or thickness
Out of dimensional spec Poor contact in test socket Measurement Molding (thickness) or singulation
Lead smear of copper Shorting of leads Visual Sawing conditions
Inadequate flatness Open joints Visual Substrate defect, Molding or
singulation method
Burrs Electrical shorts Visual Singulation process
Dimples on pads cause by test Void in solder joint and poten- Visual Aggressive probing breaks
socket contact tial open connection through plating resulting in non-
wetting spot and void in final joint
Marking defects Wrong part or unknown part Visual Poor marking, handling damage
Level 3, package to board
Voiding in joints Long term electrical open X-ray Solder paste or reflow process
Non-wetting of pads Electrical open X-ray, electrical test Part contamination or solder
process
Bridging under package Electrical short X-ray, electrical test Part or board contamination,
solder process
Liftoff of package from PCB Electrical open, less shock Visual, cross-section Too much solder paste
due to floating on the solder resistance
Sinking of package into solder Electrical short X-ray, cross section Part too heavy for reflow condi-
due to its weight causing detri- tions, paste or solder rheology
mental solder displacement at temperature
resulting in bridges and/or
poor joints.

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March 2011 IPC-7093

addition to furnishing a small outline the package has

minimal mass and can be processed using the existing
package assembly infrastructure

4.6.1.2 Tolerances Dimensions and tolerances conform

to ANSI Y14.5M, all dimensions are in millimeters and
angles are in degrees. Figure 4–38 represents the basic QFN
package outline
The QFN family detailed in JEDEC registered outline
MO-220 ranges in size from 2.0 mm x 2.0 mm to 12.0 mm
x 12.0 mm graduating in 1.0 mm increments. For each
outline there are two lead spacing formats, odd and even.
The image shown in Figure 4–39 represents the even row
variation.
IPC-7093-4-35
There are five contact pitch variations allowed for the QFN;
®
Figure 4–35 Amkor’s 28 I/O MicroLeadFrame Package 1.0 mm, 0.8 mm, 0.65 mm, 0.50 mm and 0.40 mm. The
length (L) and width of the contact can vary significantly
between suppliers. Although square outlines are most com-
mon, rectangular outlines are allowed. The examples shown
in Table 4–7 are represent a number of square and rectan-
gular QFN package outlines currently available from a
prominent package assembly service provider.

4.6.1.3 Material Specification QFN packages are avail-

able in several alloy finishes: post plated SnPb, Matte Sn,
SnBi, pre-plated NiPd with flash of Au. Surface mount
studies on parts plated with NiPd and Matte Sn show no
IPC-7093-4-36
significant difference compared to SnPb finish parts. The
following are typical of the basic materials used for QFN
Figure 4-36 Fairchild’s MLP is a Thermally Enhanced SON package assembly:
Developed for Power Switch Technology
• Die thickness: 250 µm ± 50 µm (thinner for special
applications)
• Plating: Sn/Pb, Matte Sn, SnBi, NiPd (flash Au)
• Marking: Laser
• Lead-frame: Copper Alloy, Dual gauge
• Die attach: Conductive Epoxy
• Bond Wire: 25 µm low loop
• Mold compound: Pb-free/Green capable

4.6.2 Detailed Description of LLC™ and LFCSP™

IPC-7093-4-37 Components The LLC from Analog Devices and LFCSP

Figure 4–37 Intersil’s Quad No-lead Micro Leadframe Plas-

from National Semiconductor are near chip scale plastic
tic Package (MLFP) encapsulated wire bond QFN packages with a copper
leadframe substrate in a BTC package format.

lead-frame substrate. This family is described as plastic

4.6.2.1 Part Description The LLP and LFCSP package
encapsulated device with the bottom of the die attach pad
is available in two thicknesses variations. The 0.8 mm is the
and contacts.
most prevalent thickness but the package is selectively
The die pad and perimeter I/O pads are fabricated from a available in a lower 0.6 mm profile thickness as well.
planar copper lead-frame substrate. This is encapsulated in Perimeter input/output pads are located on the outside edges
plastic with the bottom of the die attach pad (DAP) and I/O of the package. Electrical contact to the printed circuit board
pads exposed to create a very small package outline. In (PCB) is made by soldering the perimeter pads and exposed

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IPC-7093 March 2011

0.60
MAX.

0.60 (DATUM B)
MAX.

CHAMFERED CORNER
OPTIONAL 4X

SEE DETAIL B

(DATUM A)
5

6
IPC-7093-4-38

Figure 4–38 JEDEC MO-220 Package Outline

Terminal contacts:
(R IS OPTIONAL)
• The contact pads (or solder pad) are located peripherally
in single row format depending on the specific number of
pins and body size.
L
• For certain specific applications the packages are incor-
5 L1
porated with common power and/or ground pins
• All contacts are plated with matte tin solder for ease of
e/2
TERMINAL TIP surface mount processing.
e
IPC-7093-4-39 The bottom termination QFN package family (see JEDEC
MO-220) furnishes enhanced chip speed, reduced thermal
Figure 4–39 QFN Contact Design
impedance, and, because of its small outline, minimizes the
printed circuit board area required for mounting. The small
paddle on the bottom surface of the package to the PCB. size and very low profile make this package, shown in
Heat is efficiently conducted from the package by soldering Figure 4–41, ideal for high density PCBs used in small-scale
the exposed thermal paddle to the PCB as illustrated in electronic applications such as cellular phones, pagers, and
Figure 4–40. handheld PDAs.

Stable electrical ground connections are provided through In addition to their small package outline and low profile the
down bonds and through conductive die attach material. LLP and LFCSP have a low thermal resistance and reduced
Wire bonding is provided using gold wires. Perimeter and electrical parasitic.
thermal pad finish is plated as 100% Sn (Sn/Pb is available
as well). Packages are punched or sawed from a molded 4.6.2.2 Package Tolerances This JEDEC design guide-
strip during final assembly. Half-etching of the leadframe line standard for this package family applies to packages
provides mold compound locking features for the perimeter with optional thermal enhancements as well as various
pads and die thermal paddle. This package is currently height profiles and pitches. This package has terminals on
characterized as moisture sensitivity level (MSL) 3 (see all four edges of the bottom surface of the package. The
IPC/JEDEC J-STD-020 for MSL levels). LLC and LFCSP can have either a square or a rectangular

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March 2011 IPC-7093

Table 4-7 Typical Package Outline and I/O for QFN

QFN lead counts DFN/SON lead counts Dual Row lead counts
Body Size (mm) 0.8, 0.65, 0.5, 0.4 mm pitch 1.27, 0.95, 0.5 mm pitch 0.5 mm pitch

< 2 x 2 (saw only) - 4/6/8 -

2x3 - 6/8 -
3x3 4 / 8 / 10 / 12 / 16 8 / 10 -
4x4 12 / 16 / 20 / 24 / 28 - -
5x5 16 / 20 / 28 / 32 / 36 - 44 / 52
6x5 36 8 -
6x6 20 / 28 / 36 / 40 / 48 - 60/68
7x7 28 / 32 / 44 / 48 / 56 - 76 / 84
8x8 32 / 40 / 52 / 56 / 68 - 92 / 100
9x9 36 / 44 / 60 / 64 / 76 - 108 / 116
10 x 10 44 / 52 / 68 / 72 / 88 - 124 / 132
11 x 11 - - 140 / 148
12 x 12 48 / 60 / 84 / 88 / 100 - 156 / 164

through 12.00 mm. The outline detail shown in Figure 4–42

GOLD MOLDING illustrates the primary dimensions used when developing
WIRE COMPOUND
DIE PAD the land pattern and thermal paddle geometries.
The width of the metallized terminals (including lead finish)
exposed at the bottom surface of the package is detailed in
Table 4–8.

EXPOSED
For component tolerances and profile tolerances usually
THERMAL PADDLE given in the package outline drawings are converted into
maximum material condition (MMC) and least material
PIN 1 condition (LMC) based tolerances.

PERIMETER
4.6.2.3 Material Specifications In compliance with
I/O PADS
(LEADS) RoHS and WEEE, companies modified molding compounds
and, in some cases, die attach materials. In addition, there
IPC-7093-4-40 was strong support from users for converting mold com-
Figure 4–40 Analog Devices LFCSP™ (Leadframe Chip- pounds to more robust versions so that packages are
Scale Package) compatible with higher temperatures required for reflow
soldering lead-free alloys. The data supplied in Table 4–9 is
typical of the device packaging materials listed in a ‘mate-
rials declaration’ form for the LLC and LFCSP.
The change to RoHS compliant elements provided base
material sets that demonstrate capability to meet elevated
reflow conditions of 255°C (+5/-0°C) for lead-free reflow.
Additionally, most companies are offering lead-free lead
finish on all plastic encased LFCSP packages from
Sn85Pb15 to 100% Sn (tin plating) to eliminate Pb from
IPC-7093-4-41 these package types.
Figure 4–41 National Semiconductor LLP™ (Leadless
Package)
Other material elements:
body outline as well as either symmetric or asymmetric
Internal leadframe plating Ag (silver)
terminal patterns. Versions of the package may also have
External leadframe plating Sn (tin)
terminals placed in the corners at 45 degrees to neighboring
Bond wires Au (gold)
leads. The basic dimensions for the package outline are
Die element Si (silicon)
shown in increments of 0.50 mm ranging from 1.00 mm

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IPC-7093 March 2011

Table 4-9 Basic Material Elements

D for the LLC and LFCSP Devices
BSC
Category Materials Content

Mold com- SiO2 Fillers 86.9%

PIN 1
INDICATOR pounds Epoxy and Phenol Resins 12.8%
Carbon Black 0.3%
Die attach Ag (silver) 73.4%
TOP E material Epoxy Resin 18.35%
VIEW BSC Metal Oxide 2.75%
Curing Agents 2.75%
Gamma Butyrolacetone 2.75%
Leadframe Cu (copper) 97.5%
Fe (Iron) 2.35%
Zn (zinc) 0.12%
P (phosphorus) 0.03%
PITCH
PIN 1 tray carriers (Figure 4–43), or in tape and reel. SON (DFN)
INDICATOR
37 48 devices are commonly shipped in tubes or tape and reel.
36 1

EXPOSED
PAD E2
(BOTTOM VIEW)

L 25 12
24 13
0.25 MIN
5.50 IPC-7093-4-43
REF
Figure 4–43 JEDEC Tray Carrier Format
A The overall dimensions of the JEDEC shipping and han-
dling tray carrier are 135.9 mm x 322.6 mm with compo-
Source: Analog Devices nents arranged in a column and row format. The matrix of
the pocket pattern is fixed to a standard formula based on
IPC-7093-4-42
the outline of the semiconductor package. Although the
Figure 4–42 Typical LLC and LFCSP Outline Detail components mounted in the carrier are shipped with a ‘dry
pack’ wrapping, the plastic material used to mold the carrier
Table 4-8 Contact Pitch and Width Variations
must withstand thermal exposure typical of that required for
Terminal Dimensions
‘bake-out’ of components that are exposed to ambient
Contact Pitch Minimum Nominal Maximum
conditions and prone to moisture retention. For more
0.65 0.25 0.30 0.35 detailed information on the carrier tray specification see
0.50 0.18 0.25 0.30 JEDEC Publication 95 Design Guide 4.10.
0.40 0.15 0.20 0.25 All of these package delivery systems use ESD safe
materials.
Although no change may be made to a component’s part The environmental conditions these devices are designed to
number, products converted to lead-free will be identified tolerate are:
on the outer packaging label, and if space permits, a Pb-free • Moisture sensitivity JEDEC Level 1* characterization
symbol will be marked on converted devices. 85°C/85%, 168 hours
• HAST 130°C/85% RH, 96 hours
4.7 Packaging and Handling BTC parts are shipped in a
variety of standard configurations designed for automated • Temp cycle -65/+150°C, 1000 cycles
assembly system efficiency. QFN products and BTC devices • Temp/Humidity 85°C/85% RH, 1000 hours
built on substrates are shipped in tubes, stackable JEDEC • High temp storage 150°C, 1000 hours

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5 MOUNTING STRUCTURES approaches to creating multilayer circuit product. The tra-

ditional multilayer is created by printing and etching thin
This section provides information on the various materials
layers of copper clad substrates and laminating them into a
and concepts used to produce a mounting structure onto
monolithic structure which can be drilled and plated so as to
which the BTC may be placed and properly attached. Also
make connection between the layers where required.
included in addition to the physical requirements will be
electrical, thermal and construction detail intended to pro- More recently, however, alternative structures have been
vide a clear correlation with the BTC design and assembly developed to address the higher density and routing diffi-
process. Some new techniques for providing interconnec- culties associated with BTCs. These newer structures em-
tion concepts will be explored as well as a method for ploy a variety of different approaches to create suitable
embedding the BTC into the mounting structure. multilayer structures. The new structures are referred to as
High Density Interconnect (HDI) printed boards and include
5.1 Types of Mounting Structures PCBs and other simi- build-up multilayers, sequential multilayers and co-
lar types of interconnection platforms serve as the mounting laminated multilayers.
structures for BTCs and other components. There are a A key feature of these structures is their use of very small
variety of alternative mounting structures available which vias. The term microvias has been applied to describe these
serve BTC needs as interconnection substrates for electronic miniscule interconnections. A typical microvia is less than
assemblies. These structures employ a wide range of mate- 150 µm in diameter and has a capture land (where the via
rials, both organic and inorganic and have a wide range of starts) and a smaller target land (where the via ends). Figure
physical properties. Materials choice is normally made 5–1 shows one of the most popular HDI structures, although
based on cost/performance needs of the finished product. methods of stacking the micro vias have also been devel-
oped as shown in IPC-2226.
5.1.1 Organic Resin Systems Organic substrates are the
most commonly used in the construction of electronic
interconnection structures. There is a well-established
worldwide manufacturing base for this type of product. As
a result of the large manufacturing base, this type of
interconnection structure has the lowest cost among the
competing technologies. Organic materials have intrinsic
beneficial electrical properties. Most notable is a relatively
IPC-7093-5-1
low dielectric constant on average which can be made much
lower by the proper choice of resin and reinforcement. Figure 5-1 Typical Build-Up HDI Platform, 2[4]2 Layer Con-
Organic substrates are commonly reinforced using an ap- figuration
propriate material such as woven glass cloth; however,
5.2 Properties of Mounting Structures Mounting struc-
flexible circuit materials are not commonly reinforced.
tures for BTCs are identical to those that satisfy the needs of
many different component package configurations. These
5.1.2 Inorganic Structures Inorganic substrates are al-
configurations drive the complexity of the mounting struc-
ternatives to the organic substrates; they are usually refrac-
ture and determines the resin, reinforcement and, for many
tory materials comprised of sintered metal oxides. While
applications, the metallic configuration of the surface to
they are typically brittle, they have some significant benefits
which the components are attached.
not easily obtained with organic substrates.
PTH vias connect the PCB thermal pad to any electrically
Chief among the advantages are excellent thermal proper-
appropriate internal PCB plane(s). For double-sided PCBs,
ties. Like organic structures, there are a number of possible
the un-tented PTH vias has the potential for solder, during
choices available: ceramic, silicon, and enameled metals.
wave soldering of mixed assembly, to reach the PCB top
The dielectric properties of these materials tend to be higher
side and cause secondary reflow, leading to potential opens
than organic based materials and, because they are brittle,
and shorts. So PTH vias should be plated shut, plugged with
they are generally more prone to breakage. Because of the
epoxy or tented with solder mask to avoid low package
more limited vendor base for inorganic substrates, these
stand-off height due to solder wicking into the PTH vias
structures are normally more expensive.
during the reflow process. However, plating of vias shut
may increase PCB cost.
5.1.3 Layering (Multilayer, Sequential or Build-Up and
HDI) While single and two metal layer circuits are still To achieve the highest possible thermal performance, it is
common, multilayer interconnection structures are com- good to use a maximum number of PTH vias, but it is
monly required to support the interconnection of BTCs in important to keep in mind that they do impact the soldering
today’s high performance electronics. There are several surface of the PCB thermal pad. A recommended via pattern

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IPC-7093 March 2011

is 0.3 mm PTH via drill diameter on 1 mm centers but much widely available and are processed with relative ease. The
smaller vias are also being used. Improved thermal perfor- cloths are available in a number of different thicknesses and
mance can be obtained with a greater density of vias and weaves. The chemical make-up of the glass can vary and
larger vias on the same pattern that provides good solder- can affect the electrical properties. Presently, E type glass is
ability. the most commonly used glass cloth for printed circuit
substrates.
5.2.1 Resin Systems There are a number of different
resin systems suitable for use in organic laminate construc- 5.2.2.2 Glass Felt Glass felt or non-woven glass mat has
tion. There is a long and well understood history and years been commonly used as a reinforcement material for fluo-
of faithful service for the traditional resins systems. How- roplastic resins and is commonly used in low loss, RF or
ever, to support the move to meet legislated lead-free microwave applications. It has seen some application in
requirements by the EU, many new resins are being formable laminates as well but the technology is not
developed to meet the higher temperature assembly reflow widespread.
requirements. Test methods have been developed, i.e., Td
(Temperature of decomposition) and T260, T288, T300
5.2.2.3 Aramid Cloth Aramid cloth has been used to
(Time to Delaminate), to quantify material properties for
reinforce certain laminates. It is unusual in that it has a
conformance to the new EU requirements. Some of the new
negative CTE in the X and Y direction, which helps to offset
resin systems are classified to new material slash sheets
the in-plane CTE of the resin. Because of the counteracting
such as IPC-4101 /99, /101, /121, /124, /126 and /129.
expansion and contraction, laminate materials of this com-
bination can match approximately the CTE of ceramic.
5.2.1.1 Epoxy There are a number of different resin
However, a drawback of the material is that the aramid has
systems that can be used to create a printed wiring substrate.
Z axis CTE much higher than glass and, in thermal
Epoxy is among the organic resins with the longest history
excursions, can fracture nearby resin, leaving micro-cracks
and it is one of the most commonly used resin systems for
along the surface of the fibers.
PCBs. It offers a good blend of physical, electrical and
processing properties at reasonable cost. The general prop-
5.2.2.4 Aramid Paper The supply of non-woven aramid
erties are provided in Table 5–1. Higher temperature capa-
paper has diminished due to a lack of manufacturing
bility epoxy resin systems have been developed for lead-
sources. Aramid papers have been effectively used in a
free applications and are available at a cost premium.
number of multilayer applications. They have most of the
benefits of the aramid cloth with more process latitude.
5.2.1.2 Polyimide Polyimide offers the highest operating
They are often used for thin core layers at or near the
temperature among resin systems in use today. It has been a
surfaces of the multilayer printed boards to better control
favorite for military applications where the potential for
CTE. Because the aramid is organic, it has the added
board rework and repair in the field with uncontrolled
advantage of being more easily processed by laser ablation
soldering tools is anticipated. Because of its high glass
and can also be processed using plasma etching for making
transition temperature, polyimide provides a safety margin
holes. The organic nature of the material also helps to keep
and potential to reduce damage to the board when uncon-
the dielectric constant low.
trolled soldering irons are used to remove or replace a
component. The general properties are provided in Table
5–1. 5.2.3 Reliability Concerns with High Temperature Lead-
Free Soldering The higher temperatures required for sol-

5.2.1.3 Bismaleimide Triazine Bismaleimide triazine or

dering lead-free solders creates reliability concerns for the
BT resin is the most popular choice for the construction of survivability of the PCB resins as well as the integrity of the
some semiconductor packages including BTCs, because of PCB interconnect structures, such as plated-through holes
its combined advantages of high temperature capability at and vias.
reasonable cost. The general properties are provided in The properties that are most important in this respect are the
Table 5–1. thermal expansion, the glass transition temperature and the
decomposition temperature. The thermal expansion from
5.2.2 Reinforcements Reinforcements provide the di- 50–260°C, TE (50–260°C) is a composite of the thermal
mensional stability and the bulk of the mechanical proper- expansions below and above the glass transition tempera-
ties of the organic substrate laminate. Following are some of ture. The glass transition temperature (Tg) is the temperature
the more commonly used reinforcements. at which an amorphous polymer, or the amorphous regions
in a partially-crystalline polymer, changes from being
5.2.2.1 Glass Cloth Glass cloths are the most commonly in a hard and relatively-brittle condition to being in a
used reinforcement for printed board substrates. They are viscous or rubbery condition. These different molecular

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Table 5-1 Environmental Properties of Common Dielectric Materials

Material
FR-4 Multi- High Bismaleimide
(Epoxy Functional Performance Triazine/ Cyanate
Environmental Property E-glass) Epoxy Epoxy Epoxy Polyimide Ester

Coefficient of Thermal
Expansion, xy-plane, 16 - 19 14 - 18 14 - 18 ~15 8 - 18 ~15
CTE(xy) (ppm/°C)
Coefficient of Thermal
Expansion, z-axis below 50 - 85 44 - 80 ~44 ~70 35 - 70 ~81
Tg1, CTE(z,<Tg) (ppm/°C)
Coefficient of Thermal
Expansion z-axis above 240 - 390 240 - 390 240 - 390 TBD TBD TBD
Tg1, CTE(z,>Tg) (ppm/°C)
Thermal Expansion z-axis,
3.0 - 4.5 2.5 - 4.0 2.0 - 3.5 TBD TBD TBD
TE(50–260°C) (%)
Glass Transition Tempera-
110 - 140 130 - 160 165 - 190 175 - 200 220 - 280 180 - 260
ture2, Tg (°C)
Decomposition Tempera-
310 - 330 320 - 350 330 - 400 ˜334 ˜376 ˜376
ture3, Td (5%) (°C)
Soldering Temperature
170 - 205 200 - 220 215 - 260 TBD TBD TBD
Impact Index4, STII
Flexural Modulus (GPa)
Fill5 18.6 18.6 19.3 20.7 26.9 20.7
Warp6 12.0 20.7 22.0 24.1 28.9 22.0
Tensile Strength (MPa)
Fill5 413 413 413 393 482 345
Warp6 482 448 524 427 551 413
Water Absorption (wt%) 0.5 0.1 0.3 1.3 1.3 0.8
Notes:
1. CTE (z,<Tg) is also known as Alpha 1, and CTE(z,>Tg) as Alpha 2. Contact supplier for specific values of the other materials.
2. The glass transition temperature can be measured by three different methods (TMA, DSC, DMA). Of these the values obtained by TMA are the most pertinent
for the purpose of assessing reliability issues. A very rough relationship between the results of these three methods is Tg (TMA) ≈ Tg (DSC) -10°C ≈ Tg (DMA)
-20°C. Contact supplier for specific values of other materials.
3. The decomposition temperature can be measured to two different values of weight loss, Td (2%) and Td (5%). Td (5%) is more commonly used, but Td (2%) is
becoming popular because of its greater usefulness. Contact supplier for specific values of other materials.
4. Soldering Temperature Impact Index, STII, which is defined as STII = Tg/2 + Td/2 — (TE% (50 to 260°C) x 10).
5. Fill – yarns that are woven in a crosswise direction of the fabric.
6. Warp (cloth) – yarns that are woven in a lengthwise direction of the fabric.

structures result in very different physical properties. See controlled primarily by the reinforcement of the material.
Figure 5–2. The decomposition temperature (Td) measures The x-y expansion will have the greatest effect on surface
the temperature at which the resin decomposes irreversibly, mounted components and their reliability. Thermal expan-
and thereby loses weight; typically the temperature to a sion also occurs in the z-axis at a rate significantly larger
weight loss of 2% or 5% is measured. than in the x-y plane, particularly at temperatures above the
Tg. The z-axis expansion will have its greatest effect on
The impact of these three properties is captured with the
plated-through hole and via reliability.
Soldering Temperature Impact Index, STII, which is defined
as STII = Tg/2 + Td/2 — (TE% (50–260°C) x 10). This Table 5–1 shows the conditions for various reinforced resin
equation relates to the material Tg and Td plus the thermal types. All thermal expansion is measured in parts/
expansion characteristics. See Table 5–1. million/change in temperature (°C).
Where:
5.2.5 Moisture Absorption Most organic materials are
Tg is the laminate glass transition temperature
hygroscopic to some degree and soak up moisture at
Td is the temperature that the material decomposes different rates; some do so relatively rapidly. This moisture
TE is the thermal expansion from 50 to 260°C in percent absorption changes the electrical properties of the material
such as loss tangent and as well the processing characteris-
5.2.4 Thermal Expansion Thermal expansion is usually tics of the material as outgassing can result in blisters. It can
characterized in terms of changes to the x-y plane, which is also impact physical dimensions and the laminate’s weight.

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IPC-7093 March 2011

L.C.C.C.*
CTE Range
MATERIAL 5.5 7.5
20 24

▼
ALUMINUM FOR HEATSINKS 17 18

COPPER 13 15

EPOXY ‘‘E’’ GLASS

12 14

BT-‘‘E’’ GLASS
12 14

POLYIMIDE ‘‘E’’ GLASS

11 13

CYANATE ESTER-‘‘E’’ GLASS

8 10

CYANATE ESTER-‘‘S’’ GLASS 7 11

COPPER INVAR COPPER

WITH POLYIMIDE ‘‘E’’ GLASS 7 8

NONWOVEN
ARAMID/POLYIMIDE 7 8

NONWOVEN
ARAMID/EPOXY 6 10

POLYIMIDE QUARTZ
6 9

CYANATE ESTER-QUARTZ
5.7 6.3

EPOXY-WOVEN ARAMID
5.0 6.0

BT-WOVEN ARAMID
5.0 6.0

POLYIMIDE-WOVEN ARAMID
3.8 5.5

COPPER INVAR COPPER

12.5/75/12.5

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CTE (PPM/ °C)

* Leadless Ceramic Chip Carrier
IPC-7093-5-2

Figure 5-2 Material Thermal Expansion Comparison

Thus a simple way to determine that the material has ing. This technology allows local flatness measurement at
absorbed moisture is to note the increase in weight under room temperature, and also at the elevated temperatures
defined moisture exposure conditions. Table 5–1 shows the (e.g., 260°C) for implementing lead-free soldering. Tradi-
water absorption rate by weight for the various materials tional techniques of measuring overall board flatness do not
highlighted in this section. reflect the problems in attaching high terminal count BTCs
to certain local areas of a board.
5.2.6 Flatness (Bow and Twist) The planarity of 1.5,
2.25 and 3.0 millimeter thick boards varies, especially with 5.3 Surface Finishes Printed board surface finishes
respect to being able to assemble BTC type parts. Flatness serve several functions, these include: solderability provi-
is measured in relationship to the length and width of the sion and protection, reliable contact surface for
laminate or the completed printed board. The term bow is contacts/switches, wire bondable surface, and solder joint
applied to the longest dimension of the part; whereas, twist interface. Although BTCs are the focus of this document,
requirements are applied to the length across the diagonal the other components and assembly operations of the
distance. These requirements are usually set as a percentage printed board must be taken into consideration when choos-
allowance of the distance in question. Thus, the allowable ing the most appropriate surface finish. There is no single
bow of a printed board might be specified as 0.50% of the surface finish that will be best for all applications.
length of the longest dimension.
While no surface finish is ideal for all applications, the
The key to flatness in regards to the mount of BTCs, search continues for improved surface finish solutions.
however, needs to be evaluated based on localized flatness Because of the component mix many have been satisfied
measurement with such techniques as shadow moire imag- with some of the immersion surface finishes, immersion

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March 2011 IPC-7093

silver in particular, however since the emphasis on mount- widely from 0.75 µm to 35 µm. It is generally held that the
ing BTCs is to make sure that there is sufficient solder lower thickness is not acceptable because the very thin layer
volume some companies still require some form of solder as of solder is completely transformed into copper-tin interme-
the preferred finish. The concern is mainly the uniformity of tallic, which has very poor solderability. However, studies
the final board finish as well as the flatness of the plating or on the solderability evaluation of printed boards with HASL
coating on the land to which the BTC will be attached. and other protective coatings indicate that soldering perfor-
mance as indicated by visual examination showed no
Some of the application features are provided in Table 5–2.
correlation to the solder thickness or solder coverage on the
lands observed in cross-sections. As a result, acceptance
5.3.1 Hot Air Solder Leveling (HASL) The surface finish
criteria for the solderability of printed circuit boards should
of long standing is hot air solder leveling (HASL). In this be based on functional testing of sample boards.
process, the finished printed board is dipped either vertically
or horizontally into a molten solder bath and the excess The wide variation seen in solder thickness in HASL affects
solder is blown away and leveled with hot air, giving the the coplanarity of solder termination on the printed board
process its name. The HASL process is the first soldering and hence the components. Moreover, the uneven surface
stress that the printed board experiences. Some material makes more difficult the paste-printing task, because it
combinations may be prone to delamination during the makes it more difficult to achieve good sealing of the stencil
multiple excess temperature exposures. while printing. Lack of a good seal or “gasketing” will result
in leakage of solder paste beneath the stencil. The result is
The HASL finish provides a virtual guarantee of solderabil- that the manufacturer must either increase the frequency of
ity in that the process creates one half of the soldered joint cleaning (thus lowering throughput) or risk increased po-
by fully wetting the copper substrate. The quality of the tential for bridging (thus lowering yield).
product regarding solderability can be confirmed easily
through a simple dip test, conditioned by an aging process
or by simple visual inspection. Any evidence of non-wetting 5.3.1.2 Lead-Free HASL The lead-free hot air solder
or dewetting is immediately apparent as the board exits the leveling process has proven to provide both quality and
process. reliability of the surface finish in providing long shelf life
solderability. The most likely candidates for lead-free
The HASL solder surface finish provides a long solderable HASL are Sn-Cu eutectic (227°C melting point), or Sn-
shelf life. Solderability is lost only when the intermetallic Ag-Cu eutectic (217°C melting point). Other SAC alloys
has grown through the surface. Thus, a properly applied such as 105, 305 or others may also be candidates. The
coating can last more than a year if stored correctly. In Sn-Ag-Cu alloy appears to offer an advantage due to its
addition, the coating’s solderability properties will survive lower melting point, but there are also advantages of the
several cycles of adhesive cure or paste reflow. tin-copper system since the raw materials are readily avail-
able, and represent the lowest cost. The Sn-Cu solder pool
5.3.1.1 Tin Lead HASL Although the tin lead surface is easy to manage and recycle since there are only two
finish was the main solution for many printed boards, one constituents. The solder bath is not too aggressive, has low
concern with the HASL process is the coating thickness copper pick up characteristics, and is relatively tolerant of
uniformity. Often in the process, the solder thickness varies common impurities.

Table 5-2 Key Attributes for Various Board Surface Finishes

Electroless Electrolytic
HASL NI/Immersion Ni/Electroplated Immersion
SnPb/SnCu1 OSP AU AU Silver2 Immersion Tin

Shelf Life 1 Year 6 Months > 1 Year > 1 Year 6 Months 6 Months
proper
Handling
Handling Normal Avoid physical Normal Normal Avoid physical Avoid physical
contact contact contact
SMT land Sur- Domed/Not flat Flat Flat Flat Flat Flat
face topology
Multiple Good, need Fair, better Good Good Fair/Good Fair/Good
assembly robust with thick
reflow cycles laminate coatings
Notes:
1. Tin copper alloy is the preferred alloy for lead-free HASL
2. May require an organic preservative in order to remain untarnished.

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The melting point is low enough for most current equipment either method will work. The coating thickness can range
and components and, with some of the newer laminate from very thin (0.01 µm) to relatively thick 0.2 to 0.5 µm.
properties, is compatible with the printed board fabrication The thicker coatings are preferred over the thinner coatings,
sequence and processing. In order to fine tune the process, especially if there is need for multiple reflow cycles and/or
solder alloy bath suppliers have added a proprietary stabi- a long wait (e.g., days) between soldering of each side. It
lizing constituent—HASL, which is identified as Sn-0.7Cu. should be noted that all OSPs are not alike since there are
A typical alloy developed for lead-free soldering is SnCuNi specially developed OSPs to withstand the higher reflow
with a melting temperature of 227°C and a processing profiles associated with lead free.
temperature for soldering of 250°C to 260°C [482°F to
500°F]. Copper dissolution can be a problem if the bath The OSP surface has many advantages. Most important of
exceeds 0.85% copper which will likely increase the inci- all, it avoids the key problem of the tin/lead HASL by
dence of bridges, icicles, and other defects. The Sn- keeping the board surface flat. It is also lead-free and will
0.7Cu+Ni is 227–265°C (38°C variation) vs. Sn63Pb37 meet with EU legislative requirements. An OSP may also
183–250°C (67°C variation). improve gasketing, thereby reducing solder paste printing
The finish has good solderability which is retained through related defects and thus provides better overall yield.
thermal excursions and storage. The finish is smooth and Because the OSP coating is transparent, the coated termi-
bright and less domed than the tin/lead it is replacing. The
nations maintain their copper appearance, further enabling
solder bath composition can be held stable by the use of a
the detection of any solder paste misprint conditions.
low copper top-up alloy, and dross losses are low. Most
Alcohol or other solvents, if used for washing off the
important is that the alloy is not aggressive towards solder
misprinted paste, will also wash off coatings, and therefore
bath materials.
will increase the risk of oxidation of the copper which
In situations where large boards (>250 x 250 mm) are used impacts solderability. However, such boards can be recoated
with large BTCs (>25 x 25 mm), it may be a good idea to if necessary. Washing and wiping the board is not recom-
increase the printed board thickness to at least 2 mm to mended, but should instead be processed in accordance with
minimize board bending and flexing. This will reduce or IPC-7526 which recommends stencil and misprinted board
eliminate interfacial failures due to mechanical stress that is application data. Process engineers should work with
caused by bending and flexing of the printed board. How- chemical cleaning suppliers to establish the correct cleaning
ever, with the conversion to lead free, thicker boards will process that will remove the wet paste and minimize
require a greater time at temperature exposure making removal of the OSP surface.
reliability a greater concern. The increase in the use of thin
PCBs (<0.5 mm in thickness) in many handheld products There are some potential process incompatibilities with
may preclude the use of HASL because of warping of the OSPs. For example, if paste or flux does not cover all land
PCBs during processing. surfaces during soldering, there may be some dewetted
appearance after reflow soldering. It is thus important for
5.3.2 Organic Surface Protection (Organic Solderability flux to get into the PTH during wave soldering to achieve
Preservative) Coatings With wide spread use of bottom topside fillet. Similarly, in the SMT process, the paste must
termination components (BTC) and more fine pitch devices cover the entire land surface to avoid dewetted appearance
such as the land grid array, the need for increased control of at the land edges. Another example may be potential
PCB flatness is more critical. As an alternative to HASL, incompatibility between no-clean fluxes and certain sol-
which can cause warping, an alternative surface finish is vents. There is also the potential of solderability concerns
organic solderability preservative (OSP). An OSP is an when the assembly is subjected to multiple thermal cycles
anti-tarnish coating of an organic compound (such as a during reflow, wave, and hand soldering.
benzimidazole-based compound) which is applied over
exposed copper surfaces to prevent oxidation. An OSP is
5.3.3 Noble Metal Platings/Coatings With the EU’s leg-
commonly a water-based organic compound that selectively
bonds with copper to provide an organometallic layer that islation to remove lead from electronic solder, noble metals,
protects the copper, preserving its solderability. for example gold and palladium, are seeing increased use as
PCB surface finishes. Two other noble metal surface fin-
Various chemistries of OSPs are available. Some common ishes have gained popularity, and are electroless
ones are benzotriazol, imidazol and benzimidazol. These nickel/electroless palladium/immersion gold (ENEPIG) and
coatings keep the copper surface solderable by preventing direct immersion gold (DIG). These are also sometimes
oxidation or tarnish. The coating is commonly applied either called universal surface finishes since they can be soldered
by dipping the board in an OSP bath or by spray. As long as to, wire bonded to, and are also suitable as contactable
the process is controlled to achieve uniform OSP coating, surface finishes. ENEPIG, in particular, can alleviate solder

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March 2011 IPC-7093

joint brittleness problems occasionally seen with ENIG (ENIG) process, another combination of electroless and
when used with SAC lead-free BTC termination finishes. immersion plating processes have been developed. The
switch to lead-free solder has raised many issues on the
5.3.3.1 Electroless Nickel/Immersion Gold (ENIG)
manufacture, processing, and reliability of lead-free elec-
troless nickel/immersion gold (ENIG) provides very good
tronic products. Some of the evaluations included a Ni-
shelf life, a flat soldering surface for SMT processing, and
7%P/Pd/Au (ENEPIG) (5 µm/0.06 µm/0.03 µm) process.
a good surface for electrical probe contact required for
in-circuit-test (ICT). The ENIG finish provides solderable
5.3.3.4 Direct Immersion Gold (DIG) Direct immersion
surfaces which can survive through multiple reflow opera-
gold (DIG), is another surface finish that is able to deposit
tions and they are less prone to handling related problems.
a fine and uniform gold layer directly on the copper
The presence of nickel plating strengthens the through-hole
surfaces. By examining the deposition reaction of the flash
barrels during multiple reflow cycles and rework of
gold plating bath, it can be confirmed that copper does not
through-hole components. Noble metal plating finishes
co-deposit with gold and also that the main driving force for
typically cost more than OSP finishes, and are either
deposition is an auto-catalytic reaction. The copper surface
comparable or more expensive than HASL, depending on
roughness affects solder spread-ability, and the solder joint
the complexity of the PCB. If it is desired to mix multiple
characteristics are excellent when the film thickness is
board finishes on a single board, for example Ni/Au in some
within the range of 30 to 80 nm. In addition, good wire
areas and OSP in others, this can be difficult and expensive
bonding characteristics can also be derived from deposits
to achieve in manufacturing.
plated by a neutral pH, auto-catalytic type heavy electroless
The reducing agents used in the electroless nickel process gold plating bath, atop the flash gold.
contain either phosphorous or boron. In the reduction of the
Lead-free solder results are usually inferior (spread less) as
nickel in the electroless nickel deposition, either phospho-
compared to tin/lead eutectic solder with a DIG finish. It is
rous or boron is incorporated into the nickel deposit. The
necessary to understand this characteristic when lead-free
level of these co-deposited elements should be controlled
solder is utilized, in that the IMC layer changes at 150°C
within the specified process limit. Variation of phosphorous
with time and shows:
or boron level, outside the specified process limits, may
have adverse effects on the solderability of the finish and a) A small difference between Sn/Ag/Cu solder and tin/lead
possibly the reliability of the solder joints. solder IMC layer thickness at 0 hours
b) After 100 hours of exposure the IMC thickness is usually
5.3.3.2 Electrolytic Nickel/Electroplated Gold Another
equal
version of a nickel/gold combination is the electrolytic
nickel/electroplated gold surface finish. This plating is c) The IMC layer of Cu3Sn thickness continues to grow as
similar, however it results in a different grain structure from the heating time increases
electroless nickel/immersion gold, and does not exhibit the d) As with tin/lead solder, Cu3Sn is clearly apparent when
’black pad’ joint cracking phenomenon. Sn/Ag/Cu solder is used
Electrolytic nickel/electroplated gold is applied after pattern
5.3.3.5 Immersion Silver Immersion Silver is a metallic
plating and most often before solder mask, and therefore
solderability preservative. It can be permanent, becoming an
carries some risk of surface contamination. Solder mask
integral part of the assembled board, or sacrificial, prevent-
applied over electrolytic nickel/electroplated gold exhibits
ing copper oxidation and preserving solderability through
lower solder mask adhesion than other surface finishes. This
the assembly process. Immersion silver is also a good
can create problems during assembly of BTCs, and espe-
surface for contact probe testing.
cially during rework. If the solder mask dams covering the
conductors between BTC lands and vias peel off, solder will The industry continues to search for alternative surface
flow from the lands into the vias and cause insufficient or finishes that can overcome the disadvantages associated
open solder joints. with the HASL, OSP, and ENIG finishes. Some of the most
promising alternative surface finishes are immersion silver
Another concern is that it can be difficult to control the gold
and immersion tin.
thickness across the board. The gold may be too thin (for
example in areas with dense circuitry) or the gold may be
5.3.3.6 Immersion Tin Immersion tin has a relatively
too thick (for example in isolated circuits). This latter
long history but its use has been limited due to earlier
situation may lead to gold embrittlement due to excessive
concerns about intermetallic formation and reduced solder-
gold (>3%) in the solder joints.
ability. These concerns seem to be getting addressed in more
5.3.3.3 Electroless Nickel / Electroless Palladium / Im- recent processes. Immersion tin is a metallic solderability
mersion Gold (ENEPIG) In order to address some of the preservative that is sacrificial, preventing copper oxidation
problems with the electroless nickel/immersion gold and preserving solderability through the assembly process.

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IPC-7093 March 2011

Due to the higher contact resistance of tin it is not as good process can be modified to accommodate a solder filled
as immersion silver for contact probe testing. One of the via hole in a surface mount land.
concerns about the amount of tin in the solder joint of • Step small boards into arrays for handling. Depending on
lead-free solder is the growth of tin whiskers as the unit the design, some boards can be separated from the array
experiences changes in various stresses. and fluxed as single images before shipping.
Both immersion silver and immersion tin are deposited on
the board surface using the immersion method of metal 5.4 Solder Mask Solder mask is a polymer coating which
deposition. serves to protect copper surfaces which are not to be
soldered. Unlike the laminate, which is a composite, solder
5.3.3.7 Solid Solder Deposition Solid Solder Deposit mask is commonly a homogeneous material. As the name
(SSD) has been in existence since 1986. It is a method for suggests, solder mask is used to mask off the outer surfaces
pre-loading the surface mount lands with all of the solder of the board where solder is not required. Having solder
needed to complete the component attachment, in a solid mask over the copper also helps to prevent bridging
form. The SSD process uses an adhesive flux coating to hold between conductors. Because of process changes for lead-
the components in place during the final reflow cycle. The free soldering, evaluating solder mask performance takes on
adhesive flux once dried has a much higher holding power a whole new meaning.
than solder paste and it does not matter if it is smeared as it In the past not all boards required a solder mask because the
is non conductive and non corrosive. This means that conductors and lands were spaced quite far apart. The solder
placing components with lead styles that are blind or bridges between adjacent conductors during wave soldering
underneath the component body can be done with more were not likely. But with the advent of fine lines and spaces,
predictability and achieve better yields. the use of a solder mask has become almost mandatory for
The basic steps for the SSD application are shown in Figure boards that are going to be wave soldered. On a full SMT
5–3. board where no wave soldering is required, tenting or
plugging of via holes is done to assist drawing a vacuum on
The manufacturing considerations for an SSD product are: some ICT testers. Also, the application of solder mask to
• Solid Solder Deposit Application Process Sequence (see block or plug a via allows closer spacing between a via and
Figure 5–4) the adjacent conductors.
• Printing paste onto pads and reflowing it without disturb-
ing it is an easier method for applying solder paste. All 5.4.1 Wet and Dry Film Solder Masks Permanent solder
defects associated with Z-axis pressure from component masks are available in dry film and wet film. Dry film masks
placement is eliminated. can have an aqueous or a solvent base. In both cases, the
• Reflowing solder paste on to surface mount lands also mask starts out as a polymer film, which is applied to the
highlights solderability issues associated with the surface board by vacuum lamination. Wet film solder masks, as the
finish. De-wetting is easily identified without the com- name implies, are liquid or paste-like. They include pho-
ponents in the way. toimageable and wet screenable solder masks. The latter are
differentiated by the method of cure. Some wet screenable
• Reflowing solder without components allows proper
solder masks can be cured by UV light and some can be
out-gassing of the flux. Consequently the formation of
cured thermally in convection or IR ovens. UV masks do
voids is decreased or eliminated.
not provide as good adhesion as thermal masks but require
• Cleaning flux residue from bare boards is easier and only seconds to cure as opposed to 30–60 minutes for
more efficient without the components in the way. thermal cure.
• The adhesive flux supplied with SSD is tackier than
Each of the liquid solder masks has advantages and disad-
solder paste and will last up to 6 months if stored
vantages. They are inexpensive and highly durable. Being
properly.The design of a SSD printed circuit board is no
liquid, they flow between conductors and prevent the
different than a standard printed circuit board.
formation of air pockets. There is no trim waste, and the
The design considerations for an SSD product are: thickness of the mask can be controlled for each design.
Since the wet film solder masks are screened on (a mechani-
• Completely surround every surface mount feature with
cal process), they are difficult to register and have a
solder mask. This means dams in between all pads to
tendency to skip over conductors, especially on fine line
help shape the SSD during flattening.
boards. They also tend to bleed onto the lands and surface
• Isolate all holes including via holes so that paste does not mount lands during cure. Wet screenable masks are difficult
drain during reflow. to use on boards with fine lines and spaces (<200 µm), and
• Identify lands with via holes in them and the SSD they are also vulnerable to voids, bubbles and pin holes. The

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March 2011 IPC-7093

IPC-7093-f5-3

Figure 5–3 SSD Application Basic Fabrication Steps

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IPC-7093 March 2011

Coated or plated BTC land pattern and DAP

Stencil print solder paste on land pattern and DAP

Reflow solder and clean to remove flux residues

Flatten the SSD surface and stencil print adhesive flux

IPC-7093-5-4

Figure 5-4 SSD Process Steps

use of screenable mask has been on decline as photoimage- control. Not many film thicknesses are commercially avail-
able solder masks have gained in popularity. able, and this can limit flexibility and increase cost. Typi-
cally, most dry film solder masks are 75 µm to 100 µm thick.
The wet film solder mask cannot successfully tent via holes.
The degree of fill needs some control in order to develop a The thicker masks can cause problems in reflow soldering
plug that prevents chemistry from going through the via. as well. For example, a dry film mask applied between the
Partially filled vias trap process chemicals and are difficult lands of BTCs can cause standoff problems during reflow
to clean. soldering because of the rocking effect of the mask. For this
reason, dry film solder mask should not be used between the
Dry film solder masks have some advantages over their wet
lands of BTCs or in assemblies that have components glued
screen counterparts. The former provide very accurate
to the bottom side for wave soldering.
registration, which is critical in preventing solder bridging
or bleeding on fine line boards, as well as sharper resolution.
Tenting of via holes is also superior with dry film solder 5.4.2 Photoimageable Solder Masks Photoimageable
masks because they are never in a liquid state and do not solder masks combine the advantages of dry film and wet
drip into the via during vacuum lamination. However some solder masks. Dry film is also a photoimageable mask.
problems may arise when trying to laminate a semisolid dry Focusing on wet film photoimageable masks provide accu-
film over an uneven board surface with conductors and rate registration; they are easy to apply, encapsulate the
lands. Any bow and twisting of the board will compound the circuit lines totally, have excellent durability, and are less
problem, possibly causing air pockets underneath the dry expensive than dry film.
film near conductors.
Photoimageable masks can be either screened on or applied
Dry film masks are more costly than the wet film variety, by a process called curtain-coating, in which the board is
and the supplier base is limited. Moreover, the application passed at high speed through a curtain or waterfall of solder
process for dry film solder masks is sometimes difficult to mask.

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March 2011 IPC-7093

The photoimageable mask may contain solvent along with and repeat” where elements of an individual board are
photopolymer liquid. If the solvent is added in the mask, the repeated to match the arrangement of the boards on the
liquid mask is screened on, solvent is dried off in an oven, subpanel. It is vital that the exact layout used by the board
and then the mask is exposed to UV light by off-contact or manufacturer is understood to accurately provide the rela-
on-contact methods. (If no solvents are used, the liquid is tionships of the land pattern for a BTC on one board with all
100% reactive to UV light.) The off-contact method requires other land patterns of sister boards in the same panel.
a collimated light system to minimize diffraction and scatter Inconsistent arrangement of the assembly array can result in
in liquid. This makes the system more expensive. The misprints when stenciling solder paste onto the panel for
on-contact approach needs no collimated UV light source, surface mount assembly.
and the system is relatively cheaper. Photoimageable solder
masks can tent only very small via holes. Most photoim- 5.4.4 Via Protection
ageable wet film masks will not reliably tent 0.35 mm via
holes because it is difficult to cure polymer in via holes. If 5.4.4.1 Encroached vias The encroached via concept is
tenting is required, dry film is needed because only dry film one that permits solder mask being on the land without
can tent via holes effectively. filling the via plated-through hole. Encroachment vias take
the primary solder mask opening and adjust it so that it is
5.4.3 Registration Registration between individual slightly larger than the via hole size.
boards within a multi board panel becomes critical for any
This concept will permit any outgassing or cleaning of the
surface mount application. This is especially true when the
via plated-through hole, provide more surface coverage and
board is made in a panel array format to assist the assembly
increase adhesion between the solder mask and copper of
process and throughput characteristics. Board manufactur-
the annular ring. It will also provide a larger web between
ers inherently build printed boards in a manufacturing panel
the land and the via, and thus should minimize solder mask
format; assemblers also want to take advantage of the
removal during BTC removal for rework. See Figure 5–5.
multiple board array format when they complete their
assembly.
5.4.4.2 Via Filling Via filling, capping, flooding, tenting
The positioning and orientation of individual boards on any and plugging (conductive or nonconductive) are some of the
panel is usually at the discretion of the board manufacturer. process names applied to techniques used to cover or fill via
The manufacturer optimizes the use of the material in the holes with different materials. Materials currently being
panel and the tolerance conditions that can be achieved with used to protect vias include standard liquid photoimageable
the material used to build a particular board. It is a well and non-imageable solder masks, dry film solder masks,
known fact that organic materials are prone to movement specially formulated hole plugging inks, conductive inks,
(e.g., growth and/or shrinkage); thus, the board manufac- liquid dielectric materials and even materials not used in
turer, based on their knowledge of materials and their other PCB constructions.
predicted dimensional change movement, will commonly
The processes for protection of via structures serve different
adjust the phototool to compensate for material stretch or
purposes. Via filling is normally performed on boards that
shrinkage depending on the circuit, the board size and the
use both reflow soldering and wave soldering. Via filling is
particular properties of the selected material.
also recommended under certain specified conditions, such
It is important to understand that assembly companies as for boards where exposed vias under BTCs are exposed
frequently build their stencils based on a process of “step to a wave solder. The concern is based on the fact that, when

Drilled and plated via hole

Solder Mask overlaps

onto the via land

Via land outline

IPC-7093-5-5

Figure 5-5 Comparing Solder Mask off Via Land with a Solder Mask Encroached Via Land

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IPC-7093 March 2011

a board with BTCs on the first side is processed through prior to solder mask application; the via is filled with a
wave soldering, a large amount of heat can transfer from the conductive or nonconductive material.
vias. This can be very significant because some BTCs can • Filled Via – A via with material applied into the via
have very high via densities beneath them. targeting a full penetration and encapsulation of the hole.
There are three basic characteristics of via protection • Capped Via – A secondary operation providing a metal-
addressed in IPC-4761. The first is a bumped via, where the lized coating covering the via. The metallization is on
hole being plugged or filled with material protrudes above both sides.
the surface of the hole interface producing a convex shape.
The second characteristic is one that has a dimple in the Via plugging is frequently used in conjunction with BTCs to
construction where the hole plugging or fill material recedes prevent solder flow to the BTC solder joints when wave
below the hole interface producing a concave shape. The soldering is used. Table 5–3 shows the relationship between
last of the conditions is identified as a planarized via where via filling and the surface finish conditions.
the excess hole plugging or fill material protruding above
As a general rule, via flooding and capping processing
the hole interface has been removed by a process to produce should be performed after a surface finish has been applied.
a coplanar surface. See Figure 5–6. For OSP and ImAg (immersion silver) finishes, via capping
must be done after the surface finish is applied because the
harsh chemicals that are used to clean the copper surface
can become trapped around the via cap. These trapped
chemicals can damage the via wall resulting in open vias.
Applying the via caps after the surface finish has been
applied can degrade some surface finishes (e.g., OSP, ImAg,
ImSn) due to the thermal exposure that is necessary to cure
the via cap material.

There are presently seven different methods of via

plugging/capping identified in IPC-4761. These are shown
in Figure 5–7. It is important to realize that the choice of
tented, plugged and filled vias for via protection can have
IPC-7093-5-6 direct impacts on the subsequent assembly processes.
Figure 5-6 Planarized and Capped Via Protection Example Besides identifying the seven via protection methods, there
are also pros and cons indicated in IPC-4761. The prefer-
The following definitions apply to the various via filling ence of the plugging method among the options presented
operations. There are four basic concepts which include: will depend on the capabilities of both the fabricators and
• Tented Via – A via covered with dry film solder mask; the the assemblers. To avoid complication during assembly, it is
via has no fill. When tenting from both sides there may imperative that all involved in the manufacturing process
be issues with air entrapment and expansion during mass understand the trade-offs among the options.
soldering. When tenting on one side there may be issues
For printed boards with HASL finish, the solder coating will
with chemical entrapment during the assembly process,
effectively prevent most surface degradation due to chemi-
especially when using aggressive flux.
cal exposure. HASL finishes also increase overall wall
• Flooded Via – A via that is flooded with LPI solder mask; thickness of the via barrel. It should be noted that for vias
the via is partially filled or the walls are coated with that are solder coated before plugging, the solder coating
solder mask. This process could possibly be improved by will melt during second side reflow. As a result, the
using a vacuum assist table. plugging material can become loose. In some cases, when
• Plugged Via – An additional operation which is done there is excessive solder coating thickness or solder

Table 5-3 Via filling/encroachment to surface finish process evaluation

Surface Finish Tenting Flooding Capping Plugging Encroaching

HASL Okay Okay Okay Okay Okay

OSP Okay Not Recommended Okay Okay Okay
ENIG Okay Okay Okay Okay Okay
ImAg Okay Not Recommended Okay Okay Okay
ImSn Okay Not Recommended Okay Okay Okay

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IPC-7093-f5-7

Figure 5-7 Via Protection Methods

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IPC-7093 March 2011

entrapped within via during fabrication, solder can poten- To achieve mechanical constraint within a chosen and
tially outgas and spatter or drain to the remaining openings. useful range, the total thickness of the core in the multilayer
should be approximately 25% of the board’s total thickness.
5.5 Thermal Spreader Structure Incorporation (e.g., Constraining core board is more often used because the core
Metal Core Boards) When structural, thermal, or electrical layers may be imaged, etched, and connected to the plated-
requirements dictate, a conductive constraining core or through hole. The thicker center core must be pre-drilled
metal core can be added to the organic substrate to make the before lamination to accommodate drilled and plated holes
new structure. It is recommended that the board circuit layer needed to join the two outer sections of the PCB. Better
configuration be made symmetrical about the center of the thermal cycle survival has been shown in some studies for
core. It is possible to create structures that are asymmetrical structure having two constraining cores in the board rather
(i.e., having a different number of layers to either side of the than one.
core); however, plated-through holes going through the
entire stack may be less reliable due to the differences in Another configuration is to have a special constraining core
expansion on either side of the metal or constraining core. board made by bonding a multilayer board to each side of a
See Figure 5–8. thick metal core after each of the boards has been com-
pleted. The composite board is then sequentially drilled,
plated, and etched to form plated-through hole connections
between the two boards. Coupons should be provided to test
the integrity of the composite structure.
Symmetrical around core (metal or constraining)
5.5.2 Heat Transfer Pathway Metal core boards add
significantly to the thermal mass of the assembly. This may
force the preheating soldering process to be operated at
abnormally high limits. These designs should be thoroughly
Asymmetrical around core (metal or constraining) evaluated under production conditions prior to release.
Laminate ruptures and discoloration and grainier textured
solder are typical effects that have been observed. The heat
transfer path between components and the planes are
Two core (metal or constraining)
usually accomplished through either direct contact with the
IPC-7093-5-8
plane or through thermal vias positioned under the compo-
Figure 5-8 Metal Core Board Construction Examples nent and connected to the thermal core or plane in its
position.
The advantage of the asymmetrical design is that it can
separate electrical properties and functions from mechanical 5.5.3 Thermal Pad Attachment In order to obtain peak
features, and/or areas requiring heat dissipation. Among the performance of some BTC high pin count packages the
drawbacks are the significant differences in the coefficient printed board must be properly designed and the package
of thermal expansion of the board and the core material. The mounted with special consideration. For enhanced thermal,
circuit board may distort during assembly soldering/reflow electrical, and board-level performance, the exposed pad on
operations, or while the system is in use if exposed to the package should be soldered to the board using a
excessive operating temperature variations. corresponding thermal pad on the printed board. For proper
heat conduction through the board, thermal vias should be
Some compensation can be achieved by having additional incorporated in the printed board design in the thermal pad
copper planes added to the back of the interconnection region. Clearance between the inner row’s terminations and
product. The extra copper plane may increase the expansion the thermal pad are required for vias to route the inner row
coefficient slightly and make soldering more difficult due to signals. The amount of clearance required depends on the
the need to put more energy into the board to assure proper application.
solder joint formation; however, a positive effect is that it
enhances thermal conductivity. The printed board land pattern design should take into
account the dimensional tolerance of package, the printed
5.5.1 Lamination Sequences The more desirable con- board, and board assembly. Some of the factors that can
structions are those where circuit layers are symmetrical significantly affect the mounting of the BTC package on the
about the core chosen to serve at the center of the board. By board and the quality of the solder joints are:
so doing, individual multilayer circuits can be produced
• The amount of solder paste coverage in the thermal pad
separately, each with their own laminating sequence. For
region
example, a four layer board might be manufactured having
vias through the entire four layers and this can be duplicated • The stencil design for peripheral and thermal pad region
for use on either side of the core. • The type of via used to interconnect the BTC

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March 2011 IPC-7093

• The printed board thickness

• The plated finish on the terminations of the package
• The surface finish on the board
• The type of solder paste
• The reflow profile
Ideally, the size of the thermal pad should match the
exposed die paddle size of the BTC. Due to needed
clearance for vias, the thermal pad size may need to be IPC-7093-5-9
reduced to less than the package paddle size. From a board
Figure 5-9 Examples of Type VII Filled and Capped Vias
mounting perspective, there are no major issues if the board
thermal pad is smaller than the package paddle size,
5.6 Solderless Interconnections Systems Due to the
however from a thermal efficiency perspective, there is
regulations eliminating the use of some materials in the
minimal efficiency loss as long as the thermal pad on the
fabrication of the electronic assembly interconnecting struc-
board is close to the same size as the die inside the package.
tures, several alternative and unique assembly methods
The thermal pad design on the printed board should have designed to eliminate solder completely from the assembly
75% paste coverage and may use a hatch pattern to reduce process are generating interest. One approach for discussion
the amount of total solder paste. The number of openings is a process identified as Solderless Interconnection process,
should be chosen in order to maintain a web thickness e.g., plating process. In this process, tested and burned-in
between openings of approximately 0.20 mm. This will packaged components are encapsulated and the electrical
allow space for flux volatiles to escape, thus minimizing connections are made to component leads using an electro-
voids. plating process during the circuit patterning, thus bypassing
the soldering process.
5.5.4 Thermal Vias In order to effectively transfer heat
The BTC packages are devices which conform to a common
from the top metal layer of the PCB to the inner or bottom
fundamental grid pitch in order to facilitate design and
layers, thermal vias should be incorporated into the thermal
testing. The other components that are part of the electronic
pad design. The number of thermal vias will depend on the
assembly should also be available in a bottom only termi-
application, power dissipation, and electrical requirements.
nation mode. The prospective of benefits of such processing
Although more thermal vias improve the package’s thermal
include: lower material use, reduced energy requirements,
performance, there is a point of diminishing returns where
fewer manufacturing steps, simpler designs with fewer
additional thermal vias may not significantly improve the
wiring layers, higher performance, improved thermal man-
performance. Usually BTC suppliers recommend incorpo-
agement, better EMI and ESD protection, obviation of
rating an array of thermal vias at 1.0 mm to 1.2 mm pitch
concerns about metal finish solderability, solder joint quality
with via diameters of 0.3 mm to 0.4 mm. The number of
or tin whiskers.
thermal vias should be determined for each application
operating environment and condition. The burned-in or tested components are bonded to a
temporary or permanent organic base material, after which
Thermal vias may take several configurations. They could
the components and base material are over molded with an
be left open, they could be filled with thermally conductive
insulating material. The assembly is inverted and the com-
materials, they could be plated shut or capped with plating
ponent leads or terminations are accessed by ablation of the
as in the description of a type VII via fill defined shown in
organic base material. Vias are then plated along the circuit
Figure 5–9. Any thermal via should be connected to a plane
layers as shown in Figure 5–10.
within the multilayer board in order to transfer the heat to a
cooler material surface. The concept for BTC removal or Structures fabricated without having to be exposed to high
replacement needs to address the soldered connection of the temperatures can open doors to new potentials in terms of
thermal pad and the amount of mass that must be heated in interconnection and thermal management. The structures
order to disconnect the BTC from the mounting surface. themselves could be assembled in a modular form into 3D

IPC-7093-5-10

Figure 5–10 Example of Circuit Development of Solderless Connection Technology

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IPC-7093 March 2011

structures that are interconnected on all sides. There are terms, the family of BTC components includes: peripherally
several of these concepts being developed which make the leaded dual (two) and quad (four) sided devices, peripheral
interconnecting substrate part of the assembly process and multi-row (in-line and staggered leads) and full and partial
thus the lines of responsibility for testing become somewhat area array devices. The leads on the bottoms of the packages
blurred. Only time will tell as to which application provides can be rectangular or round depending on the type with
the most benefit to the user and the status of the infrastruc- lead-frame devices (e.g., QFN) typically represented by the
ture that can provide this form of interconnection method- former and substrate devices (e.g., LGA) represented by the
ology. latter. (see Figure 6–1) Because BTC packages do not have
solder balls terminations, the electrical connection between
6 PRINTED CIRCUIT ASSEMBLY DESIGN CONSID-
the package and the assembly board must be made using
ERATIONS
only the solder deposited on to the circuit board. Getting
This section provides information on the design principles sufficient solder on the lands and making viable and reliable
for incorporating bottom termination components (BTC) solder joints is one of the significant challenges for this type
into electronic products including modules and product or product. Thus, special attention is needed in designing
board design concepts. The principles define placement and the land pattern.
interconnection rules and the mounting characteristics that
The component land pattern for the PCB is commonly
must be considered during the design process. Methods of
predicated either on guidelines developed by the component
mounting structure requirements are detailed to the extent
manufacturer, within a company or by following established
that they coincide with the assembly process considerations.
industry standards such as IPC-7351. While BTCs such as
Emphasis is also placed on the thermal management of the
the SON and QFN have been available for some time, they
final assembly and the contribution that the mounting
have not been broadly used and thus the learning experience
structure provides to the assembly.
with them is still limited and industry guidelines may not
6.1 BTC Part Description BTC parts are a near chip have been refined. The development of an optimum geom-
scale plastic encapsulated wire bond package with a copper etry may require some experimental trials. Moreover, be-
leadframe or organic laminate substrate in a BTC package cause certain structures of the exposed die attach paddle and
format. The QFN and LGA are representative of the the package lands on the bottom side of the package, certain
package technology. The QFN variation offers a number of constraints must be considered.
significant benefits over standard plastic lead-frame pack-
The SON and QFN versions are of high interest to industry.
ages:
The 0.8 mm is perhaps the most prevalent thickness but the
• Reduction in board mounting space as die size is closer package is selectively available in a lower profile thickness
to the package size. as well such as 0.6 mm. Perimeter input/output pads are
• Superior electrical characteristics are obtained due to located on the outside edges of the package. Electrical
minimal lead lengths, reducing the electrical path dis- contact to the printed circuit board (PCB) is made by
tance between die and PCB. soldering the perimeter pads and exposed paddle on the
• Lower thermal resistance because the bottom exposed bottom surface of the package to the PCB. Heat is efficiently
die attach paddle can be soldered directly to a corre- conducted from the package by soldering the exposed
sponding thermal feature on the PCB surface. thermal paddle to the PCB as illustrated in Figure 6–2.

• The QFN leadframe type package assembly process Stable electrical ground connections are provided through
utilizes existing proven SO-IC leadframe package infra- down bonds and through conductive die attach material.
structure. Wire bonding is provided using gold wires. Perimeter and
• Standard SMT assembly equipment can be used and high thermal pad finish is plated as 100% Sn (Sn/Pb is available
assembly yields can be realized from the self-aligning as well). As noted in Sections 3 and 4 SON and QFN
characteristic of the low mass package. packages are punched or sawed from a molded strip during
final assembly. Half-etching of the leadframe provides mold
Coplanarity is not an area of concern for this component compound locking features for the perimeter pads and die
family because all contacts are flush with the bottom of the thermal paddle. This package is currently characterized as
package. In regard to moisture sensitivity level (MSL), the moisture sensitivity (MSL) level 3 (see J-STD-020 for MSL
molding compounds used for encapsulation are a resin- levels).
based material, so moisture absorption will vary depending
on the size of the specific package, the size of the die attach Terminal contacts:
pad (DAP) and the number of wire-bonds.
• The contact pads (or solder pad) are located peripherally
6.1.1 BTC Package Variations The BTC packages are in single row format depending on the specific number of
available in various lead formats and thicknesses. In general pins and body size.

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March 2011 IPC-7093

SON (DFN)
(QFN)

QFN QFN
Multi-row Multi-row
Staggered

LGA LGA LGA

Full Array Partial Array Depopulated Array
(with thermal spreader) IPC-7093-6-1

Figure 6-1 Family of Bottom Termination Components (BTC)

impedance, and, because of its small outline, minimizes the

printed circuit board area required for mounting. The small
size and very low profile make this package ideal for high
density PCBs used in small-scale electronic applications
such as cellular phones, pagers, and handheld PDAs.
In addition to their small package outline and low profile,
the BTC devices have a low thermal resistance and reduced
electrical parasitic.

6.1.1.1 Board Material As detailed in Section 5 standard

epoxy glass substrates (FR-4) are compatible with BTC
assembly. Use of a substrate with lower coefficient of
thermal expansion (CTE) can improve reliability. A printed
board can also be affected by factors such as number of
metal layers, laminate material selected, balanced construc-
IPC-7093-6-2
tion, trace density, operating environment, site population
Figure 6-2 QFN Bottom Termination Component Lead- density, and mounting of components on the reverse side of
Frame Array the printed board. For specific board material specifications
refer to IPC-4101.
• For certain specific applications the packages are incor-
porated with common power and/or ground pins.
6.1.1.2 Surface Finish The surface finish on the printed
• All contacts are plated with matte tin solder for ease of
board is also very important to proper design of the
surface mount processing.
assembly. There are a variety of finishes available (see
The bottom termination QFN package family (see JEDEC Section 5), and many times a compromise is required in
MO-220) furnishes enhanced chip speed, reduced thermal order to meet the conditions of all the components that are

47
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IPC-7093 March 2011

part of the assembly. The methodology for the analysis guidelines are offered to help the user in developing the
includes the finish on the component package and the proper printed board design and surface mount practices and
compatibility with the alloy that has been chosen to solder requirements but that characterization of the processes used
all of the parts into place. for assembly.
6.1.3.1 PCB Design Guidelines The PCB land pattern
6.1.2 Termination Formats The SON and QFN device
dimensions required for a design are shown in Figure 6–4.
packages are available in both Pullback and No-Pullback
In the figure, the dimensions ZD max and GD min (and ZE
contact configurations and soldering the exposed die attach
max and GE min) are the outside to outside and inside to
pad (DAP) to the PCB optimizes thermal performance. (See
inside land dimensions, respectively. The dimension X and
Section 4.)
Y indicate the width and the length of the land, respectively.
In the Pullback configuration the standard solder pads are Two additional clearances CLL and CPL are also defined to
offset from the edge of the package by 0.1 mm. In the avoid solder bridging.
No-Pullback configuration the standard solder pads extend While CLL defines the minimum distance between land to
and terminate at the edge of the package as compared in land for the corner joints on adjacent sides, CPL defines the
Figure 6–3. minimum distance between the inner tip of the peripheral
The advantage of the No-Pullback design is that the lands and the outer edge of the thermal pad. In developing
end-exposed contact feature offers a more visible solder the land pattern for the SON with contact only on two sides,
fillet after board mounting. the designer can apply the same basic rules. See Figure 6–5.
In order to design a proper land pattern, tolerance analysis
6.1.3 Mounting Conditions In order for components to is required on package and printed board dimensions. The 6
perform at peak level, special considerations must be I/O package outline example illustrated in Figure 6–5 is
addressed to properly design the circuit board and to mount typical of the configuration selected for power amplifiers,
the package. For example, for enhanced thermal, electrical, signal translators and load switching functions.
and board level performance, the exposed die attach pad With contacts only on two sides of the package, the land
(DAP) on the package needs to be soldered to the board pattern and DAP layout is less complex than the quad
using a corresponding thermal pad on the board. Recent data contact variations. The example shown in Figure 6–6 is the
indicate that this may be important for board reliability as land pattern of the 6 I/O devices illustrated in the Figure
well. In addition, to assure proper heat conduction through 6–5.
the board for higher power devices, thermal vias may be
For component tolerances, the profile tolerances usually
needed in the PCB in the thermal pad region. The PCB
given in the package outline drawing are converted into
assembly design should account for the dimensional and
Maximum Material Condition (MMC) and Least Material
manufacturing tolerances of all elements of the design
Condition (LMC) based tolerances. The minimum and
including the package, PCB, and assembly.
maximum values can thus be obtained for various QFN type
There are a number of factors which may impact mounting packages. In order to determine the land pattern dimensions,
BTC packages on the board and the quality of solder joints, three sets of tolerances are involved; one set for the overall
These factors include: amount of solder paste coverage in component tolerances, and the other two sets for the leads
thermal pad region, stencil design for peripheral and thermal on each end. Since it is unrealistic to assume that all three
pad region, type of vias, board thickness, lead finish on the tolerances will be at their worse case, a more realistic RMS
package, surface finish on the board, type of solder paste, (root-mean-square) system is used here as described in
and reflow profile. It should be emphasized that these IPC-7351. See Figure 6–7.

Die Attach Die Attach

Material Mold Compound Material Mold Compound
Gold Wire Gold Wire

Die Die
Cu Cu

Exposed Exposed Die Exposed Exposed Die

Contact Attach Pad Contact Attach Pad

Pullback Terminal No-Pullback Terminal

IPC-7093-6-3

Figure 6-3 Comparing Pullback and No-Pullback Configurations

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March 2011 IPC-7093

The dimension between internal component pads, shown in

ZDMAX Figure 6–7 is not normally shown in package outline
D2'
drawings. Since this dimension is required to determine the
land pattern length, it is calculated as follows:
CLL
CPL
Space between pads [S]min = Amin – 2T1max
Space between pads [S]max = Amin + [S]tol (rms)
ZEMAX GEMIN E2' AEMAX

Where,
[S]tol (rms) = √(Amax – Amin)2 + 2(T1max – T1min)2
The board tolerance defines the difference between the
ADMAX
MMC and LMC of each land pattern dimension and is
Y
GDMIN assumed as 0.05 mm in this example. The placement
tolerance is also assumed as 0.05 mm Diameter of True
Position (DTP), given that most placement machines have
X placement accuracy between 20 and 70 microns. The
IPC-7093-6-4 minimum values for solder joint fillets, defined in Figure
Figure 6-4 Land Pattern and DAP Land Layout Guide
6–8, used to calculate the land pattern dimensions are:

IPC-7093-6-5

Figure 6-5 Basic Outline Drawing for the 6 I/O SON

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IPC-7093 March 2011

solder fillets cannot be formed on these sides. The fourth

side, however, has either all or half of the thickness of the
lead exposed on the side of the package, depending on the
full lead or lead pull back options. Since the pad pattern
dimension is most likely to be larger than the nominal lead
dimension, solder joints may assume some angular shape or
fillets as shown in Figure 6–8 for full lead option.
It should be noted that the formation of toe fillets is not
guaranteed unless specific measures are taken (usually by
the BTC supplier) to ensure solder wetting to the sides of
the leads during typical reflow assembly. It is generally
observed, however, that the toe fillets are formed depending
on the type of solder paste used and length of exposure of
package to environment. The toe fillet, if formed, will
improve the solder joint reliability and allocation must be
made for its formation. Although the toe fillet is not
expected to form for the lead pullback option, the same land
IPC-7093-6-6 pattern as the one for full lead option can be used for this
Figure 6-6 Recommended Land Pattern for JEDEC 6 I/O design. Table 6–1 shows the target conditions for three
SON Package variations of land patterns.

6.1.3.2 Land Pattern Design Calculations With the as-

sumptions and tolerances previously described, the land
W
1 6 pattern dimensions are determined by using the following
P relations:
B 2 5
3 4 Zmax = Amin + 2JT + TT
Xmax = Wmin + 2JS + TS
A Gmin = Smax – 2JH – TH

H Where:
TT, TH, and TS are the RMS values of toe, heel and side
T tolerance accounting for component, board, and placement
IPC-7093-6-7
tolerances.
Figure 6-7 QFN Component and Land Pattern Composite
The calculations for these values are defined in more detail
in IPC-7351 document. The above calculation for Gmin does
not account for the leads on all four sides of the package. In
order to include this and to avoid any solder bridging
A between the two perpendicular leads on each corner, a
EXPOSED minimum clearance, CLL, is needed. This clearance is
COPPER
(Cu) assumed as 0.1 mm and the final value of Gmin is determined
by using the following constraint:
Gmin ≥ Amax + 2 CLL
JH JT JS Where:
A SEC. A-A
Amax = (Lead Pitch) X (# of leads on one side –1) + Pad
IPC-7093-6-8
Width
Figure 6-8 Definition of Toe, Heel and Side Fillets
Finally, the pad length is determined as:
Minimum Toe Fillet = JT min = 0.1 mm
Y = (Zmax – Gmin)/2
Minimum Heel Fillet = JH min = 0.05 mm
Using the above methodology, the perimeter land pattern
Minimum Side Fillet = JS min = 0.0 mm
dimensions for various QFN packages with full-lead option
The values are selected recognizing that both sides and one are listed in Table 6–2. It should be noted that the calculated
end of the leads are embedded in the mold compound and Xmax dimension (pad width) from the above equations is

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March 2011 IPC-7093

Table 6-1 Quad Flat No Lead Tolerance Goals for Solder Joint Formation
Minimum (Least) Median (Nominal) Maximum (Most)
Lead Part Density Level C Density Level B Density Level A

Toe (JT) 0.20 0.30 0.40

Heel (JH) 0.00 0.00 0.00
Side (JS) -0.04 -0.04 -0.04
Round-off factor Round off to the nearest two place decimal, i.e., 1.00, 1.05, 1.10, 1.15
Courtyard excess 0.1 0.25 0.5
Note: The rationale for the relatively large negative heel stems from the tolerances for the lead lengths as also being relatively large. To maintain a minimum
clearance of 0.20 mm to the thermal tab it becomes necessary to trim the heel by -0.2 mm. Without a thermal tab the heel can usually be increased to as
much as 0.50 mm.

reduced for 0.4 and 0.5 mm pitch devices to avoid any 6.1.3.4 Land Pattern Design Adjustment To ensure a
solder bridging issues. The pads may also be rounded on the robust design and to minimize any possibility of solder
inner edge. Also, because of rectangular dimension of the bridging during board assembly, a minimum metal-to-metal
package in most cases, the suffix D and E from dimension clearance of 0.2 mm is required. Therefore, a final adjust-
notations in Figure 6–4 (e.g., ZD and ZE) are dropped in the ment to the land pattern is made by overlaying the package
table and it is implied that Zmax = ZDmax = ZEmax. outline with the maximum metal dimensions and adjusting
the land pattern to maintain 0.2 mm minimum metal-to-
The Xmax dimension reduced for the 0.4 and 0.5 mm pitch metal clearance. Land pattern dimensions are determined
devices to avoid solder bridging. Refer to ‘Exposed Pad initially using the following:
Variations’ in the Package Outline Drawing for specific D2
and E2 dimensions. D2’ should be equal to Component D2 Zmax = Amin + 2JT + TT
or D2’TH max above, whichever is minimum. Analysis of
the land pattern geometry requires the consideration of a) Note: Amin is the package external outline minimum value.
component tolerances, b) the PCB tolerances, and c) the See Figure 6–10.
accuracy of the equipment used for placing the component.
In addition, minimum values of toe, heel, and side fillets 6.1.3.5 Thermal Pad Design As noted, BTC devices are
must be considered for the formation of reliable solder designed with an exposed thermal pad to conduct heat away
joints. from the package and into the PCB. By incorporating
thermal vias into the PCB thermal pad, heat is dissipated
more effectively into the inner metal layers of the PCB.
6.1.3.3 PCB Land Pattern Development The PCB land
Depending upon the package pad size, the PCB thermal pad
pattern for the QFN may be furnished by the component
size is modified to avoid solder bridging between the
manufacturer, guidelines developed by the board assembler,
thermal pad and the perimeter pads. This is done by defining
or by following an industry standard such as IPC-7351.
a minimum clearance between the outer edges of the
Because of exposed thermal paddle and the package perim-
thermal pad and the inner edges of the perimeter pads. This
eter pads on the bottom side of the package, constraints
minimum clearance is fixed at 0.2 mm.
should be added to the IPC methodology.
The number of thermal vias incorporated into the design
The tolerance analysis requires the consideration of: will depend on the power dissipation and electrical require-
• Component tolerances ments of the specific application. There is a point of
diminishing returns where additional thermal vias may not
• PCB tolerances significantly improve the performance of the package. This
• Accuracy of the equipment used for placing the compo- is shown in Figure 6–11 where the effect of number of vias
nent is plotted for 7 mm x 7 mm, 48-lead packages.

The PCB land pattern for the BTC defined in Figure 6–9. A via diameter of 0.3 mm is used for this simulation. As the
via pitch decreases, more vias can be incorporated for the
The thermal land is a metal (normally copper) region same thermal pad size; however, the incremental perfor-
centrally located under the package and on top of the PCB. mance improvement reduces. Thermal vias are necessary
It has a rectangular or square shape and should match the because they conduct heat from the exposed pad of the
dimensions of the exposed DAP on the bottom of the package to the ground plane. The number of vias is
package (1:1 ratio). The legend for the mechanical dimen- application specific and is dependent upon electrical re-
sions referenced in Figure 6–9 is furnished in Table 6–3. quirements and power dissipation. The thermal performance

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IPC-7093 March 2011

Table 6-2 Package and Land Pattern (Pullback and No-Pullback) Dimensions
Package Package Dimensions with Tolerance Board Land Pattern Dimensions
Leads/ Lead D D E E b b L L D2’th
Size I/O Side Pitch (min) (max) (min) (max) (min) (max) (min) (max) Xmax Yref Amax Gmin Zmax max

8
6x5 4 1.27 5.90 6.10 4.90 5.10 0.35 0.47 0.5 0.7 0.50 0.96 NA 4.39 6.31 4.09
(dual)

3x3 12 3 0.8 2.90 3.10 2.90 3.10 0.28 0.40 0.5 0.7 0.42 0.57 2.02 2.17 3.31 1.87
4x4 12 3 0.8 3.90 4.10 3.90 4.10 0.28 0.40 0.5 0.7 0.42 0.96 2.02 2.39 4.31 2.09
5x5 16 4 0.8 4.90 5.10 4.90 5.10 0.28 0.40 0.5 0.7 0.42 0.96 2.82 3.39 5.31 3.09
6x6 20 5 0.8 5.90 6.10 5.90 6.10 0.28 0.40 0.5 0.7 0.42 0.96 3.62 4.39 6.31 4.09
7x7 28 7 0.8 6.90 7.10 6.90 7.10 0.28 0.40 0.5 0.7 0.42 0.96 5.22 5.39 7.31 5.09
8x8 32 8 0.8 7.90 8.10 7.90 8.10 0.28 0.40 0.5 0.7 0.42 0.96 6.02 6.39 8.31 6.09
9x9 36 9 0.8 8.90 9.10 8.90 9.10 0.28 0.40 0.5 0.7 0.42 0.96 6.82 7.39 9.31 7.09
10x10 44 11 0.8 9.90 10.10 9.90 10.10 0.28 0.40 0.5 0.7 0.42 0.87 8.42 8.57 10.31 8.27
8
2x3 4 0.65 1.90 2.10 2.90 3.10 0.23 0.35 0.3 0.5 0.37 0.76 NA 0.79 2.31 0.49
(dual)
8
3x3 4 0.65 2.90 3.10 2.90 3.10 0.23 0.35 0.5 0.7 0.37 0.96 NA 1.39 3.31 1.09
(dual)
4x4 16 4 0.65 3.90 4.10 3.90 4.10 0.23 0.35 0.5 0.7 0.37 0.92 2.32 2.47 4.31 2.17
5x5 20 5 0.65 4.90 5.10 4.90 5.10 0.23 0.35 0.5 0.7 0.37 0.96 2.97 3.39 5.31 3.09
6x6 28 7 0.65 5.90 6.10 5.90 6.10 0.23 0.35 0.5 0.7 0.37 0.95 4.27 4.42 6.31 4/12
7x7 32 8 0.65 6.90 7.10 6.90 7.10 0.23 0.35 0.5 0.7 0.37 0.96 4.92 5.39 7.31 5.09
8x8 40 10 0.65 7.90 8.10 7.90 8.10 0.23 0.35 0.5 0.7 0.37 0.96 6.22 6.39 8.31 6.09
9x9 44 11 0.65 8.90 9.10 8.90 9.10 0.23 0.35 0.5 0.7 0.37 0.96 6.87 7.39 9.31 7.09
10x10 52 13 0.65 9.90 10.10 9.90 10.10 0.23 0.35 0.5 0.7 0.37 0.96 8.17 8.39 10.31 8.09
3x3 8 2 0.50 2.90 3.10 2.90 3.10 0.18 0.30 0.5 0.7 0.28 0.96 0.78 1.39 3.31 1.09
3x3 12 3 0.50 2.90 3.10 2.90 3.10 0.18 0.30 0.5 0.7 0.28 0.94 1.28 1.43 3.31 1.13
3x3 16 4 0.50 2.90 3.10 2.90 3.10 0.18 0.30 0.3 0.5 0.28 0.69 1.78 1.93 3.31 1.63
4x4 20 5 0.50 3.90 4.10 3.90 4.10 0.18 0.30 0.5 0.7 0.28 0.94 2.28 2.43 4.31 2.13
4x4 24 6 0.50 3.90 4.10 3.90 4.10 0.18 0.30 0.3 0.5 0.28 0.69 2.78 2.93 4.31 2.63
5x5 28 7 0.50 4.90 5.10 4.90 5.10 0.18 0.30 0.5 0.7 0.28 0.94 3.28 3.43 5.31 3.13
5x5 32 8 0.50 4.90 5.10 4.90 5.10 0.18 0.30 0.3 0.5 0.28 0.69 3.78 3.93 5.31 3.63
6x6 36 9 0.50 5.90 6.10 5.90 6.10 0.18 0.30 0.5 0.7 0.28 0.94 4.28 4.43 6.31 4.13
6x6 40 10 0.50 5.90 6.10 5.90 6.10 0.18 0.30 0.3 0.5 0.28 0.69 4.78 4.93 6.31 4.63
7x7 44 11 0.50 6.90 7.10 6.90 7.10 0.18 0.30 0.5 0.7 0.28 0.94 5.28 5.43 7.31 5.13
7x7 48 12 0.50 6.90 7.10 6.90 7.10 0.18 0.30 0.3 0.5 0.28 0.69 5.78 5.93 7.31 5.63
8x8 52 13 0.50 7.90 8.10 7.90 8.10 0.18 0.30 0.5 0.7 0.28 0.94 6.28 6.43 8.31 6.13
8x8 56 14 0.50 7.90 8.10 7.90 8.10 0.18 0.30 0.3 0.5 0.28 0.69 6.78 6.93 8.31 6.63
9x9 60 15 0.50 8.90 9.10 8.90 9.10 0.18 0.30 0.5 0.7 0.28 0.94 7.28 7.43 9.31 7.13
9x9 64 16 0.50 8.90 9.10 8.90 9.10 0.18 0.30 0.3 0.5 0.28 0.69 7.78 7.93 9.31 7.63
10x10 68 17 0.50 9.90 10.10 9.90 10.10 0.18 0.30 0.5 0.7 0.28 0.94 8.28 8.43 10.31 8.13
10x10 72 18 0.50 9.90 10.10 9.90 10.10 0.18 0.30 0.3 0.5 0.28 0.69 8.78 8.93 10.31 8.63
8x8 68 17 0.4 7.90 8.10 7.90 8.10 0.15 0.25 0.3 0.5 0.25 0.76 6.65 6.80 8.31 6.50
10x10 84 21 0.4 9.90 10.10 9.90 10.10 0.15 0.25 0.3 0.5 0.25 0.76 8.25 8.79 10.31 8.49
12x12 100 25 0.4 11.90 12.10 11.90 12.10 0.15 0.25 0.5 0.7 0.25 0.96 9.85 10.39 12.31 10.09

of a package may be improved by increasing the number of should be at least 75 µ larger than the via hole diameter. The
vias. Figure 6–12 shows the effect for a 36 I/O BTC with a solder mask thickness should be the same across the entire
9 x 9 mm body and 7 x7 mm pad. PCB.
The via diameter should be 0.2 mm to 0.33 mm with 1 oz. Two via diameters illustrated are 0.2 mm and 0.33 mm.
copper via barrel plating. It is important to plug the via to Different patterns are also shown to depict possible layouts
avoid any solder wicking inside the via during the soldering for specific numbers of vias. Two die sizes are shown in this
process. The thermal vias can be tented with solder mask on example, 2.1 mm x 2.1 mm and 6.4 mm x 6.4 mm. For a
the top surface of the PCB. The solder mask diameter given number of vias, placing the vias toward the periphery

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March 2011 IPC-7093

Pin 1 Mark Options V2

A
A V1

E E

B
B

C C

D V2

Pull back QFN package (bottom view) PCB land pattern layout

Pin 1 Mark Options V2

A A V1

E E

B B

C C1

D
D

No-Pull back QFN package (bottom view) PCB land pattern layout
IPC-7093-6-9

Figure 6-9 Comparing Pull Back to no-Pull Back Package Outline and Land Pattern Thermal Land Layout

of the pad provides up to 5% improvement over centrally Because the copper etching process has tighter control than
placed vias. There is diminishing improvement, however, as the solder masking process, NSMD is preferred over SMD.
the number of vias increases. The solder mask opening on NSMD pads is larger than the
copper land to allow the solder to adhere to the sides of the
6.1.3.6 Solder Mask Design Two types of land patterns copper land, improving reliability of the solder joints.
are used for surface mount packages: ‘Non-Solder Mask
Defined’ lands (NSMD) and ‘Solder Mask Defined’ lands The recommended solder mask opening should be 120 µm
(SMD). NSMD has an opening that is slightly larger than to 150 µm larger than the copper land size to allow for
the land geometry, while the SMD land surface is defined by solder mask registration tolerances, typically between
a solder mask opening that is smaller than the metal land 50 µm to 65 µm. The solder mask web must be a minimum
geometry. Figure 6–13 illustrates the two different types of of 75 µm in width to adhere to the PCB surface. This
solder mask to land pattern geometry. constraint allows each land to be individually masked for

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IPC-7093 March 2011

Table 6-3 Legend for Basic Mechanical Attributes dimension is close to the theoretical maximum, it is recom-
Dimensions A, B, C, D, and E of PCB are 1:1 ratio with mended that the thermal pad area should be solder mask
package pad dimensions. For specific detailed package defined in order to avoid any solder bridging between the
dimensions, refer to respective marketing outlines. thermal pad and the perimeter pads. The mask opening
Terminal Pitch A should be 100 microns smaller than the thermal pad size on
Terminal Width B all four sides. This will guarantee 25 µm solder mask
Terminal Length C
overlap even for the worse case mis-registration.
Exposed DAP Width D
6.1.4 Package Tolerances The JEDEC design guideline
Exposed DAP Length E
standard for QFN package family detailed in Section 4
Thermal Via Diameter. Recom- V1
mended 0.2 – 0.33 mm applies to packages with optional thermal enhancements as
Thermal Via Pitch. Recommended V2 well as various height profiles and pitches. This package has
1.27 mm terminals on all four edges of the bottom surface of the
Source: National Semiconductor package. A BTC may have either square or rectangular body
outline as well as either symmetric or asymmetric terminal
patterns. Versions of the package may also have terminals
placed in the corners at 45° to neighboring leads. The basic
W1
dimensions for the package outline are in increments of
W
0.50 mm ranging from 1.00 mm through 12.00 mm. See
1 6 Figure 6–15.
P
B 2 5 T1
The outline detail shown in Figure 6–15 illustrates the
3 4
primary package outline dimensions used when developing
the land pattern and thermal pad geometries. The width of
A the metallized terminals (including lead finish) exposed at
H the bottom surface of the package are detailed in Table 6–4.
The component tolerances and profile tolerances usually
T
IPC-7093-6-10 given in the package outline drawings are converted into
maximum material condition (MMC) and least material
Figure 6–10 SON 0.5 mm Pitch, 6 Pin with Thermal Tab
condition (LMC) based tolerances.

6.1.4.1 Circuit Routing, Thermal Pad and Via Design

For best performance, all circuit traces should be as short as
possible. To be most effective, the input and output capaci-
THERMAL tors should be placed close to the BTC device to minimize
VIA parasitic trace inductance. Using wide conductors for V-IN,
V-OUT and GND will help minimize parasitic electrical
effects along with enhancing the thermal transfer between
the case and the ambient environment.
THERMAL
PADDLE Additional good practices are:

IPC-7093-6-11
• Dedicate an internal power plane to spread the heat and
optimize thermal dissipation.
Figure 6-11 DAP to PCB Interface Example
• Make the heat sink plane within the circuit board as large
lead pitches of 0.5 mm and higher. However, for 0.4 mm as possible to minimize board and die temperature.
pitch parts with PCB land width of 0.25 mm, not enough • Use conductive copper plated vias to make the electrical
space is available for solder mask web in between the lands. and thermal tie to the heat sink plane.
It is recommended to use a trench type solder mask opening
As stated, the SON and QFN package is designed to provide
where a big opening is designed around all lands on each
a superior thermal performance. This is partly achieved by
side of the package with no solder mask in between the
incorporating an exposed die paddle on the bottom surface
lands, as shown in Figure 6–14.
of the package. However, in order to take full advantage of
It is better to round the inner edge of the solder mask, this feature, the PCB must have features to effectively
especially for corner leads, to allow for enough solder mask conduct heat away from the package. This can be achieved
web in the corner area. For the cases where thermal land by incorporating thermal pad and thermal vias on the PCB.

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March 2011 IPC-7093

40

D via = 0.33mm

36

D via = 0.33mm
32

D via = 0.33mm
(ºC/W)

28

24 Die: 2.1 x 2.1mm

20

Die: 6.4 x 6.4mm

16
0 4 8 12 16 20 24 28 32 36 40

Number of Vias
IPC-7093-6-12

Figure 6–12 The Affect of θJA vs. Number, Distribution and Diameter of Thermal Vias and Die Sizes for a 36 I/O QFN with a
9 x 9 mm Body and 7x7 mm Thermal Land

Solder Mask Land Land Solder Mask

Substrate

NSMD SMD
IPC-7093-6-13

Figure 6–13 Comparing Optional Solder Mask Variations

While a thermal pad provides a solderable surface on the top

surface of the PCB (to solder the package die pad on the
board), thermal vias are needed to achieve a suitable thermal
path to inner and/or bottom layers of the PCB to remove the
heat.
(A) Generally, the size of the thermal pad on the PCB should
SOLDER
MASK
match the exposed die paddle feature provided on the
device. However, depending upon the die paddle size, this
size needs to be modified in some cases to avoid solder
bridging between thermal pad and the perimeter pads. This
is done by defining a clearance between the outer edges of
(B)
IPC-7093-6-14 the thermal pad and the inner edges of perimeter pads. It
should be noted that the D2'TH dimension gives the
Figure 6–14 Solder Mask for (A) Perimeter Lands for 0.5
theoretical maximum value. Since the size of the exposed
mm and Higher Pitch Parts, and (B) for 0.4 mm Pitch Parts
die paddle on the component may actually be much smaller

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IPC-7093 March 2011

A
D PITCH
PIN 1
BSC INDICATOR
37 48
36 1
PIN 1
INDICATOR b

EXPOSED
TOP PAD E2
E
VIEW BSC (BOTTOM VIEW)

L 25 12
24 13
0.25 MIN
5.50
REF
IPC-7093-6-15

Figure 6–15 Representative BTC Outline Detail

Table 6-4 Contact Pitch and Width Variations shown in Figure 6–16 where the effect of number of vias
Terminal Dimension plotted for 7 mm x 7 mm, 48 contact package. A via
Contact Pitch Minimal Nominal Maximum diameter of 0.3 mm was used for this simulation. As the via
pitch decreases more vias can be incorporated for the same
0.65 0.25 0.30 0.35
thermal pad size but the incremental performance improve-
0.50 0.18 0.25 0.30
ment diminishes.
0.40 0.15 0.20 0.25
With this constraint, the maximum size of the thermal pad is
calculated by the following relationship and is listed under
than this value, the actual D2' dimension should be modified the graph in figure 6–16 for various package sizes. Based on
by Component D2 ≤ D2' ≤ D2'TH max Note: QFN with this and similar thermal simulations, it is recommended that
down-bond ring design does not require the ring to be an array of thermal vias should be incorporated at 1.0 mm
soldered to the board. The thermal pad design on the board to 1.2 mm pitch with via diameter of 0.3 mm to 0.33 mm.
should be based on the exposed paddle area, excluding the Representative of these arrays are shown in Figure 6–17 for
ring area. 7x7 mm, 48 lead and 10x10 mm, 68 lead packages.
In order to effectively transfer heat from the top metal layer
of the PCB to the inner or bottom layers, thermal vias need 6.1.4.2 Standard Grids Standard grids offer the potential
to be incorporated into the thermal pad design. The number for significant improvement in routing and BTC compo-
of thermal vias will depend on the application and power nents are key. The industry is presently compelled to deal
dissipation and electrical requirements. Although more with legacy component lead pitches because of the long
thermal vias improve the package thermal performance, established precedent. The now registered and accepted
there is a point of diminishing returns as additional thermal range of options include: 0.100” (2.54 mm) which was the
vias may not significantly improve the performance. This is original single de facto standard for IC components. It has

30

29

28

27
(C/W)

26

25

24

# of Vias 4 9 16 36
Matrix 2x2 3x3 4x4 6x6
Pitch (mm) 2.4 1.8 1.2 0.9
IPC-7093-6-16

Figure 6–16 Effect of Number of Thermal Via on Package Thermal Performance

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March 2011 IPC-7093

wiring. Adding additional layers to make all of the required

connections may actually reduce circuit performance. See
Figure 6–18.

IPC-7093-6-17

Figure 6–17 PCB Thermal Pad and Via Array for 7x7 mm,
48 lead and 10x10 mm, 68 Lead Packages

the advantage of allowing the designer to lay out his entire 80% Rule Standard Base Grid
IPC-7093-6-18
design using that value as a fundamental pitch. The first full
metric pitch of 1.0 mm was established, from this point on Figure 6–18 Comparison of the 80% Rule with Standard
the “80% Rule” has been in effect. The component pitches Grid Systems for Routing Improvement
for IC packages that followed in service of the new
convention were 0.8 mm, 0.65 mm, 0.5 mm, 0.4 mm and BTC area array components based on the “80% Rule”,
0.3 mm. increase routing complexity requiring more sophisticated
routing tools. Note that only 2 of the 5 grid pitches derived
The key thing to remember is that the “80% Rule” has been
from the concept have the ability to conform to a common
applied regardless of the component lead configuration, be
grid based on the smallest defined lead pitch for component
it two sided, four sided or area array. The effect is illustrated
I/O (in this case 0.5 mm). In contrast, on the right side of
in Figure 6–18. As can be seen in the graphic on the left,
Figure 6–18 can be seen a number of components based on
following the de facto 80% rule leads to greatly increase
the use of a common grid pitch where it can be seen that
routing complexity as only 2 of the 5 grid pitches derived
every component lead falls on grid allowing for high
from the concept have ability to conform to a common grid
efficiency “Manhattan routing” of circuits.
based on the smallest defined lead pitch for component I/O
(in this case 0.5 mm which is the accepted lower limit for
effective soldering). This might seem a trivial concern but it 6.1.5 Attachment Techniques Because of the small
has far reaching impact in design. metal pad termination surface area and the sole reliance on
printed solder paste on the PCB surface, care must be taken
If components of varying grid pitch are used in the assembly to form reliable solder joints for BTC packages. This is
as seen on the left side of the figure, the routing of further complicated by the large thermal pad underneath the
interconnections will be more complex and more sophisti- package and its proximity to the inner edges of the leads.
cated routing tools are required and, more importantly more Although the pad pattern design suggested above might help
layers as well. In contrast, on the right side can be seen the in eliminating some of the surface mounting problems,
same number of components with placement based on the special considerations are needed in stencil design and paste
use of a common grid pitch and wherein it can be seen that printing for both perimeter and thermal pads. Since surface
every component lead falls on grid. “Manhattan routing” is mount processes vary from company to company, careful
the term frequently used for electronic circuits using the process development is recommended.
principals of base grid, street and avenue routing. This has
a number of compelling benefits.
6.1.5.1 Stencil Design for Perimeter Pads Though it is
For example, there is potential for much improved routabil- not commonly their responsibility, the designer of the PCB
ity as the streets and avenues used for routing channels are should understand stencil design requirements. In general,
perfectly defined making the routing much easier and faster. the optimum and reliable solder joints on the perimeter pads
No less important is all of the circuit board real estate which should have about 50 µm to 75 µm standoff height and
can be potentially returned to use for components. Clearly, desirably, a fillet on the outside terminal ends if possible. A
the mixture of peripheral and area array leads of various solder joint with good standoff height but no fillet, or
lead pitches results in much more complex circuit routing minimal fillet at the terminal end, should still provide a
challenges. This necessitates the distancing of components reliable interface for most applications. The first step in
and addition of many more circuit layers than would achieving good standoff is the solder paste stencil design for
normally be required to accommodate the redistribution perimeter pads. The stencil aperture opening should be so

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IPC-7093 March 2011

designed that maximum paste release is achieved. This is provide smaller multiple openings. This will typically result
typically accomplished by considering the following two in 50 to 80% solder paste coverage.
ratios:
1. Area Ratio = Area of Aperture Opening/Aperture Wall 6.1.5.3 Via Types and Solder Voiding Voids within sol-
Area; and der joints can have an adverse effect on high speed and RF
2. Aspect Ratio = Aperture Width/ Stencil Thickness applications as well as on thermal performance. As the
typical BTC package incorporates a large center pad,
For rectangular aperture openings, as required for this
controlling solder voiding within this region can be difficult.
package, these ratios are given as Area Ratio =
Voids within this center plane can increase the current path
LW/2T(L+W), and Aspect Ratio = W/T, Where L and W are
of the circuit. The maximum size for a void should be less
the aperture length and width, and T is stencil thickness. For
than the via pitch within the plane. This recommendation
optimum paste release the area and aspect ratios should be
greater than 0.66 and 1.5 respectively. It is recommended would assure that any one via would not be rendered
that the stencil aperture should be 1:1 to PCB land sizes as ineffectual based on any one void increasing the current
both area and aspect ratio targets are easily achieved by this path beyond the distance to the next available via.
aperture. The opening can be reduced for the lead pullback
The presence of small voids in the thermal pad region is not
option because of reduction of solderable area on the
likely to result in degradation of thermal and electrical
package. The stencil should be laser cut and electro pol-
performance. The specific thermal simulation shown in
ished. The polishing helps in smoothing the stencil walls
Figure 6–19 indicates that combining smaller multiple voids
which results in better paste release. It is also recommended
up to 50% of the thermal pad area, does not result in a loss
that the stencil aperture tolerances should be tightly con-
in thermal performance. It should also be noted that the
trolled, especially for 0.4 mm and 0.5 mm pitch devices, as
voids in thermal pad region do not impact the reliability of
these tolerances can effectively reduce the aperture size.
perimeter solder joints.
More detailed information for stencil development is avail-
able in IPC-7525. Large voids in thermal pad area should be avoided. In order
to control these voids, via filling may be required. Filling
6.1.5.2 Stencil Design for Thermal Pad In order to the via holes, located in the DAP area, will prevent solder
effectively remove the heat from the package and to from wicking inside the via during the reflow solder
enhance electrical performance the die pad needs to be process. There are different methods employed within the
soldered to the PCB thermal pad. For larger thermal pad industry for this purpose: “via tenting” (from top or bottom
geometry it is recommended that the stencil be designed to side) using dry film solder mask, “via plugging” with liquid

Thermal Performance vs. Solder void %

6mm MLF 36ld

60

50 JA
JA, JB, JV (ºC/W)

40 JB

JV
30

20

10

0
0 50 100

Solder void, %
IPC-7093-6-19

Figure 6–19 Effect of Voids on Thermal Performance

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March 2011 IPC-7093

photo-imageable (LPI) solder mask from the bottom side, pad (<0.002 in). By accepting larger depressions, air/gas
“via encroaching,” or “via capping.” Via filling is discussed entrapment within the depression may create voids that
more in 5.4.4.2. bridge between vias.

All of these options have pros and cons when mounting 6.1.5.4 Solder Joint Standoff Height and Fillet For-
QFN package on the board. While via tenting from top side mation The design should facilitate the creation of a
may result in smaller voids, the presence of solder mask on suitable solder joint standoff. Solder joint standoff is a direct
the top side of the board may hinder proper paste printing. function of amount of paste coverage on the thermal pad
On the other hand, both via tenting from bottom or via and the type of vias used for BTCs with an exposed pad at
plugging from bottom may result in larger voids due to the bottom. It is worthwhile for the designer to know, that
out-gassing, covering more than two vias. Finally, en- board mounting studies have shown that the package
croached vias allow the solder to wick inside the vias and standoff increases by increasing the paste coverage and by
reduce the size of the voids. However, it also results in using plugged vias in the thermal pad region.
lower standoff of the package, which is controlled by the The standoff height varies by the amount of solder that wets
solder underneath the exposed pad. Figure 6–20 shows or flows into the PTH via. The encroached via provides an
representative X-ray pictures of QFN packages mounted on easy path for solder to flow into the PTH and decreases
boards with different via treatments. In case of via tenting, package standoff height while the plugged via impedes the
the solder mask diameter should be 100 µm larger than via flow of solder into the via due to the plugged via’s closed
diameter. barrel end. In addition, the number of vias and their finished
hole size will also influence the standoff height for en-
Encroached via, depending on the board thickness and croached via design. The standoff height is also affected by
amount of solder printed underneath the exposed pad, can the type and reactivity of solder paste used during assembly,
result in solder protruding from the other side of the board. PCB thickness and surface finish, and reflow profile. To
It should be noted that the vias are not completely filled with achieve the preferred 50 µm thick solder joints it is
solder, suggesting that solder wets down the via walls until recommended that the solder paste coverage be at least 50%
the ends are plugged. This protrusion is a function of PCB for plugged vias and 75% for encroached via types.
thickness, amount of paste coverage in the thermal pad
region, and the surface finish of the PCB. Manufacturers The peripheral solder joint fillets formation is also driven by
note that this protrusion can be avoided by using lower multiple factors. Due to the singulation process during
volume of solder paste and reflow peak temperature of less package assembly, a majority of the commercial non-
than 215°C in the case of SnPb soldering. pullback BTC devices are furnished with uncoated copper
on the exposed terminal ends. The resulting bare copper on
Via filling and capping is a good option to prevent the issues these surfaces will oxidize and may compromise solder
with tenting, flooding, and encroach vias though it does wetting during typical reflow assembly process, especially
require a secondary process. It is important to ensure that if the packages are not stored in a controlled environment.
the capping process produces minimal depressions in the Additional measures would need to be taken by suppliers to

Plugged Vias Encroached Vias

IPC-7093-6-20

Figure 6–20 X-Ray Example Showing Voids in the Thermal Pad

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IPC-7093 March 2011

IPC-7093-6-21

Figure 6–21 Solder Protrusion from the Bottom Side of PCB for Encroached Vias

coat or plate exposed copper terminal ends to ensure solder lead-free HASL is being reconsidered by some despite
wetting. It is, however, possible that a solder fillet will be board warpage and uneven solder surface. When using
formed depending on the solder paste (flux) used and the immersion tin, some concern should be considered due to
level of oxidation. solderability and health concerns.
The fillet formation is also a function of PCB land size, For an (ENIG) electroless nickel immersion gold finish, the
printed solder volume, and the package standoff height. The gold thickness should range from 0.05 µm to 0.20 µm to
land size concepts for toe and heel fillets, along with 1:1 avoid solder joint gold embrittlement. ENIG is a good
aperture, will provide sufficient solder for fillet formation if choice but has black pad concerns; however, the concern is
the package standoff is not excessive. Since there is only generally for PCBs when using BGAs. Black pad is less of
limited solder available, higher standoff—controlled by a concern with BTCs.
paste coverage on the thermal pad—may not leave enough
solder for fillet formation. Conversely, if the standoff is too Using a PCB with Organic Solderability Preservative coat-
low, large convex shape fillets may form. ing (OSP) finish is also recommended as an alternative to
Ni-Au. A high temperature OSP must be utilized if perform-
When solder wetting to the exposed terminal ends of the ing a lead-free soldering process. OSPs may not survive
BTC leads does occur, solder fillets will form along the multiple reflow processes such as for double sided assem-
BTC perimeter, especially when these parts are mounted on blies. OSP is a good choice (lower cost) but multiple reflow
the PCB with a protruding land pattern and 1:1 stencil or hole-fill in wave are some of the key concerns in OSP.
aperture for peripheral located land patterns. Since center High temp OSPs are available to address these concerns but
land coverage and via type were shown to have the greatest they do add to the cost.
impact on standoff height, the volume of solder necessary to
create optimum fillet varies. Immersion silver is acceptable as a flat surface but other
issues such as champagne voiding and caving from inad-
If protrusion of the solder through thermal vias cannot be
equate plating processes are concerns and must be ad-
avoided, the components may have to be assembled on the
dressed. Also, immersion silver shelf life is limited and this
top side (or final pass) assembly, as the protruded solder will
plating type will tarnish if not protected and may not be
impede acceptable solder paste printing on the other side of
suitable for assemblies requiring multiple reflows. Immer-
the PCB. See Figure 6–21.
sion Silver addresses most of the issues in OSP but planar
microvoids, creeping corrosion and tarnishing in salty and
7 ASSEMBLY OF BTCs ON PRINTED BOARDS sulfur environments are a concern.
The assembly processes for attaching BTCs requires careful
For a PCB with Hot Air Solder Leveling (HASL) finish, the
process development and control. Process defect rates can
surface flatness should be understood and monitored to
be significantly reduced: however good process control is a
ensure uniform solder connections across the BTC.
necessity.
Since all surface finishes of some concerns, it may be wise
7.1 PCB Surface Finish Requirements A uniform PCB to consider two finishes: OSP for single sided; ENIG and
plating thickness is key for high assembly yield. There is no immersion silver for double sided and mixed (SMT and
perfect surface finish. All finishes have some issues. Even Through Hole) boards. Use of nitrogen in reflow and wave

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March 2011 IPC-7093

will allow additional flexibility in using OSP but one can get The solder pad on the device should be aligned with the
away without nitrogen with ENIG even when using no clean lands on the board such that a complete solder connection is
flux. Use of aggressive flux allows additional flexibility. made between the device pad and the board land. Also, it is
When using aggressive flux, OSP can be used even without recommended for pull-back packages that the board land
nitrogen. So it is important to keep in mind that use of extend beyond the outer edge of the device package to allow
nitrogen, type of flux, reliability concerns and cost sen- visual access for inspection of solder joint flow.
sitivity play a critical role selection of surface finish. See
Section 5. 7.2.1 Consideration for Soldering Process Because of
the small terminal pad surface area and the sole reliance on
For more information on surface finishes, see IPC-2221 and
printed solder paste on the PCB surface, care must be taken
IPC-6012.
to form reliable solder joints for BTC packages. This is
further complicated by the large thermal pad underneath
7.2 PCB Design Proper land pattern design is critical for
some BTC packages and its proximity to the inner edges of
maintaining high yields and good reliability of BTC solder
the leads. Although the land pattern design might help in
joints. Figure 7–1 shows examples of good BTC land
eliminating some of the surface mounting problems, special
patterns; Figure 7–2 shows examples of poor land patterns
considerations are needed in stencil design and paste print-
for BTC type parts.

IPC-7093-7-1

Figure 7-1 Example of Good Land Patterns for Bottom Termination Components

IPC-7093-7-2

Figure 7-2 Example of Poor Land Patterns for Bottom Termination Components

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IPC-7093 March 2011

ing for both perimeter and thermal pads. Since surface reliable assemblies that use BTC technology. The surface
mount processes vary from company to company, careful mount assembly process uses solder paste to connect the
process development is recommended. BTC terminations to the lands on the board. Solder paste
can be applied to the lands using several methods including
7.2.2 Component Preconditioning Bake BTCs shipped screen or stencil printing and dispensing or jetting.
in moisture barrier bags require special handling to insure
Solder paste consists of a homogeneous mixture of metal
proper surface mount conditions are met. The moisture
powder particles and flux. The metal content (typically 90%
barrier bag will be labeled with the proper instructions
by weight) in the solder paste determines the amount of
concerning the correct handling of the BTCs. BTCs exposed
solid alloy in the solder joint. Metal powder particles are
to room temperature and humidity conditions beyond the
generally spherical in shape. A uniform powder shape aids
cumulative time specified on the label must be baked prior
the printing or dispensing process and it decreases the
to surface mount reflow. The BTC size, thickness and MSL
surface area, which minimizes oxidation.
determine the bake times and conditions. Industry standard
bodies such as JEDEC publish tables with bake times and Flux, solvent and jelling agent makes up the remainder of
temperatures. J-STD-033 should be followed to prevent the solder paste volume. The activators in the flux remove
damaging the BTC devices. oxides from the solder particles, the land patterns, and the
BTC termination surfaces to promote good solderability
7.2.3 Component Preparation for Assembly Compo- during the reflow process. The solvents have an important
nent solder dipping is not recommended for BTC terminal role in controlling the tackiness of the paste and affecting
surface preparation. Dip soldering will not maintain copla- the rheological properties. The formation of voids in the
narity and makes the BTC unproducible during assembly. BTC solder joint may be related to the solvents in the solder
Inconsistent solder on the thermal plane can raise the BTC paste. Solvents with low boiling points and/or improper
and cause the signal terminations to not make contact during reflow parameters can increase the incidence of voids in
reflow creating solder opens. Non uniform solder volume on BTC solder joints.
the signal terminations can also create a non contact
condition resulting in solder opens in random locations. See For successful fine pitch BTC printing, the solder paste must
Figure 7–3. pass through very small apertures in the stencil. The solder
paste needs to remain printable and tacky for an extended
Land pattern and thermal pad geometry on the PCB must be period of time, and it must maintain print definition prior to
sized and aligned to ensure uncompromised electrical and and during reflow. Solder paste viscosity, particle size and
mechanical interface with the BTC device. The example stencil life are critical parameters for solder paste applica-
shown in Figure 7–4 illustrates the potential for compro- tion.
mising the solder interface between surfaces.
Solder paste dispensing is not as widely used as printing due
7.2.4 Solder Paste and its Application The quality of to a reduction in throughput speed; however, selective
the paste print is a critical factor in producing high yield dispensing allows for more flexible paste volume deposition

IPC-7093-7-3

Figure 7-3 Comparison of Solder Dipped and a Non Solder-Dipped BTC and Resultant No Solder Condition

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March 2011 IPC-7093

IPC-7093-7-4

Figure 7-4 Undersized PCB Pads Resulting in Potential Areas Where Pure Tin Finish Has Not Mixed with SnPb Solder Paste

and placement for tighter process control. A technology critical for uniform reflow-solder processing. Stencils are
referred to as solder paste “jetting” has greatly increased usually made of stainless steel or electroformed nickel.
solder deposition speed while still allowing for the flexibil- Apertures should be trapezoidal to ensure uniform release of
ity of volume and placement accuracy. The jetting technol- the solder paste to reduce smearing. The solder joint
ogy, however, requires specific solder paste formulations thickness for the attachment of BTCs should typically be
which may have limited wide industry acceptance. Future 50 µm to 75 µm after reflow.
refinements in the equipment and dispensing methods could
make this technology more viable and desirable as a way of Aperture modifications:
maintaining tighter process control. • Specify ≤0.6 mm radius to inside corners of all apertures

7.2.4.1 Particle Size and Paste Selection A Type 3 or 4,

• Reduce all 0.8 mm pitch and finer aperture widths to
low residue, no-clean solder paste (Sn63/Pb37 or 50% of pitch
96.5Sn/3.0Ag/0.5Cu) is commonly used in mounting BTC • Segment BTC thermal pad apertures to reduce printed
packages; however, water soluble flux materials are also solder volume by 50% or less, or as specified by the
widely used. Solder paste composition is often a compro- manufacturer’s recommendation
mise given the variety of components which must be placed
on a PCB, and special SMT specific solder pastes are being Note: Segmented solder paste deposits may not be required
marketed by solder paste vendors that minimize voiding in on some components. Apertures with a dimension greater
the solder joint. than 5.0 mm [0.200 in] are broken into multiple apertures.

The solder particle size is classified by J-STD-005 (see Stencil thickness:

Table 7–1).
It is recommended to use a 125 µm [0.005 in] stencil thick-
Table 7-1 Particle Size Comparisons ness for ≤ 0.5 mm [0.020 in] pitch or smaller and a 150 µm
Solder paste Maximum par- [0.006 in] stencil thickness for larger pitches. The stencil
type Mesh ticle size [m] may require stepped areas to allow for both small pitches
Type 2 -200/+325 80 and larger pitches on the same board. Typical BTC arrays
Type 3 -325/+500 50 and passive components as small as 0402 and 0201 may
Type 4 -400/+500 40 also require a 125 µm thick stencil.
Type 5 -500 30
The stencil thicknesses should all be considered as recom-
mendations for a Laser Cut stencil. A checkerboard pattern
7.2.4.2 Stencil Thickness and Aperture Design The should be used on large thermal pads. Thickness of the
formation of reliable solder joints is a necessity. The large stencil (C) is usually in the 100 µm to 150 µm [0.004 in to
numbers of terminal contacts on some BTC type parts can 0.006 in] range. The actual thickness of a stencil is
present a challenge in producing a uniform solder print dependent on other surface mount devices on the PCB. A
thickness. To this end, careful consideration must be applied squeegee durometer of 95 or harder or a metal squeegee
to the stencil design. The stencil thickness, as well as the should be used to distribute the paste. The blade angle,
etched pattern geometry, determines the precise volume of pressure, and speed must be fine-tuned to ensure even paste
solder paste deposited onto the device land pattern. Stencil transfer. An inspection of the stenciled board is recom-
alignment accuracy and consistent solder volume transfer is mended before placing parts; as proper stencil application is

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IPC-7093 March 2011

the most important factor with regards to reflow yields later paste rheology, handling time, standoff distance, blade
in the process. See Figure 7–5. hardness and speed, and re-flow process details are critical
in conjunction with careful stencil design to ensure maxi-
In order to effectively remove the heat from the package and
mum yield and minimum failure rates. It is important to find
to enhance electrical performance the die paddle needs to be
out what printing techniques are used at any assembly
soldered to the PCB thermal pad. If the solder paste
facility where the BTC will be installed. Each of these sites
coverage is too large, it is recommended that smaller
should be able to provide recommendations for stencil
multiple openings in stencil be used instead of one big
design limitations.
opening for printing solder paste on the thermal pad region.
This will typically result in 50 to 80% solder paste coverage. Another commonly used ratio and preferred technique is
Some examples of different stencil configurations are shown area ratio. An area ratio of greater than 0.66 is recom-
in Figure 7–6 describing ways to achieve an appropriate mended for laser cut foils. The formula to calculate area
level of coverage. ratio is the area of the stencil aperture divided by the area of
the stencil aperture walls. Area of aperture divided by area
7.2.4.3 Importance of Paste Volume It is very important of aperture walls equals L*W/2*(L+W)*T >0.66.
to design a stencil aperture that will provide good paste
The stencil aperture opening should be designed such that
release. In order to ensure good paste release, an aspect ratio
of 1.5 minimum is recommended for laser cut foils. Aspect maximum paste release is achieved. This is typically ac-
ratio is the ratio between stencil aperture width and stencil complished by considering the following 2 ratios and Figure
thickness. The aspect ratio relates to the manufacture of 7–7.
stencils and the solder paste stencil aperture and/or thick- Area Ratio= LW / 2T (L + W)
ness and may need to be modified to maintain acceptable Aspect Ratio = W/T
aspect ratio.
Where L and W are the aperture length and T is the stencil
Using thicker stencils may increase the probability of thickness
balling and bridging, while compensating for the increased
Aperture Width (W)
thickness with a reduction in aperture size diminishes the Aspect Ratio = > 1.5
Stencil Thickness (T)
release efficiency, leading to less predictable printed vol-
ume. Using thinner stencils necessitates the use of a 1:1 Area of Aperture (L × W)
Area Ratio = > 0.66
Area of Aperture Walls (2 × (L + W) × T)
aperture to feature ratio which increases the chances of even
minor misalignment causing balling, while any reduction in Note: If the apertures are different than described above,
the aperture to feature ratio or less than perfect release then recalculate the area ratio. But for simplicity, the
threatens insufficient volume, starved or open joints, and previous equation may be used and will result in a slightly
may lead to poor mechanical strength. conservative number.
Regardless of the stencil features, proper care must be given Use of electroform stencils can yield success with area
to the printing process at the assembler’s facility and are ratios of <0.6. IPC-7525 Stencil Design Guidelines contains
best handled by qualified technical staff. The preparation, more information on other stencil design rules.

100 µm Thickness 125 µm Thickness 150 µm Thickness

R0.16 R0.08 R0.06

0.690 0.620 0.565

DEVICE AND CIRCUIT BOARD PAD SIZE IS 0.635mm SQUARE

STENCIL APERTURE SIZE

NOT TO SCALE IPC-7093-7-5

Figure 7-5 Recommended Aperture Dimensions for Commonly Used Stencil Thicknesses

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March 2011 IPC-7093

1.5 mm dia. aperture 1.0 mm dia. aperture 1.3x1.3 mm aperture 1.3x1.3 mm aperture
@1.6 mm pitch @1.2 mm pitch @1.65 mm pitch @1.5 mm pitch
37% coverage 50% coverage 68% coverage 81% coverage
IPC-7093-7-6

Figure 7-6 Thermal Pad Stencil Designs for 7x7 mm and 10x10 mm BTC Devices

alignment. This is equipment and process dependent.

L Slightly misaligned parts (less than 25 percent off the land
center) will automatically self-align during reflow (see
Figure 7–8). Grossly misaligned packages (greater than
50% percent off land and pad centers) should be removed
prior to reflow as they may develop electrical shorts, as a
result of solder bridges during reflow solder processing.
W 7.2.5.1 Vision Systems for Placement Accuracy
T Placement accuracy is a very critical part of the BTC
IPC-7093-7-7 process. It is strongly recommended to not move a BTC
Figure 7-7 Solder Stencil Aperture Wall Area
after machine placement to correct placement problems as
this may cause solder bridging in adjacent solder joints,
In addition to the variable constraints in stencil thickness since the connections cannot be seen visually. The place-
and aperture design to balance volume and proper release, ment machine’s accuracy is largely dependent on the vision
gold embrittlement is an issue with some BTC components system and the ability of the nozzle to hold the component.
that have a gold finish (more so when also combined with an Matching the vision system to the application is also
ENIG finish PCB). In order to get enough volume to important. The vision system determines the X, Y and theta
mitigate embrittlement, there may be situations where offset of each component prior to placement. In addition to
thicker stencils or overprinting may be considered. How- determining the component offset, the vision system can
ever, these methods for applying solder can lead to issues also inspect the component for dimensional integrity.
with solder paste release and bridging. Charge-Coupled Device (CCD) camera-based systems em-
ploy two lighting methods, referred to as binary and gray
7.2.5 Component Placement Impact The pick and place scale. Both methods can be sensitive to contrast and lighting
accuracy governs the package placement and rotational changes.

Target Acceptable Not acceptable

< 25% > 25%

IPC-7093-7-8

Figure 7-8 Assessing Maximum Pre-Reflow Off-Land Acceptance

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There are two popular methods for package alignment using desirable for placing BTC components because it eliminates
machine vision: package silhouette, where the vision system placement error due to variations in the component outline.
locates the package outline; and terminal recognition, where
Placement machine nozzle designs vary from supplier to
the vision system locates the terminals or leads of the
supplier. It is important that the correct nozzle is chosen
package.
which will have sufficient surface area to hold the part
Some vision systems can directly locate on the pad metal- without any shifting during the placement process. The
lization pattern. Both methods are acceptable for BTC nozzle must gasket against the part, not allowing vacuum
placement. The terminal recognition type alignment tends to leakage. Tactile sensing, which helps control the Z axis
be more accurate, but is also slower since more complex (vertical) stroke of the spindle, is desirable because it
vision processing is required of the pick and place machine. prevents a component from being crushed between the
The package silhouette method allows the pick and place vacuum nozzle and the substrate.
system to run faster, but is generally less accurate. Both
Also, without leads or balls to act as a hard stop or standoff,
methods are acceptable, and have been successfully dem-
extra care must be taken to limit the Z axis pressure of the
onstrated by major pick and place equipment vendors and
part into the solder paste, which can result in solder shorts.
contract PCB assembly houses.
Depending upon the type of pick and place system, a change
7.2.6 Reflow Soldering and Profiling As with all SMT
in package carrier format may be required. Local fiducials
components, it is important that profiles be monitored on all
may also be helpful in helping the vision systems recognize
new board designs. In addition, if there are multiple package
the exact location of the land pattern for the BTC, similar to
types on the board, the thermal profile should be measured
what is used for fine-pitch peripheral leaded parts.
at multiple locations. Component temperatures may vary
Gray scale systems use front lighting, which illuminates the because of surrounding components, location of the device
component from below. Surface features are reflected into on the board, and package densities. To maximize the
the CCD camera for processing. Binary systems use back self-alignment effect of a BTC (see Figure 7–9), it is
lighting, which illuminates the component from above. The recommended that the maximum reflow temperature speci-
outline of the component is projected into the CCD camera fied for the solder paste not be exceeded. A good guide is to
for processing. Binary imaging, which is the older of the subject the PCB to a temperature ramp not exceeding 4°C
two methods, locates a feature using the contrast between per second. The reflow profile guidelines are based on the
black and white images. Gray scale systems can usually temperature at the actual solder pad to PCB land pad solder
interpret 256 levels of contrast. Both systems use an joint location.
algorithm to determine the center of the component. Binary
The actual temperature at the solder joint is often different
imaging requires less computing capability than gray scale
than the temperature settings in the reflow system due to the
imaging.
location of the system thermocouple placement. The reflow
Gray scale imaging places BTC components based on land system needs to be profiled using thermocouples at various
location while binary imaging places BTC components locations on the PC board. Thermocouples should be placed
based on the component outline. In some cases the tolerance on one of the largest as well as the smallest components on
between the BTC outline and the location of the printed the PCB. It is suggested that the peak temperature differen-
board lands is significant. Gray scale imaging is more tial between the smallest and largest package be 10°C or

IPC-7093-7-9

Figure 7-9 Metal Defined Land Solder Joint

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less for average size PC boards. See J-STD-020 for reflow From Table 7–2, it is important to note that the sample BTC
recommendations. BTCs are typically moisture sensitive only achieves a maximum temperature of 240°C even
and fall into level classifications defined by JEDEC. Spe- though the oven temperature is set to 260°C. This is
cific levels are stated on moisture sensitive labels shipped consistent with the reflow requirements of 250°C maximum
with BTC devices. Commercial BTC devices may be for the BTC body temperature. Analyses of the solder joint
compatible with SnPb and/or lead-free solder processing obtained from this profile indicated excellent joint forma-
and the supplier is responsible for defining the maximum tion. Table 7–3 shows the profile variation between a
reflow profile limit (e.g., 215–245°C peak body tempera- tin/lead profile and those used for lead-free SAC alloys.
ture). See IPC-1756.
Figure 7–11 and Table 7–4 show the details for several SAC
alloys used in developing a specific profile for two versions
7.2.6.1 Example of Thermal Profile Development
Solder paste is applied and a sample BTC is mounted on a of SAC.
specific board intended to be assembled using a lead-free
7.2.6.2 Unique Profile for Each Printed Board Assem-
solder paste. The board was a four layer multilayer board,
bly There is some misunderstanding by some people that
1.5 mm thick, 75 mm by 95 mm in size, and was to be sent
one convection oven profile will work for all boards and
through a reflow oven using a lead-free assembly. Thermo-
hence there is no need for developing a unique profile for
couples were placed on the BTC lands and on the bottom of
each board. This is simply not true because each board has
the FR-4 board to monitor the temperatures at these loca-
a different thermal mass and one may have different loading
tions. A third thermocouple to monitor the oven environ-
patterns (distance between boards as they are loaded in the
ment temperature was also attached on top of the FR-4
oven). Even the same double-sided board, depending upon
board. The temperature profile was monitored in seven
component placement and distribution of copper planes on
different oven zones, approximately 30 seconds apart. The
each side, may require a different profile for each side. A
data gathered and the temperature profile used to mount the
specific profile for each printed board assembly may be
sample BTC to this board is shown in Table 7–2, Table 7–3
needed since a different thermal mass could be associated
and Figure 7–10. To achieve this profile, the oven environ-
with each board. This is recommended so that a proper
ment was set to 260°C maximum with a maximum zone
profile is assured.
slope of 2.0°C/sec.
Table 7-2 Typical Reflow Profile for Eutectic (63Sn/37Pb) Solder Paste
Profile Elements Straight Line Profile Low Soak Profile

Ramp rate 0.8 – 1.2°C/sec (RT to Peak temp) 1.5 – 2.0°C/sec (RT to 145°C)
Dwell @ 145 to 160°C N/A 30 – 120 seconds
2nd Ramp rate N/A 1.5 – 2.0°C/sec (to Peak temp)
Time above liquidus (183°C) 45 – 75 seconds
Peak temperature range 210 – 225°C typical (240°C max)
Ramp-down rate to RT 1 – 3°C/sec typical, (4°C/sec max)
Note: For details, please refer to solder paste manufacturer’s recommendation

Table 7-3 Profile Comparison Between SnPb and SAC Alloys

Profile Topic SnPb Alloy Lead-free Alloy (SAC)

Alloy Solidus temperature 183°C 217–220°C

Alloy soldering temp range 210–220°C 235–245°C
Minimum peak reflow temperature ** 205°C 230°C
Component ramp up rate 1–4°C/sec * 1–4°C/sec *
Component ramp down rate 2–4°C/sec * 2–4°C/sec *
Soak or preheat activation temperature 100–180°C * 140–220°C *
Soak or preheat activation time 60–120 seconds * 60–150 seconds *
Dwell time above liquidus 60–90 seconds 60–90 seconds
Dwell time at peak temp. 20 seconds max 20 seconds max
* Verify with the supplier
** Coolest Temperature on the board

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250

225 Straight Ramp

200 Low Soak

Degrees (C) 183

150

100

50

RT

0 60 120 180 240 300 360

Seconds
IPC-7093-7-10

Figure 7-10 Profile for Tin/Lead Solder Reflow

250
240

217
200

150
Degrees (C)

100

50

RT

0 60 120 180 240 300 360

Seconds
IPC-7093-7-11

Figure 7-11 Profile for SAC Alloy Solder Reflow

There is also a misconception that if you need to change a 7.2.7 Reflow Process Impact on Material Flux has two
profile, simply change the belt speed. Having to change only key attributes. First it must remove contamination and,
the belt speed is certainly easy, but it may not be the right second, it must protect the solderable surfaces after con-
approach. Changing the belt speed changes the temperature tamination removal. A common mistake is to use a
of the board in every zone. Consideration must be made for time/temperature profile that consumes the flux before the
the thermal profile to ensure the large thermal masses solder melts. Ideally, the flux would be consumed just as the
achieve accurate reflow while not causing an excessive solder begins to melt. Activation time should range from 90
temperature condition on the small thermal masses. to 120 seconds. Flux usually becomes active at around

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Table 7-4 Typical Reflow Profile for Lead-Free

(SAC305 or SAC405) Solder Paste
Profile Elements Convection or IR

Ramp rate (RT to Peak temp) 0.8 – 1.2 °C/s

Time above liquidus (217°C) 35 – 80 seconds
Peak temperature range 235 – 240 °C typical (260°C max)
Ramp-down rate to RT 1 – 2 °C/sec typical (6°C/sec max)
Note: For details, please refer to solder paste manufacturer’s recommendation

130°C for tin lead solder pastes. Typically, solder paste For the range cited, the lower temperatures are suitable for
activation for lead-free solder will be higher, in the 150°C the typical tin/lead or tin/lead-silver alloys used for standard
range; however, it is recommended to work with your solder attachment processes. The upper end of the range will
paste supplier for recommendation on that specific solder permit reflow of high lead alloys, which are used to attach
paste. pins to PGA packages. Users faced with reflow of a
specialty alloy have been successful in mixing two primary
Component termination finish will affect solderability.
fluids to tailor a vapor phase system for a specific stable
There are a number of component terminal finishes being
boiling point. Higher temperatures will permit shorter times,
used today, including tin/lead, gold, tin and palladium. It is
which may be advantageous with some solder pastes.
important to select a flux and solder alloy that works well
with the finish being used on the BTCs. The primary vapor phase should be inert and not introduce
contaminants that must be removed later. Solder paste
Components can be damaged by the incorrect application of
chemicals that dissolve in the fluid are carried in the high
heat. All components have a heat exposure limit. Most
boiling vapor then deposited on the surface of the boards.
tin/lead compatible surface mount components should tol-
Such residues tend to be difficult to remove. Minimizing
erate a peak temperature of 220ºC for up to 60 seconds.
solder paste residue in the primary fluid will maximize the
Lead-free BTCs will be rated to a higher temperature which
lifetime of the fluid, prevent boiling point elevation due to
is approximately 240–260°C. Thermal shock, caused by the
dissolved paste ingredients, and simplify cleaning.
rapid application of heat, can crack certain components.
However, since the peak temperature of reflow ovens varies, The secondary vapor blanket was originally CFC-113, a
the intent is to heat the solder in a controlled established lower boiling fluorinated material, which formed a low cost
profile to a solder joint temperature of 210–220°C for sacrificial ‘lid’ over the more costly primary fluid. The
tin-lead products and for 235–245°C for lead-free products. constant exposure to the high boiling primary fluid at the
interface of the two fluids could cause the secondary fluid to
Warpage is another consideration as BTCs packages be-
undergo thermal decomposition at the interface, generating
come larger. Flatness is important to proper seating of the
HCl (hydrochloric) and HF (hydrofluoric) acid vapors.
package and solder joint reliability. The higher temperature
These corrosive vapors often attacked the soldering equip-
reflow profile required for lead-free soldering may cause
ment over time. While in theory the vapors could be
excessive PCB warpage and should be evaluated.
absorbed in flux residues and cause problems for high
reliability products, this was rare in comparison to the attack
7.2.8 Vapor Phase Vapor phase reflow can be operated
on the equipment.
as a single fluid system or a two fluid system, utilizing a
primary and a secondary fluid. The process was developed With the phase out of CFC-113, a low boiling perfluorocar-
using the two-fluid approach in batch equipment; but bon was introduced to replace it. This second generation
modern in-line systems are normally operated with only one secondary blanket fluid was more stable than CFC-113 for
fluid. Whichever system is used, the maximum temperature prolonged exposure to the high boiling vapor phase fluids.
reached by assemblies in vapor phase (VP) reflow depends As surface mount technology grew, most users converted to
on the choice of the primary fluid. Primary fluids are the higher throughput in-line machines, which used the
available in a number of temperature ranges, with single fluid approach. Defluxing after vapor phase reflow
218–222°C being common with tin lead products and should be done with either a bipolar solvent formulation or
235–245°C for lead-free products. While all the primary include an aqueous cleaning formulation that can ensure
fluids can be classed as perfluorocarbons, the basic structure removal of all the solder paste residues, with the choice of
(amine, cyclic or ether) will determine the key properties of cleaning process based on the composition of the solder
in-use stability solder paste chemicals solubility and overall paste. Secondary factors influencing the decision would be
process economics. The choice of a fluid is normally based compatibility, and the component to PWB surface spacing.
on the melting point of the solder alloy to be reflowed. In addition, most companies gave serious thought to con-

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sidering the potential chemical loss from using this type of dissipation vias. The X-ray pictures confirm that only
equipment since many perfluoro compounds are very long- minimal solder actually flowed down the ground land vias;
lived global warming compounds. some voiding is seen but does not hurt thermal dissipation
or reliability.
7.2.9 Cleaning vs. No-Clean Residue from the surface
Factors that determine the post-reflow BTC package stand-
mount process can create resistive connections between off from the board include the BTC package weight, the
pads on BTC packages. If a low residue, no-clean solder volume solder paste, the land size and land configuration
paste is used, PCB cleaning is not required and has little (solder mask defined or non-solder mask defined). However,
effect on a BTC. With the elimination of materials contain- for packages with a large I/O count, the package weight may
ing CFCs, most companies have moved to a no-clean or have less effect on the standoff height.
aqueous flux-based system.
For QFN components the solder joint standoff is a direct
“No clean” fluxes and solders simply mean that there are no
function of amount of paste coverage on the thermal pad
harmful residues left on the board that could cause corrosion
and the type of vias used for BTCs with exposed pad at the
or damage to the components if left on the board. Residues
bottom. Board mounting studies have shown that the
have sometimes been shown to be a collection point for
package standoff increases by increasing the paste coverage
outside contamination on the board surface. Because there
and by using plugged vias in the thermal pad region. The
are so many different types of no-clean solder pastes
standoff height varies by the amount of solder that wets or
available, application specific evaluations should be per-
flows into the PTH via. An open via provides an easy path
formed to identify if any remaining residue still needs to be
for solder to flow into the PTH and decreases package
removed from the boards in final production.
standoff height while the plugged via impedes the flow of
The cleaning process itself must be analyzed to ensure that solder into the via due to the plugged via’s closed barrel end.
no residual cleaning material is left behind under the parts. In addition, the number of vias and their finished hole size
Because of the low profiles and the geometry of the BTC, will also influence the standoff height for open via design.
cleaning solution may penetrate under the part but may not
The standoff height is also affected by the type and
always completely rinse out. Depending on the chemistry
reactivity of solder paste used during assembly, PCB
used, this could introduce long-term reliability concerns.
thickness and surface finish, and reflow profile. To achieve
Refer to IPC-CH-65 and IPC-9201 for guidance in cleaning
50 micron thick solder joints, which help in improving the
assemblies.
board reliability, it is recommended that the solder paste
coverage be at least 50% for plugged vias and 75% for
7.2.10 Package Standoff The package standoff is one of
encroached via.
the prime parameters determining the reliability of the BTC
solder joints. Package standoff for a BTC is defined as the The fillet formation is also a function of PCB land size,
distance between the land on the bottom of the package printed solder volume, and the package standoff height. The
substrate and the land on the top of the board surface. This land size recommended for most BTCs, along with 1:1
distance varies depending on the volume of solder paste. stencil aperture, will provide sufficient solder for fillet
When BTCs are soldered onto the board, the flux and formation if the package standoff is not excessive. Since
solvent within the printed paste material separates from the there is only limited solder available, higher standoff—
alloy. The post-reflow standoff height will be approximately controlled by paste coverage on the thermal pad—may not
50% of the original solder paste thickness. The standoff leave enough solder for fillet formation. Conversely, if the
height on all BTCs should be verified during the set up of standoff is too low, large convex shape fillets may form.
your process. It is recommended to establish the process to This is shown in Figure 7–13.
reproduce the standoff height for specific components. The figure also shows that although the contact ends are not
The standoff height is also affected by the type and percent plated solder fillets were still formed when these parts are
of powder in the solder paste, PCB surface finish, and mounted on the PCB with a protruding land pattern and 1:1
reflow profile. Standoff heights are inversely proportional to aperture for peripheral leads. Since center pad coverage and
the land diameters, i.e., as land diameters increase, stand off via type were shown to have the greatest impact on standoff
heights decrease. For non-solder mask defined (NSMD) height the volume of solder necessary to create optimum
lands, a solder mask relief around the land may reduce the fillet varies. Package standoff height and PCB pads size will
standoff height, because the solder will wet out along the establish the required volume.
conductors as well as along the edges of the land. This is
If solder protrusion cannot be avoided, the components may
shown in Figure 7–12.
have to be assembled on the top side (or final pass)
Additionally, the figure shows lead-free, SAC-305 solder assembly, as the protruded solder will impede acceptable
paste did not readily flow down ground land thermal solder paste printing on the other side of the PCB.

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IPC-7093-7-12

Figure 7-12 SAC Alloy Flow Characteristics

underfill materials to spread effectively under the part. Test

vehicle evaluation is recommended to determine if these
materials are appropriate or required for the application and
mission life of the electronics assembly.

7.3.3 Depaneling of Boards and Modules During a me-

chanical depaneling process stress may be placed on solder
joints in the area being punched or routed. Suppliers of
mechanical routing equipment should recommend specifi-
cations for keep out areas. Laser routing is an attractive for
singulation as it is noncontact; however, laser systems are
IPC-7093-7-13
more costly.
Figure 7-13 Post Assembly Contact and DAP Solder Joint
Profile 7.4 Inspection Techniques Inspection of a BTC on a
PCB is typically accomplished by using transmission type
7.3 Post-SMT Processes There are several processes
X-ray equipment. In most cases, 100 percent inspection is
that must be considered after the reflow operation. Some of
not performed. Typically X-ray inspection is used to estab-
these are shown in the following sections and require
lish process parameters, and then to monitor the production
various degrees of careful handling in order to maintain the
equipment and process. There are many different types of
integrity of the assembly.
X-ray inspection equipment available and functionality
varies. X-ray inspection system features range from manual
7.3.1 Conformal Coatings Special consideration should
to automated X-ray inspection (AXI).
be taken when using conformal coatings with BTC type
packages. Allowing coating material to wick underneath the Different systems also provide single or multiple dimen-
package may cause early solder joint failures due to the “Z” sional inspection capabilities. Depending on size and
axis expansion of the coating material during thermal weight, a BTC will self-align to the land pad using surface
excursions. tension during the solder reflow process. As a result, it is
unlikely that a BTC will be marginally misaligned. If
7.3.2 Use of Underfills and Adhesives Underfill and misalignment does occur it is likely to be by an entire pad.
adhesive (edge and/or corner bonding) may extend the This effect makes it possible to do a gross visual alignment
solder joint life during vibration and shock. The use of check after reflow. Visual checks can be aided by the use of
solder mask in the PCB design may make the standoff PCB fiducial marks which also aid manual placement of
distance between the PCB and BTC too small for most units during any rework.

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7.4.1 X-Ray Usage X-ray inspection is generally used under inspection, and the thickness and features of the board
when there is a high proportion of hidden solder joints that upon which it sits. BTC’s with copper heat sinks, for
are not visually accessible, and when there are a significant example, will typically require higher tube voltage and tube
number of un-testable solder joints. Examples of un-testable current/power settings. On the other hand, BTC’s with
solder joints are redundant connections, and back-to-back aluminum heat sinks will typically require less since alumi-
BTCs where the fanout vias are inaccessible and space does num has a lower atomic number than copper and is therefore
not allow for additional test points. X-ray methods can more transparent to X-rays.
complement the test process chosen, and can provide faster
feedback to the manufacturing line; however, solder bond- 7.4.2 Scanning Acoustic Microscopy Scanning acoustic
ing is not necessarily observable through X-ray and other microscopy (SAM), also called scanning acoustic tomogra-
testing might be necessary to prove metallurgical bonding. phy (SAT), is a nondestructive failure analysis tool. It uses
sound waves to scan the internal layers of an assembly. This
Depending on the capability of the X-ray system being used,
technique can also locate delamination or voids inside a
X-ray can detect solder related defects such as bridging,
BTC package as well as locating similar anomalies in
open solder joints, insufficient solder, and excessive solder
underfill after the BTC has been attached to the substrate.
volume but, in general, X-ray is not considered to be a
reliable inspection technique to confirm good solder joints, The SAM illustration in Figure 7–17 shows locating a
especially those marginal solder joints that may lead to flip-chip assembly with the sample being inspected being
intermittent contact. Other defect types such as missing immersed in liquid during the SAM analysis. Voids or areas
solder, misregistration, and package popcorning can also be of delamination that are open to liquid ingress, however,
identified. In addition to defect detection, X-ray can be used cannot be detected with this method.
to provide trend analysis for solder volume and solder joint
The resolution of delamination or void detection depends on
shape.
the acoustic frequency used for analysis. Resolution in-
creases with increasing frequency, however there is less
7.4.1.1 X-Ray Image Acquisition Real Time X-ray in-
penetration at the higher frequencies. A 230 MHz transducer
spection systems utilize an X-ray source and a detector can bring detection resolution down to around a 25 mm gap.
system which converts the invisible X-ray image into a A single point observation is called a SAM, a line scan is
video display signal. These systems provide immediate called a b-SAM, and an area scan is called a c-SAM.
imaging results of samples. The images produced from
these systems should not be distorted or include false
7.4.3 BTC Standoff Measurement BTC standoff mea-
artifacts induced by the X-ray system itself. Figure 7–14,
surements are important for process control and should be
7–15 and 7–16 illustrates a comparable level of image
checked during process development and subsequent pro-
quality that should be expected from a manual X-ray
cess validation. Feeler gauges provide a nondestructive
inspection system. Real time systems are available in a
method of determining the approximate finished standoff of
broad range of sizes from small desktop systems to large
the BTC after reflow. Feeler gauges can be used at each
console floor models. They are also available with a broad
corner after reflow and the combined results can be used to
range of X-ray tube voltages and tube currents or powers.
determine an average standoff measurement. This method is
There is not a specific X-ray tube voltage or current/power not as accurate as cross-sectioning, but it is much less
needed to inspect BTCs. The settings required will, in part, expensive and nondestructive provided that the operator
depend on the sensitivity of the particular X-ray system does not attempt to force a feeler gauge under the device.
employed, the structure and characteristics of the BTC Doing so could result in breaking solder joints.

IPC-7093-7-14

Figure 7-14 X-Ray Images Using Various Techniques to Detect Missing Solder

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• Overall Solder Joint Quality – evidence of proper wet-

ting
• Solder Joint Shape – evidence of proper reflow
• Solder Joint Surface Texture – smooth vs. irregular
• Overall Solder Joint Appearance – flux residue, etc.
• Solder Joint Defects – solder shorts, opens, cold solder

Endoscope inspection technology is best suited for inspect-

ing only the exterior row BTC solder joints. A limitation of
this technology is the inability to view interior rows with the
same level of quality and clarity. It is sometimes possible to
focus on interior solder joints but not at the same level of
detail as the exterior rows.

IPC-7093-7-15
7.4.5 Destructive Analysis Methods If the nondestruc-
Figure 7-15 Typical X-Ray After Process tive measures used to identify a malfunction do not succeed
in eliciting the cause of failure, then destructive analysis
techniques may be used. Such techniques will render the
analyzed assembly unusable. Once the cause of the failure
has been identified the information can be used to imple-
ment corrective actions to eliminate the problem.

7.4.5.1 Cross-Sectioning If nondestructive methods fail

to identify the cause of an anomaly, it may be necessary to
use destructive methods to isolate the problem area. One
method traditionally employed for failure analysis is cross-
sectioning, enabling an operator to analyze a specific section
of the component, substrate and solder joint.

If more than one area is suspect then it needs to be

determined whether those areas can be accessed sequen-
tially on the same component. If not, then the areas will
need to be prioritized according to the possibility of finding
IPC-7093-7-16
the problem or more than one component will need to be
analyzed.
Figure 7-16 Wire-bond X-Ray to Leadframe Illustration
Next, if the problem area is a part of a larger assembly, it
may need to be isolated into a small more manageable
The feeler gauge measurement method does require ad-
portion by cutting it out of the larger assembly. Care must be
equate space around the BTC for unrestricted access. The
taken to ensure that the area of analysis is not tampered with
standoff height of a BTC can give some indication that the
or destroyed during the cutting and polishing process.
solder joint reflowed completely and uniformly. Since each
package has its own stand-off characteristics, users should For proper sectioning, the sample should be molded in resin
develop a part assembly profile in order to make the use of to alleviate chipping or destruction of the sample during
feeler gauges applicable. cross-sectioning. If fine polishing of the area of interest is
going to be required, then the sample should be sectioned a
7.4.4 Optical Inspection Endoscopy is an optical inspec- reasonable distance away from the interface of interest
tion method that permits visual inspection of tiny objects in leaving sufficient distance for fine polishing of the interface.
a small, confined area. This technology has been adapted
In some cases, the entire component may need to be ground
and applied to BTC solder joint inspection. Adding local-
through and looked at for the integrity of various interfaces.
ized fiducial locations also can help in identifying accurate
A common failure analyzed through cross-sectioning is an
position for placing BTC devices.
open occurring in an assembly. Such opens may occur at the
BTC solder joints can be inspected and analyzed for a solder interface. See Appendix A for detailed instructions
variety of critical factors such as: for performing cross-sectioning.

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Input Reflected
Pulse Pulse

Sample T - Transducer

- Ultrasound

- Application
Zone

Fluid
IPC-7093-7-17

Figure 7–17 Scanning Acoustic Microscopy

7.4.5.2 Dye Penetrant Dye penetrant methods can be practical. Similar to testing BGAs, BTCs can be tested with
used during process set-up and in failure analysis to detect a probe if a conductor and via is added as a test point.
solder joint cracking and wetting problems, and package Electrical testing is used to evaluate the functionality of the
delamination. In this process, the sample is immersed in a electronic assembly. There are two commonly used electri-
low viscosity liquid dye which penetrates most cracks, cal test approaches: in-circuit test (ICT) and functional test
delaminated areas, or open voids. The sample component (FT).
can then be peeled away and examined for the presence of
ICT utilizes a dedicated bed-of-nails fixture to probe the
dye in the solder joints or at material interfaces.
completed assembly. This test method is used to detect
If a fluorescent dye is used, the sample is inspected under faults caused by the manufacturing process and also to
UV light. The dye enhances the visibility of flaws that might isolate the majority of nonfunctional components. The faults
otherwise be difficult to detect. The presence of dye on a found by ICT include solder bridging, solder opens, com-
solder land indicates poor wetting to the land, and can be ponent mis-orientation, wrong component, component not
used to estimate the portion of the land that was not wetted; functional and conductor short.
however, very thin cracks may be so small that liquids
cannot completely enter because the surface tension of the Another approach is to place a low cost in-circuit tester near
liquid will not allow it. See Appendix B for detailed the end of the assembly line and use it as a manufacturing
instructions for performing dye penetrant testing. defect analyzer (MDA). Boards are tested immediately after
the components are placed and soldered. Problems are
quickly relayed back to manufacturing so corrective action
7.5 Testing and Product Verification Testing methodol-
can take place while the product is being assembled.
ogy will vary depending on complexity of the assembly and
product application. During the initial stages of prototype ICT can be supplemented by a complete functional test at
and preproduction development a great deal of data is the end of assembly. This test for product functionality can,
necessary in order to fine-tune the process for a particular depending on type of product and the acceptability require-
assembly. A good design will provide feedback from some ments, be as simple as a ‘go/no-go’ test or as complex as a
of the test sequences that can be used to institute process complete exercising of all circuit functionality. FT is used to
improvement procedures. detect device faults on the assembly at speed. With the
higher temperatures on lead-free solder pastes, there may be
7.5.1 Electrical Testing Electrical testing may require an increase in oxidized test lands or test vias. Typically, with
the adoption of boundary scan to verify solder joint integrity tin/lead alloys you may print and reflow solder pastes to
if net access for mechanical probing is restricted or not provide a soldered test point for the ICT probes. Lead-free

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March 2011 IPC-7093

solder pastes do not spread as well and may cause issues accordance with J-STD-001; workmanship requirements
with ICT. It is recommended to run a quick experiment shall follow the requirements of IPC-A-610.
during the development stage of the process to understand
This section establishes the practicable process develop-
the impact of lead-free solder pastes on this process.
ment and maintenance criteria as well as attempting to
address the issues related to an acceptable assembly process.
7.5.2 Test Coverage Given the current complexity in
electronic assemblies, the level of ‘coverage’ of test has
7.6.1 Voids in BTC Solder Joints Voiding should be
become an industry issue. The more complex a board or
minimized by solder process development and recurring
assembly, the more difficult it is to fully test. Indeed, it may
process controls. The thermal pad joint of BTCs can have
be difficult to test even a reasonable portion of the assembly
substantial voiding mainly due to the relatively large area of
in a reasonable, i.e., cost effective, period of time.
the joint. Most vendors recommend a minimum of 50%
While test of an assembly may be aided by incorporating coverage of the solderable area of the thermal pad; however,
test into the silicon devices, this strategy is not applicable to thermal calculations should determine the actual required
bare boards. Thus the challenge of test is to provide test minimum coverage area to allow for proper heat transfer
coverage at a high level of confidence within a reasonable (see Figure 7–18). Solderable surface area does not include
period of time. open, filled or solder mask encroached vias unless they are
An effective process monitoring system consists of overlap- overplated or filled with solderable material.
ping tools that create a large bandwidth of coverage. If the various process parameters such as reflow profile and
Multiple tools and methods are required since there is not paste printing guidelines discussed in this document are
one single tool or method that provides the desired cover- followed, voids can be greatly minimized. As has been
age. Optical inspection, X-ray, SAM, ICT and FT are stated, a good stencil design tries to achieve 50 to 60% paste
examples of overlapping coverage. These verification meth- coverage of the thermal pad. Proper stencil aperture design
ods should be used to monitor products and process; they with respect to any vias located in the thermal pad can also
should not be used solely to screen and separate good and minimize voids. Based on agreement between user and
bad product. supplier, Table 7–5 can be used as a process guideline for
void occurrence in different applications. The resulting
7.5.3 Burn-In Testing Burn-in is an operational and en- thermal pad contact percentage is based on the goal of the
vironmental test of the complete assembly at the upper stencil design intending to have 50% coverage of the
limits of the application. This test typically finds more thermal pad. Table 7–5 shows the maximum potential
component related problems than solder joint defects. The voiding expected for the indicated stencil design and via
use of burn-in testing is still in use for component evalua- conditions.
tion. Burn-in on electronic assembly is decreasing in favor The results shown in Table 7–5 are consistent with those
of some form of accelerated test exposure to screen out shown in Figure 7–18 through Figure 7–21. The examples
marginal results. and X-ray images indicate that the most desirable pattern is

7.5.4 Product Screening Tests Environmental stress

screening (ESS) is used to screen ongoing production for
poor product quality and latent defects. The purpose of ESS
is to accelerate the latent defects to actual failures, thus
eliminating these latent defects from causing failures in the
field. Care must be taken that the ESS procedures are not
sufficiently severe to damage good product and produce
new latent defects. Solder fatigue life on BTCs shall be
evaluated on the thermal cycling of these ESS tests, other
tests, and the operating life thermal environments.

7.6 Assembly Process Control Criteria for Plastic BTCs

BTC solder joints have a tendency to voiding from the
release of volatiles in the solder paste during the solder
reflow process. The degree of voids permitted in the BTC
assembly attachment process and the impact on reliability is
IPC-7093-7-18
of interest to members of the electronics industry. The
detailed requirements for end product acceptance shall be in Figure 7-18 Typical Thermal Plane Voiding

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Table 7-5 Guidelines for Void Criteria in Thermal/Ground Planes of BTCs

Design Application No Vias in Plane Open Vias in Plane Capped Via in Plane

Stencil Design Solid 50% Potential Voiding 70 % Potential Voiding 35 % Potential Voiding
Stencil Design Segmented 35% Potential Voiding 45% Potential Voiding 25% Potential Voiding
Stencil Design Dot Pattern 15% Potential Voiding 35% Potential Voiding 15% Potential Voiding
Assembly Contact 25% of Pad 15% of Pad 32.5% of Pad
Solid Stencil Level A Level A Level A
Assembly Contact 32.5% of Pad 22.5% of Pad 37.5% of Pad
Segmented Stencil Level B Level A Level B
Assembly Contact Dot 42.5% of Pad 32.5% of Pad 43.5% of Pad
Pattern Stencil Level C Level B Level C
Note: Levels A, B, and C reflect the design producibility. Level A = General; Level B = Moderate; Level C = High

one that avoids solder paste over via location and using the Some X-ray systems can distort the size of voids due to
dot pattern appears to provide greater attachment potential parallax issues. It is possible to accurately measure the true
through less voiding. volume of a void but the procedure can be involved and
requires a known reference for radiometric calibration of the
It is also important to understand the relationship between
X-ray film or detector. In most cases the effort is better spent
paste applied on large thermal pads and any thermal vias in
on identifying and eliminating the cause of the voids. BTC
those pads. Figure 7–19 shows solder paste printed over
solder joints are prone to more voiding than other solder
plugged thermal vias using segments on the left and dots on
joints due to the nature of the thermal pad joint itself. BTC
the right. The corresponding X-ray images in Figure 7–20
solder joints are formed mainly between two parallel
showed far less voiding for solder paste dots compared to
surfaces and depending on the ability of volatiles or other
solder paste segments.
trapped gasses to escape can result in voiding.
Figure 7–19 shows relatively large solder voids when using
All of these options have pros and cons when mounting
the solder paste segment approach compared to using solder
BTC packages on the board. While via tenting from top side
paste dots. Another set of examples are provided in Figure
may result in smaller voids, the presence of solder mask on
7–21 and Figure 7–22.
the top side of the board may hinder proper paste printing.
The appearance of a void after reflow assembly is an On the other hand, both via tenting from bottom or via
indicator that the reflow process has taken place. However, plugging from bottom may result in larger voids due to
a change in void size or frequency of voids may be an out-gassing. Finally, open vias allow the solder to wick
indication that the manufacturing parameters need to be inside the vias and reduce the size of the voids. However, it
adjusted. Two reported causes of voids are trapped flux that also results in lower standoff of the package, which is
has not had enough time to be released from the solder controlled by the solder underneath the exposed pad.
paste, and contaminants on improperly cleaned circuit
boards. Voids appear in an X-ray image as a lighter area 7.6.2 Solder Bridging Solder bridging is unacceptable.
inside the solder joint. Electrical testing, optical inspection (endoscope) or X-ray

IPC-7093-7-19

Figure 7-19 Solder Paste Segments vs. Solder Paste Dots Printed over Plugged Thermal Vias

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March 2011 IPC-7093

IPC-7093-7-20

Figures 7-20 X-Ray Images Showing Solder Segment and Solder Dot Voiding Results

IPC-7093-7-21

Figure 7-21 Solder Paste Printing Strategy: Segments (left) vs. Solder Dots (right)

IPC-7093-7-22

Figure 7-22 Solder Segments vs. Solder Dots – Void Potential

inspection is necessary to detect solder bridging. Poor solder or X-ray inspection is usually necessary to detect solder
paste printing, inaccurate placement, manual ‘tweaking’ opens. Poor solder paste printing, inaccurate placement and
after placement and solder splattering during reflow are manual ‘tweaking’ after placement, are typical assembly
typical causes of solder bridging. related causes of solder opens. Coplanarity and substrate
solderability problems can also cause opens. Excessive
7.6.3 Opens Solder opens are also unacceptable. A com- mechanical stress can also cause solder joints to crack and
bination of electrical testing, optical inspection (endoscope) create opens.

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7.6.4 Cold Solder The reflow profile should reach tem- 7.6.7 BTC Component Solderability Testing Solder-
peratures high enough to ensure that the solder melts ability evaluations using standard ’Dip and Look’ tech-
completely and proper wetting of the land surface occurs. A niques can result in false negative test results for some BTC
cold solder joint can reduce mechanical integrity and can devices. BTC packages which have non-symmetrical pad
cause the component to fail electrically or function inter- patterns and/or configurations can result in unintended flux
mittently. Optical inspection after cross-sectioning is the interactions and a lack of molten solder contact. See Figure
best way to inspect for cold solder joints. 7–23 and 7–24. It is recommended that Test S, Surface
Mount Process Simulation Test as defined in J-STD-002, be
7.6.5 Defect Correlation/Process Improvement The
used for the testing of BTC packages.
manufacturing process produces solder joints that are either
acceptable or unacceptable. This can be determined through
inspection using methods and tools discussed previously. In
many cases a visual inspection of a BTC is the first clue to
any problems. An operator can look at the edge of the BTC
on all four sides.
To directly observe the solder connections under a BTC,
X-ray or optical inspection (endoscope) is necessary. These
methods can be used to inspect for obvious defects such as
bridges and missing solder joints.
Quantitative measurement of the solder bond X-ray image
can be performed using image analysis software. Such
software is useful but not necessarily required for the
inspection of BTCs. The advantage of the software is in its
IPC-7093-7-23
ability to identify and display subtle variations in the size
and shape of the solder bond image which is not easily Figure 7-23 Dip and Look Test
observed by an operator. These subtle variations are a
signature of the process used to manufacture the part and
can be used to monitor the process and to correct for
deficiencies. A number of signatures can be correlated with
known process deficiencies.

7.6.6 Effect of Insufficient and/or Uneven Heating A

common process problem is insufficient or uneven heating
of the BTC. This problem occurs more often during rework
but can also be seen in production when working with
multilayer boards with many ground or power planes. The
problem can also happen on double-sided boards when a
shielded component is on the backside near the location of
the BTC. The problem occurs when a thermal conductor
removes the heat from the BTC preventing thorough wet-
IPC-7093-7-24
ting of the solder. The X-ray image of this problem is
characterized by a variation in the size of the solder joint at Figure 7-24 Process Simulation Test
different locations under the package.
7.6.8 Solder Ball Defects Solder balls, which form for a
Insufficient heating is generally characterized in an X-ray variety of reasons during reflow, are a reliability concern,
image by small partially reflowed solder joints in the center especially when fine pitch devices are involved.
or to one side of the package. Insufficient heating may also
be characterized by a jaggedness around the perimeter of 7.7 Repair Processes
these solder joints; indicating that the solder partially
reflowed but not long enough to completely wet to the land. 7.7.1 Rework/Repair Philosophy In general, the rework
Misalignment of the BTC with respect to the land is also an station for BTCs are typical of systems currently used for
indicator of inadequate heating. The X-ray image of mis- rework of BGAs. The system should have a split light
alignment is characterized by elongated solder joints which system, an XY table for alignment and a hot air reflow
may or may not have a consistent orientation. system with top and bottom heater for component removal.

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If the BTC is being removed from tightly packed boards 7.7.2 Removal of BTC
such as cell phones, a laser rework system may have an
advantage since they will not heat the neighboring compo- 7.7.2.1 PC Board Bake It is recommended to bake the
nents as would be the case when using hot air systems. PCB for approximately 24 hours at 125°C prior to rework in
order to drive off residual moisture that could cause other
The standard industry practice for rework consists of
component failures during the rework reflow process.
various steps including:
Proper handling of the PCB during the bake cycle should
• Printed board assembly – bake 125ºC for 24 hours also be taken into account.
• Printed board assembly – preheated to 125ºC
7.7.2.2 PC Board Preheat Once the PCB has finished
• Reflow of component solder
the baking process, the PCB under rework is then placed in
• Removal of component <via machine vacuum, manual the rework holder and preheated to a temperature of 125°C.
plunger or tweezers> Localized heating of the area under rework is recommended
• Cleaning and prep of PCB lands (use 4°C/second maximum ramp rate).
– Screening or dispensing of solder paste onto PCB Specialized vacuum collets come in contact with the rework
– “Bumping” of solder paste onto device component. These collets incorporate a hot gas shroud that
heats up the part to a temperature required for reflowing the
• Placement and reflow of new component
solder interconnects. Once the solder reflows, the vacuum
• Inspection of solder joints lifts the unit from the PCB. The nozzle size and hot gas flow
should be optimized to keep the heat flow localized to the
To remove the faulty component from the board, heat from
component being removed, while uniformly heating the
hot air or lasers should be applied from the top and bottom
component.
heaters. An air nozzle with the correct size should be used
to conduct the heat to the BTC component such that the
vacuum pick up tool can properly remove the component. 7.7.3 BTC Assembly Defect Repair In the event of de-
The laser does not require different size nozzles for removal. fects occurring after component attachment, the board
assembly will require rework to remove and replace the
Once the BTC component is removed, the site is cleaned device. Since most of the soldered joint is inaccessible,
and dressed to prepare for the new component placement. A correction of the defect will generally require the complete
de-soldering station can be used for solder dressing. removal and remounting or replacement of the component.
Usual applications for BTC devices involve mounting on
A mini-stencil with the same stencil thickness, aperture small, thin, densely populated PCBs. These factors, coupled
opening and pattern as the normal stencil is placed on the with the small size of the components themselves, can lead
component site. A mini-metal squeegee blade deposits to challenges in reworking defects. Because of product
solder paste in the specific area. dependent complexities, the following is only a guideline
The printed pad should be inspected to ensure even and and a starting point for the development of a successful
sufficient solder paste before component placement. Unlike rework process for these packages.
in repair of BGAs, the correct amount of paste is critical for The rework process includes the following steps:
successful rework of BTC.
1. Board preparation
In situations where neighboring parts are in close proximity 2. Component removal
with the BTC components and the mini-stencil method is 3. PCB land clean up
not an option, apply solder paste carefully on each land
using a syringe. The volume of solder paste will be difficult 4. Application of solder paste
to control unless an automated dispenser is used as in the 5. Component alignment and placement
case with higher end dispensing systems available in laser 6. Component attachment
rework systems. 7. Inspection of rework
A vacuum nozzle is used to pick the new package up. The
split light system displays images of both the BTC leads and 7.7.3.1 Component Removal In order to facilitate the
the footprint on the PCB. The two superimposed images are removal of the component from the PCB, the solder joints
aligned manually (or automatically in higher end systems) attaching component to the board should be reflowed.
by adjusting the XY table. Once the PCB and the package Ideally the reflow profile used for removing the component
are aligned, the package is placed down on the PCB. The should be the same as that used for component attachment.
replaced component is then soldered to the PCB. Figure 7–25 shows a typical component removal setup.

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IPC-7093 March 2011

900 nanometers), and time in milliseconds (generally less

VACUUM HOT than a second for a typical solder joint), with or without the
CUP GAS GAS use of built-in preheat. In addition to using traditional
SHROUD preheaters, the laser can be programmed for post-heat
operations (just a few milliseconds) to achieve desired
solder joint quality.
Because laser soldering time is measured in milliseconds (as
opposed to seconds), the intermetallic thickness is less than
1 µm.
LFCSP
7.7.3.3 PCB Land Preparation for Reattachment Once
PCB the component has been removed, the site should be
adequately prepared to receive the replacement device.
CONVECTIVE HEATER Cleaning the site is done in two steps:
IPC-7093-7-25 1. Desoldering – Desoldering is achieved through the use
Figure 7–25 Solder is Heated to Liquidus State and the of a ‘desoldering braid’ in conjunction with a blade-type
BTC is Withdrawn Before Solder Re-Solidification soldering iron typical of that shown in Figure 7–26. The
width of the blade should match the maximum width of
The time the solder alloy is above liquidus can be reduced the component footprint, and the blade temperature
as long as the reflow is complete. During reflow, localized should be low enough to avoid any damage to the circuit
heating of the PCB from the bottom side using a heating board.
source is recommended. There are several heating methods
Non-contact heated vacuum systems are also used in
for bottom side heating including, but not limited to, hot air
high-end rework stations since the procedure allows for
and IR. Reflow of the solder joint is achieved by directing
the cleaning of the PCB lands using a vacuum system so
heat to the topside of the component; this can be accom-
as not to scratch the board or damage the land.
plished using a heat gun or IR radiation. During the reflow
of the solder joints, a vacuum cup operating within the 2. Cleaning – The site should be wiped clean using a lint
confines of the gas shroud attaches to the top side of the free cloth and solvent. The solvent is usually specific to
component. Once the reflow of the solder joints has taken the type of solder paste used in the original assembly.
place, either a vacuum-assisted suction cup or some me-
chanical lifting technique such as tweezers can be employed
BLADE TYPE
to lift the component off of the PCB. Use ESD-safe DESOLDERING HEATED IRON
BRAID/WICK
components which are properly grounded, when using
manual lifting devices. Given the small size of the com-
SOLDERING CLEAN
ponents, the vacuum pressure should be kept below LANDS
0.5 kg/cm2. This will prevent the component being lifted out
before all the joints have been reflowed and avoid pad lift.
Note: Because of the potential for internal damage during
IPC-7093-7-26
repeated thermal exposure, removed components should not
be reused. Figure 7–26 Desoldering of the BTC Mounting Site

7.7.3.2 Laser Enabled Rework for BTC Assemblies 7.7.3.4 Application of Solder Paste When reworking
Laser technology has gone through a tremendous change, BTC components there are two main approaches to attach-
from traditional YAG and CO2 lasers to semiconductor ing the device onto the already-populated PCB. One in-
technology of diode lasers. Many applications exist where volves the selective solder application on to the PCB while
laser soldering will be more cost-effective than traditional the other involves the selective application of the solder
methods discussed above. Laser soldering has proved to be onto the replacement part. The application of the solder
cost-effective selective soldering of components when con- paste is accomplished by one of several methods including
tact or convection reflow is not technically feasible. solder paste printing, solder paste dispensing or hand
soldering.
Unlike hot air/gas rework systems, laser soldering does not
need special fixtures that add to variable cost. Focused laser Pad geometries of the BTC component present a challenge
soldering parameters are controlled in four stages; preheat in producing an even solder line thickness on reflow. A
temperature, laser power (8 to 30 W), wave length (800 to number of critical features of the print stencil should be

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considered. Stencil alignment accuracy and consistent sol-

der volume transfer is critical for uniform reflow solder
processing. The stencil thickness, as well as the etched
pattern geometry, determines the precise volume of solder
paste deposited. Stencils are usually made of brass or
stainless steel, with stainless steel being more durable.
As a guide it is recommended to use a 125 micron [0.005 in]
stencil thickness for the BTC components.
Laser formed stencil apertures are normally trapezoidal, as
shown in Figure 7–27 where dimension A is greater than
dimension B. This form factor helps to ensure a uniform
release of the solder paste and minimizes solder paste
smearing.

A
B
IPC-7093-7-28

STENCIL Figure 7-28 Example of Window Pane Pattern on Stencil

IPC-7093-7-27 • The stencil aperture sizes need to be closely controlled in

Figure 7-27 Typical Laser Ablated Stencil Aperture Geom- the case of peel and release type of stencils as the
etry geometries are critical
• The recommended stencil thickness should be between
Due to the smaller land geometries and dense component
75 µm and 125 µm [0.003 in and 0.005 in]
population of the PCBs, accurate and uniform screen-
printing of solder paste onto an already populated board is • Stencils can be made from a variety of materials but are
very difficult. It is recommended that the solder paste be typically made from brass, stainless steel or polyimide.
applied directly onto the base of the component before See Figure 7–29.
placement. The process is shown in Figures 7–30 and 7–31 where:
Land geometries along with the existence of a large area • The component is placed and secured onto a stencil
ground pad of the BTC presents a challenge for making sure fixture
that the stencil is designed properly for solder paste appli-
• Solder paste is then applied using a metal squeegee blade
cation in order to produce an even solder thickness upon
reflow. A number of print stencil features are critical (see Note: The minimal standoff height of BTC package may not
7.2.4): leave enough gap for efficient post reflow solder cleaning,
• For optimum paste release the area and aspect ratios
should be greater than 0.66 and 1.5 respectively.
• For ‘stay-in-place’ stencils on the PCB the aspect ratio is
not important as it is not released from the PCB.
• It is recommended that the stencil aperture should be 1:1
to PCB land sizes as both the area and aspect ratio targets
can be achieved using this guideline.
• For the larger exposed solder pads (such as the center
ground) found on some BTC designs the stencil opening
in this area needs to be divided into an array of smaller
openings. Dividing the larger exposed pads into the
smaller screen openings reduces the risk of solder
voiding and allows the solder joints for the smaller
terminal lands to be at the same height as the larger ones.
IPC-7093-7-29
It is recommended that “window pane” stencil opening
patterns are used for the large exposed thermal pad as Figure 7-29 Typical Metal Stencil for Printing onto Compo-
shown in Figure 7–28. nent

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solder surface on the side of the package, access to an

exposed pad underneath the device and space on the board.
However, hand soldering cannot access unexposed bottom
side terminations. In addition the geometries involved
require a very high degree of hand soldering precision and
excellent tooling else damage to the component and nearby
components is likely. For these reasons, hand soldering is
IPC-7093-7-30
not a recommended practice for solder paste application on
Figure 7-30 BTC Device is Clamped into Stencil Fixture BTCs.
Application onto the part-solder “bumping”: Due to the
smaller geometries, dense component population of the
SQUEEGEE PCBs, accurate and uniform screen printing of solder paste
SOLDER using a print and release stencil design is difficult and
requires a high degree of operator dexterity and skill. In
these cases it is recommended that the solder paste be
applied directly on top the base of the component before
placement. Either metal stencils, paste dispensing or poly-
imide “peel and release” stencils can be used. Once the
IPC-7093-7-31
device is “bumped” the component can be precision placed
and reflowed similar to other area array devices. See Figure
Figure 7-31 Solder Paste is Transferred Through Stencil 7–33
Apertures onto the Undersurface Features of the BTC

therefore, the manufacturer recommends that the operator

use a Type 3, 4, or 5 no clean solder paste (see J-STD-005).
Application via dispensing: Solder paste dispensing can be
used for dispensing solder paste in a very controlled fashion
onto the PCB. Typically a programmable X-Y-Z axis
controller such as a robot moves into the correct position
where a precise volume of paste is dispensed. Very accurate
placement and controllable volumes of paste are the result
of this technique.
Application via hand soldering: Hands soldering of leadless
packages can be achieved in some cases for the peripheral
pads. Access to these pads depends on the existing of a

IPC-7093-7-33

Figure 7-33 Solder Bumping Method Using a Stencil

7.7.3.5 Component Alignment and Placement The ac-
curacy of component placement of the package is equip-
ment and process method dependent. It is challenging to
place the parts in many cases as the package sizes of BTC
devices tend to have a small footprint. While BTC do have
the ability to self align to an extent due to their small mass,
this is counterbalanced by the greater surface tension of lead
free solders. Slightly misaligned parts should self-align
during reflow as a result of surface tension within the liquid
solder. Grossly misaligned parts are likely to result in
shorting and bridging.
There are a variety of methods one can use to place the parts
IPC-7093-7-32
including the use of a split beam optical system as part of
Figure 7-32 Typical Dispensing System the rework system or a stay in place alignment stencil.

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A split-beam system is used to place either a “bumped” aligned to land patterns of the device being placed, placed
component–a component which has solder applied to its and adhered to the PCB. After solder paste is rolled in to the
bottom side (see Figure 7-35)–or to place a component in to apertures and the stencil wiped of any remnant solder paste,
solder paste which has been printed/dispensed onto the PCB a bumped part is then align and placed in to those apertures
(see Figure 7-34). This type of split-beam optical system is by hand. The part is then reflowed as previously described.
used to align the component to the to the solder pad array on
the PCB as the BTC leads are located on the underside of 8 RELIABILITY
the package. This imaging system will provide an image of
This section provides insight into the method of stress
the leads that are superimposed and by adjustment overlaid
testing in order to validate that a part, board or assembly
onto the corresponding footprint of the PCB and therefore
will work for a specific period of time within an acceptable
align the component with the pad array. This alignment is
failure limit. Information is concentrated on the solder joint
done at magnification. The placement machine must have
and the metallurgical bond between the attachment surfaces.
the capability of allowing for fine adjustments in X, Y and
the rotational axis. Once aligned and placed, the reflow 8.1 Accelerated Reliability Testing The validation and
profile used should be optimized to mimic the original qualification tests should follow the guidelines given in
assembly profile. IPC-SM-785, Guidelines for Accelerated Reliability Testing
of Surface Mount Solder Attachments and/or IPC-9701,
Performance Test Methods and Qualification Requirements
for Surface Mount Solder Attachments. For some products,
the accelerated temperature cycling (ATC) needs to be
combined with mechanical shock and/or vibration testing.
Accelerated reliability testing is carried out on design
prototypes, typically to failure or until a predetermined
reliability goal is achieved. The appropriate reliability goal
can be determined with an appropriate acceleration model
(see IPC-D-279). Once failure occurs, the resulting failure
modes are analyzed as to the underlying failure mecha-
nism(s). If it fails expectations then corrective action is
necessary. Either the assembly process needs to be im-
proved or the product needs to be redesigned. In either case
retesting may be necessary after the corrective action has
IPC-7093-7-34 been implemented.
Figure 7–34 Alignment Stencil on PCB Recognizing that a matrix was needed to determine the
exact requirements and the testing necessary for perfor-
mance under various conditions the IPC Product Reliability
Committee developed the following table ’’Product Catego-
ries and Use Environments.’’ Table 8–1 attempts to relate
seven product categories by typical application to the
thermal, mechanical, atmospheric, and electrical perfor-
mance requirements that they must meet during typical
manufacturing processes, storage, and during operation.

8.2 Damage Mechanisms and Failure of Solder At-

tachments The reliability of an electronic assembly de-
pends on the reliability of the sum of the individual
elements of the mechanical thermal and electrical interfaces
(or attachments) between these elements. One interface
type, the surface mount solder attachment, is unique since
IPC-7093-7-35 the solder joint not only provides the electrical interconnec-
tion, but is also the sole mechanical attachment of the
Figure 7–35 “Bumped” Part Placed and Reflowed
electronic components to the printed board. It often pro-
A second method which can be used for rework involves the vides the critical heat transfer function as well. A solder
use of a stay-in-place stencil which acts as the alignment joint in isolation is neither reliable nor unreliable; it be-
guie of the part onto the PCB. In this method the stencil is comes so only in the context of application.

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Table 8-1 Accelerated Testing for End Use Environments

Worst-case use environment Accelerated testing
Approx.
Typical accept.
Use Tmin Tmax ΔT(1) tD Cycles/ years of failure Tmin Tmax ΔT(2) tD
category °C °C °C hrs year service risk % °C °C °C min

1) Consumer 0 +60 35 12 365 1–3 1 +25 +100 75 15

2) Computers +15 +60 20 2 1 460 5 0.1 +25 +100 75 15
3) Telecom -40 +85 35 12 365 7–20 0.01 0 +100 100 15
4) Commer- -55 +95 20 12 365 20 0,001 0 +100 100 15
cial aircraft
5) Industrial & -55 +95 20 12 185 10 0.1 0 +100 100 15
automotive &40 12 100
Passenger &60 12 60
Compart- &80 12 20
ment
& COLD(3)
6) Military -55 +95 40 12 100 10 0.1 0 +100 100 15
Ground & &60 12 265
ship
& COLD(3)
7) Space
Leo -55 +95 3 1 8 760 5–30 0.001 0 +100 100 15
Geo to 100 12 365
& COLD(3)
8) Military
avionics
a -55 +95 40 2 365 10 0.01 0 +100 100 15
b 60 2 365
c 80 2 365
&20 1 365
& COLD(3)
9) Automotive -55 +125 60 1 1 000 5 0.1 0 +100 100 15
under hood &100 1 300
& COLD(3) & LARGE
&140 2 40 ΔT(4)
& = in addition
(1) ΔT represents the maximum temperature swing but does not include power dissipation effects; for power dissipation calculate ΔT; power dissipation can make
pure temperature cycling accelerated testing significantly inaccurate. It should be noted that the cyclic temperature range, ΔT is not the difference between the
possible minimum, Tmin and maximum, Tmax, operational temperature extremes; ΔT is typically significantly less.
(2) All accelerated test cycles shall have temperature ramps, 20°C/minute and dwell times at temperature extremes shall be 15 minutes measured on the test
boards. This will give ~24 test cycles/day.
(3) The failure/damage mechanism for solder changes at lower temperature; for assemblies seeing significant cold environment operations, additional “COLD”
cycling, from perhaps -40 to 0°C, with dwell times long enough for temperature equilibration and for a number of cycles equal to the “COLD” °C operational cycles
in actual use is recommended.
(4) The failure/damage mechanism for solder is different for large cyclic temperature swings traversing the stress-to-strain -20 to +20°C transition region; for
assemblies seeing such cycles in operation, additional appropriate “LARGE ΔT” testing with cycles similar in nature and number to actual use is recommended.

The characteristics of these three elements—component, ment structure during either temperature changes causes
substrate, and solder joint—together with the use condi- thermal expansion mismatches or PCB/component warping
tions, the design life, and the acceptable failure probability or bending. These higher stresses combine with less strong
determine the reliability of the surface mount solder attach- solder to base material connections due to inadequate
ment. The general characteristics of most lead free solders wetting or interfacial structural weaknesses to cause brittle
as compared to tin/lead solders, include (1) significantly interfacial failure.
greater strength, (2) significantly slower creep rates, (3)
8.2.1 Differences in Accelerated Testing of SAC vs.
greater difficulties of proper spread, and (4) significantly
Tin/Lead SAC solder joints may develop additional failure
higher soldering temperatures.
modes and damage mechanisms during accelerated test,
The consequence of the greater strength and the slower such as temperature cycling, as compared to tin/lead sol-
creep rates are higher stresses on the whole solder attach- ders. The reasons for this are founded in the facts that SAC

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March 2011 IPC-7093

solders are stiffer and have much lower creep rates; both of distributed throughout the solder volume. This, however, is
these conditions generate higher stresses. rarely the case and problems with ‘embrittlement’ have
occurred with less than 3% by wt. of Au.
8.2.2 Mixed Alloy Soldering Since the only solder in the
board to package interconnect comes from the solder paste It is important to put the issues into the correct perspective.
there is no risk of mixed alloy soldering that exists in BGAs. Au- and Ag-embrittlement occurs with the thick and some-
However, since any assembly may have both BGAs and what uncontrolled deposits that can result from electroplat-
BTCs the possibility of mixed alloy exists, thus alloy ing of Au and Ag; they do not occur with immersion plating
selection should consider, mounting land finish, BTC ter- of either Au for ENIG or imAg as a surface treatment.
minal finish and BGA ball solder alloy compatibility. 8.2.7 Stand-Off Height Increasing stand-off height is one
way to enhance the solder joint reliability of bottom
8.2.3 Mold Compound Material Mold component selec-
termination components. The design of the center pad
tion has an impact on the package reliability. Selection of
(thermal pad), its coverage and the number and size of vias
mold material should be based on meeting package reliabil-
on it has been shown to have the largest impact on standoff
ity requirements like moisture sensitivity level and meeting
height. Increased standoff can be achieved by using a
the board level reliability. Board level reliability directly
thicker stencil. There are limits to this option due to aperture
depends on the CTE of the mold compound. Mold com-
area and aspect ratio requirements for paste release and
pound with lower CTE preformed worse in reliability
floating risk of the center pad. Also, since multiple types of
testing than ones with higher CTE close to the board
components are mounted on the same board, using a thicker
material. The mold compound modulus also impacts the
stencil for one or two components is not desirable.
stiffness of the package. Higher modulus will result in stiffer
package and lower fatigue life. One alternative is to increase the thickness of the plating on
the thermal pad on the underside of the package. This has
8.2.4 Die Size Die size has significant impact on board been used by Amkor in the Bump MLF concept as shown in
level reliability. As the die to package ratio decreases the Figure 8–1. A plating thickness of 100 microns increased the
board level reliability increases. With smaller die the board stand-off height of the package solder joints by 100 microns.
level reliability is better because the die edge, which has a This resulted in a 2X increase in the board reliability of the
low CTE, is farther away from the peripheral solder joints. package as shown in Figure 8–2.

8.2.5 Full vs. Half Etched Leadframe Package pads can

come with two options: a full pad and a half etched pad. The
package pad is the same and both cannot be soldered on the Plate-up Bump
on Lead
side to create a fillet there is no impact on reliability. Since
the package is going through singulation process after
plating the exposed side leads are not plated. The copper on
the side lead is oxidized and is not solderable during reflow.
Plate-up Bump
In some cases when a side lead fillet is created data indicates on Die Paddle

improvement in reliability.

8.2.6 Gold/Silver/Palladium Embrittlement As the joint IPC-7093-8-1

standoff is very small in BTCs compared to BGAs, noble
Figure 8-1 Plate-Up Bumped Option
metal embrittlement could be a reliability issue.
Gold, palladium, as well as silver-embrittlement, work in 8.3 PCB Design Considerations Several design charac-
combination. “Au/Ag-embrittlement” is the weakening of teristics impact the solder joint reliability.
the solder structure by too many weak interfaces with the
8.3.1 Land Size Another influence on reliability is the
crystalline AuSn-IMC platelets and the solder. Larger num-
geometry of the solder joint that is derived from the land
ber of such IMC platelets result in higher density of such
metallization on the board. Since BTCs are leadless devices,
interfaces and an increased SJ weakness. There is an
the solder joint shape relates to the land. A larger land under
interfacial loading that comes from a CTE-difference be-
a BTC package provides better reliability as shown on
tween these IMCs and the surrounding solder volume. There
the Weibull plot in Figure 8–3. Comparing a 7 mm package
is little practical difference in the effect of either AuSn-
with 28 terminations and with land sizes of 0.28 mm x
IMCs, AgSn-IMCs or any combination of them.
0.6 mm and a 48 terminal package with land size of
The widely-used 3 to 4% by wt. of noble metal in the solder 0.23 mm x 0.4 mm QFNs, results in a 2X improvement in
joint is basically a rule-of-thumb. It applies to the total fatigue life. The larger land results in a larger solder joint
solder volume and assumes that the IMCs are uniformly and longer path for a complete crack to formation.

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8.3.2.1 Methods for Inspecting BTCs An approach

99.0 demonstrated as effective for Inspecting BTCs for unsol-
Weibull
90.0 dered connections and cold solder joints requires:
W2 RRX - SRM MED

Non Bumped 1. Solder Paste Inspection (SPI) to determine whether

F=5 / S=25
(Std) sufficient solder paste is present.
Cumulative % Failed

50.0
Bumped
W2 RRX - SRM MED
2. Automated Optical Inspection (AOI) to inspect fillets
F=7 / S=23 formed on device sides or flanks.
10.0 Automated X-ray inspection (AXI) can also cover the
5.0 inspection for sufficient solder. In that case, an SPI system
is not necessary, but AOI is still required. It is important to
note that AXI alone does not have the required detection
1.0 rate to protect against BTC assembly defects like unsol-
1000.0 10000.0 dered connections and cold solder joints.
Cycles to Failure
8.3.2.2 Inspectable Side Fillets Require BTCs with Wet-
β1=10.08, η1=4447.98, ρ=0.97
table Flanks In the method discussed above, the AOI
β2=14.00, η2=2255.67, ρ=0.97 IPC-7093-8-2
system is used to establish whether proper BTC assembly
Figure 8-2 Cracks in QFN Solder Joints after Temperature was achieved by allowing for the evaluation of solder fillets
Shock visible along the sides (flanks) of the device. To achieve
externally visible solder fillets after reflow assembly re-
99.0
quires wettable flanks at the BTC component edges.
Weibull
90.0 7mm-28 Perimeter side edges of BTC (e.g. QFN components accord-
W2 RRX - SRM MED
ing to JEDEC MO220), typically have exposed copper on
F=30 / S=0 the cut or punch separation surfaces or flanks. These
50.0
Cumulative % Failed

7mm-48
W2 RRX - SRM MED exposed copper areas are wettable as long as the copper is
F=23 / S=7 not significantly oxidized. After even a few days of storage,
however, copper surfaces may oxidize to the point that
10.0
sufficient solder wetting is no longer possible with typical
5.0 No-Clean fluxes. For this reason, exposed copper areas of
QFN leads that have no special treatment to ensure solder-
ability are not expected to be wettable. See QFN example in
1.0
Figure 8–4.
100.0 1000.0 10000.0
Cycles to Failure
β1=8.60, η1=2124.93, ρ=0.98 QFN with wettable
β2=9.61, η2=1106.65, ρ=0.93 flank is expected to
IPC-7093-8-3
have side fillets
QFN
Figure 8-3 Land Size Impact on Fatigue Life of 7 mm BTC
QFN contact
Package
Solder joint
8.3.2 Fillet Formation While BTC suppliers typically do
not require fillets to be formed on the toe of their packages,
PCB
it is generally agreed that these fillets can improve reliabil-
ity. Solder fillets are formed along the flank or perimeter toe IPC-7093-8-4
edges of BTCs. Toe fillet formation should not be expected
since some BTC suppliers do not protect exposed copper Figure 8-4 QFN with Wettable Flanks
from oxidation after device singulation. 8.3.2.3 Specification for BTC Flank Wettability JEDEC
MO220 defines the basic characteristics of QFN compo-
The surface mount process parameter can also influence
nents which generally now should also apply to all BTCs. In
fillet formation. Some of the variables are PCB land size,
addition, the following are also required for specification
solder paste volume, solder paste flux activity, reflow
purposes related to BTC Flank Wettability:
atmosphere and standoff height. When a fillet forms, it
increases the joint length which provides a longer path for • Each IO lead must have a visible flank at the side of the
the crack to form. component (no pullback I/O leads).

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March 2011 IPC-7093

• Each flank must be wettable. mented to its current form, presented in IPC-D-279, as
• Mold compound is not allowed on any part of the flank additional test results became available.
of the IO leads.
The model is for uncoated solder attachments. The com-
• Double or Multi rows with similarly blinded IO leads are plexity and vast differences in conformal coatings make it
not inspectable using the method described here. impossible to develop a generic model that considers all the
Flanks shall also meet the same solderability requirement as variables. Products with conformal coatings should be
the rest of the device. evaluated using test vehicles having the same coating and
test vehicles without the coating in order to assess the
8.3.3 Board Thickness Thinner printed boards result in impact of the coating on reliability.
better board level reliability. The board material FR4 (~17 Appropriate DfR-measures to improve reliability can take
ppm/°C) has a larger CTE than the package mold compound one of two forms, which are best employed in combination
(~10 ppm/°C). Thinner PCBs reduce cyclic strains due to for improved reliability margins. These measures are:
the global CTE mismatch between the PCB and the package
by flexing and increase solder joint fatigue life. Tests 1. CTE-tailoring to reduce the global expansion mismatch;
conducted on 10 mm -68 lead and 5 mm -32 lead packages 2. Increasing attachment compliancy to accommodate the
using 0.8 mm and 1.6 mm thick boards show at least 30% global expansion mismatch;
improvement in fatigue life for the thinner board. See Figure
8–5. 3. Eliminate the effect of the global expansion mismatch by
mechanically coupling the component and the substrate
with an appropriate underfill;
99.0
Weibull Further, a DfR procedure aiming at high-reliability should
90.0 also include:
W2 RRX - SRM MED

F=26 / S=4 4. Choosing base materials that have not too large a local
50.0 1.6mm
Cumulative % Failed

Thick CTE-mismatch with solder; or

W2 RRX - SRM MED
Board 0.8mm
Thick F=29 / S=1 5. In case item 4 cannot be done, reduce the continuous
Board wetted length to reduce interfacial stresses.
10.0
5.0 CTE-tailoring involves choosing the materials or material
combinations of the PCB and/or the components to achieve
an optimum DCTE. An optimum DCTE for active compo-
1.0 nents dissipating power is ~1–3 ppm/°C (depending on the
100.0 1000.0 10000.0 power dissipated) with the PCB having the larger CTE, and
Cycles to Failure
0 ppm/°C for passive components. Of course, since an
β1=13.69, η1=1254.23, ρ=0.97 assembly has a multitude of components, full CTE-
β2=9.42, η2=854.83, ρ=0.94 IPC-7093-8-5
optimization cannot be achieved for all components—it
Figure 8-5 Weibull Plot Showing Thinner Board Results in needs to be for the components with the largest threat to
Higher Fatigue Life reliability. For military applications with the requirement of
hermetic—and thus ceramic—components, CTE-tailoring
8.4 Voids in Thermal Pad Voids in thermal pads could has meant the CTE-constraining of the PCBs with such
cause reliability concern. There is no rule of what is the materials as Kevlar™ and graphite fibers, or copper-Invar-
acceptable level of voiding. It is specific to the component copper and copper-molybdenum-copper planes. Such solu-
and the use condition of the device. As long as the thermal tions are too expensive for most commercial applications
pad is providing sufficient coverage for cooling require- for which glass-epoxy or glass-polyimide are the materials
ments during maximum operation condition, then it is of choice for the PCBs. Thus, CTE-tailoring has to take the
acceptable. The requirements should derive from thermal form of avoiding larger size components that are either
modeling. ceramic (CGAs, MCMs), have plastic with Alloy 42 lead-
frames (TSOPs, SOTs), or are plastic with rigid bonded
8.5 Design for Reliability (DfR) Process The fatigue silicon die (PBGAs).
behavior of surface mount solder joints has been investi-
gated experimentally in numerous studies. The results of the Increasing attachment compliancy for BTC solder attach-
studies that were carried out in a manner to assure the same ments means increasing the solder joint height (see Section
damage mechanism as the mechanism operative in typical 8.2.7) or switching to a compliant leaded attachment tech-
electronic products have yielded a mathematical solder nology. For compliant leaded attachments increasing lead
fatigue model. This model has been expanded and aug- compliancy can mean changing component suppliers to

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those having lead geometries promoting higher lead com- ture is above half the absolute melting temperature of the
pliancy or switching to fine-pitch technology. material. For example, the melting temperature of 63/37
Sn/Pb solder is 456º Kelvin (183.6°C), half the absolute
The DfR-process needs to emphasize a physics-of-failure
melting temperature is 228K or -45°C. Hence, creep defor-
perspective without neglecting the statistical distribution of
mation can occur in solder at a given load even at tempera-
failures. The process might involve the following steps:
tures as low as -45°C.
1. Identify Reliability Requirements: expected design life
The relation between stress experienced by the solder joint
and acceptable cumulative failure probability at the end
and the activation energy is expressed by the general creep
of this design life.
equation:
2. Identify Loading Conditions: use environments (e.g.,
IPC-SM-785) and thermal gradients due to power dissi-
pation, which may vary and produce large numbers of
e = Aδn S–Q
kT D

mini-cycles (Energy Star). Where:

3. Identify/Select Assembly Architecture: part and substrate e = strain rate
selections, material properties (e.g., CTE), and attach-
Α = constant
ment geometry.
δ = stress
4. Assess Reliability: determine reliability potential of the
designed assembly and compare to the reliability require- n = stress exponent
ments using the approach shown here (see IPC-9701), or Q = activation energy
some other suitable technique; this process may be k = Boltzmann constant
iterative.
Τ = temperature in degrees kelvin
5. Balance Performance, Cost and Reliability Require-
ments. Creep strain is the result of thermally activated dislocation
motion and/or movement of vacancies and atoms when the
material is subjected to a given load. Stress relaxation over
8.5.1 Wear-Out Mechanisms The primary failure mech- time observed in solder joints is a direct result of creep
anism that affects the reliability of any solder joint connec- processes. Hence the damage accumulated in solder joints
tion is damage accumulation by thermo-mechanical pro- during temperature cycling is a result of creep and fatigue
cesses such as creep and fatigue. Failures are also caused by processes. Deformation due to creep has been observed in
electro-migration and thermal-migration of metal which packages which have been subjected to both cyclic loading
result in opens. Both the thermal-mechanical and electrical as well as static loading conditions.
failures can be increased by chemical reactions or species
which can cause corrosion or enhance migration of metallic Static loading conditions can arise, for example, from the
ions (shorts). A solder bump wear-out failure in the field has weight of a heat sink on a package. Depending on how the
never been observed. This indicates both the robustness of board is placed, that is, sideways, right side up, or inverted,
the solder bump and conservativeness of the reliability the solder joints can experience shear, compressive or
models that will be subsequently explained. tensile loads. The constant load in one direction can cause
failure by creep processes.

8.5.2 Creep-Fatigue Interaction Solder joints can see

8.5.2.1 Electro-Migration In alloy systems, the mobility
large strains during temperature cycling. The strains are
of each atomic species under an applied electric field is
generated by the difference in the thermal expansion be-
different based on the effective valence and mass of the
tween the die and the substrate. The cyclic nature of the
species. Electro-migration has been observed on chips as
temperature variation causes the strains experienced by the
well as in solder joints. In a joint, migration of voids to chip
solder joints to be cyclic and, therefore, the damage in the
or board interface has been observed. Small voids can
solder to be a function of the number of thermal cycles. By
coalesce causing a mechanical reliability concern or current
this definition, solder joints experience thermal creep-
crowding can occur if the effective conductive cross section
fatigue. At uniform strain distributions, fatigue causes
is reduced. In both cases observing design rules with regard
damage by the initiation and propagation of micro-cracks.
to current density and dimension can solve the problem.
Fracturing of solder joints is increased with high rates of
change of strain.
8.5.2.2 Corrosion Solder joint corrosion is usually
In general, components see thermal cycling which can range caused by moisture and ionic contaminants. This can be
from 0.4 Tm to 0.8 Tm, where Tm is the absolute melting prevented by proper packaging design and process control.
temperature of solder. As a rule of thumb, creep is an Due to the close proximity of flip chip solder joints, the
operative deformation mechanism whenever the tempera- cleanliness of the solder joints is essential. Residues from

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corrosive processing chemicals must be minimized. De- Table 8-3 Typical Heights (Joined)
pending on use conditions, the flip chip solder joints should Solder Bump Diameter Height Range
be either hermetically sealed, or encapsulated with a mate- Condition (µm) (µm) (µm)
rial that prevents a continuous moisture path. Option A 150 82 64–100
Option B 125 77 64–95
8.5.2.3 Thermo-Migration Thermo-migration is caused Option C 100 70 64–85
by excessive thermal gradients across solder bumps incor-
Option D 150 >82 64–100
porated on the terminations of BTC packages, especially at
higher IC junction temperatures. In the thermo-migration
process, atoms diffuse in the direction of, or in opposition to predict performance of a solder bump footprint with
to, the thermal gradient. Atoms in the solder bump can similar characteristics and packaging but varying DNP.
diffuse, leading to voiding at the interface of the solder and
the UBM (Under Bump Metallurgy). The bump will even- 8.5.3.2 Effect of Thermal Expansion Mismatch The
tually become electrically open. For a given bump geom- neutral point or geometric center of solder bumps remains
etry, thermo-migration is a function of thermal gradient, stationary relative to the substrate during thermal excur-
ambient temperature, and alloy composition. sions. Determination of the neutral point is critical for
calculating DNP. Figure 8–6 illustrates the result of near-
8.5.3 Solder Thickness Mechanical Reliability There interface failure due to thermal excursion of dissimilar
are numerous factors that can affect the mechanical reliabil- materials.
ity of BTC attachments. Some of these are:
• Strain
• Temperature Hold Times
• Chip Underfill
• Solder Alloy Composition

8.5.3.1 Strain The effect of strain is significant. Its im-

pact on solder bump fatigue is dependent upon several
factors. These are determined by the design, application and
manufacture of the device. Table 8–2 shows the CTE
difference between the chip silicon, alumina, leadframe,
printed board; all which can be part of a typical BTC
package. Strain is directly proportional to DNP, the distance
from the furthest, functional solder bump to the neutral IPC-7093-8-6
point on the chip.
Figure 8-6 The Crack Formation is the Result of the CTE
Table 8-2 Coefficients of Thermal Mismatch
Expansion for Typical Materials
The geometrical shape of the solder joint can greatly affect
Material CTE (ppm/°C)
the local strain. The top and bottom land diameters com-
Silicon 2.8 bined with the volume of solder will determine the height of
GaAs 6.0–7.0 the joint, a prime influence on reliability. Stress ‘‘riser’’
Solder (Sn3Pb97) 28–29 factors can influence crack initiation and propagation.
Chip underfill 18–35
Ideally a tall, slender solder column will distribute the strain
in the solder joint and extend fatigue lifetime. A short, squat
Alumina 6.0–7.0
solder joint may reduce product life.
FR-4 16–19
Copper leadframe 17–18
8.5.3.3 Temperature Cycling Frequency Testing of the
life of components under actual use conditions would take
as long as the design life of the component. For this reason,
Strain is inversely proportional to joint height. Table 8–3
packages are tested by accelerating the thermal cycles, i.e.,
furnishes typical heights for varying solder bump diameters.
by increasing the temperature range and decreasing the hold
The resources required to perform these test are often times at each end of the cycle. Increasing the temperature
limited. Consequently, methods have evolved that use range subjects the joints to greater strain, the extent of
existing solder bump footprints with known fatigue histories which is determined by the thermal expansion mismatch

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IPC-7093 March 2011

between the different materials. Hence, increasing the tem- assemblies are used in a number of non-hermetic applica-
perature range should increase the damage stored in the tions. Reliable operation without corrosion effects will
joints if enough time is allowed for the elastic stresses depend on process control in terms of well sealed sites,
generated in the solder joints to relax out by converting the cleaning of the attach sites, and controlling environmental
elastic strains into plastic deformations by creep. If enough exposure to avoid contaminants from the application envi-
time is not allowed during the hold times, which is typically ronment. In general, this wear-out mechanism is best
the case with accelerated tests, then the damage stored is not controlled through design and process control.
equal to what it would be if the solder joints were allowed
Electro-migration mechanisms are affected by current den-
to creep completely. However, it needs to be noted that
sity. If the designer keeps current density within the
increasing the temperature range of the test much beyond
constraints of the materials being used, and there is strict
the temperatures in the field will cause a confounding of
process control on defects, electro-migration should not be
multiple damage mechanisms.
a problem for most applications.
The design of the temperature cycle ideally should be such
that the stresses generated because of the thermal expansion 8.6.1 Reliability Factors Creep-fatigue is the primary
mismatch have enough time to relax out. However, this is mechanism for wear-out of BTC assemblies. Creep-fatigue
impossible for accelerated testing. Increasing the frequency is accumulated damages caused by cyclic thermal stressing
of cycling can change the failure mechanism and/or sup- by the environment or application and the creeping of the
press the damage stored per cycle in the solder joints. For solder under these loads. This cycling behavior causes
example, changing the temperature rapidly during thermal plastic deformation within the BTC interconnects, which
shock testing can cause high strain rates as well as high initiates a crack that will eventually grow to open or
strains due to component warpage to be imposed on the substantially degrade the interconnect. Most system appli-
solder, which changes the failure mechanism. cations will have temperature changes which will eventually
With near-eutectic solders it is necessary to have hold times fatigue the interconnects.
ranging from 5–10 minutes to achieve a significant, but still It is important that the user of BTC package technologies
incomplete, creep in the joints. The stress relaxation in high have a fundamental understanding of the intrinsic material
lead (90%Pb-10%Sn) solders is slower than that observed in properties and on the design/process driven dimensions for
eutectic solders and therefore the hold times at the tempera- their application. The application environment factors in-
ture extremes need to be greater. Thermal cycles represent volved in fatigue are temperature, temperature cycle range,
the number of thermal excursions a flip chip or chip scale and hold times of the temperature cycling. The BTC
product will be exposed to during its lifetime. These assembly will affect the reliability in terms of presence of
excursions consist of power on-off cycles and environmen- under-fill, the symmetry of interconnect pattern, misalign-
tal temperature fluctuations. Temperature cycling tests the ments and variations of bump geometries and device size.
inelastic properties of the solder, namely stress-relaxation as
a function of temperature and time. Under thermal cycling, the failures will first occur at
locations farthest from the thermal expansion center point. It
is possible to develop detailed models, as most are based on
8.6 Wear-Out Mechanisms Review Bottom termination
some form of the Coffin-Manson equation for low-cycle
interconnects have many potential failures, but there are
fatigue modified to account for the effects of creep. A model
primarily five degradation or wear-out mechanisms which
for each BTC approach could be established if the geometry,
affect metal interconnects. These are:
material and application conditions are known. There are
• Creep various published data on bottom only termination type
• Fatigue component reliability. It is extremely important that a user
• Corrosion establish this level of knowledge to apply these technologies
reliably.
• Electro-migration
• Solid state diffusion
8.6.2 Benefits of Reinforcement BTC underfill can sub-
These mechanisms can all lead to degradation and eventual stantially enhance fatigue life. When the underfill is applied
failure of BTC interconnects. They are very dependent on correctly, it reduces the solder joint strain level by constrain-
materials used, processing defects, reduced geometries, ing the expansion of the BTC interconnect to be used in a
assembly stresses, and environmental conditions. Creep is wider range of environments and larger device sizes can be
caused by stresses or displacements applied to the intercon- accommodated. Underfill material must be carefully se-
nect in one direction. Properly selected materials can lected, so that it adheres to the assembly surface, but does
minimize this mechanism for most environments. Corrosion not adversely stress the BTC interconnect joints. The
could become a concern in some applications. The BTC material must have properties which allow easy application

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March 2011 IPC-7093

to avoid process defects, and it also must not contain or trap To clarify the difference between the two requires an
contaminants which could initiate corrosion related prob- explanation and a definition of reliability. Reliability is
lems. defined in IPC-SM-785 ‘Guidelines for Accelerated Reli-
ability Testing of Surface Mount Solder Attachments’ by:
If an underfill fails, it will most likely lose adhesion to the
device and/or substrate. This would lead to failure due to
Reliability is the ability of a product to function under
fatigue, creep, or it could also increase chances of corrosion
given conditions and for a specified period of time
and other failure mechanisms.
without exceeding acceptable failure levels.
8.6.3 Event Related Failures The assembled BTC as-
In the short term, reliability is threatened by infant mortality
sembly can experience unexpected thermal and/or mechani-
failures due to insufficient product quality; these infant
cal transients, which are isolated events related to mainte-
mortalities caused by defects can be eliminated prior to
nance or just abnormal system operating conditions. These
shipping by the use of appropriate screening procedures.
events could, if they are severe enough, cause catastrophic
failure, or they can initiate failure sites which will then fail Long-term failures are the result of premature wear-out
at a later date. These types of failures are best accommo- damage caused by inadequate designs of the assembly. It is
dated by selecting the most robust technology that can be for this reason that IPC-D-279 ‘Design Guidelines for
used. There are some additional failure mechanisms which Reliable Surface Mount Technology Printed Board Assem-
need to be considered when using flip chip technology. blies’ has been developed.
Most BTC finishes are 63/37 tin/lead alloy, tin, gold or
SAC, thus some BTC interconnects use alloy combinations 8.7.1 Damage Mechanisms and Failure of Solder
that include lead content to improve ductility. This can lead Attachments The reliability of electronic assemblies de-
to trace amounts of radioactive elements which emit alpha pends on the reliability of their individual elements and the
particles which can cause soft errors in semiconductor reliability of the mechanical, thermal, and electrical inter-
devices. It is important to factor the lead and underfill, much faces (or attachments) between these elements. One of these
lower level particle emissions for proximity to sensitive interface types, surface mount solder attachment, is unique
device features to minimize this effect. Most semiconductor since the solder joints not only provide the electrical
devices have ESD protection placed near the pads and most interconnections, but are also the sole mechanical attach-
available devices are not configured for flip chip intercon- ment of the electronic components to the printed board and
nection. Rerouting layers will be applied to the surface of often serve critical heat transfer functions as well.
the device to convert these devices to a BTC array configu- A solder joint in isolation is neither reliable nor unreliable;
ration. This will result in some metal runs in close proximity it becomes so only in the context of the electronic compo-
to device structures that are not protected. nents that are connected via the solder joints to the printed
8.7 Design for Reliability Issues and Concerns The board. The characteristics of these three elements – compo-
reliability of electronic assemblies requires a definitive nent, substrate, and solder joint together with the use
design effort that has to be carried out concurrently with the conditions, the design life, and the acceptable failure prob-
other design functions during the developmental phase of ability for the electronic assembly determine the reliability
the product. There exists a misconception in the industry, of the surface mount solder attachment.
that quality manufacturing is all that is required to assure the
reliability of an electronic assembly. 8.7.2 Solder Joints and Attachment Types Solder joints
are anything but a homogeneous structure. A solder joint
Consistent high quality manufacturing and all that this
consists of a number of quite different materials, many of
implies in terms of Design for Manufacturability (DfM),
which are only superficially characterized. A solder joint
Design for Assembly (DfA), Design for Testability (DfT),
consists of:
etc., is a necessary prerequisite to assure the reliability of
the product. Only a Design for Reliability (DfR) can assure • the base metal at the printed board
that the design, manufactured to good quality, will be • one or more intermetallic compounds (IMC)
reliable in its intended application. Thus, adherence to
• a layer from which the solder constituent forming the
quality standards is necessary but not sufficient. For ex-
PCB-side IMC(s) has been depleted
ample, solder joint quality is generally measured against
criteria in both IPC-A-610 ‘Acceptability of Electronic • the solder grain structure, consisting of at least two
Assemblies’, for overall workmanship and ANSI/J-STD- phases containing different proportions of the solder
001 ‘Requirements for Soldered Electrical and Electronic constituents as well as any deliberate or inadvertent
Assemblies.’ However, meeting these criteria does not contaminations
assure reliable solder connections, only quality solder con- • a layer from which the solder constituent forming the
nections. component-side IMC(s) has been depleted

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• one or more IMC layers of a solder constituent with the 8.7.4 Global Expansion Mismatch The global expansion
component base metal mismatches result from differential thermal expansions of
• the base metal at the component an electronic component or connector and the printed board
to which it is attached via the surface mount solder joints.
These thermal expansion differences result from differences
8.7.3 Solder Interface Grain Structure Effects The
in the CTEs and thermal gradients as the result of thermal
grain structure of solder is inherently unstable. The grains
energy being dissipated within active components. This
will grow in size over time as the grain structure reduces the
global expansion mismatch will cyclically stress, and thus
internal energy of a fine-grained structure. This grain
fatigue, the solder joints. The cyclically cumulative fatigue
growth process is enhanced by elevated temperatures as
damage will ultimately cause the failure of one of the solder
well as strain energy input during cyclic loading. The grain
joints, typically a corner joint, of the component causing
growth process is thus an indication of the accumulating
functional electrical failure that is initially intermittent. See
fatigue damage. At the grain boundaries contaminants like
Figure 8–8.
lead oxides are concentrated; as the grains grow these
contaminants are further concentrated at the grain boundar-
ies, weakening these boundaries. After the consumption of
~25% of the fatigue life micro-voids can be found at the
grain boundary intersections; these micro-voids grow into
micro-cracks after ~40% of the fatigue life; these micro-
cracks grow and coalesce into macro-cracks leading to total
fracture as is schematically shown in Figure 8–7.
The different surface mount solder attachment compositions
can have significantly different failure modes. Solder joints
with essentially uniform load distributions, e.g., QFNs, flip
chip, BGA, CGA, show similar behavior. Solder joints with
non-uniform load distributions, i.e., those on bottom termi-
nation only components, leadless chip carriers, CSPs and all
leaded solder joints, show localized damage concentrations IPC-7093-8-8
with the damage in the form of macro-cracking. The solder
joints frequently connect materials of highly disparate Figure 8-8 Solder Crack Due to Cte Mismatch after 1000
Cycles
properties, causing global thermal expansion mismatches
and are made of a material, solder, that itself often has 8.7.5 Local Expansion Mismatch The local expansion
properties significantly different than the bonding structure mismatch results from differential thermal expansions of the
materials, causing local thermal expansion mismatches. The solder and the base material of the electronic component or
severity of these thermal expansion mismatches, and thus PCB to which it is soldered. These thermal expansion
the severity of the reliability threat, depends on the design differences result from differences in the CTE of the solder
parameters of the assembly and the operational use envi- and those of the base materials together with thermal
ronment. excursions.

IPC-7093-8-7

Figure 8-7 Depiction of the Effects of Accumulating Fatigue Damage in the Solder Joint Structure

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Local CTE-mismatches typically range from ΔCTE~7 solder joint reliability testing. However, in the current
ppm/°C with copper to ~18 ppm/°C with ceramic and ~20 absence of generally useful reliability acceleration models,
ppm/°C with Alloy 42 and KovarTM. Local thermal expan- there currently are no qualification requirements for lead
sion mismatches typically are smaller than the global free solder joint.
expansion mismatches since the acting distance, the maxi-
The validation and qualification tests should follow the
mum wetted area dimension, is much smaller, in the order of
guidelines given in IPC-SM-785, Guidelines for Acceler-
hundreds of microns.
ated Reliability Testing of Surface Mount Solder Attach-
ments. However, for large components with significant heat
8.7.6 Internal Expansion Mismatch An internal CTE-
dissipation, for components of asymmetric construction,
mismatch of ~6 ppm/°C results from the different CTEs of
and for small global CTE mismatches, temperature cycling
the Sn-rich and Pb-rich phases of the solder. Internal
tests are inadequate to provide the required information; full
thermal expansion mismatches typically are the smallest
functional cycling including external temperature and inter-
since the acting distance, the size of the grain structure, is
nal power cycling is necessary.
much smaller than either the wetted length or the compo-
nent dimension in the order of less than 25 µm.
8.10 Screening Procedures

8.8 Solder Attachment Failure The failure of the solder

8.10.1 Solder Joint Defects The solder joint defects of
attachment of a component to the substrate to which it is
greatest reliability concern are those involving inadequate
surface mounted is commonly defined as the first complete
wetting for whatever reason. Properly wetted solder joints
fracture of any of the solder joints of which the component
have adequate strength even for severe mechanical loading
solder attachment consists. Given that the loading of the
conditions as well as no diminished thermal cyclic fatigue
solder joints is typically in shear, rather than in tension, the
reliability. However, solder joints not properly wetted, can
mechanical failure of a solder joint is not necessarily the
prematurely fail both as the result of mechanical and
same as the electrical failure. Electrically, the mechanical
thermal cyclic loading. Voids in the solder joints are
failure of a solder joint results, at least initially, in the
generally regarded as not constituting a reliability threat.
occasional occurrence of a short-duration (<1 µs) high-
However, there are some exceptions. Large voids reducing
impedance event during either mechanical or thermal dis-
the solder joint cross-section enough to reduce a required
turbance. From a practical point of view, the solder joint
thermal heat transfer function, such as those for the thermal
failure is defined as the first observation of such an event.
pads on MLF and QFN devices, can cause premature device
For some applications this failure definition might be failure.
inadequate. For high-speed signals with sharp rise times,
signal deterioration prior to the complete mechanical failure 8.10.2 Screening Recommendations Effective screen-
of a solder joint might require a more stringent failure ing procedures need to be capable of causing the failure of
definition. Similarly, for applications which subject the latent solder joint defects, i.e., weak inadequately wetted
electronic assemblies to significant mechanical vibration solder joints, without causing significant damage to high
and/or shock loading, a failure definition that considers the quality solder joints. The best recommendation is random
mechanical weakening of the solder joints as the result of vibration (6–10 grams for 10–20 minutes), preferably at low
the accumulating fatigue damage might be necessary. temperature, e.g., 40°C. This loading does not damage good
solder joints, but overstresses weakly bonded ones. Thermal
8.9 Validation and Qualification Tests Performance test shock can also be successfully used, however some damage
methods and qualification requirements are specified in to good solder joints can be expected, particularly for larger
IPC-9701; IPC-9701A includes guidelines for lead free components.

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9 DEFECT AND FAILURE ANALYSIS CASE STUDIES 9.1.2 Insufficient Solder Failures

This section provides information on BTC package attach-

ment defects.
The illustrations are provided to assist the user as a process
effects condition The illustrations may be used as a trouble-
shooting guide and controlled experiment characteristics in
order to determine potential solutions for eliminating any
problems.

9.1 Solder Attachment Failures

9.1.1 Solder Attachment Failure Conditions

IPC-7093-9-3

Figure 9–3 Cross section of BTC open joint due to insuf-

ficient solder paste volume during printing.

IPC-7093-9-1

Figure 9–1 Optical image of acceptable QFN edge termi-

nations. Solder fillets should exist if the design incorpo-
rates pads that extend beyond the package width.

IPC-7093-9-4

Figure 9–4 Cross section of BTC reliability failure after

1000 cycles due to insufficient solder paste volume during
printing.

IPC-7093-9-2

Figure 9–2 Optical image of acceptable QFN edge termi-

nations. Solder fillets should be visible to a minimum of 75%
of the width of the termination.

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9.1.3 Land, Nonsolderable 9.2 Package Failures

IPC-7093-9-5 IPC-7093-9-8

Figure 9–5 Nonsolderable land on LGA package. Figure 9–8 Cross section image of QFN with an open joint
caused by nonwetting of the solder to the bottom land of the
QFN.

9.2.1 Package Warpage

IPC-7093-9-6

Figure 9–6 3-D X-ray shows non-wet joints on a QFN.

9.1.4 Termination, Nonsolderable

IPC-7093-9-9

Figure 9–9 Cross section of LGA with a corner joint failure.

The paste wicked to the package.

IPC-7093-9-7

Figure 9–7 Optical image of unacceptable QFN edge ter-

minations. The solder rise is limited and an open joint can
be seen. The package is also ‘floating’ above the surface of
the pads. IPC-7093-9-10

Figure 9–10 Concave warpage on 15x15 mm BTC.

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IPC-7093 March 2011

9.3 Dewetting Failures 9.4 Cracked Solder Joint Failure

9.3.1 Dewetting on QFN 9.4.1 Cracks in Solder Joints

IPC-7093-9-13

Figure 9–13 Defect Condition of QFN edge joints showing

insufficient solder in a joint.
IPC-7093-9-11

Figure 9–11 Good wetting on QFN thermal pad after print-

ing and reflow.

Solder joint cracks

IPC-7093-9-14

Figure 9–14 Cracks in QFN solder joints after temperature

shock.

IPC-7093-9-12

Figure 9–12 Dewetting on QFN thermal pad after printing

and reflow.

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9.5 Component Failures 9.5.2 Lead Configuration Conditions

9.5.1 Tilted Component

IPC-7093-9-17

IPC-7093-9-15 Figure 9–17 Full lead option on BTS component.

Figure 9–15 Tilted BTC causing high joint height open on
the left.

IPC-7093-9-18

Figure 9–18 Half etched option on BTS component.

IPC-7093-9-16

Figure 9–16 Tilted BTC causing good height on the right.

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IPC-7093 March 2011

9.5.3 Joint Configuration Condition 9.5.4 Solder Joint Volume

IPC-7093-9-19 IPC-7093-9-21

Figure 9–19 Small fillet due to nonwetting of the side Figure 9–21 Large fillet due to increase of solder volume.
copper.

IPC-7093-9-22
IPC-7093-9-20
Figure 9–22 No Side fillet on bottom termination compo-
Figure 9–20 Side fillet on bottom termination component nent.
good wetting to copper lead.

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9.6 Voids 9.6.2 Voids in Solder Joints Microsection and X-Ray

9.6.1 Voids in Solder Joint Through Xray

IPC-7093-9-25

Figure 9–25 BTC component with a large edge joint. The

joint did not have any cracking after shock test.

IPC-7093-9-23

Figure 9–23 Target Condition of QFN edge joints where

showing a moderate level of voiding within joints is accept-
able. All joints have reflowed.

IPC-7093-9-26

Figure 9–26 16-pin QFN with voids in the joint and the
thermal pad but well within action level.
IPC-7093-9-24

Figure 9–24 Acceptable Condition of QFN edge joints

showing an increased level of voiding within the joints but
well within any action level.

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IPC-7093 March 2011

9.6.3 Voids in Thermal Pad

IPC-7093-9-27

Figure 9–27 QFN component with increase level of voiding

to above 30%. Could be a reliability concern.

IPC-7093-9-28

Figure 9–28 Acceptable Condition of QFN edge joints

showing an increased level of voiding within the joints but
well within any action level.

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10 GLOSSARY AND ACRONYMS PBBO Polybrominated Biphenyl Oxide

PBDE Polybrominated Diphenyl Ether
AABUS As Agreed Upon Between User And Supplier. PBGA Plastic Ball Grid Array
ASIC Applications Specific IC PCA Printed Circuit Assembly
ASM Array Surface Mount PCB Printed Circuit Board
ASMP Application Specific Module Packaging PCM Phase Change Materials
BGA Ball Grid Array PLCC Plastic Leaded Chip Carrier
BOC Board-On-Chip PSA Pressure Sensitive Adhesives
BT Bismaleimide-Triazine PTH Plated Through-Hole
BTC Bottom Termination Components QFN Quad Flat No-Lead
CBGA Ceramic Ball Grid Array QFP Quad Flat Pack
CGA Column Grid Array RDS Rectangular Die Size
COB Chip-On-Board RF Radio Frequency
CPU Central Processing Unit RFID Radio Frequency Identification
CSP Chip Scale Packages RMS root mean, square
CTE Coefficient Of Thermal Expansion RoHS Restriction of Hazardous Substances
CTF Critical To Function SDRAM Synchronous Dynamic random access memory
DAP Die Attach Pad SMD Solder Mask Defined
DBDPE Decabromodiphenyl Ether SMOBC Solder Mask Over Bare Copper
Df Dissipation Factor SMT Surface Mounting Technology
DFN Dual Flat No-lead SO-DIMM Small Outline Dual In-Line Memory Module
DfR Design For Reliability SOIC small outline integrated circuit
DIG Direct Immersion Gold SON Small Outline No-lead
Dk Dielectric Constant SPC Statistical Process Control
ENEPIG Electroless Nickel/Electroless SRAM Static random access memory
Palladium/Immersion Gold
SSO Simultaneously Switching Output
ENIG Electroless Nickel Immersion Gold
TAB Tape-Automated Bonding
FAT Flux Activation Time
TBBPA Tetrabromobisphenol A
FBGA Fine Pitch Ball Grid Array
Td Decomposition Temperature
FC Flip Chip
TFBGA Thin Profile Fine Pitch Ball Grid Array
FPT Fine Pitch Technology
Tg Transition Temperature
HASL Hot Air Solder Level
TIM Thermal Interface Materials
HAST Highly Accelerated Stress Testing
UFPT Ultra Fine Pitch Technology
HDB High Density Printed Boards
UtRAM Uni-transistor Random Access Memory
I/O Input/Output
UUT Unit Under Test
IMC Intermetallic Compound
UV Ultraviolet
IR Infrared
VFBGA Very Thin-Profile Fine-Pitch Ball Grid Array
LCP Liquid Crystal Polymer
LFBGA Low-Profile Fine-Pitch Ball Grid Array 11 BIBLIOGRAPHY AND REFERENCES
LGA Land Grid Array
LMC Least Material Condition 1. D. Bernard and B. Willis, Common Process Defect
MCM Multichip Module Identification of QFN Packages Using Optical and X-Ray
MCM-L Multichip Module-Laminate Inspection. SMTAI Proceedings, 2007
MCP Multichip Package
2. F. Schuler, M. Rosch, Johannes Horber, Klaus Feldmann,
MD Metal Defined
Reliability Aspects of Electronic Devices for Advanced
MDS Multi Device Subassembly
MLC Multilayer Ceramic
Packages, Circuit World, Vol 34, No 3, 2008.
MMB Moisture Membrane Bag 3. A. Syed, and W. J. Kang, Board Level Assembly And
MMC Maximum Material Condition Reliability Considerations For Qfn Type Packages, SMTAI
MSL Moisture Sensitivity Level Proceedings, 2003
NSMD Non Solder Mask Defined
OEM Original Equipment Manufacturer 4. Engelmaier, W., Surface Mount Solder Joint Reliability:
OSP Organic Solderability Preservative Issues, Design, Testing, Prediction, Workshop Notes, Engel-
PBB Polybrominated Biphenyl maier Associates, Inc., Mendham, NJ, 1995.

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APPENDIX A
Metallographic Preparation

INTRODUCTION b) Removal of heat generated during cutting. When a

situation requires dry cutting, extreme care must be taken
Preparing tin-lead solder joints for metallographic evalua-
to avoid generating heat which may affect the specimen,
tion requires extra care. The samples are composed of high
particularly solder joints or polymeric materials. A cool-
hardness (Copper-Tin) intermetallic compound particles
ant should be chosen which can be cleaned off of the
dispersed in a very soft (Lead, Lead-Tin) matrix. This
specimen easily and completely, so that the encapsulat-
heterogeneous mass is coated on a hard basis material of
ing epoxy can bond to the sample surface.
copper or iron alloy. The lead-tin matrix can recrystallize at
temperatures achieved during the curing of some epoxy 5. Ceramic Precautions: Due to their hardness, aluminum
mounting materials or hardening of some thermoplastic oxide ceramic specimens require the use of diamond
mounting materials. Polyester or acrylic mounting materials bonded cutting equipment during both cutting and grind-
with as LOW a temperature rise during cure or setup as ing. Also, beryllium and beryllium oxide materials pro-
possible are recommended. Great care is required in reveal- duce toxic dust and must never be cut dry.
ing the undeformed, undamaged structure under the super- A2 Mounting The specimen should be encapsulated in
ficial layer. some rigid medium for grinding and polishing, so as to
General comments on metallographic sample preparation, achieve a flat, uniform surface and to protect the solder
mounting, and polishing can be found in IPC-TM-650, joint. Caution must be used to ensure that the mounting
2.1.10 and 2.1.1.2, in IPC-MS-810, ‘‘Guidelines for High procedure does not change the solder joint microstructure.
Volume Microsection,’’ and in Leco Corporation’s ‘‘Metal- Overplating with copper or nickel can help to protect highly
lography Principles and Procedures’’ which also contains deformable materials. Two mounting methods are:
reprints of ASTM E407–70 and ASTM E340–68. In addi- 1. Quick Mounting: This method utilizes a thermoplastic
tion, pages 5–12 in the ITRI publication 580 are instructive material such as polymethylmethacrylate, and typically
in dealing with tin-lead solder joint destructive physical is not entirely transparent. Filling of small cavities and
analysis (DPA). adhesion to the sample may be inferior to the results of
slow mounting. However, one mount can usually be
A1 Cutting The initial step for metallographic preparation prepared in approximately 5–15 minutes. The heat gen-
is the isolation of the component or solder joint for erated by quick mount systems varies widely from
mounting. This entails the use of a jeweler’s saw, router, product to product.
abrasive saw, or similar cutting device to remove the
2. Slow Mounting: This method typically utilizes epoxides
specimen. Several factors should be considered during this
as the mounting media. Vacuum impregnation techniques
initial step:
can be used to remove air bubbles and improve flow of
1. Cut Location: Care must be taken to remove the speci- the encapsulant into confined spaces. Some encapsulants
men without cutting too close to the solder joint of must be cured at temperatures ranging from 60 to 90°C,
interest. The cut should, however, be close enough that while others are room temperature curing, but can
excessive grinding is not required. If in doubt, leave a generate even higher temperatures by exothermic reac-
little extra material. Usually 2.5 mm of material around tions. Experimentation with empty molds will reveal
the area of interest is sufficient. whether this is a problem. Curing in a water bath helps to
2. Fixturing: Care must be taken to ensure that damage is remove excess heat. Mounting time scan vary from 1 to
not done to the specimen while holding it for cutting. 8 hours depending upon the product and the curing
3. Cutting Speed: A smooth, consistent feed rate and conditions.
pressure should be maintained to avoid damaging the A3 Preparation for Mounting When mounting a speci-
specimen. Vibration of the specimen during cutting must men, it is important that it be oriented properly. Proper
be avoided. orientation depends upon your grinding and polishing
4. Cutting Fluids: Oil, water, or other types of coolant equipment and technique. Practice will determine what
should be used with abrasive blades, especially diamond works, and what does not. Here are two basic mounting
blades. The cutting fluid serves two main purposes: methods:
a) Removal of the cutting debris, allowing for efficient 1. Vertical Mounting: The sample is held vertical relative to
material removal. the bottom of the mold either by gluing it to the mold

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March 2011 IPC-7093

floor or by using special clips. The encapsulant can then 6. The hard intermetallic compounds such as Cu6Sn5,
be poured into the mold until it is full. Cu3Sn, Ni3Sn2, Ni3Sn7, AuSn, AuSn2, AuSn4, FeSn,
2. Half-Mounts: The sample is placed horizontally into a FeSn2, and Ag3Sn can cause grooves and channels in the
mold which is half full of previously cured encapsulant. soft lead or lead-tin matrix when the particles break free
The mold is then filled with encapsulant and allowed to and roll downstream. Manually or automatically moving
cure. The sample is then ground from the side, and may or rotating the sample counter to the wheel rotation will
not fit into some automatic machines. If this is a problem, minimize grooves and channels.
then vertical mounting should be used. Note: The grind-
A5 Polishing The next stage of metallographic prepara-
ing and polishing sections of this procedure were written
tion following the grinding step is polishing the sectioning
from the point of view of manually grinding and polish-
plane. Polishing is a less severe continuation of the speci-
ing the sample. Most of the concepts are applicable,
men surface abrasion. Polishing media can include dia-
however, to automatic processing. Attempts have been
mond, aluminum oxide, silicon oxide, or chromium oxide.
made to reconcile the differences between the two
Polishing media particle size progresses from about 9 µm to
procedures.
as fine as 0.05 µm to produce a uniform, scratch free
surface. This is usually divided into coarse (9 to 1 µm) and
A4 Grinding The third step of sample preparation involves
fine (1 to 0.05 µm) polishing. Again several factors should
removing material from the specimen to expose the areas of
be considered during this step:
interest. Grinding is an abrasive process to slowly remove
deformed surface material and reveal underlying, nonde- 1. Cleanliness: WASH THE SAMPLE FREQUENTLY. It
formed regions. Grinding is typically done using silicon is extremely important that the sample and anything that
carbide papers, progressing from 120 to 1000 grit depend- comes near it (including hands and work benches) be as
ing on the amount of material removal required. Several clean as possible at all times during polishing. The
factors should be considered during this step: sample should be washed and rinsed with warm soapy
water before beginning to polish the sample and after
1. Pressure: Sample hardness dictates, to some extent, the each step. Brief ultrasonic cleaning is the most effective
amount of pressure required. Pressure should be kept way to clean out small cavities such as cracks or voids.
light to avoid excess deformation of the specimen
2. Polishing Cloth Selection: The primary difference be-
surface.
tween grinding and polishing is that while grinding grit is
2. Time: The grinding time for each piece of grinding paper fixed in place, polishing uses freely flowing particles in a
should be kept short. Excessive grinding time can cause slurry. This slurry is held on a cloth which determines the
faceting as the grinding paper wears down and the extent of the surface relief and the polish quality. Lower
particles get dull. Faceting is usually corrected by nap cloths will produce a flatter surface than high nap
switching to a new, sharp piece of grinding paper. cloths, but may not remove all scratches as effectively.
3. Cutting Fluid: As with the cutting operation, fluid is Special low nap fine polishing cloths can produce a very
used to remove debris and prevent the specimen from flat, nearly scratch-free surface.
overheating. Water is the most common cutting fluid. 3. Polish Extenders: Extenders play an analogous role in
4. Ceramic Materials: Due to the hardness of ceramics, polishing to that of the cutting fluid in grinding, remov-
components, packages and substrates made of ceramics ing debris and minimizing heat generation. An extender
such as aluminum oxide (alumina) or beryllium oxide also ensures proper dispersion of the polishing media.
(beryllia) require the use of diamond bonded cutting Care must be taken to use the proper amount of extender.
wheels and grinding disks. Mechanical processes such as Too much extender will allow the sample to float,
grinding and polishing of beryllia pieces create a dust causing excessive relief. Too little extender may allow
defined as a hazardous material; this dust must be the encapsulant to soften and absorb polishing media,
suppressed by sufficient coolant and cutting fluid. OSHA especially diamond particles. The extender used is a
and EPA handling requirements will supersede any function of the polishing medium, and is usually either
technical handling or use requirements. The beryllia dust deionized water or a special polishing oil.
mixed with the fluid is defined as a hazardous material; 4. Pressure: Polishing pressure should be very light. Ex-
this aspect must be considered during disposal. cessive pressure causes excessive surface relief
5. Viewing Window: Often during precision grinding it is 5. Direction: Coarse polishing can be done either of two
helpful to look clearly at the sample from above. This ways. Trial and error will indicate which is best for you,
can be accomplished by grinding and polishing a flat area and results may vary for different types of samples.
on the surface of the epoxy perpendicular to the section- Omni-directional polishing involves rotating the sample
ing plane. Some automatic equipment does not allow around the polishing wheel either counter to, or with the
mounting of these irregularly shaped samples, however. wheel rotation. In this way the polishing is performed in

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IPC-7093 March 2011

all directions. Uni-directional polishing is where the 2. A variety of etches for Copper-Tin IMC is shown in
sample is held stationary, and the polishing scratches are Table A-1:
all aligned in one direction. This is particularly useful on Table A1-1 Etchants used to
layered structures. Fine polishing is almost always per- highlight Intermetallic compounds
formed omni-directionally. Most automatic machines Various Etchants
function only in the omni-directional mode. 95 ml H20 7 grams 100 ml 100 ml
FeCl3 H20 NH4OH, 35%
A6 Etching Etching is the final step in metallographic 10 ml 10% 75 ml HCl 100 ml 100 ml H202,
Chromic Acid H202, 3% 3%
sample preparation. The specimen should be examined
2 ml HCl 200 ml
before the etching step is performed for defects, inclusions, H20
porosity, cracks, intergranular corrosion, intermetallic com- 5 ml H2SO4
pound development, and other anomalies. Etching removes
a thin layer of abraded surface deformation, revealing the
3. Solder: Solder can be chemically etched using a dilute
microstructural details of the specimen. Etching requires the
(5% maximum) hydrochloric acid solution, but accept-
use of an acid or a base to chemically attack the sample
able results can usually be obtained by extensive final
surface. Many enchants are available for etching a variety of
polishing using extremely light pressure. Solder is ex-
materials. The disposal of the wastes generated may be a
tremely reactive to most etches, and care must be taken
problem due to the presence of heavy metals such as the
not to destroy its structure.
chromates and of toxics such as beryllia dust. See ASTM
E407–70 for safety cautions. The chemicals used should be 4. Copper:
USP or NF or better. See ITRI publication 580 for etchants • 50 ml Ammonium Hydroxide
specific to tin and its alloys and for photomicrographs of the • 50 ml Water
resulting sample surfaces. • 3 to 5 gm Ammonium Persulfate
5. Stainless Steel or Kovar:
1. Lead-Tin Phases: Nital (1–5 ml HNO3 100 ml ethanol
(95%) or methanol (95%) Immerse 5–40 seconds in 5% • 10 gm Copper Sulfate
HNO3 solution. To remove stain, immerse 25 seconds in • 50 ml Hydrochloric Acid
10% HCl-Methanol solution. • 50 ml Water

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March 2011 IPC-7093

APPENDIX B
Dye Penetrant

Dye penetrant analysis of BTC packages on printed wiring Step 4: Dry the Dye Wipe the BTC package with a
assemblies can be used to confirm assembly process param- laboratory wipe to remove excess dye. Bake the BTC
eters and solder joint quality/integrity. The following pro- package at 100ºC for a minimum of 30 minutes. Bake the
cedure utilizes a fluorescent dye that enhances defect flaws BTC package at 50 °C to 100 ºC for a minimum of 10–30
when inspected under UV light. minutes. The bake time/temperature duration may require
adjustment for your specific dye formulation, the BTC
Step 1: BTC Package Cleaning Prepare the selected BTC
packages being tested and/or assemblies with large thermal
package of interest by cleaning with an Acetone solvent
masses.
rinse. Fully submerge the BTC package in Acetone and
subject the package/solution to 60 second duration in an
ultrasonic cleaner. Remove the BTC package from the Step 5: Freeze the BTC Package It is recommended that
Acetone solvent solution, use clean compressed air to blow the BTC Package be submerged in liquid Nitrogen freezing
any residual solution from the component, and bake at the package allowing for easier pry removal. Caution should
100ºC for 20 minutes to ensure that the package is free from be exercised as liquid nitrogen will burn skin if direct
residual liquid solvent. This cleaning process is intended to contact is achieved. A use proper safety precaution (gloves,
ensure that the BTC package is free from flux residue and eye protection etc.) is required. The duration of the BTC
other materials that may impede the penetration of the dye. package being submerged in the Liquid N2 is dependant on
the package thermal mass. The liquid N2 will “boil” as the
Step 2: Apply the Dye Submerge the BTC package in dye room temperature BTC package is submerged. As the
penetrant. If full submersion of the BTC package is not package reaches equilibrium with the liquid nitrogen the
possible or removal of the BTC package from the printed boiling action will cease.
wiring assembly not possible, lay the printed wiring assem-
bly flat and apply the penetrant to the edge of the BTC
Step 6: Remove the BTC Package and Pry Remove the
package to allow the dye to wick beneath the package body.
BTC package from the liquid nitrogen bath and pry. The
Ensure that sufficient dye has been added such that the
BTC package should pry off easily provided the pry tools
entire underside of the BTC package has been covered
are adequate for the package size. Caution should be
Step 3: Vacuum After the BTC package has been sub- exercised during the pry step to insure that a vertical/tensile
merged, apply an external vacuum to draw out air that may force and not a horizontal/shear force is applied to the BTC
be entrapped under the package body. A 60 second duration package. A shearing force will affect the quality of the
under vacuum is acceptable; however, longer durations can solder joint fracture surface.
be used. Caution should be exercised during the application
of the vacuum as the dye penetrant will likely boil and
Step 7: Inspection of Fractured Solder Joints Inspect
splatter. Adjustment of the vacuum intensity can be con-
the resulting surfaces and document results. It is important
ducted to minimize the dye solution boiling. The boiling
to inspect both fracture surfaces (PCB and BTC) for
action of the dye will impact the efficiency of the dye to
presence of the dye.
wick and penetrate small cracks in the BTC package. Note:
different dye formulations have specific vacuum reaction Figure B1–1 illustrates a BTC component and PCB land
characteristics. after undergoing the Dye and Pry procedure

105
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IPC-7093 March 2011

IPC-7093-b1-1

Figure B1-1 BTC Component (left) and PCB (right) after Part Removal

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Standard Improvement Form IPC-7093

The purpose of this form is to provide the Individuals or companies are invited to If you can provide input, please complete
Technical Committee of IPC with input submit comments to IPC. All comments this form and return to:
from the industry regarding usage of will be collected and dispersed to the IPC
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1. I recommend changes to the following:

Requirement, paragraph number
Test Method number , paragraph number

The referenced paragraph number has proven to be:

Unclear Too Rigid In Error
Other

2. Recommendations for correction:

3. Other suggestions for document improvement:

Submitted by:

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IPC-7093
Design and Assembly Process
Implementation for Bottom
Termination Components
March 2011

Association Connecting Electronics Industries

3000 Lakeside Drive, Suite 309 S Association Connecting Electronics Industries

Bannockburn, IL 60015
847-615-7100 tel
847-615-7105 fax
www.ipc.org ISBN # 1-580986-90-0 ®