Chapter-1

8051 INTERFACING TO ADC 0808/0809:

The ADC 0808/0809 is a 8 Channel analog to digital convertor IC.
It has 8-channel IN0 to IN7.It has three address line i.e. Pin A,B,C
and ALE are use to select one of the analog channel of total 8
channel as shown below.
Address Input Selected
C B A channel
0 0 0 IN0
0 0 1 IN1
0 1 0 IN2
0 1 1 IN3
1 0 0 IN4
1 0 1 IN5
1 1 0 IN6
1 1 1 IN7

ADC 0808/0809 has 3 control signals:-

SOC (Start of conversion): When low to high signal is appears to
this pin of ADC , ADC then starts conversion.
EOC [End of conversion] : ADC sends this high EOC signal to
micro-controller to indicate completion of conversion.
OE [Output Enable] : When a high signal is applied to this pin ,
the output latch of ADC get enable and the converted data is
then available to micro-controller.
  The reference voltage determines the range of analog input
voltages. For example – If reference voltage is 5V then analog
voltage range is from 0V-5V . If the reference voltage is 2.56V
then the analog signal range is from 0V-2.56V.
 The frequency of clock signal applied determines the conversion
speed.

INTERFACING DIAGRAM

 ALE :- ALE input is useful in enabling the input address latches

which store the addresses on lines A, B, C.

8051 INTERFACING TO ADC

PROGRAM :-
 CLR P2.5 Make SOC low
CLR P2.3 Make ALE Low
MOV P1,#FFH Configure Port 1as input
start MOVDPTR , #2000H Initialize memory pointer
MOVA , #00H Set address for channel 0
MOVP2 , A select the channel
SETP2.3 send ALE Signal
NOP
CLRP2.3
SETP2.5 send SOC Signal
NOP
CLRP2.5
Wait JBP2.7,wait
Wait1 JNBP2.7,wait1
MOVA,P1 Get digital data
MOV@DPTR,A
SJMP start
DAC Interfacing with 8051
 Microcontroller are used in wide variety of application like gor
measuring and control of physical quantity like tempreature ,
pressure , speed , distance,etc.
 In these system microcontroller generate output which is in digital
form but the conrolling system require analog system as they
don’t accept digital data thus making it necessary to one DAC
which converts digital data into equivalent analog voltage.
 In the figure shown , we use 8-bit DAC 0808. This IC converts
digital data into equivalent analog current . Hence we require an I
and V convertor to convert this current into equivalent voltage.
 According to theory of DAC equivalent analog output is given as.

V0=Vref
Ex.
1. IF data = 00H[00000000], Vref =10 V

V0 = 10[

Therefore V0 = 0 V.

2. If data is 80H[10000000], Vref =10V

V0 = 10[
Therefore V0 = 5 V.

Different Analog output voltages for different Digital signal is

given as :
DATA OUTPUT VOLTAGE
00H 0V
80H 5V
FFH 10V

Interfacing Diagram
DAC0808 is a D/A convertor IC and this is used for converting 8 bit
digital data input to analog signal output . It is monolithic IC featuring a
full scale output current settling time of 150 ns while dissipating only
33mW with ±5V supplies. The chip accuracy of conversion is good and
power consumption is also low to make it proper.The power supply
current of the DAC0808 are independent of bit codes , and exhibit
essentially constant device characterstics over the entire supply voltage
range.

The device takes in parallel 8bit data from a microcontroller or

microprocessor and converts that data into analog signal at the output.
And the analog output from DAC is a current quantity and this needed
to be converted into voltage parameter for using in application easily.
So to convert current parameter into voltage parameter we will use op-
amp circuit as shown in circuit diagram . This op-amp circuit is called
current-to-voltage convertor.
The output analog voltage from op-amp is in linear relation with input
digital value and hence DAC conversion with DAC0808 is achieved .
Similarly you can also use other application circuits for DAC0808given in
datasheet.

IC =

Applications
 Analog to digital circuits.
 Electrical measurement.
 Audio conversion
 Hobbyist application

Eg.-Design a 8051 based system to interface DAC , Write a Program to

generate Triangular waves and square waves .
Start MOV A,#00H

start MOV P1,A

INC A

CJNE A#FF,start

@MOV P,A

DEC A

CJNE ,#00,@

SJMP start

STEPPER MOTOR INTERFACING WITH 8051:

Stepper motors

A stepper motor is a widely used device that translates electrical pulses into mechanical movement. In
applications such as disk drives, dot matrix printers, and robotics, the stepper motor is used for position
control. Stepper motors commonly have a permanent magnet rotor (also called the shaft) surrounded by
a stator There are also steppers called variable reluctance stepper motors that do not have a PM rotor. The
most common stepper motors have four stator windings that are paired with a center-tapped common.
This type of stepper motor is commonly referred to as a. four-phase or unipolar stepper motor. The center
tap allows a change of current direction in each of
two coils when a winding is grounded, thereby resulting in a polarity change of the stator. Notice that
while a conventional motor shaft runs freely, the stepper motor shaft moves in a fixed repeat-able
increment, which allows one to move it to a precise position. This repeatable fixed movement is
possible as a result of basic magnetic theory

sequence.

Table 17-3; Normal 4-Step Sequence

How much movement is associated with a single step? This depends on the internal construction of
the motor, in particular the number of teeth on the stator and the rotor. The step angle is the
minimum degree of rotation associated with a single step. Various motors have different step angles.
Table 17-4 shows some step angles for various motors. In Table 17-4, notice the term steps per
revolution. This is the total number of steps needed to rotate one complete rotation or 360 degrees
(e.g., 180 steps x 2 degrees = 360).

It must be noted that perhaps contrary to one‟s initial impression, a stepper motor does not need
more ter-

minal leads for the stator to achieve smaller steps. All the stepper motors discussed in this section
have 4 leads for the stator winding and 2 COM wires for the center tap. Although some
manufacturers set aside only one lead for the common signal instead of two, they always have 4
leads for the stators. Next we discuss some associated terminology in order to understand the
stepper motor further.

Example 17-1

Describe the 8051 connection to the stepper motor of Figure 17-9 and code a program to rotate it
continuously.

Steps per second and rpm relation

ULN2003 is used for driving the individual phases of the stepper motor. ULN2003 is a
darlington transistor array used for driving high current loads such as relays and motors.
ULN2003 has 8 individual channels each with 1A capacity. The channels can be paralleled to
increase the current capacity. Each channels are fitted with individual freewheeling diodes.
The ULN2003 is operated in current sinking mode. Each channel is activated by giving a
logic LOW at the corresponding input.

The relation between rpm (revolutions per minute), steps per revolution, and steps per second is as
follows.

The four-step sequence and number of teeth on rotor

The switching sequence shown earlier in Table 17-3 is called the 4-step switching sequence since
after four steps the same two windings will be “ON” How much movement is associated with these
four steps? After completing every four steps, the rotor moves only one tooth pitch. Therefore, in a
stepper motor with 200 steps per revolution, the rotor has 50 teeth since 4×50 = 200 steps are
needed to complete one revolution. This leads to the conclusion that the minimum step angle is
always a function of the number of teeth

Unipolar versus bipolar stepper motor interface

There are three common types of stepper motor interfacing: universal, unipolar, and bipolar. They
can be identified by the number of connections to the motor. A universal stepper motor has eight,
while the unipolar has six and the bipolar has four. The universal stepper motor can be configured
for all three modes, while the unipolar can be either unipolar or bipolar. Obviously the bipolar cannot
be configured for universal nor unipolar mode. Table 17-7 shows selected stepper motor
characteristics. Figure 17-10 shows the basic internal connections of all three type of configurations.

Unipolar stepper motors can be controlled using the basic interfacing shown in Figure 17-11,
whereas the bipolar stepper requires H-Bridge circuitry. Bipolar stepper motors require a higher
operational current than the unipolar; the advantage of this is a higher holding torque.
TIMER / COUNTER PROGRAMMING
 The microcontroller 8051 has two 16 bit timer / controller
register namely Timer 0 and Timer 1. Both these register
can be configured independently to operate as timer or an
event.
 When used as “Timer” the register is programmed to
count the internal clock pulse. The internal clock pulses
are generated from a constant clock generator, the count
loaded in the register gives constant time. The register is
incremented every machine cycle. One machine cycle
consists of 12 oscillator period and so the counting rate is
1/12 of the oscillator frequency.
 When used as “counter”, the microcontroller is
programmed to count external pulses. The register is
incremented in response to a high to lo transition * ]
of the corresponding external input pin, T0 and T1. The
external input does not have a constant frequency and
hence it is not used for timing reference.
 The T0 and T1 pins are sampled during S5P2 of every
machine cycle. When the processor finds it to be ‘0’ in one
machine cycle and ‘1’ in another machine cycle, then it
increments the Timer/ Counter register in S3P1of next
machine cycle.
 Hence, in the order to recognize the high-low transition
the microcontroller requires two machine cycle i.e. 24
oscillator periods. The maximum count rate is 1/24 of the
oscillator frequency.
The timer mode can also be for pulse width measurement.
When the gate bit is kept ‘1’, the timer runs until the INTx
pin is high. Hence the timer is counting the number of
internal clock pulse for which the pulse on INTx pin is at
logic ‘1’. For e.g. if the timer counts 1 to 10 and the cystal
is of 12MHx (i.e. one machine cycle is 1µsec),it indicates
the pulse on INTx pin as at logic ‘1’ for 10µsec.
The counter/timer register are divided into 8 bit register
called the timer low (TL0 and TL1)and timer high (TH0 and
TH1). TL0 and TH0 together form the 16 bit timer 0 and
TL1and TH1 forms the 16 bit timer 1.
The counter action is controlled by the bits in the timer
mode control register (TCON) and some instruction.

TIMER 1 TIMER 0

TH1 TL1 TH0 TL0

(8 bit) (8 bit) (8 bit) (8 bit)

Timer Control (TCON)

Timer Mode (TMOD)

 (MSB) (LSB)

GATE C/T M1 M0 GATE C/ T M1 M0

Timer 1 Timer 0
GATE – Getting control hen set timer/counter “x” is
enabled only hile ‘INTx’, pin is high and ‘TRx’ control
pin is set. When cleared, Timer ‘x’ is enabled henever
‘TRx’ control bit is set. It is used for pulse idth
measurement (PWM) of the pulse on INTx pin.
C/T – Timer or Counter selector. Cleared for timer operation
(input from internal system clock). Set for Counter
operation (input from “Tx” input pin).
 M1 M0 Operating Mode
0 0 MODE-00 8 bit timer /counter ‘THx’ ith ‘TLx’ as 5
bit prescalar.
0 1 MODE-01,8 bit timer /counter ‘THx’ and ‘TLx’ are
cascaded, there is no prescaler.
1 0 MODE-02,8 bit auto reloaded. Timer / counter ‘TLx’
holds a value hich is to be reloaded into ‘TLx’ each
time it overflows.
1 1 MODE-03, (Timer 0) TL0 is an 8 bit timer/counter
controlled by the standard timer 0 control bits
controlled by timer 1 control bits.

(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timer 1 Timer 0 INT1 INT0

 SYMBOL POSITION NAME AND SIGNIFICANCE
TF1 TCON.7 Timer 1 overflow flag. Set by hardware on
timer counter overflow. Cleared by
hardware when processor vector to
interrupt routine.
TR1 TCON.7 Timer 1 run control bit set/cleared by
software to turn timer/counter on/off.
TF0 TCON.5 Timers 0 overflow flag. Set by hardware on
timer counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
TR0 TCON .4 Timer 0 run control bit set/cleared by
software to turn timer/counter on/off.
IE1 TCON.3 Interrupt 1 Edge flag set by hardware when
external interrupt edge detected. Cleared
when interrupt processed.
IT1 TCON .2 Interrupt 1 type control bit. Set/cleared by
software to specify falling edge /low level
triggered external interrupt.
IE0 TCON.1 Interrupt 0 edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.
IT0 TCON.0 Interrupt 0 type control bit set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Mode 0 of Timer/Counter
The Mode 0 operation is the 8-bit timer or counter with a 5-bit pre-scaler.
So it is a 13-bit timer/counter. It uses 5 bits of TL0 or TL1 and all of the
8-bits of TH0 or TH1.
In this example the Timer1is selected, in this case, every 32 (25)event
for counter operations or 32 machine cycles for timer operation, the TH1
register will be incremented by 1. When the TH1overflows from FFH to
00H, then the TF1 of TCON register will be high, and it stops the
timer/counter. So for an example, we can say that if the TH1 is holding
F0H, and it is in timer mode, then TF1will be high after 10H * 32 = 512
machine cycles.0000 to 1FFF
MOVTMOD, #00H
MOVTH1, #0F0H
MOVIE, #88H
SETB TR1

In the above program, the Timer1 is configured as timer mode 0. In this

case Gate = 0. Then the TH1 will be loaded with F0H, then enable the
Timer1 interrupt. At last set the TR1 of TCON register, and start the
timer.

Mode 1 of Timer/Counter
The Mode 1 operation is the 16-bit timer or counter. In the following
diagram, we are using Mode 1 for Timer0.

In this case every event for counter operations or machine cycles for
timer operation, the TH0– TL0 register-pair will be incremented by 1.
When the register pair overflows from FFFFH to 0000H, then the TF0 of
TCON register will be high, and it stops the timer/counter. So for an
example, we can say that if the TH0 – TL0 register pair is holding
FFF0H, and it is in timer mode, then TF0 will be high after 10H = 16
machine cycles. When the clock frequency is 12MHz, then the following
instructions generate an interrupt 16 µs after Timer0 starts running.
MOVTMOD, #01H
MOVTL0, #0F0H
MOVTH0, #0FFH
MOVIE, #82H
SETB TR0

In the above program, the Timer0 is configured as timer mode 1. In this

case Gate = 0. Then the TL0 will be loaded with F0H and TH0 is loaded
with FFH, then enable the Timer0 interrupt. At last set the TR0 of TCON
register, and start the timer.
Mode 2 ofTimer/Counter
The Mode 2 operation is the 8-bit auto reload timer or counter. In the
following diagram, we are using Mode 2 for Timer1.

In this case every event for counter operations or machine cycles for
timer operation, the TL1register will be incremented by 1. When the
register pair overflows from FFH to 00H, then the TF1 of TCON register
will be high, also theTL1 will be reloaded with the content of TH1 and
starts the operation again.
So for an example, we can say that if the TH1 and TL1 register both are
holding F0H and it is in timer mode, then TF1 will be high after 10H= 16
machine cycles. When the clock frequency is 12MHz this happens after
16 µs, then the following instructions generate an interrupt once every 16
µs after Timer1 starts running.
MOVTMOD, #20H
MOVTL1, #0F0H
MOVTH1, #0F0H
MOVIE, #88H
SETBTR1
In the above program, the Timer1 is configured as timer mode 2. In this
case Gate = 0. Then the TL1 and TH1 are loaded with F0H. then enable
the Timer1 interrupt. At last set the TR1 of TCON register, and start the
timer.
Timer1 in mode 2 generates the desired baud rate when the serial port is
working on Mode 1 or 3.

Mode 3 of Timer/Counter
Mode 3 is different for Timer0 and Timer1. When the Timer0 is working
in mode 3, the TL0 will be used as an 8-bit timer/counter. It will be
controlled by the standard Timer0 control bits, T0 and INT0 inputs. The
TH0 is used as an 8-bit timer but not the counter. This is controlled by
Timer1 Control bit TR1. When the TH0 overflows from FFH to 00H, then
TF1 is set to 1. In the following diagram, we can Timer0 in Mode 3.

When the Timer1 is working in Mode 3, it simply holds the count but
does not run. When Timer0 is in mode 3, the Timer1 is configured in one
of the mode 0, 1 and 2. In this case, the Timer1 cannot interrupt the
microcontroller. When the TF1 is used by TH0 timer, the Timer1 is used
as Baud Rate Generator.
The meaning of gate bit in Timer0 and Timer1 for mode 3 is as follows
It controls the running of 8-bit timer/counter TL0 as like Mode 0, 1, or 2.
The running of TH0 is controlled by TR1 bit only. So the gate bit in this
mode for Timer0 has no specific role.
The mode 3 is present for applications requiring an extra 8-bit
timer/counter. In Mode 3 of Timer0, the 8051 has three timers. One 8-bit
timer by TH0, another8-bit timer/counter by TL0, and one 16-bit
timer/counter by Timer1.
If the Timer0 is in mode3, and Timer1 is working on either 0, 1 or 2, then
the gun control of the Timer1 is activated when the gate bit is low
or INT1 is high. The run control is deactivated when the gate is high
and INT1 is low.

GATE
The other bit of the TMOD register is the GATE bit. Notice in the TMOD
register of Figure 9-3 that both Timers 0 and 1 have the GATE bit. What
is its purpose? Every timer has a means of starting and stopping. Some
timers do this by software, some by hardware, and some have both
software and hardware controls. The timers in the 8051 have both. The
start and stop of the timer are controlled by way of software by the TR
(timer start) bits TRO and TR1. This is achieved by the instructions
“SETB TR1″ and “CLR TR1″ for Timer 1, and “SETB TRO” and “CLR
TRO” for Timer 0. The SETB instruction starts it, and it is stopped by the
CLR instruction. These instructions start and stop the timers as long as
GATE = 0 in the TMOD register. The hardware way of starting and
stopping the timer by an external source is achieved by making GATE =
1 in the TMOD register. However, to avoid further confusion for now, we
will make GATE = 0, meaning that no external hardware is needed to
start and stop the timers. In using software to start and stop the timer
where GATE = 0. all we need are the instructions “SETB TRx” and “CLR
TRx”. The use of external hardware to stop or start the timer is
discussed in Chapter 11 when interrupts are discussed.

Indicate which mode and which timer are selected for each of the
following.
(a) MOV TMOD,#01H (b) MOV TMOD,#20H (c) MOV TMOD,#12H
1. TMOD = 00000001, mode 1 of Timer 0 is selected.
2. TMOD = 00100000, mode 2 of Timer 1 is selected.
1. TMOD = 00010010, mode 2 of Timer 0, and mode 1 of
Timer 1 are selected.

Clock source for timer

As you know, every timer needs a clock pulse to tick. What is the source
of the clock pulse for the 8051 timers? If C/ T = 0. the crystal frequency
attached to the 8051 is the source of the clock for the timer. This means
that the size of the crystal frequency attached to the 8051 also decides
the speed at which the 8051 timer ticks. The frequency for the timer is
always 1/12th the frequency of the crystal attached to the 8051.
Example 9-8
Modify TL and TH in Example 9-7 to get the largest time delay possible.
Find the delay in ms. In your calculation, exclude the overhead due to
the instructions in the loop.
Solution:
To get the largest delay we make TL and TH both 0. This will count up
from 0000 to FFFFH and then roll over to zero.

Making TH and TL both zero means that the timer will count from 0000
to FFFFH, and then roll over to raise the TF flag. As a result, it goes
through a total of 65536 states. Therefore, we have delay = (65536 – 0)
x 1.085 us = 71.1065 ms.

(FFFF – YYXX + 1) X 1.085 us where YYXX are TH, TL initial values

respectively. Notice that values YYXX are in hex.

Example 9-7
Find the delay generated by Timer 0 in the following code, using both of
the methods of Figure 9-4. Do not include the overhead due to
instructions.
1. (FFFF-B83E + 1) = 47C2H= 18370 in decimal and 18370 x 1.085 fis=
19.93145ms.
2. Since TH – TL = B83EH = 47166 (in decimal) we have 65536 – 47166
= 18370.
This means that the timer counts from B83EH to FFFFH.. This plus
rolling over to
0 goes through a total of 18370 clock cycles, where each clock is
1.085 \ls in dura
tion. Therefore, we have 18370 x 1.085 (is = 19.93145 ms as the
width of the pulse.
 SERIAL COMMUNICATION IN 8051

8051 UART
Introduction

Serial communication means to transfer data bit by bit serially at a time,

whereas in parallel communication, the number of bits that can be
transferred at a time depends upon the number of data lines available for
communication.
Two methods of serial communication are

 Synchronous Communication: Transfer of bulk data in the framed

structure at a time
 Asynchronous Communication: Transfer of a byte data in the
framed structure at a time
8051 has built-in UART with RXD (serial data receive pin) and TXD
(serial data transmit pin) on PORT3.0 and PORT3.1 respectively.

Serial communication Registers

SBUF: Serial Buffer Register: It is an 8-bit register and is used for serial
communication of data in 8051 microcontroller. Whatever data is
required to be transmitted via TXD line must be placed in the SBUF
register. Similarly the received data via RXD line is saved in SBUF
register. When data is written to SBUF register then it is framed in b/w
start and stop bit before it is transmitted via TXD line and similarly
during reception of data start and stop bits are removed and actual data
bits are extracted from the received frame and then it is placed in the
SBUF register
This is the serial communication data register used to transmit or receive
data through it.SIPO/PISO

Asynchronous communication
Asynchronous serial communication is widely used for byte-oriented
transmission.
Frame structure in Asynchronous communication:

 START bit: It is a bit with which serial communication starts and

it is always low.
 Data bits packet: Data bits can be 5 to 9 bits packet. Normally we
use 8 data bit packet, which is always sent after the START bit.
  STOP bit: This is one or two bits. It is sent after the data bits
packet to indicate the end of the frame. The stop bit is always logic
high.

In an asynchronous serial communication frame, the first START bit

followed by the data byte and at last STOP bit forms a 10-bit frame.
Sometimes the last bit is also used as a parity bit.

8051 Serial Frame Structure

Data transmission rate

The data transmission rate is measured in bits per second (bps). In the
binary system, it is also called a baud rate (number of signal changes per
second). Standard baud rates supported are 1200, 2400, 4800, 19200,
38400, 57600, and 115200. Normally most of the time 9600 bps is used
when speed is not a big issue.
Interface standard

 8051 serial communication has TTL voltage level which are 0 v

for logic 0 and 5 v for logic 1.
 In computers and most of the old devices for serial
communication, RS232 protocol with DB9 connector is used.
RS232 serial communication has different voltage levels than 8051
serial communication. i.e. +3 v to +25 v for logic zero and -3 v to -
25 v for logic 1.
 So to communicate with RS232 protocol, we need to use a voltage
level converter like MAX232 IC.
  Although there are 9 pins in the DB9 connector, we don’t need to
use all the pins. Only 2nd Tx(Transmit), 3rd Rx(Receive), and 5th
GND pin need to be connected.

SCON: Serial Control Register

Serial control register SCON is used to set serial communication
operation modes. Also it is used to control transmit and receive
operations.

Bit 7:6 - SM0:SM1: Serial Mode Specifier

Normally mode-1 (SM0 =0, SM1=1) is used with 8 data bits, 1 start bit,
and 1 stop bit.
Bit 5 - SM2: for Multiprocessor Communication
This bit enables a multiprocessor communication feature in mode 2
& 3.
Bit 4 - REN: Receive Enable
1 = Receive enable
0 = Receive disable
Bit 3 - TB8: 9th Transmit Bit
This is the 9th bit which is to be transmitted in mode 2 & 3 (9-bit
mode)
Bit 2 - RB8: 9th Receive Bit
This is the 9th received bit in mode 2 & 3 (9-bit mode), whereas in mode
1 if SM2 = 0 then RB8 hold the stop bit that received
Bit 1 - TI: Transmit Interrupt Flag
This bit indicates the transmission is complete and gets set after
transmitting the byte from the buffer. Normally TI (Transmit Interrupt
Flag) is set by hardware at the end of the 8th bit in mode 0 and at the
beginning of stop bit in other modes.
Bit 0 – RI: Receive Interrupt Flag
This bit indicates reception is complete and gets set after receiving the
complete byte in the buffer. Normally RI (Receive Interrupt Flag) is set
by hardware in receiving mode at the end of the 8th bit in mode 0 and at
the stop bit receive time in other modes.
Serial port mode :
Mode 0:
• Only synchronous mode
• Data transferred on RXD clock on TXD
• Clock is fixed at 1/12 of the oscillator frequency
Mode 1:
• Asynchronous mode
• 10 bit data frame (start bit, 8 data bit and stop bit)
• Variable baud rate
• Stop bit is placed in RB 8 bit of SCON register on reception of a frame
Mode 2:
• Asynchronous mode
• 11 bit data frame (start bit, 8 data bit, programmable 9 bit and stop bit)
• On transmission 9th bit is TB 8 bit of SCON
• On reception 9th bit is placed in RB 8 bit of SCON
• 9th bit may be used for data or as a parity bit
• Baud rate may be 1/32 or 1/64 of oscillator frequency
Mode 3:
• Same as module 2 but with programmable baud rate

8051 Serial Interface

8051 UART Programming

Baud Rate calculation:

 To meet the standard baud rates generally crystal with 11.0592

MHz is used.
 As we know, 8051 divides crystal frequency by 12 to get a
machine cycle frequency of 921.6 kHz.
 The internal UART block of 8051 divides this machine cycle
frequency by 32, which gives the frequency of 28800 Hz which is
used by UART.
  To achieve a baud rate of 9600, again 28800 Hz frequency should
be divided by 3.
 This is achieved by using Timer1 in mode-2 (auto-reload mode) by
putting 253 in TH1 (8-bit reg.)
 So 28800 Hz will get divided by 3 as the timer will overflow after
every 3 cycles.
 we can achieve different baud rates by putting the division factor
in the TH1 register.

Division factor to achieve different baud rates

Baud Rate TH1 (Hex)
9600 FD
4800 FA
2400 F4
1200 E8
RS232:-
RS232 defines the signals connecting between DTE and DCE. Here, DTE
stands for Data Terminal Equipment and an example for DTE is a
computer. DCE stands for Data Communication Equipment or Data Circuit
Terminating Equipment and an example for DCE is a modem.
RS232 uses serial communication, where one bit of data is sent at a time
along a single data line. This is contrast to parallel communication, where
multiple bits of data are sent at a time using multiple data lines.The
advantage of using serial communication over parallel communication is
the number of wires required to make a full duplex data transmission will
be very less (two wires are sufficient without considering electrical lines).
the main drawback of RS232 standard is data rate and length of cable.
RS232 supports a maximum baud rate of 19200 bps and the maximum
length of the cable is 20 meters.
Signal Name Function

Protective Ground This signal is connected to chassis ground of metallic connector.

Common Ground Zero reference voltage level for all the control signals.

TxD (Transmit Pin) To transmit data from DTE to DCE.

RxD (Receive Pin) Sends data from DCE to DTE.

DTR (Data Terminal Ready) DTE is ready to accept request.

DCD (Data carrier DCE accepts a carrier from a DTE located at remote location.
Detect)

DSR (Data Set Ready) DCE is prepared to send and receive the information.

RI (Ring Indicator) Detects the incoming ring tone on the telephone line.
Signal Name Function

RTS (Request to Send) DTE call for DCE to send the data.

RTR (Ready to Receive) DTE is geared up to receive data coming from DCE.

CTS (Clear To Send) DCE is in a ready state to accept data coming from DTE.

Assume a computer (DTE) is connected to a Modem (DCE) through

RS232 interface. In order to send data from computer to Modem, the
following procedure must be followed.

 When Modem (DCE) is ready to receive, it will send a DCE ready

signal.
 When the computer (DTE) is ready to send the data, it sends a Ready
to Send (RTS) signal.
 The Modem (DCE) then sends a Clear to Send (CTS) signal to
indicate that data can be sent by computer (DTE).
 Finally, the Computer (DTE) sends data on Transmit Data (TD) line
to the Modem (DCE).
Applications
 Though RS232 is a very famous serial communication protocol, it is
now has been replaced with advanced protocols like USB.
 Previously they we used for serial terminals like Mouse, Modem etc.
 But, RS232 is still being used in some Servo Controllers, CNC
Machines, PLC machines and some microcontroller boards use
RS232 Protocol.

RxD and TxD pins in the 8051

The 8051 has two pins that are used specifically for transferring and
receiving data serially. These two pins are called TxD and RxD and are
part of the port 3 group (P3.0 and P3.1). Pin 11 of the 8051 (P3.1) is
assigned to TxD and pin 10 (P3.0) is designated as RxD. These pins are
TTL compatible; therefore, they require a line driver to make them
RS232 compatible. One such line driver is the MAX232 chip. This is
discussed next.
MAX232
Since the RS232 is not compatible with today‟s microprocessors and
microcontrollers, we need a line driver (voltage converter) to convert the
RS232′s signals to TTL voltage levels that will be acceptable to the 8051
„s TxD and RxD pins. One example of such a converter is MAX232 from
Maxim Corp. (www.maxim-ic.com). The MAX232 converts from RS232
voltage levels to TTL voltage levels, and vice versa. One advantage of
the MAX232 chip is that it uses a +5 V power source which, is the same
as the source voltage for the 8051. In other words, with a single +5 V
power supply we can power both the 8051 and MAX232, with no need
for the dual power supplies that are common in many older systems.
The MAX232 has two sets of line drivers for transferring and receiving
data, as shown in Figure 10-7. The line
drivers used for TxD are called Tl and T2,
 Chapter-2

8096 Microcontroller :

 CPU with 232 byte register file and register ALU

 8-Kbyte internal ROM
 Programmable high speed I/O unit.
 Two 16-bit Timers/Counters
 Serial port
 Pulse width modulator
 Watchdog timer
  Eight multiplexed inputs analog to digital converter with 10 bit
resolution and
 Memory controller
The MSC-96 family members are all high performance microcontroller with a 16 bit CPU and at
least 230 bytes of on-chip RAM.

• Intel MSC-96 family easily handles high speed calculations and fast input/out operations.

• All of the MCS-96 components share a common instruction set and architecture. However the
CHMOS components have enhancements to provide higher performance with lower power
consumption.

• These microcontroller contains dedicated I/O subsystem and perform 16-bit arithmetic
instructions including multiply and divide operations.

CPU: The major components of the MCS-96 CPU are the Register File and the Register /
Arithmetic Logic Unit (RALU).

• Location 00H through 17H are the I/O control registers or Special function registers (SFR).

• Locations 18H and 19H contains the stack pointer, which can serve as general purpose RAM
when not performing stack operations.

• The remaining bytes of the register file serve as general purpose RAM, accessible as bytes,
words or double-words.

• Calculations performed by the CPU take place in the RALU. The RALU contains a 17bit ALU,
the program status word (PSW), the program Counter (PC), a loop counter and three temporary
registers.

• The RALU operates directly on the Register Files, thus eliminating accumulator bottleneck and
providing for direct control of I/O operations through the SFR.

8096 Peripherals

• Standard I/O Ports – The 8096 has five 8 bit I/O ports.

• Port 0 is an input port that is also the analog input for the A/D converter.

• Port 1 is a quasi-bidirectional port.

• Port 2 contains three types of port lines.

• Quasi-Bidirectional input and output. Other functions on the 8096 share the input and output
lines with Port 2.
• Port 3 and 4 are open-drain bidirectional ports that share their pins with the address/data bus.

• Timers – The 8096 has two 16 bit timers. Timer 1and Timer 2.
• An internal clock increments the Timer 1 value every 8 state times. (A state time is 3
oscillator periods)

• An external clock increments Timer 2 on every positive and negative transition.

• Either an internal or external source can reset Timer 2.

• This two timers can generate an interrupt when crossing the 0FFFFH/0000H boundary.

• The 8096 includes separate, dedicated timers for serial port baud rate generator and watchdog
timer.

• The watchdog Timer is an internal timer that resets the system if the software fails to operate
properly.

• High Speed Input Unit (HSI) – The 8096 HIS unit can record times of external events with a
9 state time resolution. It can monitor four independently configurable HSI lines and captures the
value of timer 1 when events takes place.

• The four types of events that can trigger captures include: rising edge only, falling edge only,
rising or falling edges, or every eight rising edge.

• The HSI unit can store upto 8 entries (Timer 1 values ).

• Reading the HSI holding register unloads the earliest entry placed in the FIFO.

Microprocessors and Microcontrollers/Architecture of Micro controllers Lecture Notes

• The HSI unit can generate an interrupt when loading an entry into the HSI holding register or
loading the sixth entry into the FIFO.

• High Speed Output Unit (HSO) – The 8096 HSO unit can trigger events at specified
times based on Timer1 or Timer2.

• These programmable events include: starting an A/D conversion, resetting Timer2, generating
upto four software time delays, and setting or clearing one or more of the six HSO output lines.

• The HSO unit stores pending event and specified times in a Content Addressable Memory
(CAM) file. This file stores upto 8 commands.

• Each command specifies the action time, the nature of the action, whether an interrupt is to
occur, and whether Timer1 or Timer2 is the reference timer.
 • Every 8 state times the HSO compares the CAM locations for time matches. The HSO unit
triggers the specified event when it finds a time match.

• A command is cleared from the CAM as soon as it executes.

• Serial Port – The serial port on the 8096 has one synchronous (Mode 0) and three
asynchronous modes (Modes 1, 2 and 3).

• The asynchronous modes are full duplex.

• Mode 0, the synchronous mode, is to expand the I/O capability of the 8096 using shift register.

• Mode 1 is the standard asynchronous mode used for normal serial communication.

• Modes 2, 3 are 9-bit modes commonly used for multiprocessor communications.

• Pulse Width Modulator (PWM) – The PWM output waveform is a variable duty cycle pulse
that repeats every 256 state times.

• The PWM output can perform digital to analog conversions and drive several types of motors
that require a PWM waveform for more efficient operation.

• A/D Converter – The 8096 A/D converts an analog input to a 10 bit digital equivalent.

• The main components of the A/D Converter are: 8 analog inputs, an 8 to 1 multiplexer, a
sample and hold capacitor and resistor ladder.

• The A/D Converter can start a conversion immediately or the High Speed Output unit can
trigger a conversion at a pre-programmed time.

• The A/D converter performs a conversion in 88 state times. Upon completion of each
conversion the converter can generate a conversion complete interrupt.

• The 8X9X provides separate VREF and ANGND supply pins to isolate noise on the Vcc or
Vss lines. •

# Memory Mapping of 8096 Microcontroller: -

SFR → Special Function Register → Timers / Parto/HS, HSo.

SP → Stack Pointer.

Interrupt vector → It store ISR address.

The addressable memory space of the 8096-memory space consists of 64KB, most
of which is available to the user program for data memory.

 Factory reset: - This port will simply delete all data from your device as well
as any applications. Then it’s going to return your device back to its factory
state.
 SRF: -Out of 256 locations. The first 24 memory locations, SRF, are used to
control on chip input output section. For example, timer 1,2 Port 0,1,2;
SBUF; HSo, HS, etc.
  RALU: - The remaining 232 locations are the RAM location. This location
can be accessed as byte Band or double band, since each of these locations
can be used by RALU.
 Power down RAM: - The upper 16 byte of RAM is called power down RAM
because this location receives their power from the VPD pin, in the power
down mode. Hence in power down, only these locations are alike. Power
down mode is used to save power in microcontroller

Addressing mode of 8096 microcontroller: -

Register / memory address is continuous in 8096 and there are no register (other
than special function register). They are dedicated specially for arithmetic and
logical operation and indirect addresses pointer there are following addressing
mode.

1. Direct addressing mode: -

LDB D, S -> load a byte from direct source address to destination address.

LDWD, WS -> load a word from direct source address to destination address.

2. Immediate address mode: -

LDB, D, #25H -> Load a bite at byte destination address.

LDWD, #3000H -> Load a word at what destination address.

3. Indirect addressing mode: -

ADD BD, [S]

ADD WD, [WS] -> Add16 bit word at operand from direct address WD with a
address finded by WS.

4. Indirect with auto paste increment of pointer: -

ADD WD, [WS]+ -> Add operant from direct address WD with address find it by
WS and then increment the WS pointer {by 2} because it is a word pointer.

5. Indexed short: -
ADD WD, WS1 offset [WS2]: - Operant from direct address ws1 with direct
address find it by ws2 after adding it by offset.

6. Indexed long: -
ADD WS, WS1, Display [WS2] -> Add operant from direct address WS1 with
address pointer WS2 after adding it by displacement.

7. Implicit: -
(pre-defined instruction) SETC, POPF, PUSHF.

# Instruction set of 8096 microcontroller: -

 Data transfer
 Stack instruction
 Data bit manipulation
 Arithmetic and logical instruction
 Shift instruction
 Program flow control instruction

1. Data transfer -> LD = Load word

LDB = Load bite
ST = Store World
STB = Store bite
BMOVE = Move block
2. Stack -> PUSH
PUSHF = Push Flag
PUSHA = Push All
POPF = POP Flag
POPA = POP All
3. Data and Bit manipulation -> SETC =Set Carry
CLRVT = CLR overflow flag
CLRC = Clear Carry
 CLRB = Clear byte
CLR = Clear word
4. Arithmetic and logical -> ADD = add word
ADDB = add byte
ADDCB = add byte with carry
SUB = subtract word
SUBB = subtract byte
SUBC = subtract byte with borrow
MUL = multiply word
MULB = multiply byte
MULU = multiply word (unsigned number)
MULUB = multiply byte (unsigned number)
5. Shift Instruction -> SHL = Shift left word
SHLB = Shift lest word
SHR = Shift right word
SHRA = Shift arithmetic right word
SHRB = Shift right byte
6. Program Flow Control -> RST = To reset CPU
EI & DI = Enable and disable interrupt
DINZ = Decrement jump not zero for byte
DINZ = Decrement jump not zero for word
SCALL = short call
LCALL = Long call.
 Chapter-3
UNIT III

INTRODUCTION TO EMBEDDED SYSTEM

INTRODUCTION :-

A system is a method of working, organizing or doing one or many tasks according to a fixed plan,
program or set of rules. It is an arrangement in which all its units asseurable and work together
according to the plan or program.

Let us examine the following of a system-

Consider a watch. It is a TIME DISPLAY SYSTEM. It comprises of hardware, needles and battery, a dial,
and strap. These parts organize to shaw the real time every second. The system program update the
display after each second.

It follows the following set of rules---

I. All needles move clockwise only.

II. A thin and long needle rotates every second and returns to same position after a minute.
III. A long needle rotates every minute such that it returns to same position after an hour.
IV. A short needle rotates every hour such that it rotates to same position after 12 hours.
V. All three needles return to the same inclination after 12 hour.

EMBEDDED SYSTEM

A computer is a system that consists of a microprocessors (CPU) , a large memory comprising the

I. Primary memory RAM, ROM (semiconductor memory)

II. Secondary memory – magnetic memories located in hard disks ,tapes, pen drives etc, input
devices like keyboard, mouse , output devices like video monitor, printer etc.

“ An Embedded system is a system that has computer hard are ith soft are embedded in it as one of
its most important component. ”

 It is a dedicated computer based system for an application(s) or product. It may be either an

independent system ie a part of a larger system.
 Its software is generally embedded in the ROM of the system. Hence it does not require any
secondary memory as that in case of a computer.
COMPONENT OF EMBEDDED SYSTEM

An embedded system comprises of three component :-

I. HARDWARE – The following figure shows the hardware units of an embedded system.
II. APPLICSTION SOFTWARE – that may perform a series of tasks or multiple tasks at the same
time.
III. HARDWARE UNIT OF EMBEDDED SYSTEM

INPUT DEVICE

INTERFACING/
POWER DRIVER CIRCUIT SYSTEM
SUPPLY
APPLICA
RESET PROCESSORS PROGRM TION
MEMORY AND
OSCILLAT DATA MEMORY SPECIFIC
OR
CIRCUIT
CIRCUIT TIMER SERIAL
COMMUNICATION
PORTS

INTRRUPT PARALLEL
CONROLLER PORTS

OUTPUT
INTERFACING /
DRIVER

It has a real time operating system (RTOS) that supervisesthw application software. It provides a
mechanism to allow the processor to run a process as per scheduling and do the context switch
between the various processes (tasks).

ROLE OF RTOS—

RTOS organizes access to a resource in sequence of the series of tasks of the system. It
schedules their working and execution by—

 Following a plan to control the latencies and to meet the deadlines (latency refers to
the waiting period between running the codes of a task and the instance at which the
need for task arises )
  RTOS sets the rules during the execution of the application software.

A small scale embedded system may not need an RTOS.

SOFTWARE UNIT OF EMBEDDED SYSTEM –

An embedded system has software designated to keep in view following three constraints :-

I. Available system memory (RAM and ROM)

II. Available processor speed and
III. The need to , limit power dissipation when running the system continously in cycles of wait
for events, run, stop, and wakeup.

CLASSIFICATION OF EMBEDDED SYSTEM

The embedded system are classified as :-

I. SMALL SCALE EMBEDDED SYSTEM

 These systems are designated with a single 8or16-bit microcontroller.
 They have little hardware and software complexities and involve board-level design.
 They may even be battery operated.
 When developing embedded software of this system, an editor, assembler and cross
assembler, specific to the microcontroller or processor used are the main programming
tools.
 Generally ‘C’ is used for developing this system soft are. ‘C’ program compilation is
done into the assembly and executable machine codes are then appropriately stored in
the system memory.
 The software has to fit within the memory available and keep in view the need to limit
continuously dissipation when system is running continuously.

Small Scale Embedded System Microcontroller Example :-

a. 68HC11 Motorola CISC

b. *PIC16F8X Microchip CISC
c. 8051 INTEL CISC

*PIC—Peripheral Interface Controller

II. MEDIUM SCALE EMBEDDED SYSTEM

 These system are usually designated with a single or few 16or32-bit microcontrollers or
reduced instruction set computers (RICS).
 These have both hardware and software complexities.
 In case of complex software design, following are as programming tools used :-
  RTOS
 Source code engineering tool
 Simulator
 Debugger
 Integrated development environment(IDE)
 Software tools also provide the solutions to the hardware complexities.
 The system may also be readily available ASSPs ( Application Specific System Processor )
and IPS for a various function .

For example –

 For the bus interfacing

 Encrypting
 Deciphering discrete cosine transformations and inverse transformation
 TCP/IP protocol
 Networking connecting function

Example of Medium Scale Embedded System:-

a. 80X86 INTEL CISC

b. 68HC11XX MOTORLA CISC All microcontroller
68HC12XX
c. 80196 INTEL CISC
III. SOPHISTICATED (LARGE SCALE) EMBEDDED SYSTEM
 Sophisticated embedded system has large hardware and software complexities.
 They require scalable processors or configurable processor and programmable logic
array (PLAs).
 They are used for cutting edge applications that need hardware and software co-design
and integration in the final system. However they are constrained by the processing
speeds available in their hardware units.
 Some software function such as encryption and deciphering algorithms, discrete cosine
transformation and inverse transformation are implemented in the hardware to obtain
additional speeds.
 Some of the functions of hardware resources in the system are also implemented by
the software.
 Development available at a reasonable cost ar mau not be available at all.

Examples:-

a. INTEL 80960A CISC INTEL

b. *ARM TEXAS CISC + RISC
c. POWER PC MPC 604

*ARM—Acorn Reduced Instruction Machine

APPLICATION OF EMBEDDED SYSTEM:-

1. TELECOMMUNICATION system employs embedded systems from TELEPHONE SWITCH for the
network to CELL PHONE at the end user. Computer networking uses dedicated ROUTER and
NETWORK BRIDGE to route data.
2. CONSUMER ELECTRONICS include MP3 player, mobile phones, video game consoles, GPS
receivers and printer.
3. HOUSEHOLD APPLICATION – such as microwaves oven, washing machine and dishwasher.
4. HOME AUTOMATION -- uses wireless networking that can be used to control lights, climate,
security, audio/visual surveillance etc. all of these uses embedded devices for sensing and
controlling.
5. TRANSPORTATION SYSTEM from flight to automobiles increasing use embedded system. New
airplanes contain advanced AVIONICS such as Inertial guidance system and GPS receivers that
also have considerable safety requirement.
6. VARIOUS ELECTRONIC MOTOR – brushless DC motors, induction motors and DC motors uses
electric/electronics motor controllers, automatic electric vehicles increasing use embedded
systems to minimize efficiency and reduce pollution.
7. Embedded system are used for automotive safety system which anti-lock braking system (ABS),
electronic stability control (ESC/ESP), traction control (TCS) and automatic four-wheel drive.
8. MEDICAL EQUIPMENT uses embedded system for vital sign monitoring systems, electronic
stethoscopes and medical imaging equipments.

Example – CT, MRI, for non invasive initial inspection.

Thus embedded system are extensively used in transportation, fire safety, and security, medical
equipment, life critical systems as these system can be isolated from hacking and thus are more reliable.

HISTORY

One of the very recognizable embedded system was the Apollo Guidance Computer developed in 1965
by Charles Stark Drapon at the MIT Instrumentation Laboratory.

An early mass produced embedded system was AUTONETICS D-17 Guigance computer for micsiles
released in 1961. When the MINUTEMAN II went into production in 1966, the D-17 was replaced with a
new computer that was the first high-volume use of integrated circuit in an embedded system.

As the cost of microprocessors and microcontroller fell ,it became feasible to replace expensive knob-
based analog component such as potentiometers and variable capacitors with up/down buttons read
out by microprocessors even in consumer products. By the early 1980s memory, input-output system
components had been integrated in the same chip as a processor forming a microcontroller’s embedded
system.
EMBEDDED SYSTEM VS GENERAL COMPUTING SYSTEM

CRITERIA EMBEDDED SYSTEM GENERAL COMPUTNG SYSTEM

(general purpose register)
Contents It is a combination of special purpose It is a combination of generic hardware and
hardware and embedded software a general purpose operating system (OS) for
(operatinf system OS) for executing executing a variety of application programs.
specific set of instruction.
Operating It may or may not contain operating It contains general purpose operating
systems system for functioning. system (GPOS)
Abretions Application are not aberable by user. Application are aberable by user.
Key factor Application specific requirement are key Performance of the system is key factor.
factor.
Power Less power consumption. More power consumption.
consumption
Response Critical for some application. Not critical.
time
Execution Deterministic for certain types of Need not to be deterministic.
embedded system.
Application Few and specific application . Board class of application.

CHARACTERISTICS AND QUALITY ATTRIBUTES OF EMBEDDED SYSTEM

*CHARACTERISTICS – A typical or noticable quantity of someone or something.

*ATTRIBUTES – A quality or feature of a thing/person espicially yhay is impertart part of his nature.

Following are the quality attributes of embedded system:-

 Reliability
 Maintainability
 Response time
 Testability
 Power consumption
 Ease of usage
 Real time deadline adherence soft or hard
 Extensibility should be able to cater new requirements

CHARACTERISTICS OF EMBEDDED SYSTEMS

Unlike general purpose computing system, embedded system possess certain specific characteristics are
these characteristics are unique to each embedded system . Some of the important characteristics an
embedded system are :-

1. Application and domain specific

 2. Reactive and real time
3. Operates in harsh environment
4. Distributed system
5. Small size and less weight
6. Power concerns
1. Application and domain specific – Most embedded system are specific to a domain.
For example – An hearing aid is an application that belongs to a domain of signal processing and
telecom with another control unit designated to serve another domain like consumer electronics / cell
phone. They are designed to perform a specific job.
2. Reactive and Real time – The embedded system are designed to react in real time. Embedded system
uses sensors to take input and has actuators to bring out the required functionality.
For example – An air conditioner adjusts it mechanical parts as soon as it gets a signal from its sensor
to increase or decrease the temperature when the user operates it using a remote control. Other
example of real time emebedded system are—
 Flight control system
 Anti clock Brake system
3. Operate in harsh environment – The embedded system have to be capable of sustaining environment
condition. They are design to operate in harsh environment like a dusty one or a high temperature
zone or an area subjected to vibration and shocks(very temperature of deserts are a very low
temperature of mountain)
4. Distributed system – The embedded system can work either as an independent system or many
embedded system can work together as a distributed system to achieve some gol ar task.
The word distributed means that an embedded system may be a part of a larger system.
Example – Automatic teller machine (ATM) contains-----
 A card reads embedded unit responsible for reading and validating the users ATM card.
 Embedded transaction unit for performing transaction.
 Embedded currency contain for vending currency to the authorized person and
 A printer unit for printing thr transaction details.
Each of these are independent embedded units bit ,they work together to perform the
overall ATM money dispensing process.
5. Small size and light in weight – In most of applications of embedded system their size and light in
weight characteristics is preferred.
Example – Currently available cell phones. The cell phone which have maximum features are popular,
but also then their size and weight are important characteristics.
An embedded system that is compact in size and has light weight are desired and are more populr
than a bulky and heavy system.
6. Power concerns – We know , the more the power consumption, the less is the battery life. The power
management is a critical constraint in the design of battery operated embedded system. Low power
components like low drop-out regulators and controllers/processors with power saving modes are
preferred.
 Also the production of high amount of heat demands cooling requirement like cooling fans which in
turn occupies additional space and make the system bulky. Thus, it is desirable that the power
dissipation and heat generation of any embedded system to be low.
QUALITY ATTRIBUTES OF EMBEDDED SYSTEM
The various quality attributes that need to be addressed in any embedded system development are
broadly classified into two categories :-
1. Operational quality attributes
2. Non Operational quality attributes
OPERATIONAL QUALITY ATTRIBUTES
The operational quality attributes represent the relevant quality attributes related to the
embedded system hen it is in operational mode or ’ online’ mode. The important attributes
under this category are as follow :-
a. RESPONSE TIME :- The response time is a measure of quickness of the system, most
of the embedded system demand fast response which should be real time. The
response time gives an idea about how fast the system is tracking the input variable.
Any response delay in the system will create potential damages to the safety of the
flight.
b. THROUGHPUT :- The throughput of an embedded system is generally measured in
terms of benchmark. A benchmark is a reference point by which something can be
measured. Benchmark can be a set of performance criteria that is expected to meet
or a standard product that can be used for comparing other products of the same
product line.
c. REDIABILITY :- Readiability is a measure of how much percentage you rely upon the
proper functioning of the system or what is the percentage susceptibility of the
system to failures.
Mean time between failures (MTBF) and mean time to repair (MTTR) are terms used
in defining system reliability.
d. MAINTAINABILITY :- Maintainability deals with support and maintenance to the end
user or client in case of a technical issues and product failures or on the biases of a
routine check up.
Maintainability can be classified into two groups:-
 Scheduled or period maintenance (Preventive maintainance)
 Maintenance to unexpected Failures (corrective maintainance )
Example – An inkjet printer uses ink car trigger which are consumable
components and as per the printer many features the end user should
replace the cartridge after each ‘n’ number of printouts to grt quality print.
This is an example of scheduled preventive maintenance.
If the proper feeding pants of the printer fails the printer fails to print and it
requires immediate repair to rectify their problem. This is an example of
maintenance to unexpected failures.
e. SAFETY ANALYSIS: - Safety analysis is a must in embedded system product to evaluate
the anticipated damages and determine the best course of action to a minimum.
 The breakdown of embedded system may occur due to hardware or firmware failure.
Safety deals with the possible damages that can happen to the operators; public and
environment due to the emission of radioactive or hazardous material from the
embedded system product.
NON OPERATIONAL QUALITY ATTRIBUTES
The quality attributes that need to be addressed for the product not on yhe basis of
operational attributes. Some of them are listed below:-
a. TESTABILITY :- Testability and hardware debugging used for figuring out them
issues created by hardware problems whereas firmware debugging is employed
to figure out the probable errors that appears as result of flows in the firmware.
Debug ability has two aspects in the embedded system development context,
namely—
 Hardware level debugging
 Firmware level debugging
b. EVOLVABILITY :- For an embedded system, the quality attributes Evolvability
refers to the ease with which the embedded product (including hardware and
firmware) can be modified to take the advantage of new hardware or firmware
technologies.
c. PORTABILITY :- A standard embedded system should always be flexible and
portable. An embedded system product can be called portable if it is capable of
functioning in various environment, target processors/controllers and embedded
operating system portability is a measure of system independence.
d. PRODUCT PROTOTYPING :- Poper market study and cost benefit analysis should
be carried out before designing the product prototype. The commercial
embedded product market is highly competitive and time to market the
embedded product is a critical factor in the success of a commercial embedded
product.
COMMON DESIGN METHOD AND PROCESSOR TECHNOLOGY
Processor design is the design engineering task of creating a processor, a key component of computer
hardware. The design process involve choosing on instruction set and a certain execution paradigm (eg.
RISC or CISI) and result in a microstructure, which might be described in eg. VHDL or verilog. The
description is their implemented employing some of the various semiconductor devices fabrication
processes which is bonded onto or inserted into a socket on a printed circuit board(PCB).
The processor design is divided into design of following component :-
1. Data paths (such as ALUs, buses, piplines)
2. Control unit : Logic which controls the dataflow
3. Memory component such as register files, caches
4. Clock circuitry : such as clock drivers, clock distribution network
5. Trans-receiver circuitry
6. Logic gate cell library which is used to implement the logic

PROCESSOR IMPLIMENTATION LOGIC

Device types used to implement the logic circuits of processors include

i. Transistor-Transistor-Logic (TTL) : No longer in use of CPUs

ii. CMOS mass produced Ics : very common in CPUs
iii. CMOS-ASICs : only for CPU (processor) having special application due to cust.
iv. Field Programmable Gate Arrays (FPGA) : common for microprocessor/ microcontroller design
MAJOR TASKS IN PROCESSOR DESIGN
The processor design project, generally has following major task :-
1. Programmer visible instruction set architecture which can be implemented by a variety of micro
architectures.
2. Architectural study and performance modeling in c, c++ or system c.
3. High level synthesis (HLS) or Register Transfer Level (RTL) implementation.
4. Circuit design of speed critical components (eg cache, registers, ALUs).
5. Logic Synthesis or Logic Gate level design.
6. Timing Analysis to confirm that all logic circuit will run at the specified operating frequency.
7. Physical Design including floor planning, place and route of the logic gates.
8. Checking that RTL, gate-level, transistor-level and physical level representation are equivalent.
PERFORMING ANALYSIS AND BENCHMARKING
Benchmarking is a way of testing processor speed. Example include SPECint and SPECfp developed by
standard Performance Evaluation Corporation and consumer mark developed by embedded
microprocessor benchmark constrain EEBC.
METRICS USED FOR BENCHMARKING
Some of the commonly used matrix include :-
1. INSTRUCTION PER SEC :- Most consumers pick a computer architecture to be able to run large
base of pre-existing and pre compiled software.
2. FLOPS :- The number of floating point operation per second is often important in selecting
processors for specific application.
3. PERFORMANCE PER WATT :- System designer building multiprocessor system, pick processors
based on their speed per watt of power, because the cost of powering th eCPU outweights the
cost of processor itself.
4. System designer building real time computing system want to guarantee worst case response.
This is easier to do when the processor has low interrupt latency.
5. The processor must support a full featured instruction set .
6. LOW POWER :- for system with limited power sources (eg. Batteries, solar power)
7. SMALL SIZED AND LESS WEIGHT :- for portable embedded system for space application.
8. ENVIRONMENTAL IMPACT :- minimizing environment impact of processor during manufacturing,
reducing hazardous material.

GENERAL PURPOSE PROCESSORS

Processor technology involves the architecture of the computation engine used to implement a systems
desired functionality.
In general purpose processor, the system designer only reads to program the processors memory to
carry-out the required functionality. Software portion. These type are created to produce number of a
variety of application.

Usally general purpose processors are used to put in a product the first time it goes to the market
beavause of the use of code, a designer usually strirer to minimize compiled code size, rather than
maximize performance .

Advantages:-

I. Easy to design and use (only programming the memory)

II. System design time is less
III. Design cost is low
IV. Reprogrammability is changing functionality or improving a system becomes easy since we
have just to change the program.

Disadvantages :-

I. Performance of the system is not very good.

II. The system size is bulky, because they are built to be used in a variety of application with
different specification.
III. They consume mor power.

Example :- microcontroller. Microprocessors

SINGLE PURPOSE PROCESSOR

A single purpose processor is designed to execute one single programs. An embedded designer creates a
single processor by designing a custom digital circuit. Such processor have a single applicationfor which
they have been designed.

These processors are designed to fit a specific requirement of an end product. In the design process they
will be optimized for both power and performance.

Advantages :-

I. Performance is very good

II. Small in size (exact to fit one solution)
III. They consume less power

Disadvantages :-

I. Difficult to design thus design time is more high design/cost

II. Reprogramming is difficult and sometimes not possible
III. Limited flexibility – not easy to make changes or accommodate more feature (function)

Example
Application specific integrated circuit(ASIC)

Application specific standard product (ASSP)

APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR (ASIP)

An application specific instruction set processor (ASIP) are designed for a particular class of application
with consumer characteristics . It is an immediate courpromise between a general purpose processor
and a single purpose processor. It gives more flexibility in design than a single purpose processor and
have still better performance , low power, small size as compare to a general purpose processor.
Althought it leads to a longer design time, higher cost and also needs it own compiler.

Example :- Digital signal processor (DSP)

A DSP is optimized to efficiently perform repetative and numerically intensive tasks such as matrix-
operation, convolution for real time filter design . DSPs normally run at very high clock rate and their
operating speed is measured in terms of how many millions of MAC operation they can perform per
second.

DSPs are optimized to do mathematical operations and not for supervisory application. Thus DSP based
system are integrated with the microcontrollers unit

Advantages :-

I. Optimized for computation on real time data flows as well as control oriented tasks
II. High operating speed as they work at high clock rate
III. Low power dissipation

Diasadvantages:-

I. Requires hard positioning between DSP function and contro; function

II. Requires special development tools
 Chapter-4

Von Neumann Architecture

The Von Neumann architecture was first proposed by a computer scientist John von Neumann.
In this architecture, one data path or bus exists for both instruction and data. As a result, the
CPU does one operation at a time. It either fetches an instruction from memory, or performs
read/write operation on data. So an instruction fetch and a data operation cannot occur
simultaneously, sharing a common bus.

Von-Neumann architecture supports simple hardware. It allows the use of a single, sequential
memory. Today's processing speeds vastly outpace memory access times, and we employ a very
fast but small amount of memory (cache) local to the processor.
Harvard Architecture
The Harvard architecture offers separate storage and signal buses for instructions and data. This
architecture has data storage entirely contained within the CPU, and there is no access to the
instruction storage as data. Computers have separate memory areas for program instructions and
data using internal data buses, allowing simultaneous access to both instructions and data.
Programs needed to be loaded by an operator; the processor could not boot itself. In a Harvard
architecture, there is no need to make the two memories share properties.
The following points distinguish the Von Neumann Architecture from the Harvard
Architecture:
Point of Harvard architecture Von Neumann Architecture
comparison
Arrangement In Harvard architecture, In Von-Neumann architecture,
the CPU is connected with there is no separate data and
both the data memory (RAM)and program memory.
program memory (ROM), separately. Instead, a single memory
connection is given to the
CPU.
Hardware It requires more hardware since it will In contrast to the Harvard
requirements be requiring separate data and address architecture, this requires less
bus for each memory. hardware since only a
common memory needs to be
reached
Space This requires more space. Von-Neumann Architecture
requirements requires less space.
Speed of Speed of execution is faster Speed of execution is slower
execution because the processor fetches data and since it cannot fetch the data
instructions simultaneously . and instructions at the same
time
Space usage It results in wastage of space since if Space is not wasted because
the space is left in the data memory the space of the data memory
then the instructions memory cannot can be utilized by the
use the space of the data memory and instructions memory and vice-
vice-versa. versa.
Controlling Controlling becomes complex since Controlling becomes simpler
data and instructions are to be fetched since either data or
simultaneously. instructions are to be fetched
at a time.
ISA (instruction set architecture):
The instruction set, also called ISA (instruction set architecture), is part of a computer that
pertains to programming, which is basically machine language. The instruction set provides
commands to the processor, to tell it what it needs to do. The instruction set consists of
addressing modes, instructions, native data types, registers, memory architecture, interrupt, and
exception handling, and external I/O.

An example of an instruction set is the x86 instruction set, which is common to find on
computers today. Different computer processors can use almost the same instruction set while
still having very different internal design. Both the Intel Pentium and AMD Athlon processors
use nearly the same x86 instruction set. An instruction set can be built into the hardware of the
processor, or it can be emulated in software, using an interpreter. The hardware design is more
efficient and faster for running programs than the emulated software version.

Examples of instruction set

 ADD - Add two numbers together.

 COMPARE - Compare numbers.

 IN - Input information from a device, e.g., keyboard.

 JUMP - Jump to designated RAM address.

 JUMP IF - Conditional statement that jumps to a

designated RAM address.

 LOAD - Load information from RAM to the CPU.

 OUT - Output information to device, e.g., monitor.

 STORE - Store information to RAM.

RISC and CISC Architecture :

CISC Architecture:
CISC Stands for "Complex Instruction Set Computing." This is a type of microprocessor
design. The CISC architecture contains a large set of computer instructions that range from
very simple to very complex and specialized. Though the design was intended to compute
complex instructions in the most efficient way, it was later found that many small, short
instructions could compute complex instructions more efficiently. This led to a design
called Reduced Instruction Set Computing (RISC), which is now the other major kind of
microprocessor architecture. Intel Pentium processors are mainly CISC-based, with some
RISC facilities built into them, whereas the PowerPC processors are completely RISC-based.

The CISC approach attempts to minimize the number of instructions per program, sacrificing the
number of cycles per instruction. Computers based on the CISC architecture are designed to
decrease the memory cost. Because, the large programs need more storage, thus increasing the
memory cost and large memory becomes more expensive. To solve these problems, the number
of instructions per program can be reduced by embedding the number of operations in a single
instruction, thereby making the instructions more complex.

CISC Architecture

 MUL loads two values from the memory into separate registers in CISC.
 CISC uses minimum possible instructions by implementing hardware and executes
operations.
 Instruction Set Architecture is a medium to permit communication between the
programmer and the hardware. Data execution part, copying of data, deleting or editing is
the user commands used in the microprocessor and with this microprocessor the
Instruction set architecture is operated.
 The main keywords used in the above Instruction Set Architecture are as below
CHARACTERISTIC OF CISC:-

1. Complex instruction, hence complex instruction decoding.

2. Instruction are larger than one word size.
3. Instruction may take more than single clock cycle to get executed.
4. Less number of general purpose register as operation get performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.

Example – Suppose we have to add two 8-bit number:

 CISC approach: There will be a single command or instruction for this like ADD which
will perform the task.

RISC Architecture:
RISC Stands for "Reduced Instruction Set Computing" and is pronounced "risk." RISC is a type
of processor architecture that uses fewer and simpler instructions than a complex instruction set
computing (CISC) processor. RISC processors perform complex instructions by combining
several simpler ones.

Several CPUs in the 1990s and early 2000s used RISC architecture. One of the most popular was
the IBM PowerPC processor, which Apple used in its PowerMac line of computers for nearly a
decade. In 2006, Apple switched to CISC-based Intel CPUs. Nearly all personal computers now
use CISC processors made by Intel or AMD.RISC (Reduced Instruction Set Computer) is used
in portable devices due to its power efficiency. For Example, Apple iPod and Nintendo DS.
RISC is a type of microprocessor architecture that uses highly-optimized set of instructions.
RISC does the opposite; reducing the cycles per instruction at the cost of the number of
instructions per program Pipelining is one of the unique feature of RISC. It is performed by
overlapping the execution of several instructions in a pipeline fashion. It has a high performance
advantage over CISC. RISC processors take simple instructions and are executed within a clock
cycle
 RISC Architecture

Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeling can be achieved.

Example – Suppose we have to add two 8-bit number:

 RISC approach: Here programmer will write first load command to load data in
registers then it will use suitable operator and then it will store result in desired location.

The Advantages of RISC architecture:-

 RISC(Reduced instruction set computing)architecture has a set of instructions, so high-

level language compilers can produce more efficient code
 It allows freedom of using the space on microprocessors because of its simplicity.
 Many RISC processors use the registers for passing arguments and holding the local
variables.
 RISC functions use only a few parameters, and the RISC processors cannot use the call
instructions, and therefore, use a fixed length instruction which is easy to pipeline.
 The speed of the operation can be maximized and the execution time can be minimized.
Very less number of instructional formats, a few numbers of instructions and a few
addressing modes are needed.

The Disadvantages of RISC architecture:-

 Mostly, the performance of the RISC processors depends on the programmer or compiler
as the knowledge of the compiler plays a vital role while changing the CISC code to a
RISC code
 While rearranging the CISC code to a RISC code, termed as a code expansion, will
increase the size. And, the quality of this code expansion will again depend on the
compiler, and also on the machine’s instruction set.
 The first level cache of the RISC processors is also a disadvantage of the RISC, in which
these processors have large memory caches on the chip itself. For feeding the
instructions, they require very fast memory systems.

Advantages of CISC architecture:-

 Microprogramming is easy assembly language to implement, and less expensive than

hard wiring a control unit.
  The ease of microcoding new instructions allowed designers to make CISC machines
upwardly compatible:
 As each instruction became more accomplished, fewer instructions could be used to
implement a given task

Disadvantages of CISC architecture:-

 The performance of the machine slows down due to the amount of clock time taken by
different instructions will be dissimilar
 Only 20% of the existing instructions is used in a typical programming event, even
though there are various specialized instructions in reality which are not even used
frequently.
 The conditional codes are set by the CISC instructions as a side effect of each instruction
which takes time for this setting – and, as the subsequent instruction changes the
condition code bits – so, the compiler has to examine the condition code bits before this
happens.

CISC vs RISC
 The following points differentiate a CISC from a RISC −

CISC RISC

Larger set of instructions. Easy to Smaller set of Instructions.

program Difficult to program.

Simpler design of compiler, Complex design of compiler.

considering larger set of
instructions.

Many addressing modes causing Few addressing modes, fix

complex instruction formats. instruction format.

Instruction length is variable. Instruction length varies.

Higher clock cycles per second. Low clock cycle per second.

Emphasis is on hardware. Emphasis is on software.

Control unit implements large Each instruction is to be executed

instruction set using micro- by hardware.
program unit.

Slower execution, as instructions Faster execution, as each

are to be read from memory and instruction is to be executed by
decoded by the decoder unit. hardware.

Pipelining is not possible. Pipelining of instructions is

possible, considering single clock
cycle.

ARM Processor:

The ARM architecture processor is an advanced reduced instruction set computing [RISC]
machine and it’s a 32bit reduced instruction set computer (RISC) microcontroller. This ARM is a
family of microcontroller developed by makers like ST Microelectronics, Motorola. The ARM
architecture comes with totally different versions like ARMv1, ARMv2, etc.

Architecture of ARM

The ARM Architecture consists of:

 Arithmetic Logic Unit

 Booth multiplier
  Barrel shifter
 Control unit
 Register file

Block diagram of ARM

Arithmetic Logic Unit (ALU):

The ALU has two 32-bits inputs. The primary comes from the register file, whereas the other
comes from the shifter. Status registers flags modified by the ALU outputs. The V-bit output
goes to the V flag as well as the Count goes to the C flag. Whereas the foremost significant bit
really represents theS flag, the ALU output operationis done by NO Redto get the Z flag. The
ALU has a 4-bit function bus that permits up to 16 opcodes to be implemented.

Booth Multiplier Factor:

The multiplier factor has 3 ,32-bit inputs and the inputs return from the register file. The
multiplier output is barely 32-Least Significant Bits of the merchandise. The entity
representation of the multiplier factor is shown in the above block diagram. The multiplication
starts whenever the beginning 04 input goes active. Fin of the output goes high when finishing.

Booth Algorithm

Booth algorithm is a noteworthy multiplication algorithmic rule for 2’s complement numbers.
This treats positive and negative numbers uniformly. Moreover, the runs of 0’s or 1’s within the
multiplier factor are skipped over without any addition or subtraction being performed, thereby
creating possible quicker multiplication. The figure shows the simulation results for the
multiplier test bench. It’s clear that the multiplication finishes only in16 clock cycle.
Barrel Shifter

The barrel shifter features a 32-bit input to be shifted. This input is coming back from the
register file or it might be immediate data. The shifter has different control inputs coming back
from the instruction register. The Shift field within the instruction controls the operation of the
barriershifter. This field indicates the kind of shift to be performed (logical left or right,
arithmetic right or rotate right). The quantity by which the register ought to be shifted is
contained in an immediate field within the instruction or it might be the lower 6 bits of a register
within the register file.

Digital Signal Processors (DSP):

Digital Signal Processor (DSP) is actually a special-purpose CPU used for digital signal
processing-based applications. Once a signal is converted into digital data, using multiple
different available algorithms (such as Fast Fourier Transform), its components can be isolated,
analyzed and rearranged more easily than in analogue form. It provides ultrafast instruction
sequences, such as shift and add, and multiply and add, which are commonly used in math
intensive signal processing. DSP is having versatile application in multiple different fields,
including biomedicine, sonar, radar, seismology, cell phones, fax machines, audio, digital TV,
sound cards, modems, hard disks, imaging and communications, speech and music processing. It
can also be used to create the concert hall and along with surround sound effects in stereo and
home theatre equipment.

Digital Signal Processors (DSPs) have following characteristics:

a) Real-time digital signal processing capabilities. DSPs typically have to process data in real
time, i.e., the correctness of the operation depends heavily on the time when the data processing
is completed.

b) High throughput: DSPs can sustain processing of high-speed streaming data, such as audio
and multimedia data processing.

c) Deterministic operation: The execution time of DSP programs can be foreseen accurately, thus
guaranteeing a repeatable, desired performance.

d) Re-programmability by software: Different system behavior might be obtained by re-coding

the algorithm executed by the DSP instead of by hardware modifications.

Example:

1.TMS320C54X from Texas instruments.

2.SHARC of analog device

3.5600XX OF Motorola

Chapter-5

WATCH DOG TIMER IN EMBEDDED SYSTEMS

A watch dog timer (WDT) is a Hardware timer that automatically generates a system RESET if the main
program neglects to regular services.

It is often used to automatically RESET an embedded device that hangs because of software or hardware
fault.

A watchdog timer in embedded systems is a piece of hardware that can be used to automatically detect
software anomalies and RESET the processor if any fault occurs.

For those embedded systems that cannot be constantly watched by a human, Watchdog timers are the
solution.

Most embedded systems need to be self reliant. It is not usually possible to wait for someone to reboot
them if software hangs. Some embedded designs such as space probes are simply not accessible to
human operators. If their software ever hangs, such systems are permanently disabled.

A watchdog timer is a piece of hardware that can be used to automatically detect software anomalies
and RESET the processor if any occur. In general a watchdog timer is based on a timer that counts down
from some initial value to zero.

The embedded system soft are selects the counter’s initial value and periodically restarts it. If the
counter ever reaches zero before the software restarts it, the software is presumed to be
malfunctioning and processor restart signal is asserted. The processor and the embedded software its
running will be restarted as if a human operator has RESET it by cycled power.

Watchdog Timer
PROCESSOR

RESET

CLOCK
FIG : A Typical Watchdog SETUP

The figure shows a typical arrangement. As shown, the watchdog Timer is a chip external to the
processor. However it could also be included within the same chip as the CPU. The output from the
watchdog timer is tied directly to the processor is RESET signal.

KICKING THE DOG:-

The process of restarting the atchdog timer counter is sometimes called ‘Kicking the Dog’.