IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO.

9, SEPTEMBER 2001 1037

AMGIE—A Synthesis Environment for CMOS

Analog Integrated Circuits
Geert Van der Plas, Student Member, IEEE, Geert Debyser, Member, IEEE, Francky Leyn, Associate Member, IEEE,
Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Senior Member, IEEE, Willy Sansen, Fellow, IEEE,
Petar Veselinovic, Member, IEEE, and Domine Leenaerts, Senior Member, IEEE

Abstract—A synthesis environment for analog integrated cir- ture is analog and interaction with nature or transportation of
cuits is presented that is able to drastically increase design and signals is, therefore, inevitable through analog interface circuits.
layout productivity for analog blocks. The system covers the com- All this explains the booming market share of mixed-signal
plete design flow from specification over topology selection and
optimal circuit sizing down to automatic layout generation and integrated circuits (ICs) seen on the market today with reported
performance characterization. It follows a hierarchical refinement average growth rates well above 20% and, therefore, well above
strategy for more complex cells and is process independent. The industry average. On the other hand, although the analog circuits
sizing is based on an improved equation-based optimization ap- occupy only a small part of the area in these mixed-signal
proach, where the circuit behavior is characterized by declarative ICs, they require an inversely large part of the design time and
models that are then converted in a sequential design plan. Sup-
porting tools have been developed to reduce the total effort to set cost and are often responsible for design errors and expensive
up a new circuit topology in the system’s database. The perfor- redesign iterations. Most steps in an analog design are basically
mance-driven layout generation tool guarantees layouts that sat- still handcrafted, ranging from extensive and repeated SPICE
isfy all performance constraints. Redesign support is included in simulation runs through manual place and route with the assis-
the design flow management to perform backtracking in case of de- tance of parameterized device generators. All this does not fit
sign problems. The experimental results illustrate the productive-
ness and efficiency of the environment for the synthesis and process well with the short design cycles of time-to-market critical ap-
tuning of frequently used analog cells. plications. Clearly, there is an industrial need to increase analog
design productivity and to lower the design risk. Therefore, it
Index Terms—Analog design, analog synthesis, design reuse,
layout, performance optimization, transistor sizing. is necessary to develop computer-aided design (CAD) tools
that assist designers with the design of analog and mixed-signal
integrated systems and eventually automate (large parts of) it.
I. INTRODUCTION Only in this way can the analog design community fully take
advantage of the capabilities offered by the technology. This is
I N RECENT years, there has been an increasing tendency in
the electronics market to integrate complete systems, which
before occupied one or more boards, onto a single-chip or mul-
even more true when looking at future SoCs in which most of
the differentiation or added value will be achieved at the system
tichip module. This is the evolution toward systems on a chip level and the design at the lowest levels in the design hierarchy
(SoC) or systems on a package [1]. A typical example is the will mostly be automated through synthesis or through reuse
highly competitive telecommunications market, where cost and (also for analog circuits).
performance are strong driving factors. Technologically, this Research in analog design automation, however, has been
integration has been made possible because of the increasing relatively slow, lagging far beyond its digital counterpart. An
miniaturization of very large scale integration technology. overview of the recent state of the art was presented in [2]. The
Most of the functions in such an integrated system are per- earliest analog synthesis tools such as IDAC [3], OASYS [4], or
formed with digital circuitry, which perform digital signal pro- BLADES [5] relied very much on design knowledge captured
cessing. Analog circuits, however, are always needed at the in- and hardcoded in expert-system-like structures such as design
terface between the electronic system and the outer world. Na- plans or rules. This required an expert designer to formalize
and encode the design plan with a large amount of heuristics
Manuscript received June 10, 1999; revised July 18, 2000. This work was sup- being thrown in to come to a unique design solution, possibly
ported in part by the Esprit Project ADMIRE, by the European Space Agency,
and by the Belgian Federal Office for Scientific, Technical, and Cultural Affairs using some restricted iterations and backtracking. Although this
under Program ASTP4 and Program GSTP2. This paper was recommended by approach delivers fast results once the plan is built, the time
Associate Editor R. Saleh. needed to derive and craft a plan is long and the flexibility in
G. Van der Plas, F. Leyn, J. Vandenbussche, G. G. E. Gielen, and W. Sansen
are with the Department of Electrical Engineering, the Katholieke Universiteit changing the plan to a new specification target set is low. This re-
Leuven, ESAT-MICAS, 3001 Leuven-Heverlee, Belgium. strained the industrial use of these early approaches. The second
G. Debyser is with DNS Belgium VZW, 3000 Leuven, Belgium. generation of experimental synthesis tools, therefore, relied on
K. Lampaert is with Conexant Systems, Inc., Newport Beach, CA 92660
USA. numerical optimization techniques, which allows more flexi-
P. Veselinovic is with ASM Lithography, 5503 LA Veldhoven, The Nether- bility and user control and reduces the setup time at the expense
lands. of larger runtimes. The optimization techniques used solve for
D. Leenaerts is with the Philips Research Laboratories, 5656 AA Eindhoven,
The Netherlands. the degrees of freedom in the design such that the performance
Publisher Item Identifier S 0278-0070(01)06891-9. specifications are satisfied and some user-defined design objec-
0278–0070/01$10.00 © 2001 IEEE
1038 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

tives (e.g., minimum power consumption) are minimized. Dif-

ferences between the different approaches basically mount to
the way how the circuit performance is evaluated at each itera-
tion of the optimization loop. A first subgroup of methods use
analytic models that describe the basic performance relations
in the circuit by a set of (explicit or implicit) simplified sym-
bolic equations. These methods are relatively fast, but their ac-
curacy is higher for rather linear (e.g., small-signal) character-
istics. Examples of such systems include for instance OPASYN
[6], OPTIMAN [7], STAIC [8], ISAID [9], and GPCAD [10] at
the level of basic analog blocks and SD-OPT [11] at the level of
- converters. A second subgroup of methods use numerical
simulation in the inner loop of the optimization. These methods
have the full SPICE accuracy, but are extremely slow (unless
the optimization space considered is very restricted) and still
require many design constraints (e.g., stability constraints) to
be incorporated into the optimization problem in order to guar-
antee a properly functioning circuit. Examples of such systems
include for instance FRIDGE [12], MAELSTROM [13], ANA-
CONDA [14], and ASTRX/OBLX [15]. The former three use
plain-vanilla SPICE; the latter uses asymptotic waveform eval-
uation to boost the linear (small-signal) simulations, but requires
the designer to provide analytic formulas for all other character-
istics. MAELSTROM and ANACONDA try to reduce central
processing unit (CPU) time by spreading the optimization over
a pool of parallel workstations.
Most of the above tools, however, cover only part of the
entire analog design flow and, therefore, only partially fulfill Fig. 1. Hierarchical design flow implemented in the AMGIE system.
the increasing need observed in industry today for an integrated
synthesis environment that increases analog design productivity and radio frequency, where the topologies tend to change with
from specification to layout. For instance, SD-OPT [11] and every new design.
FRIDGE [12] can be used in combination to cover the higher In Section II, an overview will be given of the functionalities
level and lower level design, respectively, of - converters, and design flow of the AMGIE analog synthesis environment.
but no layout solution is provided. ASTRX/OBLX [15], on Also the software architecture of the entire system will be de-
the other hand, has a companion analog layout synthesis scribed. In Section III, the different design steps will then be dis-
tool KOAN/ANAGRAM [16], but no solution is offered for cussed and the corresponding design tools and their underlying
selecting a good topology from a library. In this paper, a fully algorithms will be explained in detail. In Section IV, the produc-
integrated analog synthesis environment called AMGIE is tiveness and efficiency of the system will be demonstrated by
presented that implements a top-down hierarchical refinement means of representative experimental results. Conclusions will
design strategy for analog designs and covers the full design be formulated in Section V.
path from specifications over best topology selection and
optimum circuit sizing down to automated layout generation II. OVERVIEW OF THE AMGIE ANALOG SYNTHESIS
followed by automatic verification and datasheet extraction. ENVIRONMENT
The system is also complementary metal–oxide–semiconductor
(CMOS) process independent and has an open library interface In this section, first the functionality and supported design
to add new circuit topologies into the library relatively easily. flow of the AMGIE system are described followed by a descrip-
As every new circuit requires some amount of modeling, the tion of the software architecture.
approach is best suited for topologies that will be used in
several designs. For instance, in many companies, the same A. Design Flow of the Analog Synthesis Environment
basic limited set of op-amp structures is always used for most The design strategy implemented in the AMGIE analog
applications, e.g., in -converters. Hence, their design could synthesis environment is a performance-driven top-down
be entirely automated while guaranteeing a fully customized bottom-up strategy, which consists of the sequence of design
solution for every set of specifications and for every selected steps shown in Fig. 1. Each of these steps is implemented in a
CMOS process. In this way, technology porting of a basic separate software tool: either a new tool that has been developed
cell library can be automated. On the other hand, some of the or an existing commercial tool (especially for simulation and
individual tools of the AMGIE system can also be used as point back-end tasks) that has been integrated in the system. Their
tools to leverage the design of the so-called “once-in-a-lifetime” details will be described in Section III. The design flow is now
circuits as, for instance, is the case in domains like telecom described in more detail.
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1039

1) The user first has to select the desired type of circuit that the system is the layout, the annotated schematic, the
(s)he wants to synthesize (the so-called “functionblock,” datasheet, and design documentation.
e.g., an op amp—the definition of a functionblock is an
implicit behavior with a defined set of parameters, i.e., the Low-level circuits (such as op amps) are handled in a flat
specifications) and then has to enter the desired specifica- way as fully expanded transistor-level circuit schematics in the
tions for this circuit (including the performance specifica- above design flow (Step 5 is then trivial). For circuits of a higher
tions, the optimization targets, and a choice of the tech- complexity level (e.g., analog-to-digital converters), this is no
nology process). longer possible and the above design flow is executed in an hi-
erarchical way. According to the divide and conquer strategy,
a) : the performance value is con-
hierarchy is used when the circuit is too complex to be designed
strained in an interval, possibly the upper or
as one block and, therefore, is decomposed in easier to design
lower bound is . The interval can be open
subblocks (like a comparator in the converter). As hierarchical
or closed (inequality constraint) or be a single
splitup is complicated by the interactions between the different
value (equality constraint). The majority of the
subblocks (e.g., there is a large interaction at the level of differ-
performance specifications belong to this category.
ential pairs and current mirrors in an op-amp), our rule of prac-
For instance, the gain bandwidth should be higher
tice is to introduce hierarchy only when the resulting subblocks
than or equal to 10 MHz.
can be designed separately much easier than the overall block
b) @ : the performance value is con-
strained in an interval at a certain parameter value. as a whole; if not, it is preferred to design the block (e.g., an
For instance, the settling time should be smaller op-amp) without decomposition. In the hierarchical case, sizing
than 10 s for settling to within 0.1%. Both the set- and optimization (Step 3) then becomes specification transla-
tling time value and the settling accuracy are to be tion, which maps the specifications of the top-level cell to the in-
specified. dividual specifications of each of the subcells (such as the com-
parator in the analog-to-digital converter). The subcells are then
2) The most promising topology for the functionblock synthesized separately (Step 5), one by one, using the same de-
capable to meet these specifications is chosen from the sign flow and the resulting subblock layouts are returned up the
system’s cell library by the topology selection tool. hierarchy to assemble the layout of the top-level cell (bottom-up
3) Then this topology is optimally sized such that all speci- layout assembly in Step 6). If needed, redesign iterations are car-
fications are satisfied and the optimization targets are op- ried out across the design hierarchy.
timized by the sizing and optimization tool. The system supports two different design styles: 1) standard
4) The resulting design is then automatically extensively cells and 2) custom cells. Standard cells are cells that have been
simulated in the verification tool in order to verify that completely designed before within the AMGIE system or added
the design meets all performance specifications. If design to the AMGIE cell library by a silicon foundry, third party, or
failures or specification violations are noticed during this the user himself. In this way, the system, thus, automatically
verification step, then previous design steps have to be supports the reuse of previous, possibly silicon-proven designs.
changed and part of the design flow has to be iterated The above design flow has been encoded in a software
through backtracking (this is called redesign). module called the design controller. This module is the central
5) If the selected topology is defined in terms of nonprimi- “brain” of the AMGIE system and controls the execution of
tive subblocks (e.g., an op-amp within a filter), the system every synthesis run according to the embedded design flow.
then first synthesizes these subblocks at this point in the The next step in the design flow can only be executed if the
design flow by applying the complete design flow to every previous step has been terminated successfully. In this way, the
such subblock. When all nonprimitive subblocks are syn- system can also guarantee full consistency in the data during
thesized, the design flow of the higher level block con- the design, since no step can be executed before all required
tinues. Note that hierarchy is used only when a decom- data have been correctly created before. Note, however, that
position in more or less noninteracting subblocks is pos- the designer at any time can redo a previous step or, at his
sible. For example, in our approach, an op-amp is sized own responsibility, change the design after any step before
as one block and is not further decomposed into sub- proceeding. Part of the design flow is also the handling of
blocks like differential pairs, current mirrors, etc., be- redesign in the case of design failures. In the present AMGIE
cause it is impossible to easily distribute specifications version, the design controller does not yet automatically impose
such as power-supply rejection ratio or settling time over the corrective action to be taken in case of redesign. As this
the different subblocks. largely depends on the actual design data, it would require
6) An optimal layout is then generated or assembled by the sophisticated design expertise to be built in the design con-
layout generation tool. troller. Instead, the system includes a redesign wizard, which
7) The circuit is then extracted from the layout (including is automatically invoked when a redesign action is needed
all layout parasitics) and again extensively simulated in and proposes to the designer some possible context-specific
the verification tool and a datasheet is generated. In case alternative actions. The designer is then ultimately responsible
of design errors or specification violations, the same re- for deciding on the actual backtracking action that has to be
design procedure as outlined in Step 4 is followed. If taken in order to correct the problem. It must be noted though
not, the design is successfully completed. The output of that redesign iterations seldom occur.
1040 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 2. Software architecture of the AMGIE system.

B. Software Architecture of the AMGIE System The AMGIE system needs two libraries for its operation.
1) Cell Library: This library contains all information about
The overall software architecture of the AMGIE system is the analog cells needed for topology selection, sizing
shown in Fig. 2 and has been developed in a very modular way. and optimization, verification, and layout generation.
The system consists of a number of separate subtools, which The AMGIE system can only design circuits for which
are implemented as UNIX processes. The user interacts with the corresponding data are included in the cell library. In
the design controller by means of the graphical user interface order to allow the designer to trade off short design time
(GUI). The individual subtools (such as the topology selection for flexibility and optimized performance depending on
tool, the sizing and optimization tool, the verification tool with his particular application, the cell library contains both
links to different simulators, and the layout generation tool) are standard and custom cells.
connected to the design controller and pass design data between 2) Technology Library: This library contains all technology
them in this way. AMGIE stores data in a runtime database process specific information that is needed by the dif-
for the cell that is under design. Two libraries, the technology ferent tools in the system.
library and the cell library, store the design knowledge that
There is also a library interface (bottom of Fig. 2) where the
is used by the design tools. The complete system has been
designer or library developer can include new cells and pro-
integrated in a commercial electronic design automation (EDA)
cesses into the above libraries in a relatively easy way, so that
framework. The actual design database is implemented in this
the capabilities of the AMGIE system can grow beyond the ini-
framework’s database. The integration within a commercial
tial capabilities delivered by the tool developers.
framework also offered the advantage that existing commercial
tools could be used for simulation, extraction, layout viewing,
III. DETAILED DESCRIPTION OF THE ANALOG DESIGN STEPS
schematic capture, and framework services. All data exchange
occurs through a procedural interface called data representation In this section, the core steps in the analog design flow and
interface. In this way, the implementation details of the libraries the technical and algorithmic details of the corresponding tools
and runtime database are hidden from the subtools and this of the AMGIE system will be described in detail.
modular design makes extension or modification of the libraries
possible without changing the subtools. This should also make A. Topology Selection
it possible to move to another EDA framework with a relatively The topology selection tool selects from all topologies in the
small effort or to extend AMGIE relatively easily with new AMGIE cell library those that are able to satisfy the specifi-
software pieces. cations of the functionblock as determined in the specification
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1041

Fig. 3. Filter sequence implemented in the topology selection program.

sheet and ranks them in order of preference. The topology selec- between different performances are taken into account and,
tion tool actually works by eliminating inappropriate topologies therefore, some topologies may pass the boundary-checking
from all possible candidates stored in the library and by ranking filter, but cannot meet the specifications in the end. Eliminating
the remaining ones (see Fig. 3). Elimination of a circuit topology those topologies is exactly the task of the second filter. Some
is possible because the topology does not have the correct func- heuristics based on the relative position of the specification
tionality, does not fit to the selected process, or is incapable values within the feasible performance intervals or on the
of meeting the required specifications. The latter elimination is maximum size of the intervals’ intersection can be applied to
carried out by applying a sequence of three consecutive filters on perform already an initial ranking of the surviving topologies.
the list of candidate topologies [17]: first a boundary-checking In our case, the ranking is based on the ranking value ,
filter is applied, then an interval-analysis-based filter, and finally which, for a topology , is calculated according to the following:
a rule-based ranking filter. The resulting list is presented in order
of preference to the user through a GUI. The user can accept the
proposed topology or force the AMGIE system to choose any
other topology from the list. The three filters are now discussed
in detail. (2)
1) Boundary-Checking Filter: The first two filters use
quantitative information about the feasible performance space Example: Fig. 4(a) shows a comparison of four topologies
of a topology. This means that it is calculated what the achiev- ( to ) based on the feasible interval for one performance
able performances of each topology in the selected technology parameter with a specification range . The selection process
process are, given the acceptable ranges in biasing values and rejects , whose feasible interval does not overlap with ,
device sizes, and that it is checked whether the specified per- and ranks the remaining topologies as , depending
formances are included in this performance space or not. Since on the size of the intersection region. Fig. 4(b) depicts another
the calculation of the performance space is a time-consuming comparison of four topologies, this time based on feasible
process, this step is split in two consecutive filters. The first ranges for two performance parameters and . and
filter only calculates the multidimensional boundary box of are rejected and the ranking of the remaining topologies
the feasible performance space and checks whether this box is .
overlaps with the space determined by the input specifications. 2) Interval-Analysis Filter: The second filter (see Fig. 3)
This is called boundary checking (first filter in Fig. 3). If we takes the interdependencies between the different perfor-
denote the performance specification for performance as mances into account in order to calculate the complete feasible
and its feasible range for topology as performance space more accurately and to eliminate more
, then topology is an acceptable topology inappropriate topologies that have passed the first filter. This
if means solving all (in)equalities simultaneously for the per-
formance variables bounded by the required specifications. In
(1) order to do so, techniques from interval analysis are used in
combination with Chernykov’s algorithm that can solve all
The feasible performance interval values are calculated from systems of nonlinear equations, including inequalities, using
the declarative model that characterizes every circuit in the a piecewise-linear approximation for all nonlinear functions
library (see next section). Since the boundary-checking filter [17]. This system of equations is derived from the declarative
essentially considers each performance parameter independently model that is stored with every topology in the library (see the
of all the others, boundary checking is simple and fast and next section). Topology selection now consists of checking if
can already eliminate most of the unfit topologies from the the calculated solution space constrained by the specifications
library. The disadvantage, however, is that no interdependencies is empty or not. If not, the topology is accepted; otherwise, it is
1042 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

(a)
(a)

(b) (b)

Fig. 4. Boundary checking illustrated for (a) one and (b) two performance Fig. 5. (a) Feasibility check with the relations between two parameters and (b)
characteristics, respectively. the result of the combination of both filters.

rejected. The drawback of the technique is its exponential com- conceptually looks as follows:
putational complexity behavior with the size of the problem.
Therefore, only the most important specifications are taken into speed requirement (3)
account in this filter, making the CPU time still acceptable in noise requirement
practice. Note also that this filter is only applied to topologies
surviving the preceding boundary-checking filter. (4)
Example: The improvement that this filter brings over power requirement (5)
boundary checking is depicted in the examples of Fig. 5(a) and
(b). Fig. 5 differs from Fig. 4(b) in that the interdependency design equations (6)
(functions and ) between the performance parameters
and has been added. For the topology and for two The total number of model variables in the used model was
performance parameters and , Fig. 5(b) shows (1) the larger than 25. Eight different CSA-PSA topologies were con-
user-specified specification intervals, (2) the initial boundary sidered: either PMOS or NMOS input transistors for the CSA,
intervals as stored in the cell library, together with (3) the re- each in combination with four different orders for the PSA. The
maining solution space for those parameters after a calculation resulting order of the topologies depends on the specifications,
took place, taking into account the relationship between as shown in Fig. 7. The figure shows in the vertical axis the rank
and . Point d, for example, belongs to the solution space of of the eight topologies as a function of the requirement.
the topology for the given specifications, while point c is 3) Rule-Based Ranking Filter: The last filter that—if de-
outside of it, in contrast with simple boundary checking that sired—can be applied to (re)rank the remaining list of candi-
would accept both c and d. date topologies is a heuristic rule-based filter approach, where
Practical Example: Let us now consider the practical an inference engine executes a number of rules stored in a data-
example of a particle/radiation detector front end consisting base, to decide on the final ranking of the remaining topologies.
of a charge-sensitive amplifier (CSA) and an th-order The rules can encode both general heuristics as designer-spe-
pulse-shaping amplifier (PSA) as shown in Fig. 6. Note that the cific preferences. They are implemented in if-then form.
op amps are depicted symbolically here, but are implemented An example of such a rule based on cell attributes is
as full transistor schematics in reality. If we denote by the
specifications, the topology’s design parameters, and the tech- if
nology parameters, then the model used for interval analysis then before (7)
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1043

Fig. 6. Block diagram of the PDFE (both the CSA op-amp and the PSA integrators represent full transistor circuits).

Fig. 7. Results of topology selection. Order of the eight different topologies as a function of the power requirement.

B. Sizing and Optimization flicting performance tradeoffs. The approach taken for the cir-
cuit sizing in the AMGIE system is improved equation-based
After topology selection, an unsized schematic is available. circuit optimization. The use of optimization provides flexibility
The next step in the design flow is sizing and optimization and easy setup time; the use of equations provides speed of ex-
where, for the lowest-level cells, the optimal device sizes ecution.
and biasing will be determined for the selected topology to It alleviates many of the drawbacks of the traditional equa-
meet the performance specifications in the target technology tion-based approaches by using techniques of symbolic analysis
process while minimizing some cost function (e.g., power for declarative model derivation and of constraint satisfaction
consumption). At higher levels in the design hierarchy, the tool for design-plan generation on the one hand and encapsulated
searches for the optimum subblock parameters. In this case, device models to obtain high accuracy on the other hand. Also,
equations describe the performance of the higher level blocks an operating-point-driven formulation of the design problem is
in terms of the parameters of the lower level subblocks. Power used to speed up the evaluations. This will now be explained in
and area estimators of these subblocks are used to assess the more detail in the next sections.
implementation cost. 1) Sizing-Model Generation: The general flow for gener-
The most difficult problem in circuit sizing is to solve for the ating a sizing model is shown in Fig. 8 [18]. The circuit be-
degrees of freedom in the design while managing the many con- havior is first characterized by a declarative model that contains
1044 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 8. Sizing-model generation procedure and usage.

all the expressions [direct current (dc), alternating current (ac), Example: The approach is now illustrated for a simplified
transient, etc.] that fully describe the relationships between the example to demonstrate the concepts. Fig. 9 shows part (the dc
circuit behavior and the circuit parameters. These equations are part) of the declarative model that corresponds to a common-
declarative, i.e., they only specify relationships that must hold source single-transistor amplifier with resistive load, as shown
simultaneously between different variables, but they do not de- in Fig. 10. The model is represented as a bipartite graph con-
scribe a direction nor sequence of solution (they are not assign- taining two different types of vertices: ovals for the variables,
ments). DC equations are derived automatically from the circuit rectangles for the constraining equations. Note that the graph is
topology; ac equations are derived by means of symbolic anal- undirected. The declarative equations are shown in the equation
ysis techniques like with the ISAAC [19] or SYMBA [20] tools; at the bottom of the next page.
transient and other equations to date still have to be provided by In total, there are 14 variables constrained by ten indepen-
the designer. In this way, most of a declarative model can be dent equations. Hence, there are four degrees of freedom in this
generated automatically. The resulting model however is still simplified example. (In reality, there are many more equations
declarative and, therefore, not yet suited for computer execu- capturing also the ac and transient behavior of the circuit.) This
tion. The equation manipulation tool DONALD [21] is, there- means that four independent variables can be selected as input
fore, used to automatically determine the degrees of freedom variables. Many combinations are possible. If we choose, for
in the design, then to choose a set of independent input vari- instance, the variables as
ables (equal to the number of degrees of freedom), and then to input set, then the originally undirected bipartite graph can be
turn the undirected declarative model into a directed sequen- directed using constraint propagation techniques, as shown in
tial computation plan, which indicates how (by means of which Fig. 11, indicating the direction and order in which the equa-
equations, in which direction, and in which sequence) all the de- tions have to be solved in order to calculate the values of the
pendent variables have to be calculated from the values of the remaining ten dependent variables (single line ovals) out of the
independent ones. DONALD uses techniques of constraint sat- values of the independent variables (double line ovals). The
isfaction to determine the ordering of the computation plan and latter information can then be written in C code as a procedural
has a builtin algorithm to find a computation plan free of equa- design plan and compiled for optimal evaluation speed.
tion clusters if possible. The computation or design plan is then 2) Operating-Point-Driven Formulation: The choice of the
written out in C code, compiled, and stored in the AMGIE cell li- independent input variables in the computational plan, which, of
brary, ready to be used for circuit sizing and optimization by the course, are then also the optimization variables in the circuit op-
OPTIMAN tool during an actual AMGIE synthesis run. All this timization, is a very important factor in the performance of the
model generation is done offline and thanks to the supporting sizing tool. As shown in [23], the choice of variables directly
tools drastically reduces the setup time needed to include a new controlling the operating point of all MOS devices is to be pre-
schematic in the AMGIE system. With this approach setup times ferred over all other input sets. In the presented approach the
of less than 8 h have been achieved for moderate-complexity cir- voltages at all nodes and currents in all branches are, therefore,
cuits [22]. Considering that the whole design flow can be exe- specified as input variables (of course taking into account the
cuted in less than 20 min, the proposed environment also allows physical dependencies resulting from the Kirchoff laws to ob-
quick sizing plan evaluation and debugging, which is not true tain independent variables only). As a result of this, the time
for any other previous approach, since either the setup time is consuming dc operating-point calculations can be avoided as
much higher or the optimization time is much larger. all devices in the circuit can be solved independently and oper-
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1045

Fig. 9. Undirected bipartite graph.

calculating the value of for which

(18)

where is the drain current, are the operating-

point voltages applied to the transistor, and are the width
and length of the transistor, is the device model’s parameter
set, and is the temperature of the device.
Some simple device models, such SPICE MOS Level 1, allow
an explicit solution of the following:

Fig. 10. Example circuit to illustrate design plan generation. (19)

ating-point convergence problems often encountered in numer- For deep submicrometer technologies, more advanced device
ical simulation are avoided. Solving a device in our case requires models must be used, such as BSIM3v3, Philips MOS model 9,

(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
1046 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 11. Directed bipartite graph.

or the EKV model [24]. In this case, the device equation must be For example, in the case of a fingered transistor, the
iterated according to (18), e.g., using a bisection method, which source and drain areas are shared, resulting in smaller
converges always since the function typically is monotonic. overall source and drain area and junction capacitance.
These device models are, therefore, called encapsulated func- The GCM parameter determines which MOS variant
tions in the sizing tool and are not hardcoded in the design plans. and, therefore, which drain/source area function is used.
3) Device Model and Technology Parameters: The whole For example, the total area occupied by a simple MOS
sizing approach is technology-process independent through the transistor is given by
use of a technology metamodel, i.e., all technology parameters
are represented as variables in the equations used in the sizing
plan and their actual values during sizing are read in from the
technology file in the technology library corresponding to the (20)
selected technology process specified by the user at the start-up
of a synthesis session. where the core MOS area and the routing space are esti-
Four categories of parameters have been identified. mated as
1) SPICE Device Model Parameters: These are the well
known parameters used for simulation of circuits in any
SPICE-like simulator. They are used to determine the op- (21)
erating current and voltages and small-signal parameters
of each device. (22)
2) Mismatch Model Parameters: These model the statis-
tical intradie differences between nominally identical Also other device geometry parameters like
devices, which heavily influence characteristics such are derived in this way. These are
as offset voltage or power-supply rejection ratio. These essential to estimate parasitics of the devices like the
mismatches are modeled using the model of [25]. bulk capacitances, extrinsic drain/source resistances, etc.
3) Geometric Model Parameters: These define the layout 4) Technology Info Model Parameters: These define extra
implementation of the device. Since, in general, there are technology-specific information used to characterize
multiple ways of laying out a given sized device (e.g., the the devices. For example, the width and length of MOS
normal and the fingered variants of a MOS transistor), the transistors are constrained between a minimal and pos-
geometry calculation method (GCM) parameter is used sibly maximal value and they need to be snapped to grid.
to indicate the correct layout variant during sizing. This These technology constants are implemented through
GCM parameter triggers the proper set of equations to the process-specific parameters LMIN, WMIN, LGRID,
calculate or estimate the geometric dimensions of every WGRID, LMAX, and WMAX. By specifying the length
device from its device sizes in the selected technology. and width of the MOS transistors as a ratio to their
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1047

minimal value according to The optimization variables are the independent input vari-
ables of the stored design plan of the selected schematic. For
optimization algorithms that cannot handle the constraints di-
rectly, such as VFSR, penalty functions are added to the opti-
(23) mization target. The cost function used during optimization is
as follows:
and by using the and design-model variables (26)
instead of the process-dependent and , an important
technology dependence can be removed from the design where the penalty terms are added to handle the equality and
plans that makes them more generic. inequality constraints. Different choices of penalty functions are
4) Hierarchical Circuits—Power and Area Estima- possible, such as
tors: When sizing hierarchical blocks, the performance
specifications of the subblocks has to be determined. To associate
a cost with a specification choice, estimators are used. They link
the subblock’s performance with its feasibility, power, and area
(27)

(24)
(28)
These estimators can be implemented with: 1) manually de-
rived equations (for example, an analog sensor interface [26]);
For optimization algorithms that can handle constraints directly
2) by fitting to (automatically generated) design points [27],
such as SQP, of course no penalty terms are added to the cost
[28]; or 3) by empirically derived formulas [29]. Using opti-
function.
mization, the toplevel block parameters are then translated to
Originally, only the nominal performance could be op-
subblock specifications. With high-quality estimators, an op-
timized. Recently, however, the approach was extended to
timal tradeoff in terms of power and area of the overall system
include also the impact of process parameter and operating
is achieved.
parameter variations on the circuit performance, allowing to
5) Circuit-Optimization Formulation: Once the design plan
simultaneously optimize the circuit performance and the design
is available in the library, the OPTIMAN program [9] can then
yield and robustness [34].
perform the actual circuit sizing and optimization as part of an
The developed sizing approach results in a very fast sizing
AMGIE synthesis run, as shown in Fig. 8. The compiled sizing
process. CPU times between a few minutes (for low-complexity
plan of the selected circuit schematic is retrieved from the cell li-
circuits of about ten MOS transistors) to one hour (for complex
brary and linked to an optimization algorithm to tune the circuit
circuits of approximately 100 MOS transistors) are reached on a
toward the user defined specifications while optimizing some
standard SUN Ultra 1–170 workstation while, at the same time,
user defined design target, e.g., minimum power consumption.
achieving high accuracy.
The OPTIMAN tool is very modular in that the same optimiza-
Practical Example: Letusnowconsiderthepracticalexample
tion problem can be solved with several different optimization
of a symmetrical operational transconductance amplifier (OTA)
algorithms. In the AMGIE system, the user can select the opti-
with class AB output buffer, as shown in Fig. 12. The specification
mization algorithm as one of the options to be chosen in the spec-
set that has been limited to the following specs: low-frequency
ification sheet window. At this moment, both global-optimization
gain ( ), gain-bandwidth (GBW) product, slew rate (SR),
algorithms, such as very fast simulated reannealing (VFSR) [30],
phase margin (PM), random offset voltage , and capacitive
as well as local-optimization algorithms, such as Hooke-Jeeves
load . Using Donald and ISAAC and adhering to the
[31], minimax [32], or sequential quadratic programming (SQP)
principles proposed previously in this section, a fast compiled
[33], can bechosen. The range ofall optimizationvariables as well
design plan has been created. It uses the black-box device models,
as a default initial solution is provided for every schematic in the
dc operating-point formulation, mismatch model, and analytical
cell library, but can also be modified by the designer. After the
equations, linking the specifications to the device’s parameters.
sizing optimization in the AMGIE system, the resulting optimal
In addition to these equations, design constraints have been
device sizes are automatically back-annotated onto the schematic
added that generate a penalty when transistors leave preferred
of the circuit under design.
operating-point regions (overdrive voltage limits, saturation
The used formulation of the analog circuit sizing as an opti-
limits, etc.). Thus, the generated design plan can now be used
mization problem is as follows:
to perform optimizations. The specification values used for
find optimizations are summarized in Table I. Since, at first, no
good design point is known (to start of the optimization), the
global-optimization algorithm VFSR is employed. In Fig. 13(a),
s.t. for both the temperature and best cost achieved during a typical
for (25) optimization run is shown. The corresponding trace of the
1048 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

C. Layout Generation
After sizing the circuit, performance is verified (see Sec-
tion III-D). If this verification is passed successfully, a fully
customized layout of the circuit is automatically generated
by the LAYLA tool [35]. This tool implements a direct
performance-driven place and route methodology [36]. The
performance degradation due to layout-induced effects is
quantified for every layout solution and the placement and
routing routines are driven in such a way that this performance
degradation for every performance does not exceed
the user-defined performance margins and in the
final layout solution

Fig. 12. Schematic of the symmetrical OTA with class AB output buffer. (29)

TABLE I The allowed performance margins for layout can be derived

SPECIFICATIONS OF THE SYMMETRICAL OTA WITH CLASS AB OUTPUT BUFFER from the specifications as follows:

(30)
The performance degradation is calculated using a first-order
linear approximation using the sensitivities of the performances
to the different layout parasitics

(31)

most important optimization (independent) variables is shown resulting in

in Fig. 13(b). It can be clearly seen that after a short period of
random exploration, the annealing algorithm finds a design point (32)
that conforms to the constraints (specifications, extra design
constraints) and that the power and area target are optimized The values of the layout parasitics are extracted (calculated
subsequently. However, in the latter optimization stage, large and/or estimated) for every intermediate layout solution. The
changes in the optimization variables are still possible. As can sensitivities are obtained from numerical simulations that
be seen in Fig. 13(b), at about iteration 5000, the three most are performed only once at the beginning of the layout genera-
important design variables change simultaneously. The input tion process.
stage current drops in value, the compensation capacitance In addition to performance constraints, additional geomet-
is decreased correspondingly, and the class AB ratio (i.e., rical requirements can be enforced by the designer, such as sym-
driver to output stage) is increased. In fact, the optimization metry requirements both for devices as for nets. Also, the ori-
algorithm has found that decreasing the input stage current entation of devices can be fixed. Busses and pins can be con-
and compensation and keeping the output stage constant is strained to be placed on a specific side of the circuit layout, etc.
advantageous to reduce the overall power consumption, while The layout generation is split up in two parts: first placement
still fulfilling all specifications. Since we now have a good followed by routing. The placement algorithm [37] uses simu-
design point, we can calculate the power-area tradeoff curve lated annealing to place the devices. Symmetry constraints are
using the local optimization algorithm SQP. While maintaining enforced in the move set. Other constraints are enforced through
the specifications set forth in Table I, the power and area weights the performance-driven mechanism: any violation of the perfor-
are modified to look for alternative designs. In Fig. 14, the mance margins for a layout solution according to (32) is penal-
resulting power-area points have been plotted for the original ized via an extra penalty term that is added to the cost function.
specification set and two modified sets (low-frequency gain A first effect included in this way is the performance degrada-
and random offset voltage). As can be seen from the figure, tion caused by (estimated) interconnect parasitics (capacitances
the power-area tradeoff curve is flat and curls up. This is associated with every wire and resistances associated with every
explained by the fact that a power minimum does allow large wire segment in the layout) according to
transistors to be created, while an area minimum shrinks all
transistors to their minimal sizes and, thus, allows only one
power point. Furthermore, relaxing the low-frequency gain
and random offset voltage specifications influences the lowest
possible area, but not the power (this is because power is largely
GBW, determined). In addition, relaxing specifications (33)
grows the tradeoff curve considerably.
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1049

(a)

(b)

Fig. 13. Trace of VFSR optimization. (a) Cost and temperature. (b) Important optimization variables.

The inclusion of junction capacitances in the above formula fa- entation and variant of the devices), but as it is not possible to
vors on-the-fly device merges at the diffusion level. put all matching devices exactly next to each other while also
A second effect included is the matching of devices. Matching satisfying all other constraints, their distance is determined by
devices are handled simultaneously in the move set (same ori- the performance-driven mechanism according to the impact of
1050 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 14. Power area trade of symmetrical OTA with class AB buffer stage.

their mismatch on the performance

(34)

Other effects have been included following the same mecha- Fig. 15. Schematic of the Miller compensated OTA with PMOS input stage.
nism, e.g., thermal effects [38].
The resulting placement is then interconnected by a perfor-
mance-driven router [39]. The performance degradation caused GBW. In Table II, the sensitivities of these specifications with
by the actual routing parasitics is quantified and constrained in respect to the internal node capacitances are summarized, as
the same way as during placement by including any excess per- are the estimated degradations of the placement and routing
formance degradation in the cost function of the line expansion phase. The final performance degradation remains within the
algorithm. In addition, as a post operation, the router can also requested values, as shown in Table III.
trade off any remaining slacks on the performance degradation The resulting layout is then checked for layout rule violations
for an improved yield with respect to local catastrophic defects (design rule check) and compared with the schematic (layout
(pinholes and spot defects). By ripping up and rerouting nets ac- versus schematic). If these checks do not return any errors, the
cording to the modified cost function, the layout can be made actual parasitic elements of the circuit are extracted from the
less sensitive to these defects, always without exceeding the mask layout and back-annotated on the schematic to allow a
original performance degradation margins. In this way, a fully detailed verification of the circuit performance.
customized circuit layout is obtained that satisfies all specifica-
tions and has a high robustness. D. Verification
Practical Example: In Fig. 15, the schematic of a Miller Detailed verification of the circuit performance is performed
compensated OTA is shown. With the discussed performance twice in the design flow: first in the top-down path to verify the
driven place and route approach the layout of Fig. 16 has circuit sizing without the layout-induced degrading effects and
been generated. In this (limited) example, two performance second in the bottom-up path after layout extraction to verify
specifications have been taken into account: the PM and the the circuit with inclusion of the actual layout-induced degrading
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1051

Fig. 16. Performance-driven layout of the Miller compensated OTA.

TABLE II
SENSITIVITY AND PERFORMANCE DEGRADATION OF THE MILLER COMPENSATED OTA

TABLE III
PERFORMANCE OF THE MILLER COMPENSATED OTA

effects. Verification implies a number of checks to be performed for instance, the correct biasing, which varies from schematic
on the circuit as well as the execution of a simulation script to to schematic, the clocking in case of clocked circuits, etc. The
automatically simulate and extract all actual performance values verification process is fully automated and requires no interven-
obtained by the design. For this, a link to existing numerical tion from the user.
simulators is provided; the actual simulator that is used can be The nominal performance of the circuit can be verified with
chosen by the user. The resulting performance values are then only a limited number of simulation jobs. A number of circuit
compared to the specifications and the datasheet of the design is performances are however influenced by device mismatches,
generated, indicating whether all specifications have been met which is a statistical phenomenon. Commercial simulators pro-
or not. vide Monte Carlo type of statistical simulation capabilities, but
A generic verification script has been defined for every type no commercial simulator provides an integrated statistical mis-
of circuit, e.g., an op-amp. As shown in Fig. 17, during veri- match model. Therefore, a circuit preprocessor has been de-
fication, every circuit is considered as a black box that has a veloped, called MMPRE [40], that replaces all MOS transis-
specific functionality. Except for the external input and output tors in the netlist by an equivalent statistical mismatch model
pins, no signals are monitored inside the circuit. The verifica- according to the Pelgrom mismatch model [25], as shown in
tion script verifies the requested performance behavior of the Fig. 18. The mismatch-dependent performance specifications,
functionblock, independent of the actual circuit implementation as for instance the random part of the input offset voltage of an
of that block. Details about the actual implementation and its op-amp, are then verified by invoking statistical simulations on
special properties are, therefore, encapsulated in a verification this modified netlist in the corresponding simulation step in the
harness that is predefined for every schematic. This includes, verification script.
1052 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 19. Blackbox op-amp in its test harness for slew rate analysis.

(a)

Fig. 20. Output signal and measurements.

specification. The transient simulation mode is selected.

The simulated time is set to one and a half period of the
square wave.
3) The transient simulation job is run in batch mode.
4) The slew rate specification is extracted from the signal on
the output node. The positive slew rate is defined as the
slope of the output signal between 20% and 80% of its full
swing. The negative slew rate is the slope between 80%
(b) and 20% in the negative transition. The slew rate of an
Fig. 17. Circuit under test. Encapsulated circuit (a) with biasing and clocking op-amp is the minimum of the absolute value of negative
templates (topology specific), and (b) the verification template (functionblock and positive slew rate
and verification task specific) are applied to generate a test harness.

(35)

The average slopes are extracted by measuring the time

elapsed between subsequent threshold passes. This is
shown in Fig. 20.
5) The extracted value is stored in the specification sheet and
Fig. 18. For mismatch simulations, every MOS transistor is replaced by an compared to the specifications.
equivalent statistical model. To avoid an expensive simulation run for every extracted spec-
ification, all transient and small-signal jobs are combined into
Example: An example is now provided to illustrate the gen- two simulation jobs.
eral concept of the verification script. The example presented
is the extraction of the slew rate of an op-amp. The script is as E. Redesign Wizard
follows. Although a performance-driven design methodology is
1) The topology is encapsulated by a biasing and clocking adopted in the AMGIE system, in some cases the tool may not
circuit (see Fig. 17). The biasing is realized through cur- reach a design solution that satisfies all specifications. This
rent sources and mirror transistors to generate all biasing may be because the specifications are too tough for the selected
voltages and currents. The values used have been calcu- circuit schematic or because simplified models used in earlier
lated during sizing and are inserted from the database. design steps incorrectly predicted the actual circuit behavior.
2) The resulting generic op-amp is placed in a dc feedback Any such specification violations are detected by the tools
loop, and loaded with the load specified in the specifica- themselves (for instance, the sizing tool flags that it is incapable
tion sheet (see Fig. 19). For slew rate extraction, a square of meeting the specifications) or by one of the two detailed
wave is applied. The parameters of the square wave (am- verification steps. In all these cases, the redesign wizard is
plitude, rise time, period) are derived from the slew rate automatically started. This tool scans the status and the history
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1053

TABLE IV
SPECIFICATIONS COMMON TO ALL OTA DESIGNS

* Values extracted for the design with GBW 15 MHz and pF.

of the design that failed. It then checks this against a redesign

database where different predefined redesign scenarios, which
contain procedures to remedy and restart the design process,
(a)
have been stored. The (possibly multiple) scenarios applicable
to the actual design problem are then presented to the designer.
The designer selects an appropriate scenario and is guided step
by step to put the design back on track. At present, no automatic
redesign mechanism has yet been implemented that has the
builtin intelligence to automatically choose the best redesign
scenario for every possible situation. The redesign scenarios
in the database have been added by experienced designers.
They are generic, i.e., circuit independent. It is possible for a
designer to add his own scenarios to a private database.
Example: Examples of implemented scenarios are the fol-
lowing.
1) If a design fails during sizing of the cell and if there
are alternative topologies, select the next most promising
topology. (This is the most straightforward redesign sce-
nario.)
2) If a design fails during sizing of the cell, increase the max-
(b)
imum bounds on allowed power consumption and/or chip
area. It is often found that a selected topology can reach Fig. 21. (a) Power and (b) area results of OTA example.
the requested performances, but not within the (often ar-
bitrarily) specified power or area bounds.
3) If a design failure is detected during verification after
sizing and the performance specification causing the
failure has been calculated during sizing with an inac-
curate approximate formula, restart the sizing with the
specification value for this performance tightened with
the same amount by which the simulated performance
differs from the calculated one.
4) If the verification after layout extraction fails, redo the cir-
cuit sizing and optimization after updating the estimated
layout parasitics with the actually extracted parasitics of
the extraction step.

IV. EXPERIMENTAL RESULTS

The capabilities of the AMGIE system are now illustrated
Fig. 22. Schematic of the high-speed OTA.
with practical synthesis examples, some of which have also
been fabricated and measured. The AMGIE system can be
used both by novice and experienced designers. The examples examples illustrate that a synthesis system like AMGIE allows
in this section have been generated by both types of designers. to generate high-performance analog designs in a very short
The first example set, the design of an OTA, has been generated total design time from specification to verified layout. Hence,
in an analog circuit design class project. The second example such a system increases both analog design optimality and
has been generated by an experienced analog designer. Both design productivity.
1054 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 23. Typical layout generated during the class project.

A. Operational Transconductance Amplifier TABLE V

SPECIFICATIONS OF THE PDFE, PERFORMANCES OBTAINED BY A MANUAL
The design of OTAs is a frequently occurring task. The REFERENCE DESIGN, PERFORMANCES OBTAINED BY THE AMGIE SYSTEM,
AMGIE cell library contains a number of topologies imple- AND THE MEASURED PERFORMANCE

menting the OTA function. With this library, a class of EE

Master students has generated a number of designs. They were
divided in nine groups, each of which received a different
requirement of GBW (5, 15, 45 MHz) and load capacitance (5,
10, 20 pF). The specifications that were common to all projects
are summarized in the second column of Table IV. The exercise
was performed on HP 712/80 UNIX workstations. All groups
succeeded in the task without redesign iterations. The fastest
design time was 1 h, the slowest 2 h and 15 min. The time spent
getting acquainted with the tool is included in these reported
times. An experienced tool user can accomplish the same task ation. The block diagram of a typical PDFE is shown in Fig. 6
in 40 min from specification to layout. [41]. An incident particle will generate a charge pulse on the
Fig. 21(a) and (b) shows the achieved power consumption and detector proportional to its energy. The purpose of the PDFE
area of the nine designs. Fig. 22 shows the schematic of the typ- is to transform this charge pulse in an electronically measur-
ically selected topology, while Fig. 23 shows a typical layout able quantity. This is achieved by an analog preprocessing chain
result. The simulated performance is verified against the specifi- comprising a CSA and a PSA. The charge packet is integrated
cations in the third column of Table IV and all specifications are onto a capacitor by the CSA and then shaped by the PSA to
satisfied. None of the designs encountered redesign iterations. a Gaussian pulse whose peak amplitude is proportional to the
This project showed that even less experienced designers can original energy. This pulse is created by differentiating the in-
generate good designs in a short time with the AMGIE system. tegrated charge and subsequently integrating the spike times.
The only limitation is that sufficient cells must be available in The value of is allowed to vary between one and four and will
the library to have sufficient coverage of typical performance be determined by the synthesis tool depending on the required
ranges encountered in practical applications. specifications ( is, thus, a topological variable). The most im-
portant specifications of this front end for a certain ESA exper-
iment are summarized in Table V. The peaking time is defined
B. Particle Detector Front End as the time delay between the incidence of a particle and the
A second example is the design of a particle detector front top of the Gaussian pulse. The counting rate defines the max-
end (PDFE), which is used in nuclear physics or space satellite imum number of particles that may occur before the tails of
experiments to measure the energy of infalling particles or radi- the gaussian pulses cause a measurement error. The noise of the
VAN DER PLAS et al.: AMGIE—A SYNTHESIS ENVIRONMENT FOR CMOS ANALOG INTEGRATED CIRCUITS 1055

Fig. 24. Hierarchical structure of the CSA-PSA custom cell.

system is expressed as an equivalent number of electron charges, , the differentiator with pole-zero cancellation PSA DIF, and
which is directly related to the lowest possible particle energy the integrator PSA INT. The topologies available for these four
that is still detectable. The gain and the output swing define the functionblocks are all flat (i.e., specified at the device level).
amplification and range of signals at the output of the system. Starting from the specifications of Table V, the tool has
The value of the detector capacitance is required to optimally selected the custom CSA-PSA topology (with variable number
(noise) match the front end to the detector. The power and area of integrators ). The optimization of the topology uses power
must be minimized. The technology used is a 1P2M 0.7- m and area estimators to determine the optimal specifications of
CMOS. the composing subblocks [26]. The optimization time is typi-
The custom CSA-PSA cell in the AMGIE system has been cally 20 min on a Sun Ultra 1-170 workstation. The CSA-PSA
implemented as an hierarchical topology. The full schematic is subsequently verified using behavioral simulation. Using the
of the topology is shown in Fig. 24. The CSA-PSA topology derived subblock’s specifications, a topology is selected for
uses four functionblocks: CSA, the active feedback resistance each of the subblocks and the chosen topologies are sized. The
1056 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Fig. 25. Generated layout of the CSA-PSA.

sizing down to automatic layout generation and performance

characterization. It follows a hierarchical refinement strategy for
complex cells and is process independent. The sizing is based
on an improved equation-based optimization approach, where
the circuit behavior is characterized by declarative models that
are then converted in a sequential design plan. Supporting tools
have been developed to reduce the total effort to set up a new
circuit topology in the system’s library. The performance-driven
layout generation tool guarantees layouts that satisfy all perfor-
mance constraints. The experimental results illustrate the pro-
ductiveness and efficiency of the environment for the synthesis
of frequently used analog cells.

REFERENCES
[1] H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L.
Todd, Surviving the SOC Revolution a Guide to Platform-Based
Design. Norwell, MA: Kluwer, 1999.
[2] L. R. Carley, G. Gielen, R. Rutenbar, and W. Sansen, “Synthesis tools
for mixed-signal ICs: Progress on front-end and back-end strategies,” in
Fig. 26. Measured time response of the CSA-PSA circuit to an incident Proc. IEEE/ACM Design Automation Conf., June 1996, pp. 298–303.
particle of 100 fC. [3] M. Degrauwe et al., “IDAC: An interactive design tool for analog CMOS
circuits,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 1106–1116, Dec.
1987.
resulting performance after sizing (down to the device level) is [4] R. Harjani, R. Rutenbar, and L. R. Carley, “OASYS: A framework for
analog circuit synthesis,” IEEE Trans. Computer-Aided Design, vol. 8,
summarized in the fourth column of Table V. All specifications pp. 1247–1266, Dec. 1989.
are satisfied. The width of the input transistor is 1623 m, its [5] F. El-Turky and E. Perry, “BLADES: An artificial intelligence approach
length 1.3 m. The integration capacitor of the CSA is 215 to analog circuit design,” IEEE Trans. Computer-Aided Design, vol. 8,
pp. 680–692, June 1989.
fF. Compared with an existing reference design (third column [6] H. Koh, C. Séquin, and P. Gray, “OPASYN: A compiler for CMOS op-
of Table V), the tool has been able to aggressively reduce erational amplifiers,” IEEE Trans. Computer-Aided Design, vol. 9, pp.
the power consumption from 40 mW down to 7 mW, without 113–125, Feb. 1990.
[7] G. Gielen, H. Walscharts, and W. Sansen, “Analog circuit design opti-
sacrificing any extra area. The layout has been generated with mization based on symbolic simulation and simulated annealing,” IEEE
LAYLA, following the hierarchy of the CSA-PSA front end. J. Solid-State Circuits, vol. 25, pp. 707–713, June 1990.
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an analog synthesis system,” in Proc. Eur. Design and Test Conf., Mar. Belgium, in 1969. He received the M.Sc. degree
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[18] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Katholieke Universiteit Leuven, Leuven-Heverlee,
Analog Integrated Circuits. Norwell, MA: Kluwer, 1991. Belgium, in 1992. He is currently working toward
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Vazquez, “Efficient symbolic computation of approximated small-signal versiteit Leuven. His current research interest is in the
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Aug. 1995, pp. 79–82. M.Sc. degree in electrical and mechanical engi-
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gorithm with guaranteed convergence for analog integrated CMOS cir- Leuven-Heverlee, Belgium, in 1992.
cuits,” in Proc. ACM/IEEE Int. Conf. Computer-Aided Design, Nov. From 1992 to 2000, he was a Research Assistant
1998, pp. 304–307. with the ESAT-MICAS Laboratory of the Katholieke
[24] D. Foty, MOSFET Modeling with SPICE: Principles and Prac- Universiteit Leuven. In 2000, he joined DNS Bel-
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May 1989.
[26] J. Vandenbussche, S. Donnay, F. Leyn, G. Gielen, and W. Sansen, “Hier-
archical top-down design of analog sensor interfaces: From system-level Francky Leyn (S’95–A’01) received the M.Bc. de-
specifications down to silicon,” in Proc. IEEE Design, Automation, Test gree in electronics from the Katholieke Hogeschool
Eur. Conf., Feb. 1998, pp. 716–720. Brugge-Ooostende, Oostende, Belgium, in 1989 and
[27] R. Harjani and J. Shao, “Feasibility and performance region modeling of the M.Sc. degree in electrical and mechanical en-
analog and digital circuits,” Analog Integr. Circuits Signal Processing, gineering from the Katholieke Universiteit Leuven,
vol. 10, no. 1, pp. 23–43, Jan. 1996.
Leuven-Heverlee, Belgium, in 1993.
[28] G. Van der Plas, J. Vandenbussche, G. Gielen, and W. Sansen, “Es-
He is currently a Research Assistant with the
teMate: A tool for automated power and area estimation in analog
ESAT-MICAS Laboratory of the Katholieke Uni-
top-down design and synthesis,” in Proc. IEEE Custom Integrated
versiteit Leuven working on computer-aided design
Circuits Conf., May 1997, pp. 139–142.
for analog integrated circuits. His current research
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interests include modeling and sizing methodologies
CMOS A/D converters,” in Proc. IEEE Design, Automation, Test Eur.
for analog building blocks.
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in electrical and mechanical engineering from the
with constraint programming modeling and minimax optimization,” in
Katholieke Universiteit Leuven, Leuven-Heverlee,
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Belgium, in 1992 and 1998, respectively.
[33] R. Fletcher, Practical Methods of Optimization, 2nd ed. New York:
From 1992 to 1996, he was a Research Assistant
Wiley, 1987.
with the ESAT-MICAS Laboratory of the Katholieke
[34] G. Debyser and G. Gielen, “Efficient analog circuit synthesis with si-
Universiteit Leuven. In 1996, he joined Conexant
multaneous yield and robustness optimization,” in Proc. ACM/IEEE Int.
Systems, Inc., Newport Beach, CA. His current
Conf. Computer-Aided Design, Nov. 1998, pp. 308–311.
research interests include analog design automation.
[35] K. Lampaert, G. Gielen, and W. Sansen, Analog Layout Generation for
Performance and Manufacturability. Norwell, MA: Kluwer, 1999.
[36] E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli, “Au-
tomation of IC layout with analog constraints,” IEEE Trans. Computer-
Aided Design, vol. 15, pp. 923–942, Aug. 1996. Jan Vandenbussche was born in Leuven, Belgium,
[37] K. Lampaert, G. Gielen, and W. Sansen, “A performance-driven place- in 1971. He received his M.Sc. degree in electrical
ment tool for analog integrated circuits,” IEEE J. Solid-State Circuits, and mechanical engineering from the Katholieke
vol. 30, pp. 773–780, July 1995. Universiteit Leuven, Leuven-Heverlee, Belgium,
[38] , “Thermally constrained placement of analog and smart power in- in 1994. He is currently working toward the Ph.D.
tegrated circuits,” in Proc. Eur. Solid-State Circuits Conf., Sept. 1996, degree on the design automation of analog-to-digital
pp. 160–163. and digital-to-analog converters at the same univer-
[39] , “Analog routing for manufacturability,” in Proc. Custom Inte- sity.
grated Circuits Conf., May 1996, pp. 9.4.1–9.4.4. He is currently a Research Assistant with the
[40] W. Verhaegen, G. Van der Plas, and G. Gielen, “Automated test pat- ESAT-MICAS Laboratory of the Katholieke Univer-
tern generation for analog integrated circuits,” in Proc. IEEE VLSI Test siteit Leuven. His current research interest include
Symp., May 1997, pp. 296–301. design and design automation of analog integrated circuits.
1058 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001

Georges G. E. Gielen (S’87–M’92–SM’99) Petar Veselinovic (M’99) received the Dipl.Ing. in

received the M.Sc. and Ph.D. degrees in electrical electrical engineering from the Belgrade University,
engineering from the Katholieke Universiteit Belgrade, Yugoslavia, in 1992, and the Ph.D. degree
Leuven, Leuven-Heverlee, Belgium, in 1986 and in electrical engineering from the Eindhoven Univer-
1990, respectively. sity of Technology, Eindhoven, The Netherlands.
After he was a Postdoctoral Researcher and From 1992 to 1997, he was a Research Assistant
Visiting Lecturer with the University of California, with the Microlectronics Group of the Faculty of
Berkeley, he joined the Katholieke Universiteit Electrical Engineering, Eindhoven University of
Leuven, where he is currently a Professor of Elec- Technology. In 1997, he joined ASM Lithography,
trical Engineering. He has authored or coauthored Veldhoven, The Netherlands, where he is currently
two books and more than 100 papers in books, a Systems Engineer, responsible for throughput and
journals, and conference proceedings. His current research interests include the productivity. His research interests include systems architecture and design.
design of analog and mixed-signal integrated circuits, especially in analog and Dr. Veselinovic received the 1995 Best Paper Award from the International
mixed-signal computer-aided design tools and design automation (modeling, Journal on Circuit Theory and Applications.
simulation, and symbolic analysis, analog synthesis, analog layout generation,
analog and mixed-signal testing). He is the coordinator or partner of several
(industrial) research projects in this area.
Dr. Gielen is a Member of the Board of Governors of the IEEE Circuits
and Systems Society and Chairman of the IEEE Benelux Circuits and Systems
chapter. He is involved in the program committees of many conferences and
is also on the editorial board of several journals. He was the 1997 Laureate of
the Belgian National Academy of Sciences, Literature, and Arts award in engi-
neering sciences and received the 1995 Best Paper Award of the International
Journal on Circuit Theory and Applications.

Willy Sansen (S’66–M’72–SM’86–F’95) was

born in Poperinge, Belgium, on May 16, 1943.
He received the M.Sc. degree in electrical engi- Domine Leenaerts (M’94–SM’96) was born in
neering from the Katholieke Universiteit Leuven, Geldrop, The Netherlands, in 1964. He received
Leuven-Heverlee, Belgium, in 1967 and the Ph.D. the M.Sc. and Ph.D. degrees in electrical engi-
degree in electronics from the University of Cali- neering from the Technical University Eindhoven,
fornia, Berkeley, in 1972. Eindhoven, The Netherlands, in 1987 and 1992,
Since 1981, he has been a Professor with the ESAT respectively.
Laboratory of the Katholieke Universiteit Leuven and In 1992, he became a Research Scientist and then
was Head of the Electrical Engineering Department an Assistant Professor with the Technical University
from 1984 to 1990. He was a Visiting Professor with Eindhoven. In 1995, he was a Visiting Scholar with
Stanford University in 1978, Federal Technical University Lausanne in 1983, the Department of Electrical Engineering and Com-
the University of Pennsylvania, Philadelphia, in 1985, and the Technical Uni- puter Science, University of California, Berkeley, and
versity Ulm in 1994. He has been involved in design automation and in nu- also a Visiting Professor with the Electronic Research Laboratory of the same
merous analogue integrated circuit designs for telecom, consumer electronics, university. Since 1997, he has been a Visiting Professor with the Technical Uni-
medical applications, and sensors. He supervised 39 Ph.D. dissertations and has versity of Lausanne. He is currently with the Philips Research Laboratories,
authored and coauthored more than 400 papers in journals and conference pro- Eindhoven, The Netherlands. He has authored or coauthored several papers in
ceedings and six books, including Design of Analog Integrated Circuits and journals and conference proceedings. His current research interests include non-
Systems (New York: Wiley, 1994). linear dynamic system theory, chaotic behavior in circuits, and analog design
Dr. Sansen is a Member of several editorial committees of journals, such as automation.
the IEEE JOURNAL OF SOLID-STATE CIRCUITS, Sensors and Actuators, and High Dr. Leenaerts received the 1995 Best Paper Award from the International
Speed Electronics. He servers on the program committees of conferences such Journal of Circuit Theory and Applications in 1995. He serves regularly on the
as ISSCC, ESSCIRC, ASCTT, Eurosensors, and Transducers. program committee of international conferences.