Electrical Engineering 1

Sequential Logic

1 Introduction to sequential Logic

So far, all of the circuits that we have looked at have had an output value (at any given time) that
depends only on the inputs (at that particular time). Logic circuits with this property are called
combinational logic. We have now completed our survey of the basic principles of combinational
logic, and we move on to consider sequential logic. Sequential systems include memory devices and
sequence generators. In this lecture we look at the most basic building block of sequential systems, the
RS latch.

1.1 Example
As an example, imagine a model train set where the train is free to move backward or forward on a
track. The direction of motion is controlled by a digital signal that causes the train to move forward
when it has a value of 1, and causes reverse when it is 0. There are two sensors on the track that can
sense when the train is overhead. They output a 1 when the train is overhead and a 0 otherwise. When
the senor outputs a 1, it causes the train’s direction to flip. The train takes 30 s to go from one end of
the track to the other.

Left Sensor
Right Sensor
Train overhead=1
Train overhead=1
Clear overhead=0
Clear overhead=0
Direction control
Forward=1
Reverse=0
Imagine that the direction control is initially at 1 (the train is going forward) and the train is in the
centre, as shown in the diagram above. The sequence that follows is:
Time 0-15s 15s 15s 15s-45s 45s 45s 45-75s
What’s Train is Train This Train is Train This Train is
happening going reaches causes now reaches causes now going
forward left sensor direction reversing right direction forward
to flip sensor to flip
Left sensor 0 1 1 0 0 0 0
Right sensor 0 0 0 0 1 1 0
Direction 1 1 0 0 0 1 1

The sequence then repeats until the power supply is turned off.

The logic has two inputs (Left sensor and Right sensor) and one output (Direction control). However,
something is happening here that we have not seen before. Consider the two columns headed “Train is
now reversing” and “Train is now going forward”. In both cases the inputs are 00. However, the
resulting output is different in the two cases. Identical inputs conditions lead to different output
conditions.

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We can construct a truth table for this (noting that it is physically impossible for both sensors to be
outputting a 1 at the same time as the train can’t be in both places at once):

Left sensor Right sensor Output

0 0 Keep doing whatever you are already doing
0 1 1 – go forward
1 0 0 – go backward

We have a truth table that involves a memory of what the system is already doing. Another more
detailed way to draw up the truth table is:

Left sensor Right sensor Present output New output

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0

We have a circuit where the new output is dependent not only on the new input conditions, but also on
whatever value the output presently has. In other words, the present value of the output is
contributing to the decision as to what the future value of the output must be.

1.2 The RS latch

The device that accomplishes this function is called the RS latch. It has two inputs: SET: (often
abbreviated to S) and RESET (often abbreviated to R).

RESET Q

SET Q

The output Q behaves according to the following truth table:

Set Reset Qnew

0 0 Q
0 1 0
1 0 1

When SET=0 and RESET=0, the value of Q will not change from its current value (Qnew=Qpresent). The
device output said to be latched. When SET=1, the output Q transitions to a new value of 1 (regardless
of the current value of Q). When RESET=1, Q transitions to a new value of 0 (regardless of the current
value of Q). In the next lecture we will look at how the RS latch is constructed and how it is used.

1.3 The “not allowed” state

If SET=1 and simultaneously RESET=1, then we are telling the device to change its output both to 0
and 1 at the same time. This makes no sense, and is called the “not allowed” state, and we should try to
make sure that it never happens. For our model train set we can guarantee that this can’t happen,
because the sensors are far apart and the train can never be over both at the same time.
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2 Astable and Bistable Devices
2.1 Devices whose output is fed back to the input
We observed earlier that in a latch device, the current value of the output is contributing to the decision
as to what the new value of the output must be. This means that the output is being fed back to be
combined with the inputs to the device. Before we look at the detail of the latch construction, we will
spend some time to think about what it means to feed back an output to the input and what its
consequences are.

2.2 Odd number of inversions in a loop: astable circuits

The simplest circuit we can construct that has the output fed back to the input is this:

Output

In circuits where the output is fed back to the input, it can sometimes be confusing to know which
signal is going in which direction. So at the start we will use arrows to make it clear. When we get
more experienced and familiar with the circuits, we will stop using the arrows.

At first glance the circuit above makes no sense: the output must do the opposite to the input, but the
output is the input. The circuit starts to make more sense when we remember that the inverter (like all
logic gates) has a delay. When we apply an input to the device, there is a delay (we normally call it )
before the corresponding output will appear. So if we imagine that the input to the inverter has just
become 1, then the output will become 0 after a delay of . This 0 is immediately fed back to the input
which causes the output to become 1 after a further delay of . And so on… The behaviour looks like
this:

 
The circuit never settles to a stable output value: it is said to be astable. The output oscillates as a
square wave with period of 2. This circuit is called a ring oscillator, and is commonly used to
measure the typical delay  of logic gates produced in a manufacturing batch. The value of  typically
ranges from a few nanoseconds to 10s of picoseconds. This gives a very high frequency of oscillation
that is difficult and expensive to measure accurately. We can make the frequency more manageable by
using a larger odd number of inverters, e.g.:

Output

Now when the input of the first inverter becomes 1, this causes the output of the final inverter to
become 0 after a delay of 3t. This leads to oscillation at a lower frequency:

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  
2.3 Even number of inversions: bistable circuits
Now let’s consider a ring of two inverters:

This circuit has two possible states, both of which are stable:

0 1 1 0
Q=0 Q=1

If Q=0, then the two inversions in the loop will reinforce the existing value of Q, and it will stay at 0
indefinitely (until the power supply to the circuit is turned off). Likewise, if Q=1 the loop will
reinforce this value and it will stay at 1. So we have created a memory device that can store the value
of a bit for as long as we need. When we use memory devices as building blocks in larger circuits, it is
often useful to make the complement of Q available as an additional output. So we include an
additional wire to take the middle node out as an additional output Q:

Although we have created a 1-bit memory, it is not (yet) useful. We have no way to control the value
that is stored at Q. Furthermore, when the device is powered up we have no way of knowing whether
Q will become 1 or 0; it will settle into one or the other state at random.

2.4 Making the bistable useful

We need to include a way to inject a required value into the memory. This can be done by replacing
one inverter with a NOR gate.

Q
SET
Q

The NOR gate will output a 0 when any of its inputs are 1. So if SET=1 then the output of the NOR
gate will go to 0. This will cause Q to go to a new value of 1. If SET=0, then the output of the NOR

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gate is the complement of Q: once again we have a self-reinforcing loop of two inversions that causes
Q to retain whatever value it currently has. This gives us the following truth table:

SET Q Q = SET+Q Qnew

0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
So we have found a way to make the memory store a 1. We also need a way to make it store 0. This
can be done by replacing the second inverter by a NOR gate:

RESET
SET
Q

The circuit that we have now produced is an RS latch. If SET=0, RESET=0, then we have the self-
reinforcing loop of two inversions and Q and Q retain whatever value they already had. If SET=1 and
RESET=0 then Q will go to go to 1. If SET=0 and RESET=1 then Q will go to go to 0.

If SET=1 and RESET=1 then both Q and Q go to zero. This is a little worrying, as Q and Q are supposed
to be opposite in value. However, the condition SET=1 and RESET=1 should never occur in correct
operation so we will tolerate this peculiarity but make a mental note that we need to ensure that when
we use an RS latch we don’t allow SET=1 and RESET=1 at the same time.

2.5 The RS latch

We now have our circuit for the RS latch. This is the most fundamental building block for sequential
circuit elements. The circuit is often re-drawn as shown below right.

RESET RESET
Q
SET
Q

Q Q
SET

The truth table and symbol for the RS latch are shown below:

S R Qnew Name
0 0 Q Hold R Q
0 1 0 Reset
1 0 1 Set S Q
1 1 0 Not allowed

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2.6 Waveforms for the RS latch
The waveform below illustrates how the RS latch responds to inputs.

time

When the S input goes high, after a very short delay the Q output goes high. The second time the S
input goes high, there is no effect on the Q output because it is already high. When the R input goes
high, the Q output goes low. When R, S are both low, the Q output retains its old value.

2.7 Summary
The RS latch is a storage element that can be used to retain a single bit of information. It illustrates the
characteristic feature of sequential logic that the present value of inputs are not (by themselves)
sufficient to predict what the output of the circuit will be. The RS latch is often used as a basic building
block to create more complicated devices that are triggered by changes in a clock signal.

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3 Devices governed by a clock: flip flops
Most sequential logic systems have their activity synchronized to a master signal called a clock.
Systems that can only update their outputs at times determined by a clock signal are called
synchronous. The use of devices that only update their state at clock edges helps enormously to
simplify the job of sequential system design. The RS latch is an asynchronous device: its outputs will
update whenever the inputs change without reference to any clock signal. In this lecture we will look at
the basic building blocks for synchronous sequential systems, a family of devices called flip-flops.
Most flip-flops are based on the RS latch, but incorporate additional logic to determine their response
to the clock signal.

3.1 Synchronous and asynchronous systems

The RS latch is an asynchronous device. The output Q can change as soon as the inputs change
(subject to very short time delay):

time

In a synchronous system, there is a master signal called a clock that alternates between a value of 1
and 0 at regular intervals. All movement of data is synchronised to this clock signal. When the clock
transitions from 0 to 1 the devices read their inputs and update their outputs. At all other times, the
devices ignore their inputs and their outputs are held constant. The behaviour of a synchronous edge-
triggered RS flip flop is shown below:

Clock

time
The dashed lines show the rising edges of the clock edge. The device responds to the values of the
signals at this clock edge and updates its output accordingly. At all times other than the rising edge of
the clock, the inputs are ignored and the output is held at a constant value.

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3.2 Making the RS latch synchronise to a clock signal

3.2.1 The gated RS latch

As a first step in our thinking, consider the following device:

RESET
R Q

ENABLE
SET S Q

When ENABLE=0, the AND gates output 0. This means that the latch is holding its previous value
constant (R=0, S=0). When ENABLE=1, the device can respond to the R and S inputs as normal. Some
typical waveforms for this device are shown below:

ENABLE

SET

RESET

Q
time

3.2.2 The edge triggered RS flip flop

To produce an edge-triggered RS flip-flop, we connect two gated RS latches one after the other and
enable them with different phases of the clock (i.e. one is enabled when the clock is high, and the other
when the clock is low). This arrangement is called a “master-slave” configuration.

Master Slave

RESET R Q RESET Q
SET S Q SET Q
ENABLE ENABLE

CLOCK

The first latch (the “master”) is enabled when CLOCK=0. This means that the values at its R and S
inputs are active and will control the master’s Q and Q outputs. However, while CLOCK=0 the slave
device is disabled and will not respond to the values of R, S at its inputs. When clock changes to 1, the
master will be disabled and its outputs will latch and retain a constant value. The slave latch is now
enabled and will read the outputs of the master and set/reset its own outputs as appropriate. So the
value at the master input before the clock edge appears at the slave output. The outputs of the slave
latch are now constant and cannot change until the next rising edge of the clock.

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This is our edge triggered RS flip-flop. The circuit symbol for this device is:

R Q
S
Clock Q

The small triangle on the clock input indicated that the device responds only on the rising edge of the
clock. A typical waveform (as we saw before) for this device is

Clock

time
We can see that if S=1 at the time of the clock edge then Q becomes 1. If R=1 at the time of the clock
edge then Q becomes 0. At all other times Q just holds its value unchanged.

3.3 Commonly used flip-flops

We have now created a basic edge-triggered device. However, the RS flip flop itself is rarely used in
practice. Instead, three variants that tweak the basic RS behaviour are used in common circuits. These
are introduced below. In future lectures we will look at their application and see why they are useful.

3.3.1 The D flip-flop

The D-type flip flop is constructed as follows:

D R Q
CLOCK Clock

S Q

If D=1 when the clock edge happens, then the device will set Q to a new value of 1. If D=0 at the clock
edge, then the device will reset Q to a new value of 0. At times other than the clock edge, the device
ignores its D input and the value of Q cannot change. You can think of this as a memory bit Q that has
a new value written to it by the input D when the active clock edge occurs. Its truth table and circuit
symbol are as follows

D Clock Qnew D Q
0 0
1 1 Clock Q

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An illustrative waveform for the D flip flop is:

Clock

The device takes the value that D had at the rising clock edge, and memorises it for the rest of the
clock cycle. The output Q is the memorised bit.

3.3.2 The T flip-flop

We will soon encounter circuits where it useful to have a “toggle the output” instruction, which causes
a memorised bit Q to flip its value (if it was a 0 then it becomes a 1; if it was a 1 then it becomes a 0).
This function is provided by the T-type flip-flop (T stands for toggle). It is constructed like this:

T D Q

Clock Q

On each active clock edge a new value is loaded into the memory of the D flip-flop. We can figure out
what the new value will be by considering the truth table of the exclusive OR gate:

T Q D=T⨁Q
0 0 0
0 1 1
1 0 1
1 1 0

If T=0, then the new value loaded into memory bit is just the same as the old value already stored. If
T=1, then the new value of the memorised bit is reversed.

The T flip flop has truth table and circuit symbol as follows:

T Clock Qnew Name T Q

0 Q Hold
1 Q Toggle Clock Q

The symbol reminds us that the device will only make transitions at the rising edge of the clock.

An illustrative waveform for the T flip flop is:

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 Clock

Hold Toggle Hold Toggle Toggle

3.3.3 The JK flip-flop

The truth table and circuit symbol for the JK flip-flop are as follows

J K Clock Qnew Name

0 0 Q Hold J Q
0 1 0 Reset K
1 0 1 Set Clock Q
1 1 Q Toggle

The way to understand this is as follows:

 If J=0, K=0 at the clock edge, then the new value of Q is just the same as the old value of Q.
 If J=0, K=1 at the clock edge, then the new value of Q is 0.
 If J=1, K=0 at the clock edge, then the new value of Q is 1.
 If J=1, K=1 at the clock edge, then the new value of Q is complement of the old value of Q.
The JK flip-flop is similar to an RS flip-flop (with J playing the role of SET and K playing the role of
RESET), but it takes the condition R=1, S=1 (which is not allowed for an RS flip-flop) and does
something useful with it. The JK flip-flop uses J=1, K=1 as a toggle instruction.

It is constructed like this:

J
D Q
K

Clock Clock Q

The truth table for the new value D that is loaded into memory at the active clock edge is
J K Q D Behaviour
0 0 0 0
Hold
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0
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An illustrative waveform for the JK flip flop is:

Clock

Hold Set Reset Toggle Toggle

3.4 Summary
A flip-flop is a device that updates its state at the rising edge of the clock. At all other times its output
is held steady. We have introduced the three most useful forms of flip-flop (D, T and JK). In future
lectures we will see how these devices are applied to build useful sequential circuits.

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4 Basic ideas of counter circuits
In this lecture we will start to learn how to design sequential circuits. The design examples that we will
examine will be counters: circuits that go through a fixed sequence of output values. Counters can be
built from any type of flip-flop. In lecture 5 we will focus on design using D-type flip-flops. These are
conceptually the easiest to design with. In lecture 7 we will look at design using T-type flop flops;
these lead to simpler circuits but require a bit more thought in their design.

4.1 Example: a digital clock

A counter circuit is a sequence generator. The sequence may be something that looks like
“counting”(e.g. 1, 2, 3 … or 3, 2,1 …), or it may be a an arbitrary sequence (for example, a sequence
of control signals for a piece of machinery). The sequence advances one step on each synchronisation
pulse. To keep things simple, we’ll start with a sequence that is very familiar: a digital clock. We’ll use
this to get a basic idea of what needs to happen in a counter circuit and how we would have to organise
a circuit to achieve a counter function.

At 2 minutes to 10 o’ clock, our clock display might look something like this:

0 9 : 5 8

Each minute the display will update. So after one minute it will transition to this state:

0 9 : 5 9

After another minute, it will transition to this state:

1 0 : 0 0

Let’s think about the logic needed to build this. We need some kind of decision logic that takes the
current values and uses them to make a decision about what the next values should be. Each time a
minute is up, the current value is replaced by the new value that has been produced by the decision
logic.

This leads us to an overall structure that looks like this

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The clock values are held in some kind of element that can hold its value constant until a
synchronisation pulse is received, and then update its value. This is the characteristic of flip flop
circuits. The decision logic looks at current values and decides on new values. New values are applied
when the synchronisation pulse is received. This will be built from combinational logic.

4.2 Flip flops

Combinational logic circuits have an output (at any given point in time) that is determined purely by
the inputs at that point in time. For many application requirements this behaviour is insufficient and
we need circuits that have the ability to hold a computed result after the input condition that caused
the result has been removed. This, effectively, means that we need a device with memory.

Flip flops are devices that have a single bit of memory. Transitions of this memory bit are
synchronised to transitions of a clock input. A single bit often isn’t much use, so flip flops tend to be
used in groups with each of their memory bits forming one bit of a larger word. An example could be
a system that counts the number of cars that move past a particular road junction. A sensor would
generate a pulse each time a car passes. This pulse causes the output to increment. This means that the
new output is a function of the data input (the pulse caused by the car) and also the current state of the
output. So, for example, if the current value of the output is 0001 (i.e. the denary number 1) and a new
pulse is received then the output should transition to a new value of 0010 (the denary number 2). On
the other hand, if the current output is 0111 (the denary number 7) and a pulse is received then the
output should transition to a value of 1000 (the denary number 8). The new output is determined not
only by the input, but also by the current value of the output. This example would require four flip-
flops to build (one to hold each bit of the number) plus some additional logic gates to make the flip
flop values make the required transitions as new pulses are received.

4.3 The D flip-flop

The D flip flop truth table and circuit symbol are as follows

D Clock Q+ D Q
0 0
1 1 Clock Q

The behaviour is that when a clock edge occurs, the value of the D input just before the clock edge is
sampled and memorised in the memory bit. The value of this memory bit appears at the Q output a
short delay after the clock edge. An illustrative waveform for the D flip flop is:

In the description above, we need to distinguish between signal values that are measured just before
the clock edge and values that result just after the clock edge. The logic systems that we will analyse
and/or design will use the values before the clock edge to determine a decision as to what the output bit
must change to after the clock edge. When we do this analysis, signal values just before the clock edge
don’t have any special indication of the time at which they were measured. Signals that result just after
the clock edge are indicated with a + superscript.

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If we look at the waveform above, we can see that the values of Q and Q+ in each cycle are:
 Cycle 1: Q=0 Q+=1
 Cycle 2: Q=1 Q+=0
 Cycle 3: Q=0 Q+=1
 Cycle 4: Q=1 Q+=1

4.4 The characteristic equation

We can describe the operation of the flip-flop using a Boolean equation called the characteristic
equation:

𝑄 =𝐷

The left-hand side of this equation says what happens to the memory bit just after the clock edge. The
right-hand side shows the equation that is evaluated on data values just before the clock edge. In the
case of the D flip flop, the characteristic equation is particularly simple. It is telling us that the value of
D just before the clock edge will appear at the Q output just after the clock edge.

4.5 The structure of a counter circuit

This leads us to the overall structure of a counter circuit.

Logic computes Logic computes

next value of Q0 next value of Q1

D0 Q 0 D1 Q 1

Ck Ck

The current value is a number held in flip flops. The current values are fed into blocks of logic that
compute the next value. Each different possible sequence corresponds to a different content for these
blocks of logic. At each rising clock edge, the new value that has been computed by these blocks of
logic are read into the flip flops and become the current value.

4.6 Analysing D flip flop circuits

“Analysis” means that you are given a piece of hardware and asked to figure out what it does. Here is
an example:

D0 Q0 D1 Q1

Clock Clock

 The circuit starts with Q0=0, Q1=0. What will be the values of Q0 and Q1 on subsequent clock
cycles?
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This is fairly typical circuit for generating a sequence of 2-bit binary numbers. The output value is the
2-bit binary word Q1Q0. The values of Q0 and Q1 (before the clock edge) are used as the basis for the
decision as to what values the memory bits should move to after the clock edge (i.e. Q1+ and Q0+). This
is accomplished by feeding Q0 ,and Q1 through logic gates to produce the D inputs of the flip flops. The
exact sequence that Q1 and Q0 will follow is determined by the choice of logic gates that we use.

Diagrams that show all of the logic gates can become cluttered and hard to read, so we will sometimes
use the equivalent notation:

Q0 Q 0  Q1

D0 Q0 D1 Q1

Clock Clock

The relevant equations are:

𝑄 =𝐷 =𝑄
𝑄 = 𝐷 = 𝑄 𝑄

This means that the values of Q0 and Q1 (before the clock edge) will give rise to values of D0, D1
(before the clock edge). These values of D0, D1 form the values of Q0+, Q1+ that will be applied after
the clock edge. We can use this information to work out the sequence that Q0, Q1 will go through.

Cycle Q1 Q0 D1 D0 Q+1 Q+0

Start 0 0 0 1 0 1
1 0 1 1 0 1 0
2 1 0 1 1 1 1
3 1 1 0 0 0 0
4 0 0 0 1 0 1
And repeats forever

Note that for any given clock cycle (say cycle 2), the values of Q1+, Q0+ (i.e. the values just after the
clock edge that ends cycle 2) will become the current values Q1, Q0 for the next clock cycle (cycle 3).
So Q1+, Q0+ =1,1 for cycle 2 give rise to Q1, Q0=1,1 for cycle 3.

The sequence followed by the circuit is determined entirely by the values of Q1, Q0 at any point in
time. So as soon as we see a repeat value (here cycle 4 is the same as the start value) we know that the
circuit will just endlessly repeat the sequence that we have already seen.

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4.7 Using both of the outputs from the flip-flop
Each flip-flop normally provides a Q output, and also its complement Q. The reason for this is that it
can sometimes simplify our logic circuits if we use both Q and Q as the basis to generate our new
values. So for the circuit that we have just looked at, we could save ourselves one logic gate (the
inverter at D0) by taking our feedback from Q rather than from Q0 like this:

D0 Q0 D1 Q1

Ck Q0 Ck Q1

4.8 Interpreting the output of our example circuit

Our analysis shows that if the circuit starts at Q1Q0=00 then as each rising clock edge occurs, it will go
through the sequence

Q1Q0=00→01→10→11→00→01→10→11→ and so on forever

If we interpret Q1Q0 as the bits of a 2-bit binary number, then the denary interpretation of this is:

Output=0→1→2→3→0→1→2→3→ and so on forever

This is an example of a counter circuit. A counter is a circuit that uses flip-flops to represent a data
word, and moves these data words through a specified sequence, advancing one step further in the
sequence at each active clock edge. There are only a finite number of data words that can occur (in this
example there are 4) so eventually the counter must repeat and go through its cycle again and again.

This particular counter circuit generates a sequence that has a very obvious interpretation and
application. It is a binary up-counter. It moves through a sequence of binary numbers in ascending
order. Let’s go back to our starting example, a system that counts the number of cars that move past a
particular road junction. A sensor generates a pulse each time a car passes. This circuit shows how we
could accomplish this function. (OK, our circuit can only count up to 3, so it would have to be used in
a very quiet neighbourhood with few cars, but once we have mastered the techniques it is
straightforward to extend this design to have many more bits and a much larger count sequence.)

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5 Counter circuit design with D flip flops
5.1 Designing D flip flop circuits
“Design” means that you are given a required behaviour and asked to come up with a circuit that will
give rise to that behaviour. For a 2-bit counter built from D flip flops, that amounts to:

What goes What goes

here to give here to give
the required the required
sequence? sequence?

D0 Q0 D1 Q1

Ck Q0 Ck Q1

We have to design the logic that goes into the boxes. The inputs to this logic can be the values of Q1,
Q0 (and their complements) before the clock edge. This means that we are designing two pieces of
logic, one for D0 and one for D1. This can be done by drawing up two tables (one for D1, one for D0)
table that show:
 the values of the inputs (Q0, Q1) to the box before the clock edge
 the value that we want after the clock edge Q+
 the value that we must force D to before the clock edge in order to get the required next value

5.2 Example of counter design with D flip flops

Let’s think about this design example:

Design a binary down-counter that counts through the sequence:

Output=0→3→2→1→0→3→2→1→ and so on forever

Interpreting these denary numbers in binary means that this is what we need to design:

Q1Q0=00→11→10→01→00→11→10→01→ and so on forever

We now need to think what values of Q1+, Q0+ we need for each possible value of Q1, Q0
 When Q1Q0=00, we need Q1+Q0+=11
 When Q1Q0=11, we need Q1+Q0+=10
 When Q1Q0=10, we need Q1+Q0+=01
 When Q1Q0=01, we need Q1+Q0+=00

We now need to design two pieces of logic, one to drive D0 and one to drive D0. So we will need to
use the information above to draw up two truth tables:

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 Value before Required value Input to give us
clock edge after clock edge required next value
Q1 Q0 Q1+ D1
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q0+ D0
0 0 1 1
0 1 0 0
1 0 1 1
1 1 0 0

Our task is then to design the logic that takes the values of Q0, Q1 as inputs and produces the required
value of D at the output. This can be done with two K-maps:
Q1 Q1
Q0 0 1 Q0 0 1
0 1 0 0 1 1

1 0 1 1 0 0

Map for D1 Map for D0

This gives us our logic:

𝐷 =𝑄
𝐷 = 𝑄 .𝑄 + 𝑄 .𝑄

𝑄 𝑄 .𝑄 + 𝑄 .𝑄

D0 Q0 D1 Q1

Ck Q0 Ck Q1

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5.3 Checking our solution
We can now use the analysis procedure outlines earlier to check if this works as required. Let’s assume
we start with Q0, Q1=0,0:

Cycle Q1 Q0 𝑸𝟏 𝑸𝟎 D1 D0 Q+1 Q+0

Start 0 0 1 1 1 1 1 1
1 1 1 0 0 1 0 1 0
2 1 0 0 1 0 1 0 1
3 0 1 1 0 0 0 0 0
4 0 0
And repeats forever

At each step we have used the values of Q1, Q0 before the clock edge to compute the values of D1, D0
before the clock edge. These values of D1, D0 become the values of Q1+, Q0+ after the clock edge. The
values of Q1+, Q0+ for one clock cycle are the values of Q1, Q0 for the following clock cycle. The
sequence that we get is the required one.

5.4 Summary
In this lecture we have introduced counters as an example of the design and analysis approaches used
for sequential logic systems. Design proceeds by forming a table of the transitions of the state of the
flip flop outputs that must occur on each clock cycle, then using this to generate the requirement for
the flip flop inputs.

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6 Counter design and analysis with T flip flops
We can use any flip flop to design counter circuits. In the previous lectures we saw how to do this with
D flip flops. In this lecture we will repeat the same examples using T flip flops. The design process for
T flip flops is conceptually a little more complicated than for D flip flops, but the circuits that result
are usually simpler.

6.1 The T Flip Flop

The T flip flop has truth table and circuit symbol as follows:

T Q Clock Q+
0 0 0 T Q
0 1 1
1 0 1 Clock Q
1 1 0

As before, any signal without the + superscript refers to the value just before the clock edge. The +
superscript is used to denote values just after the clock edge. The T input can be regarded as a control
input whose function is:
 T=0 Hold the memorised bit constant
 T=1 Toggle the memorised bit

The truth table can also be drawn like this:

T Clock Q+ Name
0 Q Hold
1 Q Toggle

 When T=0, Q+=Q. In other words, the value of Q that will happen just after the clock edge is the
same as the value that Q had just before the clock edge.
 When T=1, Q+ =Q, in other words, the value of Q that will happen just after the clock edge is the
complement of the value that Q had just before the clock edge

An illustrative waveform for the T flip flop is:

Clock

Hold Toggle Hold Toggle Toggle

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6.2 Analysing T flip flop circuits
Consider the following circuit, starting in the state Q0=0, Q1=0. What sequence does it follow?

1 Q0

T0 Q0 T1 Q1

Ck Q0 Ck Q1

The relevant equations are:

𝑇 =1
𝑇 =𝑄

We can work this out by forming a table of values on successive clock cycles. The values of
Q0 ,Q0 ,Q1 , and Q1 (before the clock edge) give rise to values of T0, T1 (before the clock edge). These
values of T0, T1 will cause the values after the clock edge Q0+, Q1+ to be a flip (Q+ =Q) or a hold
(Q+ =Q) of the value before the clock edge. We can use this information to work out the sequence that
Q0, Q1 will go through.

Cycle Q1 Q0 𝑸𝟏 𝑸𝟎 T1 T0 Q+1 Q+0

Start 0 0 1 1 0 1 0 1
1 0 1 1 0 1 1 1 0
2 1 0 0 1 0 1 1 1
3 1 1 0 0 1 1 0 0
4 0 0
And repeats forever

This circuit is a 2-bit binary up-counter:

Q1Q0=00→01→10→11→00→01→10→11→ and so on forever
Denary interpretation of output=0→1→2→3→0→1→2→3→ and so on forever
It instructive to compare this circuit (built from T-types) with the circuit analysed earlier (built from D-
types):

1 Q0

T0 Q 0 T1 Q1 D0 Q 0 D1 Q 1

Ck Q Ck Q1 Ck Q0 Ck Q1
0

2-bit binary up-counter using T-types 2-bit binary up-counter using D-types

The circuit built from T types requires fewer logic gates. This is usually the case for most common
types of counter, hence the popularity of T-type flip-flops.

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6.3 Designing T flip flop circuits
We now look for a process to design a circuit that will give a required behaviour. For a 2-bit counter
built from T flip flops, this amounts to:

What goes What goes

here to give here to give
the required the required
sequence? sequence?

T0 Q0 T1 Q1

Ck Q0 Ck Q1

We have to design the logic that goes into the boxes. The inputs to this logic can be the values of Q1,
Q0 (and their complements) before the clock edge. This requires a little more thought than we needed
when we were using D flip flops. With a D flip flop, the value at the D input was simply equal to Q+.
With the T type we need to think what value T needs to have to give the required transition. We can
do this by drawing up a table that shows the value of Q before the clock edge, the value of Q+ that we
desire after the clock edge, and the value of T that is necessary in order to achieve this:

Value before clock Desired value after What operation What value of T
edge Q clock edge Q+ will give this? will give this?
0 0 Hold 0
0 1 Toggle 1
1 0 Toggle 1
1 1 Hold 0

6.4 Example: a 2-bit binary down-counter

We will now use T-type to design a binary down-counter that counts through the sequence:

Output=0→3→2→1→0→3→2→1→ and so on forever

Interpreting these denary numbers in binary means that this is what we need to design:

Q1Q0=00→11→10→01→00→11→10→01→ and so on forever

This means that we are designing two pieces of logic, one for T0 and one for T1. This can be done by
drawing up two tables (one for T1, one for T0) that show:
 the values of the inputs (Q0, Q1) to the box before the clock edge
 the value that we want after the clock edge Q+
 the value that we must force T to before the clock edge in order to get the required next value

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We draw up our tables:

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q1+ T1
0 0 1 1
0 1 0 0
1 0 0 1
1 1 1 0

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q0+ T0
0 0 1 1
0 1 0 1
1 0 1 1
1 1 0 1

Our task is then to design the logic that takes the values of Q0, Q1 as inputs and produces the required
value of T at the output. This can be done with two K-maps:
Q1 Q1
Q0 0 1 Q0 0 1
0 1 1 0 1 1

1 0 0 1 1 1

𝑇 =𝑄 𝑇 =1

We see that the desired T is not dependent on Q1 or Q0: it is simply 1 all of the time. Our circuit
solution is:
1 Q0

T0 Q0 T1 Q1

Ck Q0 Ck Q1

6.5 Summary
In this lecture we have introduced counters as an example of the design approaches used to build
counters from T-type flip-flops Design proceeds by forming a table of the transitions of the state of the
flip flop outputs that must occur on each clock cycle, then deciding what value the T input should take
at the clock edge in order to give the required output after the clock edge.

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 Index

1 Introduction to sequential Logic 1

1.1 An Example 1
1.2 The RS latch 2
1.3 The “not allowed” state 2
2 Astable and Bistable Devices 3
2.1 Devices whose output is fed back to the input 3
2.2 Odd number of inversions in a loop: astable circuits 3
2.3 Even number of inversions: bistable circuits 4
2.4 Making the bistable useful 4
2.5 The RS latch 5
2.6 Waveforms for the RS latch 6
2.7 Summary 6
3 Devices governed by a clock: flip flops 7
3.1 Synchronous and asynchronous systems 7
3.2 Making the RS latch synchronise to a clock signal 8
3.2.1 The gated RS latch 8
3.2.2 The edge triggered RS flip flop 8
3.3 Commonly used flip-flops 9
3.3.1 The D flip-flop 9
3.3.2 The T flip-flop 10
3.3.3 The JK flip-flop 11
3.4 Summary 12
4 Basic ideas of counter circuits 13
4.1 Example: a digital clock 13
4.2 Flip flops 14
4.3 The D flip-flop 14
4.4 The characteristic equation 15
4.5 The structure of a counter circuit 15
4.6 Analysing D flip flop circuits 15
4.7 Using both of the outputs from the flip-flop 17
4.8 Interpreting the output of our example circuit 17
5 Counter circuit design and analysis with D flip flops 18
5.1 Designing D flip flop circuits 18
5.2 Example of counter design with D flip flops 18
5.3 Checking our solution 20
5.4 Summary 20
6 Counter design and analysis with T flip flops 21
6.1 The T Flip Flop 21
6.2 Analysing T flip flop circuits 22
6.3 Designing T flip flop circuits 23
6.4 Example: a 2-bit binary down-counter 23
6.5 Summary 24

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