Unit –IV

Analysis and Synthesis of Sequential Logic Circuits

Sequential logic Circuit (SLC)

A sequential logic circuit is a digital circuit in which the output at any point of time depends on
prese nt inputs and past outputs. Sequential circuits include memory elements along with combinational
logic circuits. The memory elements are connected to the combinational logic circuit as a feedback path.
Fig 1 shows the block diagram of a sequential logic circuit

Fig. 1 Block diagram of sequential logic circuit.

Finite State Machines

Classification of SLC

The sequential circuits can be classified into two categories depending on the timing of their signals
1. Synchronous sequential logic circuit
2. Asynchronous sequential logic circuit
In case of synchronous sequential circuits, it is assumed that the behavior of the system synchronized
by a clock. The system behavior is determined by the values of present state and external input
signals at discrete instants of time.

In case of asynchronous sequential logic circuits the order in which input signals change affected
network behavior. Further more, these changes are allowed to occur at any instant of time
Mealy Model

Fig. _2____shows the clocked synchronous sequential Mealy machine. The output of mealy machine is
the function of present inputs and present state (Flip flop outputs).
 Fig. _2____ clocked synchronous sequential mealy machine

Moore Machine

Fig. __3___ shows the block diagram of a Moore machine. The output of Moore machine
depends only op the present state. So the output of Moore machine is a function of its present state

Fig __3___ model for Moore machine

Difference between Moore and Mealy Machine

SNo. Moore machine Mealy machine

The output of this machine is the function of the Its output is function of input as well as present
1.
present state only state present

2. Input changes do not affect the output Input changes may affect the output of the circuit

It requires more number of states for implementing It requires less number of states for implementing
3.
same function same function

4 Speed is high Speed is low

5 Design process is very complicate Less complex than Moore design

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS

 The behavior of sequential circuit can be determined from the inputs, the output and state
of its flip flops. 

 The outputs and next state are both a function of its inputs and the present state. 

 The analysis of a sequential circuit consists of obtaining a table or diagram for the time
sequence of inputs, outputs and internal states. 

 The analysis of the clocked sequential circuits can be done by following the procedure as 
Analysis Procedure

1. Identify type of circuit either Mealy or Moore circuit

2. Derive excitation equation (Boolean expression)

3. Derive next state and output equations
4. Generate state table
5. Generate state diagram

Analysis of Example Sequential Logic Circuit

Figure 7.6 shows a clocked sequential circuit. It has one input variable X, output variable Y and
two clocked JK flin flops. The flip flops are labelled as A and B and their outputs are labelled as A and
A, B and B respectively.
 Fig __4_ Sequential Logic Circuit

Step 1 : Type of circuit

The output of given logic circuit y (Fig. __4____) depends on present input and also on
present state (Flip flop outputs) of flip flops, so the given sequential logic circuit is Mealy sequential
machine.

Step 2 : Excitation equations

The excitation equations or Boolean expressions of flip flops A and B are obtained. The equations
will be in the form of present states A and B and external input x. Since there are two JK flip flops which
have output A and B. Therefore the excitation equation (equation formed for flip flop input)

For Flip flop – A

J A  xB and K A  xB

For Flip flop – A

J B  xA and K B  x A

Step 3 : Next state equations

The state equations can be derived directly from the logic diagram, we can see that the
signal for J input of the flip flop A is generated by the function xB and the signal for input K by the
function xB . Substituting J A  xB and K A  xB into a JK flip flop characteristic equation given by

Characteristic Equation of JK Flip flop

Qn1  J Qn  KQn
Substitute the JA and KA in the above equation to obtain the state equation of fkip-flop A

State equation of flip flop A

 
An1  Bx Qn  xBQn where Qn=A

An1  BxA  xBA

Simplify the above equation we get
An1  AB  Ax  Bx

Similarly we get next state equation for flip-flop B

Bn1  AB  Ax  Bx

Output equation y  ABx

Step 4 : State Table

The Table ____ shows the state table for the given sequential logic circuit. It represents the
relationship between input, output, and flipflop states. It consists of three columns: Present
state, next state and output.

Present state: it specifies the state of flip-flop before occurrence of a clock pulse

Next state :it is the state of flip flop after the application of clock

Output: this section gives the value of the output variables during the present state. Both next state and
output section have two columns representing two possible input conditions x=0 and x=1.

State Table

Output
Next state
Present state Y
x=0 x=1 x=
x=1
AB AB AB 0
00 00 10 0 0
01 01 00 0 0
10 11 10 0 1
11 01 11 0 0
5

Step 5 State diagram

State diagram is a graphical representation of a state table. Fig. ____shows the state diagram for
sequential circuit. Here each state is represented by a circle, and transition between states is indicated by
directed lines connecting the circles. The binary number inside each circle identifies the state represented
by the circle. The directed lines are labelled with two binary numbrs separated by a symbol `I' (slash).
The input value that causes the state transition is labelled first and output value is next.
0/0

Fig__5___ State diagram.

STATE REDUCTION AND ASSIGNMENTS

 Any logic design process must consider the problem of minimizing the cost of the final circuit. 

 One way to reduce the cost is by reducing the number of flip flops, i . e . by reducing the number
of states. 


 The state reduction technique basically avoids the introduction of redundant equivalent states.
The reduction of redundant states reduces the number of flip flops and logic gates required, thus
reducing the cost of the final circuit. 

 Two states are said to be redundant or equivalent, if every possible set of inputs generate exactly
the same outputs and the same next states. 

 When two states are equivalent one of them can be removed without altering input output
relationship. Let us consider the state diagram as shown in Fig. 7.8. 

 The states are denoted by letter symbols instead of their binary values because instate reduction
technique internal states are important, but input output sequences are important. The procedure
contains two steps. 
 Step 1: Finding State table for the given state diagram

First the given state diagram is converted into a state table.

Next state output

Present state
x=0 x=1 x=0 x=1
a b c 0 0

b d e 1 0

c c d 0 1

d a d 0 0

e c d 0 1

Step 2 : Finding equivalent states

It is determined from the state diagram. The equivalent state table is given for the above state diagram
as the two present states go to the same next state and have the same output for both the input
combinations. We can easily find this from the state table, states c and e are equivalent. This is because
both c and e states go to states c and d outputs of 0 and 1 for x = 0, x = 1 respectively. Therefore, the state
e can be removed and replaced by c. The final reduced table and state diagram are given in the table . The
second row have e state for the input x = l, it is replaced by c because the states c and e are equivalent.

Reduced state table

Next state Output

Present state x=0 x=1 x=0 x=1

a b c 0 0
b d c 1 0
c c d 0 1

1/0 d a d 0 0

DESIGN PROCEDURE FOR CLOCKED SEQUENTIAL CIRCUIT

The following steps are followed to design the clocked sequential logic circuit.
1. Obtain the state table from the given circuit information such as a state diagram, a timing
diagram or description.
2. The number of states may be reduced by state reduction technique.
3. Assign binary values to each state in the state table.
 4. Determine the number of flip flops required and assign a letter symbol to each flip flop.
5. Choose the flip flop type to be used according to the application.
6. Derive the excitation table from the reduced state table.
7. Derive the expression for flip flop inputs and outputs using k-map simplification (The present
state and inputs are considered for k-map simplification) and draw logic circuit using flip flops
and gates.

Analysis and design of asynchronous sequential logic

Analysis Procedure Transition Table Example on asynchronous sequential circuit

1. Determine all feedback loops in the circuit.

2. Designate the output of each feedback loop with variable Yi and its corresponding input with
yi for i = 1,2,. . . , k, where k is the number of feedback loops in the circuit

3. Derive the Boolean functions of all Ys as a function of the external inputs and the y's.

4. Plot each Y function in a map, using the y variables for the rows and the external inputs for
the columns.

5. Combine all the maps into one table showing the value of Y = Y1Y2..Yk inside each square.

6. Circle those values of Y in each square that are equal to the value of y = y1y2..yk in the same
row. Obtaining a transition table from the circuit diagram Y1=xy1 + x'y2
Y2=xy1' + x'y2 transition table Once the transmition table is available, the behavior of the
circuit can be analyzed by observing the state transition as a function of changes in the input
variables Flow Table note that this circuits has no outputs State table this is the flow table that
corresponds to the transition table in the previous example after the following state assignments:
a=00
b=01
c=11
d=10 it's called primitive flow table because it has only one stable state in each row Design
Example Given the following flow table, we are required to design an asynchronous sequential
circuit to implement it 1- convert the flow table to transition table by assigning binary values to
the states 2-put the outputs from the flow table in a table on their own 3-from the transition
table.
BLOCK DIAGRAM OFAN ASYNCHRONOUS SEQUENTIAL CIRCUIT

• n input variables
• m output variables
• k internal states
delay: like short-term
memory

Asynchronous Sequential Circuit Example

1. Excitation variables as outputs and secondary variables as inputs

Y1=xy1 + x’y2
Y2=xy1’ + x’y2
Plot functions in a map
3. Combine all maps into a transition table – stable state: y=y1y2 (circled)

4. Complete the state stable – check if unstable states will reach a stable state finally

Analysis Procedure

The procedure

1. Determine all feedback loops

2.Assign Yi's (excitation variables), yi's (secondary variables)
3. Derive the Boolean functions of all Yi's
4. Plot each Y function in a map
• the y variables for the rows
• the external variable for the columns
5. Combine all the maps into one transition table
• showing the value of Y=Y1Y2…Yk inside each square
6. Circle the stable states and derive the state table
• those values of Y that are equal to y=y1y2…yk in the same row
Asynchronous sequential circuit (vs. sequential circuit)
•Total state of the circuit: combine internal state with input value
– eg. Figure 9-3(c) has 4 stable total states: y1y2x=000, 011, 110, and 101,
and 4 unstable total states: 001, 010, 111, and 100
•There usually is at least one stable state in each row

Race Conditions

– occur when two or more binary state variables change value

in response to a change in an input variable
• When unequal delays are encountered, a race condition may cause the
state variables to change in an unpredictable manner
• y1, y2, …, yi may change in unpredictable manner in response to a
change in x1
– 00 → 11
• 00 → 10 → 11 or 00 → 01 → 11
– a noncritical race
• if they reach the same final state
• otherwise, a critical race: end up in two or more different stable states

Examples of Cycles

•Races may be avoided

– race-free assignment: only 1 state can change at any one time (Section 9-6)
–Directing the circuit through inserting intermediate unstable states with a
unique state-variable change
•A cycle: When a circuit goes through a unique sequence of unstable states
Procedure for analyzing an asynchronous sequential circuit with SR latches

Logic circuit ⇒ transition table/map

1. Label each latch output with Yi and its external feedback path (if any) with yi for i = 1, 2, …,k
2. Derive the Boolean functions for Si and Ri inputs in each latch
3.Check whether SR=0 for each NOR latch or whether S’R’=0 for each NAND latch
• If not satisfied, it’s possible that the circuit may not operate properly
4.Evaluate Y=S+R’y for each NOR latch or Y=S’+Ry for each NAND latch
5.Construct a map with the y’s representing the rows and the x inputs representing the columns
6. Plot the value of Y=Y1Y2…Yk in the map
7. Circle all stable states where Y=y.

Hazards
In the design of asynchronous sequential circuit, the circuit
– must be operated in fundamental mode with only one input changing at
any time, and
– must be free of critical races
• Hazards: unwanted switching transients at the output
– because different paths exhibit different propagation delays
– May cause the circuit to malfunction
• in combinational circuits: may cause temporary false-output value
• in asynchronous sequential circuits: may result in a transition to a wrong
stable state
– Need to check for possible hazards and determine whether causing improper operations.

Types of Hazards
Whenever the circuit must move from one product term to another, there is a possibility of a
momentary interval when neither term is equal to 1, giving rise to an undesirable 0 output
• Detected by inspecting the map: the change of input results in different product term covering
the two minterms
– minterm 111 in gate 1 and minterm 101 in gate 2
• When a circuit is implemented in sum of products (AND-OR or NAND gates),
the removal of static 1-hazard guarantees that no static 0-hazards or
dynamic hazards will occur
– If the momentary input causes the OR output to change from 0 to 1, the
output will maintain at 1 after the propagation

Hazards In Combinational And Sequential Circuits

In general, no problem for synchronous design, but a momentary incorrect

signal fed back in asynchronous sequential circuit may cause the circuit to go
to the wrong stable state Figure 9-37 Example:
•state yx1x2=111 and input x2 1→0
•next state should be 110
•hazard: output Y may go to 0 momentarily
• feeds back to gate 2 before x2’ enter gate 2
• the circuit will switch to incorrect stable state 010