1.

4-bit Carry Select Adder

AIM: To design a 4-bit Carry Select Adder using Verilog and implement it on FPGA.

TOOLS USED:

1. Vivado tool
2. Vivado Simulator
3. NEXYS4 DDR

THEORY:

A 4-bit Carry Select Adder (CSA) is a digital circuit that adds two 4-bit binary numbers,
producing a sum and carry-out. The CSA design includes two parallel adders: a fast but
power-hungry Carry Look-Ahead (CLA) adder and a slower but more power-efficient Ripple
Carry Adder (RCA).

Here's a basic overview of how it works:

1. Input: The 4-bit binary numbers to be added are provided as inputs.

2. Parallel Processing: The CSA splits the 4-bit addition into two parts. The higher-order bits
(3-0) are processed by the fast CLA adder, while the lower-order bits (0-0) are processed by
the slower RCA.

3. Carry Look-Ahead Adder (CLA): The CLA generates carry-out and carry-in signals for
each bit, allowing parallel processing without waiting for the carry propagation. This
improves the overall speed of addition.

4. Ripple Carry Adder (RCA): The lower-order bits are added using the RCA, which
propagates the carry bit through each stage. While slower than CLA, the RCA is more power-
efficient.

5. Multiplexer (MUX): A multiplexer selects the sum and carry-out from either the CLA or
the RCA based on the overall carry-in signal. If the carry-in is 0, the output comes from the
CLA; if 1, it comes from the RCA.

6. Output: The final sum and carry-out are the results of the 4-bit addition.

The use of both CLA and RCA in parallel allows for a balance between speed and power
efficiency in the 4-bit Carry Select Adder.

1
CIRCUIT DIAGRAM:

2
PROCEDURE:

1. Click on vivado and click on New Project.

2. Give the name to the project.

3. Next-> create the file and give the filename.

4. Select the FPGA XC7A35tftG256-1-> next -> finish.

5. Select the module name under sources.

6. Type the program and save it.

7. Click on Run Simulation and give the values by clicking force constant.

8. Go to file -> close simulation.

9. In project Manager go to open elaborated design under RIL analysis OK.

10. In the left side default layout -> IO planning.

11. Give the input and output keys in the scalar ports.

12. Give the switch numbers to i/p’s under the column package pin.

13. Change the i/o stid to LVCMOS33.

14. Next Save the project with the project name.

15. Go to file -> close elaborated design.

16. Go to file -> open Synthesized design -> schemantic.

17. Take the Screenshot of Report power and Report utilization.

18. Next, go to Implementation after Completing the Implementation go to generate

bitstream.

19. With no settings Changed, the generate will create a ‘bit’ file which can be used to
program the board.

20. The first prompt will ask whether or not to run Synthesis click on Yes.

21. The first prompt before launching the runs gives several options. Leave everything as
default.

22. Finally the bitstream will be generated.

23. Select Hardware Manager, then click OK. Then Click on open target.

3
SIMULATION RESULTS:

HARDWARE IMPLEMENTATION:

4
24. Next Click an auto Connect -> Click the program device after that Click on program to
Connect.

25. See the output in the FPGA.

PROGRAM:

module carry (input [3:0] A,B, input cin, output [3:0] S, output cout);
wire [3:0] temp0, temp1, carry0, carry1;
//for carry 0
fulladder fa00(A[0],B[0],1'b0,temp0[0],carry0[0]);
fulladder fa01(A[1],B[1],carry0[0],temp0[1],carry0[1]);
fulladder fa02(A[2],B[2],carry0[1],temp0[2],carry0[2]);
fulladder fa03(A[3],B[3],carry0[2],temp0[3],carry0[3]);
//for carry 1
fulladder fa10(A[0],B[0],1'b1,temp1[0],carry1[0]);
fulladder fa11(A[1],B[1],carry1[0],temp1[1],carry1[1]);
fulladder fa12(A[2],B[2],carry1[1],temp1[2],carry1[2]);
fulladder fa13(A[3],B[3],carry1[2],temp1[3],carry1[3]);
//mux for carry
multiplexer2 mux_carry (carry0[3], carry1[3], cin, cout);
//mux's for sum
multiplexer2 mux_sum0 (temp0[0], temp1[0],cin, S[0]);
multiplexer2 mux_sum1 (temp0[1], temp1[1], cin, S[1]);
multiplexer2 mux_sum2 (temp0[2], temp1[2], cin, S[2]);
multiplexer2 mux_sum3 (temp0[3], temp1[3], cin, S[3]);
endmodule
module fulladder (input a,b,cin, output sum, carry);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin& b) | (a &cin);
endmodule
module multiplexer2 (input i0, i1,sel,output reg bitout );
always @ (i0, i1, sel)
begin
if (sel == 0)
bitout = i0;
else
bitout = i1;
end
endmodule

TEST BENCH:
module carry_tb;
reg [3:0] A;
reg [3:0] B;
reg cin;
// Outputs
wire [3:0] S;

5
SYNTHESIS RESULT:

6
wire cout;
// Instantiate the Unit Under Test (UUT)
carry uut (.A(A), .B(B),.cin(cin), .S(S), .cout(cout) );

//Stimulus block - all the input combinations are tested here.

//the number of errors is recorded in the signal named "error".
initial
begin
// Initialize Inputs
A = 4'b0011;
B = 4'b0101;
cin = 0;#20
A = 4'b0011;
B = 4'b0101;
cin = 1;#20
A = 4'b0101;
B = 4'b0110;
cin = 0;#20
A = 4'b0101;
B = 4'b0110;
cin = 1;
end
endmodule

CONSTRAINTS:
set_property IOSTANDARD LVCMOS33 [get_ports (A[3]}]
set property IOSTANDARD LVCMOS33 [get_ports (A[2]}]
set property IOSTANDARD LVCMOS33 [get ports (A[1]}]
set property IOSTANDARD LVCMOS33 [get ports (A[0]}]
set_property IOSTANDARD LVCMOS33 [get ports (B[3]}]
set_property IOSTANDARD LVCMOS33 [get ports (B[2]}]
set property IOSTANDARD LVCMOS33 [get ports (B[1]}]
set property IOSTANDARD LVCMOS33 [get ports (B[0]}]
set property IOSTANDARD LVCMOS33 [get ports (s[3]}]
set property IOSTANDARD LVCMOS33 [get ports (s[2]}]
set property IOSTANDARD LVCMOS33 [get ports (s[1])]
set property IOSTANDARD LVCMOS33 [get ports (s[0]}]
set property IOSTANDARD LVCMOS33 [get ports cin]
set property IOSTANDARD LVCMOS33 [get ports cout]
set property PACKAGE PIN L5 [get ports (A[3]}]
set property PACKAGE PIN L4 [get ports (A[2]}]
set property PACKAGE PIN M4 [get ports (A[1]}]
set property PACKAGE PIN M2 [get ports (A[0]}]
set property PACKAGE PIN MI [get ports (B[3]}]
set property PACKAGE_PIN N3 [get ports (B[2]}]
set_property PACKAGE PIN N2 [get ports (B[1]}]
set property PACKAGE PIN NI [get ports (B[0]}]
set property PACKAGE PIN J3 [get ports (s[3]}]
set property PACKAGE PIN H3 [get ports (s[2]}}
set property PACKAGE PIN J1 [get ports (s[1]}]

7
UTILIZATION REPORT:

POWER REPORT:

8
set property PACKAGE PIN K1 [get ports (s[0]}]
set property PACKAGE PIN P4 [get ports cin]
set_property PACKAGE PIN L3 [get ports cout]

RESULT:

4-bit carry select adder is designed using Verilog HDL. Simulation and FPGA
implementation is performed using vivado tool. Functional verification of the design is
performed using a Verilog HDL test bench.

9
10
 2. BCD to Seven Segment Display

AIM: To design, Design a BCD to Seven segment circuit using Verilog and the result is
displayed on FPGA seven-segment display.
TOOLS USED:

1. Vivado tool
2. Vivado Simulator
3. NEXYS4 DDR

THEORY:

The BCD (Binary Coded Decimal) to seven-segment display theory involves converting a
binary-coded decimal number into a format suitable for displaying on a seven-segment
display. Each digit in a BCD number is represented by a 4-bit binary code. The seven-
segment display consists of seven LEDs arranged in the shape of an "8", with each LED
representing a segment (a, b, c, d, e, f, g). By activating specific combinations of these
segments, you can display numeric characters (0-9) and some letters (A).To convert BCD to
seven-segment display output, a decoder is typically used. The decoder takes the BCD input
and produces the appropriate signals to light up the segments corresponding to the input digit.
This can be achieved using various methods such as using logic gates, multiplexers, or
microcontroller-based solutions. Each BCD digit is decoded separately and then multiplexed
to display multiple digits simultaneously. For example, to display the BCD digit 7 on a
seven-segment display, you would need to activate segments a, b, and c, among others, based
on the mapping defined by the display's datasheet or design specifications. Overall, the
process involves decoding the BCD input into signals that control the individual segments of
the seven-segment display to represent the desired numbers or characters.

Using an FPGA (Field-Programmable Gate Array) to convert BCD to seven-segment display

involves designing a digital circuit that performs the BCD to seven-segment decoding and
driving the display using the FPGA's configurable logic blocks. By implementing the BCD to
seven-segment display conversion using an FPGA, you can achieve flexibility, efficiency,
and high-speed operation suitable for various applications.

11
LOGIC DIAGRAM:

BLOCK DESIGN:

12
PROCEDURE:

1. Click on vivado and click on New Project.

2. Give the name to the project.

3. Next-> create the file and give the filename.

4. Select the FPGA XC7A35tftg256-1-> next -> finish.

5. Select the module name under sources. we have create four modules.

6. Type the program and save it.

7. Click on Run Simulation and give the values by clicking force constant.

8. Go to file -> close simulation.

9, Go to -> IP INTEGRATOR-> Select -> create block design no changes need to do just
click on ok’.

10. Go to -> source drag the bin2bcd and seg_display to the left side and the connections as
shown. .

11. Set the remaining pins as make external by clicking on them and select the option.

12.Go to validate design then press ok.

13. Go to source -> Go to design which we have created click on it select the option Create
HDL Wrapper select it and make the design as the top by clicking the option set as top.

14.In project Manager go to open elaborated design under RIL analysis OK.

15. In the left side default layout -> IO planning.

16. Give the input and output keys as shown in the table.

17. Give the switch numbers to i/p’s under the column package pin.

18. Change the i/o stid to LVCMOS33.

19. Next Save the project with the project name.

20. Go to file -> close elaborated design.

21. Go to file -> open Synthesized design -> schemantic.

22. Take the Screenshot of Report power and Report utilization.

23. Next, go to Implementation after Completing the Implementation go to generate

bitstream.

13
SYNTHESIS RESULT:

14
24. With no settings Changed, the generate will create a ‘bit’ file which can be used to
program the board.

25. The first prompt will ask whether or not to run Synthesis click on Yes .

26. The first prompt before launching the runs gives several options. Leave everything as
default.

27. Finally the bitstream will be generated.

28. Select Hardware Manager, then click OK. Then Click on open target.

29. Next Click an auto Connect -> Click the program device after that Click on program to
Connect.

30. See the output in the FPGA.

PROGRAM:

module bcd_seven_segment (bcd, seg );

input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd)
begin
case (bcd) //case statement
0 :seg = 7'b0000001;
1 :seg = 7'b1001111;
2 :seg = 7'b0010010;
3 :seg = 7'b0000110;
4 :seg = 7'b1001100;
5 :seg = 7'b0100100;
6 :seg = 7'b0100000;
7 :seg = 7'b0001111;
8 :seg = 7'b0000000;
9:seg=7’b0000100;
default :seg = 7'b1111111;
endcase
end
endmodule
module bin2bcd( input [3:0] bin_in, output reg [3:0] tens,output reg [3:0] ones );
always @* begin
tens <= bin_in / 10;
ones <= bin_in % 10;
end

15
UTILIZATION REPORT:

POWER REPORT:

16
endmodule
module seg_display(input clk, input [3:0] digit_1, input [3:0] digit_2, output reg [7:0]
cathode,output reg [3:0] anode );
reg [17:0] count_next;
reg [17:0] count_reg=0;
always@(posedge clk)
count_reg <= count_next;
always@(*)
count_next = count_reg + 1;
always@(*)
begin
case(count_reg [17:16])
2'b00:
Begin
case(digit_1)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};

endcase
anode = 4'b1110;
end
2'b01:
begin
case(digit_2)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 'b1101;

17
SIMULATION RESULTS:

18
end
endcase
end
endmodule

TEST BENCH MODULE :

module bcd_seven_segment_tb;
reg [3:0] bcd;
wire [6:0] seg
bcd_seven_segment uut ( .bcd(bcd), .seg(seg));
initial
begin
bcd=4'b0011; #20
bcd=4'b0111;#20
bcd=4'b1001;#20
bcd=4'b0100;#20
bcd=4'b0111;
end
endmodule

CONSTRAINTS:

set_property IOSTANDARD LVCMOS33 [get_ports clk_0]

set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[0]}]
set_property PACKAGE_PIN N11 [get_ports clk_0]
set_property PACKAGE_PIN F2 [get_ports {anode_0[3]}]
set_property PACKAGE_PIN E1 [get_ports {anode_0[2]}]
set_property PACKAGE_PIN G5 [get_ports {anode_0[1]}]

19
HARDWARE IMPLEMENTATION:

20
set_property PACKAGE_PIN G4 [get_ports {anode_0[0]}]
set_property PACKAGE_PIN L5 [get_ports {bin_in_0[3]}]
set_property PACKAGE_PIN L4 [get_ports {bin_in_0[2]}]
set_property PACKAGE_PIN M4 [get_ports {bin_in_0[1]}]
set_property PACKAGE_PIN M2 [get_ports {bin_in_0[0]}]
set_property PACKAGE_PIN G2 [get_ports {cathode_0[7]}]
set_property PACKAGE_PIN G1 [get_ports {cathode_0[6]}]
set_property PACKAGE_PIN H5 [get_ports {cathode_0[5]}]
set_property PACKAGE_PIN H4 [get_ports {cathode_0[4]}]
set_property PACKAGE_PIN J5 [get_ports {cathode_0[3]}]
set_property PACKAGE_PIN J4 [get_ports {cathode_0[2]}]
set_property PACKAGE_PIN H2 [get_ports {cathode_0[1]}]
set_property PACKAGE_PIN H1 [get_ports {cathode_0[0]}]

RESULT:
The BCD to the seven-segment circuit is designed using Verilog HDL. Simulation and
FPGA implementation are performed using the Vivado tool. Functional verification of the
design is performed using a Verilog HDL test bench.

21
22
 3. BCD Adder
AIM: Design a 2-digit BCD adder and the result is displayed on an FPGA seven-segment
display.

TOOLS USED:

1. Vivado tool
2. Vivado Simulator
3. EDGE A7

THEORY:

A Binary-Coded Decimal (BCD) adder is a digital circuit used to perform addition

specifically on binary-coded decimal numbers. Binary-coded decimal is a binary
representation of decimal numbers where each decimal digit is represented by a fixed number
of binary digits. Typically, each decimal digit is represented by a four-bit binary code,
ranging from 0000 for 0 to 1001 for 9.

The BCD adder works similarly to a conventional binary adder but with modifications to
handle the BCD encoding. It consists of several stages, each capable of adding two BCD
digits along with a carry input from the previous stage. Here's a breakdown of how it works:

1. Input Stage: The BCD numbers to be added are fed into the BCD adder. Each BCD digit
is typically represented by four binary bits.

2. Binary Addition Stage: Internally, the BCD adder converts the BCD digits into their
binary equivalents and performs binary addition on them. This stage treats each digit
independently and adds them together along with any carry from the previous stage.

3. Correction Stage: After binary addition, the result might not necessarily be a valid BCD
digit. For example, if the sum of two BCD digits exceeds 9, it results in an invalid BCD
digit. The correction stage corrects such invalid digits by adjusting them to the
appropriate BCD representation. This involves checking if the sum is greater than 9
(1001 in binary) and adding 6 (0110 in binary) to the result. This correction ensures that
each digit remains in the range of 0 to 9.

4. Carry Propagation: If the sum of two BCD digits produces a carry, it is propagated to the
next higher-order BCD digit, just like in binary addition.

5. Output Stage: The corrected BCD digits are then combined to form the final BCD sum.

23
LOGIC DIAGRAM:

BLOCK DESIGN:

24
PROCEDURE:

1. Click on vivado and click on New Project.

2. Give the name to the project.

3. Next-> create the file and give the filename.

4. Select the FPGA XC7A35tftg256-1-> next -> finish.

5. Select the module name under sources. we have create four modules.

6. Type the program and save it.

7. Click on Run Simulation and give the values by clicking force constant.

8. Go to file -> close simulation.

9, Go to -> IP INTEGRATOR-> Select -> create block design no changes need to do just
click on ok.

10. Go to -> source drag the bcd_adder and seg_display to the left side and the connections as
shown.

11. Set the remaining pins as make external by clicking on them and select the option.

12.Go to validate design then press ok.

13. Go to source -> Go to design which we have created click on it select the option Create
HDL Wrapper select it and make the design as the top by clicking the option set as top.

14.In project Manager go to open elaborated design under RTL analysis OK.

15. In the left side default layout -> IO planning.

16. Give the input and output keys as shown in the table.

17. Give the switch numbers to i/p’s under the column package pin.

18. Change the i/o stid to LVCMOS33.

19. Next Save the project with the project name.

20. Go to file -> close elaborated design.

21. Go to file -> open Synthesized design -> schematic.

22. Take the Screenshot of Report power and Report utilization.

23. Next, go to Implementation after Completing the Implementation go to generate

bitstream.

25
SYNTHESIS RESULTS:

26
24. With no settings Changed, the generate will create a ‘bit’ file which can be used to
program the board.

25. The first prompt will ask whether or not to run Synthesis click on Yes .

26. The first prompt before launching the runs gives several options. Leave everything as
default.

27. Finally the bitstream will be generated.

28. Select Hardware Manager, then click OK. Then Click on open target.

29. Next Click an auto Connect -> Click the program device after that Click on program to
Connect.

30. See the output in the FPGA.

PROGRAM:
module bcd_adder (a, b, carry_in, sum, carry);
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output [3:0] carry;
reg [4:0] sum_temp;
reg [3:0] sum;
reg [3:0] carry;
always @ (a, b, carry_in)
begin
sum_temp = a+b+carry_in;
if(sum_temp> 9) begin
sum_temp = sum_temp+6;.
carry = 1;
sum = sum_temp[3:0]; end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule

module seg_display(
input clk,
input [3:0] digit_1,
input [3:0] digit_2,
output reg [7:0] cathode,
output reg [3:0] anode );

27
UTILIZATION REPORT:

POWER REPORT:

28
reg [17:0] count_next;
reg [17:0] count_reg=0;
always@(posedge clk)
count_reg <= count_next;
always@(*)
count_next = count_reg + 1;
always@(*)
begin
case(count_reg [17:16])
2'b00:
begin
case(digit_1)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 4'b1110;
end
2'b01:
begin
case(digit_2)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 4'b1101;
end
endcase
end
endmodule

29
SIMULATION RESULT:

30
TEST BENCH MODULE:
module bcd_adder_tb;
reg [3:0] a; reg [3:0] b; reg carry_in;
wire [3:0] sum; wire [3:0] carry;
bcd_adder uut ( .a(a), .b(b), .carry_in(carry_in), .sum(sum), .carry(carry));
initial begin
a = 0; b = 0; carry_in = 0; #100;
a = 6; b = 9; carry_in = 0; #100;
a = 3; b = 3; carry_in = 1; #100;
a = 4; b = 5; carry_in = 0; #100;
a = 8; b = 2; carry_in = 0; #100;
a = 9; b = 9; carry_in = 1; #100;
end
endmodule

CONSTRAINTS:
set_property IOSTANDARD LVCMOS33 [get_ports clk_0]
set_property PACKAGE_PIN N11 [get_ports clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports {a_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[0]}]
set_property PACKAGE_PIN F2 [get_ports {anode_0[3]}]
set_property PACKAGE_PIN E1 [get_ports {anode_0[2]}]
set_property PACKAGE_PIN G5 [get_ports {anode_0[1]}]
set_property PACKAGE_PIN G4 [get_ports {anode_0[0]}]
set_property PACKAGE_PIN G2 [get_ports {cathode_0[7]}]
set_property PACKAGE_PIN G1 [get_ports {cathode_0[6]}]
set_property PACKAGE_PIN H5 [get_ports {cathode_0[5]}]

31
HARDWARE IMPLEMENTATION:

32
set_property PACKAGE_PIN H4 [get_ports {cathode_0[4]}]
set_property PACKAGE_PIN J5 [get_ports {cathode_0[3]}]
set_property PACKAGE_PIN J4 [get_ports {cathode_0[2]}]
set_property PACKAGE_PIN H2 [get_ports {cathode_0[1]}]
set_property PACKAGE_PIN H1 [get_ports {cathode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports carry_in_0]
set_property PACKAGE_PIN L4 [get_ports {a_0[1]}]
set_property PACKAGE_PIN L5 [get_ports {a_0[0]}]
set_property PACKAGE_PIN N2 [get_ports {b_0[2]}]
set_property PACKAGE_PIN N3 [get_ports {b_0[1]}]
set_property PACKAGE_PIN M1 [get_ports {b_0[0]}]
set_property PACKAGE_PIN M4 [get_ports {a_0[2]}]
set_property PACKAGE_PIN M2 [get_ports {a_0[3]}]
set_property PACKAGE_PIN N1 [get_ports {b_0[3]}]
set_property PACKAGE_PIN P1 [get_ports carry_in_0]

RESULT:
The BCD adder is designed using Verilog HDL, Simulation and FPGA
implementation is performed using Vivado. Functional verification of the design is performed
using a Verilog HDL test bench.

33
34
 4. Array Multiplier
AIM: Design 4 × 4 Array Multiplier and the result is displayed it on FPGA seven-segment
display.
TOOLS USED:
Vivado Tool
Vivado Simulator
NEXYS4 DDR
THEORY:
An array multiplier is a digital circuit used to perform the multiplication of two binary
numbers. It operates on the principle of parallelism, where multiple bits of the multiplicand
and multiplier are processed simultaneously. This results in faster multiplication compared to
sequential methods like shift-and-add multiplication. The theory behind array multipliers can
be summarized as follows:
1. Binary Multiplication: At its core, array multiplication is based on the elementary
operation of binary multiplication. This operation involves multiplying each digit of the
multiplicand by each digit of the multiplier and adding up the results. The sum of these
partial products gives the final product.
2. Partial Products: In array multiplication, the partial products are generated by multiplying
each bit of the multiplicand with each bit of the multiplier. For an n-bit multiplicand and an
m-bit multiplier, this results in n × m partial products.
3. Array Structure: The array multiplier architecture consists of rows and columns of binary
multipliers. Each row represents a bit position of the multiplier, and each column represents a
bit position of the multiplicand. The intersection of each row and column represents the
multiplication of the corresponding bits.
4. Parallel Processing: One of the key advantages of array multipliers is their ability to
perform parallel processing. Since each partial product is independent of the others, they can
be computed concurrently, leading to significant speedup compared to sequential methods.
5. Addition of Partial Products: After generating the partial products, they are added together
to obtain the final result. This addition is typically carried out using a combination of full
adders and carry lookahead adders to minimize propagation delay and improve performance.
6. Overflow Handling: In binary multiplication, overflow can occur if the result exceeds the
maximum representable value. Overflow detection and handling mechanisms may be
included in the array multiplier design to ensure accurate results.

35
LOGIC DIAGRAM:

BLOCK DIAGRAM:

36
PROCEDURE:
1. Click on vivado and click on New Project.
2. Give the name to the project.
3. Next-> create the file and give the filename.
4. Select the FPGA XC7A35tftg256-1-> next -> finish.
5. Select the module name under sources. we have create four modules.
6. Type the program and save it.
7. Click on Run Simulation and give the values by clicking force constant.
8. Go to file -> close simulation.
9, Go to -> IP INTEGRATOR-> Select -> create block design no changes need to do just
click on ok.
10. Go to -> source and drag the multiplier and seg_display to the left side and the
connections as shown.
11. Set the remaining pins as make external by clicking on them and selecting the option.
12. Go to validate design then press ok.
13. Go to source -> Go to design which we have created click on it select the option Create
HDL Wrapper select it and make the design as the top by clicking the option set as top.
14. In project Manager go to open elaborated design under RTL analysis OK.
15. In the left side default layout -> IO planning.
16. Give the input and output keys as shown in the table.
17. Give the switch numbers to i/p’s under the column package pin.
18. Change the i/o stid to LVCMOS33.
19. Next Save the project with the project name.
20. Go to file -> close elaborated design.
21. Go to file -> open Synthesized design -> schematic.
22. Take the Screenshot of Report power and Report utilization.
23. Next, go to Implementation after Completing the Implementation go to generate
bitstream.
24. With no settings Changed, the generate will create a ‘bit’ file which can be used to
program the board.
25. The first prompt will ask whether or not to run Synthesis click on Yes.
26. The first prompt before launching the runs gives several options. Leave everything as
default.
27. Finally the bitstream will be generated.
28. Select Hardware Manager, then click OK. Then Click on open target.
29. Next Click an auto Connect -> Click the program device after that Click on program to
Connect.
30. See the output in the FPGA.

37
SYNTHESIS RESLUTS:

38
PROGRAM:
module multiplier (product, inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule

module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule

module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

module bin2bcd(
input [7:0] bin_in,
output reg [3:0] ones,
output reg [3:0] tens,
output reg [3:0] hundreds
);
always @(*)
begin
ones <= bin_in % 10;
tens <= (bin_in / 10) % 10;
hundreds <= bin_in / 100;
end
endmodule

39
UTILIZATION REPORT:

POWER REPORT:

40
module seg_display(
input clk,
input [3:0] digit_1,
input [3:0] digit_2,
input [3:0] digit_3,
output reg [7:0] cathode,
output reg [7:0] anode
);

reg [17:0] count_next;

reg [17:0] count_reg=0;
always@(posedge clk)
count_reg <= count_next;

always@(*)
count_next = count_reg + 1;

always@(*)
begin
case(count_reg[17:16])
2'b00:
begin
case(digit_1)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 8'b11111110;
end
2'b01:
begin
case(digit_2)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};

41
SIMULATION RESULT:

42
 endcase
anode = 8'b11111101;
end
2'b10:
begin
case(digit_3)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};

endcase
anode = 8'b11111011;
end
default:
begin
anode = 8'b11111111;
end
endcase
end
endmodule

TEST BENCH MODULE:

module multiplier_tb;
reg [3:0]inp1;
reg [3:0]inp2;
wire [7:0]product;
multiplier uut(.inp1(inp1),.inp2(inp2),.product(product));
initial
begin
inp1=3; inp2=5; #30;
inp1=13; inp2=10; #30;
inp1=10; inp2=22; #30;
inp1=10; inp2=22; #30;
inp1=8; inp2=9; #30;
$finish;
end
endmodule

43
FPGA IMPLEMENTATION:

44
CONSTRAINTS:
set_property PACKAGE_PIN N11[get_ports clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports clk_0]
set_property PACKAGE_PIN L5 [get_ports {inp1_0[0]}]
set_property PACKAGE_PIN L4[get_ports {inp1_0[1]}]
set_property PACKAGE_PIN M4 [get_ports {inp1_0[2]}]
set_property PACKAGE_PIN M2 [get_ports {inp1_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp1_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp1_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp1_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp1_0[0]}]
set_property PACKAGE_PIN M1 [get_ports {inp2_0[0]}]
set_property PACKAGE_PIN N3 [get_ports {inp2_0[1]}]
set_property PACKAGE_PIN N2 [get_ports {inp2_0[2]}]
set_property PACKAGE_PIN N1 [get_ports {inp2_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp2_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp2_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp2_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {inp2_0[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[0]}]
set_property PACKAGE_PIN F2 [get_ports {anode_0[3]}]
set_property PACKAGE_PIN E1 [get_ports {anode_0[2]}]
set_property PACKAGE_PIN G5 [get_ports {anode_0[1]}]
set_property PACKAGE_PIN G4 [get_ports {anode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[0]}]
set_property PACKAGE_PIN G2 [get_ports {cathode_0[7]}]
set_property PACKAGE_PIN G1 [get_ports {cathode_0[6]}]
set_property PACKAGE_PIN H5 [get_ports {cathode_0[5]}]
set_property PACKAGE_PIN H4 [get_ports {cathode_0[4]}]
set_property PACKAGE_PIN J5 [get_ports {cathode_0[3]}]
set_property PACKAGE_PIN J4 [get_ports {cathode_0[2]}]
set_property PACKAGE_PIN H2 [get_ports {cathode_0[1]}]
set_property PACKAGE_PIN H1 [get_ports {cathode_0[0]}]

RESULT: The array multiplier is designed using Verilog HDL. Simulation and FPGA
implementation is performed using the Vivado tool. Functional verification of the design is
performed using a Verilog HDL test bench.

45
46
 5. 8-bit RAM and ROM
AIM: To design 8-bit RAM and ROM using Verilog HDL
TOOLS USED:

Vivado Tool
Vivado Simulator
EDGE A7
THEORY:
8-bit RAM:
• Random Access Memory (RAM) is a type of volatile memory used for temporary
storage of data that the CPU needs to access quickly.
• 8-bit RAM means that each memory location in the RAM can store 8 bits of data.
• RAM is typically used for storing variables, program instructions, and intermediate
computation results during program execution.
• In FPGA implementation, RAM can be implemented using registers, flip-flops, or
dedicated RAM blocks available in the FPGA architecture.
• The FPGA design for 8-bit RAM includes address lines for selecting memory
locations, data lines for reading/writing data, control signals for read/write operations,
and a clock signal for synchronization.
• RAM can be organized as a single-port or dual-port depending on the number of
simultaneous read/write operations supported.
• FPGA allows for flexibility in designing RAM with custom features such as byte
enable signals, asynchronous/synchronous read/write operations, and different
memory capacities.
8-bit ROM:
• Read-Only Memory (ROM) is a type of non-volatile memory that stores data or
instructions permanently and is typically used for storing firmware or fixed data.
• 8-bit ROM means that each memory location in the ROM can store 8 bits of fixed
data that cannot be altered during runtime.
• ROM contents are programmed during FPGA configuration and remain unchanged
during normal operation.
• FPGA implementation of 8-bit ROM involves storing the fixed data in memory cells
or lookup tables within the FPGA fabric.
• The data stored in ROM can be accessed by specifying the memory address, and the
output is the data stored at that address.
• Unlike RAM, ROM does not require write control signals as its content is read-only.
• FPGA-based ROM can be used for storing constants, character tables, precomputed
values, or any data that doesn't change during program execution.

47
CIRCUIT DIAGRAM:
RAM:

ROM:

48
PROCEDURE:

1. Click on vivado and click on New Project.

2. Give the name to the project.
3. Next-> create the file and give the filename.
4. Select the FPGA XC7A35tftG256-1-> next -> finish.
5. Select the module name under sources.
6. Type the program and save it.
7. Click on Run Simulation and give the values by clicking force constant.
8. Go to file -> close simulation.
9. In project Manager go to open elaborated design under RIL analysis OK.
10. In the left side default layout -> IO planning.
11. Give the input and output keys in the scalar ports.
12. Give the switch numbers to i/p’s under the column package pin.
13. Change the i/o stid to LVCMOS33.
14. Next Save the project with the project name.
15. Go to file -> close elaborated design.
16. Go to file -> open Synthesized design -> schemantic.
17. Take the Screenshot of Report power and Report utilization.
18. Next, go to Implementation after Completing the Implementation go to generate
bitstream.
19. With no settings Changed, the generate will create a ‘bit’ file which can be used to
program the board.
20. The first prompt will ask whether or not to run Synthesis click on Yes.
21. The first prompt before launching the runs gives several options. Leave everything as
default.
22. Finally the bitstream will be generated.
23. Select Hardware Manager, then click OK. Then Click on open target.
24. Next Click an auto Connect -> Click the program device after that Click on program to
Connect.
25. See the output in the FPGA.

49
SIMULATION RESULTS:
8-bit RAM:

8-bit ROM:

50
8-bit RAM
PROGRAM:
module ram8bit(
input [7:0] data,
input [5:0] addr,
input we,
input clk,
output [7:0] q );
reg [7:0] ram [63:0];
reg [5:0] addr_reg;
always @ (posedge clk)
begin
if(we)
ram [addr] <= data;
else
addr_reg<= addr;
end
assign q=ram [addr_reg];
endmodule

TEST BENCH:
module ram8bit_tb;
reg [7:0] data;
reg [5:0] addr;
reg we;
regclk;
wire [7:0] q;
ram8bit u1(.data (data), .addr (addr), .we (we), .clk (clk), .q(q));
initial
begin
clk=1'b1;
data =8'h01;
addr = 5'd0;
we = 1'b1; # 10
data = 8'h02;
addr = 5'd1; # 10
data = 8'h03;
addr= 5'd2; #10
addr = 5'd0;
we = 1'b0; # 10
addr = 5'd1; # 10
addr = 5'd2; # 10
data =8'h04;
addr = 5'd1;
we = 1'b1;
end
always #5 clk = ~clk;
endmodule

51
SYNTHESIS RESULT:
8-bit RAM:

8bit ROM:

52
CONSTRAINTS:

set_property IOSTANDARD LVCMOS33 [get_ports {addr[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {addr[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {addr[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {addr[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {addr[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {addr[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {q[0]}]
set_property PACKAGE_PIN N11 [get_ports clk]
set_property PACKAGE_PIN L5 [get_ports {addr[0]}]
set_property PACKAGE_PIN L4 [get_ports {addr[1]}]
set_property PACKAGE_PIN M4 [get_ports {addr[2]}]
set_property PACKAGE_PIN M2[get_ports {addr[3]}]
set_property PACKAGE_PIN M1 [get_ports {addr[4]}]
set_property PACKAGE_PIN N3 [get_ports {addr[5]}]
set_property PACKAGE_PIN N2 [get_ports {data[0]}]
set_property PACKAGE_PIN N1 [get_ports {data[1]}]
set_property PACKAGE_PIN P1 [get_ports {data[2]}]
set_property PACKAGE_PIN P4 [get_ports {data[3]}]
set_property PACKAGE_PIN T8 [get_ports {data[4]}]
set_property PACKAGE_PIN R8 [get_ports {data[5]}]
set_property PACKAGE_PIN N6 [get_ports {data[6]}]
set_property PACKAGE_PIN T7 [get_ports {data[7]}]
set_property PACKAGE_PIN J3 [get_ports {q[0]}]
set_property PACKAGE_PIN H3 [get_ports {q[1]}]
set_property PACKAGE_PIN J1 [get_ports {q[2]}]
set_property PACKAGE_PIN K1 [get_ports {q[3]}]
set_property PACKAGE_PIN L3 [get_ports {q[4]}]
set_property PACKAGE_PIN L2 [get_ports {q[5]}]
set_property PACKAGE_PIN K3 [get_ports {q[6]}]
set_property PACKAGE_PIN K2 [get_ports {q[7]}]
set_property PACKAGE_PIN P8 [get_ports we]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports we]

53
8-bit RAM:
POWER REPORT:

UTILIZATION REPORT:

8-bit ROM
POWER REPORT:

54
8-bit ROM

PROGRAM:

module ROM (input clk, input en, input [3:0] addr, output reg [3:0] data);
reg [3:0] mem [15:0];
always @ (posedge clk)
begin
if (en)
data<= mem [addr];
else
data<= 4'bxxxx;
end
initial
begin
mem [0] =4'b0010;
mem [1]= 4'b0010;
mem[2] =4'b1110;
mem [3]=4'b0010;
mem[4]= 4'b0100;
mem[5] = 4'b1010;
mem [6] = 4'b1100;
mem [7] = 4'b0000;
mem [8] = 4'b1010;
mem [9] = 4'b0010;
mem[10] = 4'b1110;
mem [11] =4'b0010;
mem [12] = 4'b0100;
mem[13]= 4'b1010;
mem [14] = 4'b1100;
mem [15]= 4'b0000;
end
endmodule

TEST BENCH:
module ROM_tb;
regclk;
reg en;
reg [3:0] addr;
wire [3:0] data;
ROM r1(.clk (clk),.en (en),.addr (addr),.data(data));
initial
begin
clk =1'b1;
forever #5 clk = ~clk;
end
initial
begin
en =1'b0; # 10;

55
UTILIZATION REPORT:

HARDWARE IMPLEMENTATION:

8-bit RAM

8-bit ROM

56
en = 1'b1;
addr = 4'b1010; # 10;
addr= 4'b0110; # 10;
addr= 4'b0011; # 10;
en = 1'b0;
addr = 4'b1111; # 10;
en =1'b1;
addr =4'b1000;
end
endmodule

CONSTRAINTS:

set_property IOSTANDARD LVCMOS33 [get_ports {addr[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {addr[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {addr[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {addr[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data[0]}]
set_property PACKAGE_PIN L5 [get_ports {addr[0]}]
set_property PACKAGE_PIN L4 [get_ports {addr[1]}]
set_property PACKAGE_PIN M4 [get_ports {addr[2]}]
set_property PACKAGE_PIN M2 [get_ports {addr[3]}]
set_property PACKAGE_PIN J3 [get_ports {data[0]}]
set_property PACKAGE_PIN H3[get_ports {data[1]}]
set_property PACKAGE_PIN J1 [get_ports {data[2]}]
set_property PACKAGE_PIN K1 [get_ports {data[3]}]
set_property PACKAGE_PIN N11 [get_ports clk]
set_property PACKAGE_PIN M1 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports en]

RESULT: The 8-bit RAM and ROM are designed using Verilog HDL. Simulation and FPGA
implementation is performed using Vivado tool. Functional verification of the design is
performed using a Verilog HDL test bench.

57
58
 6. Fibonacci Series
AIM: To design and verify Fibonacci Sequence Generator on FPGA.
TOOLS USED:
Vivado tool
Vivado Simulator
NEXYS4 DDR

THEORY:
The Fibonacci series is a sequence of numbers where each number is the sum of the two
preceding ones, usually starting with 0 and 1. The series begins as follows: 0, 1, 1, 2, 3, 5, 8,
13, 21, and so on. The sequence is named after Leonardo of Pisa, also known as Fibonacci, an
Italian mathematician who introduced it to the Western world in his book "Liber Abaci" in
1202.
The general formula to generate Fibonacci numbers is F(n)=F(n−1)+F(n−2), where F(n)
represents the nth Fibonacci number. The first two numbers in the sequence, F(0) and F(1),
are defined as 0 and 1, respectively.
Applications of Fibonacci Series:
1. Mathematics: The Fibonacci sequence appears in various mathematical problems and
concepts, such as number theory, combinatorics, and linear algebra. It also has
connections to other mathematical sequences and series.
2. Computer Science: Fibonacci numbers are used in algorithms and programming,
especially in dynamic programming, recursion, and optimizing code. They are also
applied in data structures like Fibonacci heaps.
3. Finance: The Fibonacci sequence is sometimes used in financial analysis, particularly
in technical analysis of stock market trends and price movements. Traders and
analysts may use Fibonacci retracement levels to predict potential support and
resistance levels.

59
DIAGRAM:

BLOCK DIAGRAM:

60
PROCEDURE:
1. Click on vivado and click on New Project.
2. Give the name to the project.
3. Next-> create the file and give the filename.
4. Select the FPGA XC7A35tftg256-1-> next -> finish.
5. Select the module name under sources. we have create four modules.
6. Type the program and save it.
7. Click on Run Simulation and give the values by clicking force constant.
8. Go to file -> close simulation.
9, Go to -> IP INTEGRATOR-> Select -> create block design no changes need to do just
click on ok.
10. Go to -> source and drag the Fibonacci and seg_display to the left side and the
connections as shown.
11. Set the remaining pins as make external by clicking on them and selecting the option.
12. Go to validate design then press ok.
13. Go to source -> Go to design which we have created click on it select the option Create
HDL Wrapper select it and make the design as the top by clicking the option set as top.
14. In project Manager go to open elaborated design under RTL analysis OK.
15. In the left side default layout -> IO planning.
16. Give the input and output keys as shown in the table.
17. Give the switch numbers to i/p’s under the column package pin.
18. Change the i/o stid to LVCMOS33.
19. Next Save the project with the project name.
20. Go to file -> close elaborated design.
21. Go to file -> open Synthesized design -> schematic.
22. Take the Screenshot of Report power and Report utilization.
23. Next, go to Implementation after Completing the Implementation go to generate
bitstream.
24. With no settings Changed, the generate will create a ‘bit’ file which can be used to
program the board.
25. The first prompt will ask whether or not to run Synthesis click on Yes.
26. The first prompt before launching the runs gives several options. Leave everything as
default.
27. Finally the bitstream will be generated.
28. Select Hardware Manager, then click OK. Then Click on open target.
29. Next Click an auto Connect -> Click the program device after that Click on program to
Connect.
30. See the output in the FPGA.

61
SIMULATION RESULTS:

62
PROGRAM:
module Fibonacci (input clk, rst, output [3:0] RegA, RegB, RegC);
// Registers to store the current and previous values of the fibonacci counter
reg [3:0] RegA, RegB, RegC;
always @ (posedge clk) begin
if (rst) begin
RegA<= 4'h1; // Start RegA with the second value of fibonacci series - '1'
RegB<= 4'h0; // Start RegB with the first value of fibonacci series - '0'
RegC<= 4'h0; // Reset RegC to '0'
end
else begin
RegA<= RegB [3] ? 4'h1 :RegA + RegB; // if RegB == 8, reset RegA
RegB<= RegB[3] ? 4'h0 :RegA; // if RegB == 8, reset RegB
RegC<= RegB; // RegC is a synchronization register
end
end
endmodule

module seg_display(
input clk,
input [3:0] digit_1,
input [3:0] digit_2,
input [3:0] digit_3,
output reg [7:0] cathode,
output reg [7:0] anode);
reg [17:0] count_next;
reg [17:0] count_reg=0;
always@(posedge clk)
count_reg <= count_next;
always@(*)
count_next = count_reg + 1;
always@(*)
begin
case(count_reg[17:16])
2'b00:
begin
case(digit_1)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};

63
SYNTHESIS RESULTS:

64
 4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 8'b11111110;
end
2'b01:
begin
case(digit_2)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 8'b11111101;
end
2'b10:
begin
case(digit_3)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 8'b11111011;
end
default:
begin
anode = 8'b11111111;
end
endcase
end
endmodule

65
POWER REPORT:

UTILIZATION REPORT:

66
TEST BENCH:
module Fibonacci_tb ();
reg clk, en, rst;
wire [3:0] out;
Fibonacci u0 (clk, rst, out);
always #1 clk = ~clk;
initial
begin
$monitor ("En = %b, Out = %d", en, out);
clk = 0; rst = 1; en = 0;
#2 rst = 0; en = 0;
#2 en = 1;
#30 en = 0;
#2 en = 1;
#40 $stop;
end
endmodule

CONSTRAINTS:
set_property IOSTANDARD LVCMOS33 [get_ports clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports clk_1]
set_property IOSTANDARD LVCMOS33 [get_ports rst_0]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[0]}]
set_property PACKAGE_PIN E3 [get_ports clk_0]
set_property PACKAGE_PIN L16 [get_ports clk_1]
set_property PACKAGE_PIN J15 [get_ports rst_0]
set_property PACKAGE_PIN U13 [get_ports {anode_0[7]}]
set_property PACKAGE_PIN K2 [get_ports {anode_0[6]}]
set_property PACKAGE_PIN T14 [get_ports {anode_0[5]}]

67
HARDWARE IMPLEMENTATION:

68
set_property PACKAGE_PIN P14 [get_ports {anode_0[4]}]
set_property PACKAGE_PIN J14 [get_ports {anode_0[3]}]
set_property PACKAGE_PIN T9 [get_ports {anode_0[2]}]
set_property PACKAGE_PIN J18 [get_ports {anode_0[1]}]
set_property PACKAGE_PIN J17 [get_ports {anode_0[0]}]
set_property PACKAGE_PIN T10 [get_ports {cathode_0[7]}]
set_property PACKAGE_PIN R10 [get_ports {cathode_0[6]}]
set_property PACKAGE_PIN K16 [get_ports {cathode_0[5]}]
set_property PACKAGE_PIN K13 [get_ports {cathode_0[4]}]
set_property PACKAGE_PIN P15 [get_ports {cathode_0[3]}]
set_property PACKAGE_PIN T11 [get_ports {cathode_0[2]}]
set_property PACKAGE_PIN L18 [get_ports {cathode_0[1]}]
set_property PACKAGE_PIN H15 [get_ports {cathode_0[0]}]

RESULT: The Fibonacci Sequence Generator is designed using Verilog HDL. Simulation
and FPGA implementation is performed using the Vivado tool. Functional verification of the
design is performed using a Verilog HDL test bench.

69