8051-Microcontroller-18EC46 4 Sem ECE

MODULE - 1
1.1 MICROPROCESSORS V/S MICROCONTROLLERS
Microprocessor Microcontroller

Arithmetic and logic

ALU Timer/ IO Ports
unit
Counter
Accumulator
Accumulator Interrupt
Registers
Internal Circuits
Working Registers
Internal RAM ROM
Program Counter Stack Pointer Stack Pointer Clock

Clock Circuit Interrupt circuit Program Counter

Block diagram of microprocessor Block diagram of microcontroller

Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of

registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc.

It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU

Few bit handling instruction It has many bit handling instructions

Less number of pins are multifunctional More number of pins are multifunctional

Single memory map for data and code Separate memory map for data and code
(program) (program)

Access time for memory and IO are more Less access time for built in memory and IO.

Microprocessor based system requires It requires less additional hardwares

additional hardware

More flexible in the design point of view Less flexible since the additional circuits which is
residing inside the microcontroller is fixed for a
particular microcontroller

Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes

4
8051-Microcontroller-18EC46 4 Sem ECE

1.2. RISC AND CISC CPU ARCHITECTURES

Microcontrollers with small instruction set are called reduced instruction set computer (RISC)
machines and those with complex instruction set are called complex instruction set computer
(CISC). Intel 8051 is an example of CISC machine whereas microchip PIC 18F87X is an example of
RISC machine.

RISC CISC

Instruction takes one or two cycles Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions,
memory memory access is possible with other
instructions also.

Instructions executed by hardware Instructions executed by the micro program

Fixed format instruction Variable format instructions

Few addressing modes Many addressing modes

Few instructions Complex instruction set

Most of the have multiple register banks Single register bank

Highly pipelined Less pipelined

Complexity is in the compiler Complexity in the microprogram

5
8051-Microcontroller-18EC46 4 Sem ECE

1.2. HARVARD & VON- NEUMANN CPU ARCHITECTURE

Von-Neumann (Princeton architecture) Harvard architecture

Program Data Data

Data
Memory Memory
CPU CPU Address Bus

Data Program
Data
Memory Memory
Address Bus
Address Bus

Von-Neumann (Princeton architecture) Harvard architecture

It uses single memory space for both It has separate program memory and data
instructions and data. memory

It is not possible to fetch instruction code and Instruction code and data can be fetched
data simultaneously

Execution of instruction takes more machine Execution of instruction takes less machine
cycle cycle

Uses CISC architecture Uses RISC architecture

Instruction pre-fetching is a main feature Instruction parallelism is a main feature

Also known as control flow or control driven Also known as data flow or data driven
computers computers

Simplifies the chip design because of single Chip design is complex due to separate memory
memory space space

Eg. 8085, 8086, MC6800 Eg. General purpose microcontrollers, special

DSP chips etc.

6
8051-Microcontroller-18EC46 4 Sem ECE

1.3 COMPUTER SOFTWARE

A set of instructions written in a specific sequence for the computer to solve a specific task is called
a program and software is a collection of such programs.

The program stored in the computer memory in the form of binary numbers is called machine
instructions. The machine language program is called object code.

An assembly language is a mnemonic representation of machine language. Machine language and

assembly language are low level languages and are processor specific.

The assembly language program the programmer enters is called source code. The source code
(assembly language) is translated to object code (machine language) using assembler.

Programs can be written in high level languages such as C, C++ etc. High level language will be
converted to machine language using compiler or interpreter. Compiler reads the entire program
and translate into the object code and then it is executed by the processor. Interpreter takes one
statement of the high level language as input and translate it into object code and then executes.

1.4 THE 8051 ARCHITECTURE

Introduction

Salient features of 8051 microcontroller are given below.

 Eight bit CPU
 On chip clock oscillator
 4Kbytes of internal program memory (code memory) [ROM]
 128 bytes of internal data memory [RAM]
 64 Kbytes of external program memory address space.
 64 Kbytes of external data memory address space.
 32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O
lines)
 Two 16 Bit Timer/Counter :T0, T1
 Full Duplex serial data receiver/transmitter
 Four Register banks with 8 registers in each bank.
 Sixteen bit Program counter (PC) and a data pointer (DPTR)
 8 Bit Program Status Word (PSW)
 8 Bit Stack Pointer
 Five vector interrupt structure (RESET not considered as an interrupt.)
 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register,
PSW, SP, 16 bit program counter, stack pointer.
 ALU can perform arithmetic and logic functions on 8 bit variables.
 8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]

7
8051-Microcontroller-18EC46 4 Sem ECE

The 8051 architecture.

I/O
A0-A7
ALU PSW Port 0
SFR D0-D7

General
A B Purpose I/O
RAM Port 1

I/O
A8-
Port 2 A15

ROM
DPTR
PC
DPH I/O
INT
DPL
Port 3 CNTR
SERIAL
RD/WR

E IE
ALE System General IP
Timing purpose PCON
PSEN
area SBUF
XTAL1 System SCON
interrupt
XTAL2 Bit addressible TCON
timers area TMOD
RESET Register Bank 3 TL0
Data
buffers Register Bank 2 TH0
Register Bank 1 TL1
Memory
Register Bank 0 TH1
VCC
GND control SFR and
General Purpose RAM

 8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the
program size is more than 4 K Bytes 8051 will fetch the code automatically from external
memory.
 Accumulator is an 8 bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory. B register is used along
with Accumulator for multiplication and division. A and B registers together is also called
MATH registers.

8
8051-Microcontroller-18EC46 4 Sem ECE

 PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of
ALU and the bank select bits of register banks.
CY AC F0 RS1 RS0 OV - P
CY - carry flag
AC - auxiliary carry flag
F0 - available to the user for general purpose
RS1,RS0 - register bank select bits
OV - overflow
P - parity
 Stack Pointer (SP) – it contains the address of the data item on the top of the stack. Stack
may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default
stack will start from address 08 onwards.
 Data Pointer (DPTR) – DPH (Data pointer higher byte), DPL (Data pointer lower byte). This
is a 16 bit register which is used to furnish address information for internal and external
program memory and for external data memory.
 Program Counter (PC) – 16 bit PC contains the address of next instruction to be executed.
On reset PC will set to 0000. After fetching every instruction PC will increment by one.

1.5 PIN DIAGRAM

Pinout Description
Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output.
Pin 9 RESET. A logic one on this pin disables the microcontroller and clears the contents of
most registers. In other words, the positive voltage on this pin resets the
microcontroller. By applying logic zero to this pin, the program starts execution from
the beginning.
Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions

9
8051-Microcontroller-18EC46 4 Sem ECE

Pin 10 RXD. Serial asynchronous communication input or Serial synchronous communication

output.
Pin 11 TXD. Serial asynchronous communication output or Serial synchronous
communication clock output.
Pin 12 INT0.External Interrupt 0 input
Pin 13 INT1. External Interrupt 1 input
Pin 14 T0. Counter 0 clock input
Pin 15 T1. Counter 1 clock input
Pin 16 WR. Write to external (additional) RAM
Pin 17 RD. Read from external RAM
Pin 18, 19 XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins.
Pin 20 GND. Ground.
Pin 21-28 Port 2. If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher
address byte, i.e. addresses A8-A15 will appear on this port. Even though memory
with capacity of 64Kb is not used, which means that not all eight port bits are used for
its addressing, the rest of them are not available as inputs/outputs.
Pin 29 PSEN. If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.
Pin 30 ALE. Prior to reading from external memory, the microcontroller puts the lower
address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from
the ALE pin, the external latch latches the state of P0 and uses it as a memory chip
address. Immediately after that, the ALE pin is returned its previous logic state and P0
is now used as a Data Bus.
Pin 31 EA. By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that
even there is a program written to the microcontroller, it will not be executed. Instead,
the program written to external ROM will be executed. By applying logic one to the EA
pin, the microcontroller will use both memories, first internal then external (if exists).
Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when
the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven
low (0).
Pin 40 VCC. +5V power supply.

10
8051-Microcontroller-18EC46 4 Sem ECE

1.6 MEMORY ORGANIZATION

Internal RAM organization
R7 1F
R6 1E
R5 1D

BANK 3
R4 1C 2F
7F 78 7F
R3 1B
2E
77 70 7E
R2 1A
R1 19 2D
6F 68 .
R0 18 2C
67 60 .
R7 17
2B
5F 58 .
R6 16
R5 15
57 50 .
BANK 2

2A
R4 14 29
4F 48 .
R3 13
28
47 40 .
R2 12
R1 11 27
3F 38 .
R0 10 26
37 30 .
R7 0F 2F 28
R6 0E 25 32
27 20
R5 0D 24 31
BANK 1

R4 0C 1F 18
R3 0B
23 30
17 10
R2 0A 22

R1 09 21 0F 08
R0 08
R7 07
20 07 00 General purpose memory
R6 06
R5 05
BANK 0

R4 04 Bit addressable memory

R3 03
R2 02
R1 01
R0 00

Working Registers

Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1,
R2, R3, R4, R5, R6, and R7). There are four such register banks. Selection of register bank can be
done through RS1,RS0 bits of PSW. On reset, the default Register Bank 0 will be selected.

Bit Addressable RAM: 20h to 2Fh . The 8051 supports a special feature which allows access to bit
variables. This is where individual memory bits in Internal RAM can be set or cleared. In all there
are 128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0 or 1. A bit
variable can be set with a command such as SETB and cleared with a command such as CLR.
Example instructions are:
SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0)
Note, bit 25h is actually bit 5 of Internal RAM location 24h.
The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between 20h and 2Fh.

General Purpose RAM: 30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for
general-purpose data storage, user should take care while using the memory location from 00 -2Fh

11
8051-Microcontroller-18EC46 4 Sem ECE

since these locations are also the default register space, stack space, and bit addressable space. It is
a good practice to use general purpose memory from 30 – 7Fh. The general purpose RAM can be
accessed using direct or indirect addressing modes.

1.7 EXTERNAL MEMORY INTERFACING

Eg. Interfacing of 16 K Byte of RAM and 32 K Byte of EPROM to 8051

Number of address lines required for 16 Kbyte memory is 14 lines and that of 32Kbytes of
memory is 15 lines.

The connections of external memory is shown below.

PSEN PSEN
A14 A14
A13 A13
A13
A12 A12
A12
… 32 Kbyte
..
A9 .
A8
A8 WE
. RAM
WR 16 Kbyte .
RD OE
A3
AL A7 RAM
LE A2
..
8051 A0-A7 A0-A7 A1
A1
A0
A0
LOWER BYTE
EA ADDRESS
GND [AD0 – AD7] DAT DAT
A A
O/P O/P

AD0
- DATA BUS [AD0 – AD7]
AD7

The lower order address and data bus are multiplexed. De-multiplexing is done by the latch.
Initially the address will appear in the bus and this latched at the output of latch using ALE signal.
The output of the latch is directly connected to the lower byte address lines of the memory. Later
data will be available in this bus. Still the latch output is address it self. The higher byte of address
bus is directly connected to the memory. The number of lines connected depends on the memory
size.

The RD and WR (both active low) signals are connected to RAM for reading and writing the data.

PSEN of microcontroller is connected to the output enable of the ROM to read the data from the
memory.

EA (active low) pin is always grounded if we use only external memory. Otherwise, once the
program size exceeds internal memory the microcontroller will automatically switch to external
memory.

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore – 64 12

8051-Microcontroller-18EC46 4 Sem ECE

1.8 STACK
A stack is a last in first out memory. In 8051 internal RAM space can be used as stack. The address
of the stack is contained in a register called stack pointer. Instructions PUSH and POP are used for
stack operations. When a data is to be placed on the stack, the stack pointer increments before
storing the data on the stack so that the stack grows up as data is stored (pre-increment). As the
data is retrieved from the stack the byte is read from the stack, and then SP decrements to point the
next available byte of stored data (post decrement). The stack pointer is set to 07 when the 8051
resets. So that default stack memory starts from address location 08 onwards (to avoid overwriting
the default register bank ie., bank 0).

Eg; Show the stack and SP for the following.

[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)

MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H

PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H

PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H

POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H

POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H

13
 ON
RO61 Archdteclae

AitheoHe
Qnd
PSW YUneton Ao-Ay
Rugiahors -Do-DY
RoM
bit Data
and Adds b P
DPTR RoM
Pe DPH
DPL
16BPE Addus Bus P

e-A
Buteit netton
EASyem Addses Rogi&kons
ALE imina Pogsher
e
LP
-Inerrup
Countus
PeEN&ustum Bank 8 PCON
28UF
&eal Sata
Dnleroupt Roaister &ON
RD-e
XFRL2 Bok
TCON
ReSET Regigi TMOD
Dalo Bueas TLO
VoL Hemut Raysla THO
GND Conhot Bamk o TLI
TA

Onema) RM Srucie
Cural precuaing oatt Cecr) o
The 8o51 Pu toss o 8-bE orifhmetfe sd logè Unft ui
asoRotad Sugistuns ike A, B, PW
8P 16-bPt program 0ouotus
ond 9ata
pöula heglzlers (p PTR)
The gor1' AL Can puses asi lhmatic
2 ogfe
Vortables.The atthmuetfe unt fan chons @n ebt
mu Htpfcalfon and divison paskms 0olditoo, &ubhra ion
Tho Joie Uait on
penfom JogYca operorltons Lueh
Ex-OR, uoell au Rolata, cleor ond
a8 g Anp 0R
ompemant
 nal ReM (o) 0ala Memd
Byta Add r

R4
RB

R
R5
Bank1's R
R3
R Bit
RD
2F 1
Addseks
OE 2E
R5
Bank 8c RU
RS
2c 7
9B
A 9A 57
04
98
3F
07 Db 3
DS 25|PF
Bank bu Ru
R3
24197
2,3 F
R 90
0 R1 2 0 O8
20

Hotkng agiatas Bit AddruS

Senera pupoe

Tie &os1 hos De-be nlerma) RaM. e ntenal Rart of &o51

ORgomisec Tno hree dctintt areas
Wosking dugistuns
Bie addrsabl Peglsloss
onunaPapose aegisms
Wexking hegestes
The B2-bülzs om 0ddse 0oh 1F o ntena) RhM
Constitulz 3 wothing Jagishzas fe)
Bank o 8 hgishens (R-R)0D to Oth
Bank4 ugiktuns (Ro-R) 08h fo OFh
Bane 2 &Suglstas Ro- Rr):toh t th
bamk 3-& aqutasRo-R)1kb Fh
B E Re, AR, in-he pa dubmind utieh. bost et a ,

suoently In se

bhon&ot s RESET,he Bewto Aelool

Bir addvabu g i u
he
The gob providus 16- bys ef a biraddssah orea. DOopy
BM Orta om bk ming 0 Fokal 8addsNae bip
C16 bytisx @bh 128 bk)
Genaxa pupose 9tagiyinA
The RnM obee bik addrksahle orea 4rom 30
Orta
h
alld Qomurau punpese
RpM E s addruS aba a3 bule
Lnvesua PonNa:) progrom Membr CRom) clasifiadtnlo
Toegnal RbM EtTna RDM.
h8o51 ha Ak byfza o ahema) RoM t addses pace from
DOOoh to 0FFfh
o41om addus Aigl han oFFFh, Rfoh redshe Intenna
tbM Capaily tell oue u
go aulonaicallyatch Code
bytisrom Oxnal prbgram mamae -By
A-Ragiclau (hceomuator) oFFFh-kbgli
Ro
o Dook
Aecumblalak sa 8-E hugika and s widely sed
ke 0ddbaon, &ibration, muliplfotrë n ,divs ton8 for mamy bbewrtons
The Angise bo olean bit moni palahe
P ako used or all dola
&oB1 Ond any ranors brleueen. tha
deral mumay
B-Rgiaa
The B-ugise s uwed usth the Augia
durision Oparatiens ond ha mo mul bplfearton @nd
eltu
Joeaton we dota unet'on olte thern a
maybe albxed.
satk poinL (8 bE)
he Slatk ukens On Ova
to sove and ontema RpM Ued by he CPu
9ehive (takuback dota
The 3ugla used to atco he glace Qui chly
s tallad ha slade puinla
Auabh p)
 elach poinlz Bugisla used by u @061 f hold on
Interna RPM Odds hat s olledhe lop o -he slockh
lhen&oB1 s RESE7, he pk 800 b 076
h e &torihg o a cpu hagistn in na slhek. e calad a Pas4
oad ng lontenl o the Sadk bouk Tnto the CPu 9tugister
Ca lled a_pop ( 1 4da o pa09 e then
D e PDAd 0L 0p. 08
Sata pornla (pPR) 8p-D7addr b7 P:01
PIRs a lb bit hegixlu made up o - Joo ebiEygden
named DP and DPL PTR dok nob have a nae ntema
T-bit DPR
addsa DPHDPL

DP 3plitled ino hoo pasle 83h h

DPH Data pornlu high byte Kaving ntuna) addrs 83

DPL ala point Jno byl hauing r na addras éak
progra Counluu (Pe)
nexE
> Pe is a 16 bit egiter wktoh holdu the addves o tia
be Rxecuted. The Pe automatteall (n cremenlad
hstructton to
aht euery
Inruction bylz Pebched
T e gb51 has lb bfE Pe Kene e lan addres upto 2 bgls
t bhk-bytes o memory
only egikter that does not
have a Ihferna
rogram buntu s e
Oddsus pa

h e eost has 99 ulo pins Cooßqused a Four 8-bt pmallel perl

povto Port 4, Postg and post3
A tour povk aTe bP-dseutionap(7t) each pio Can be ConBgured
04
1}p(0) 0lo vnder optuoase Conhrof
1imews s& lourtuns:
> Robl utetoo lbtt vegtlens namey To d eiftu for 7Tmbr Dr
Ceuntax
The Jo Limuns (or) Bnnluns ore divided tng Hoo -bt reghafeng
Colld hmar loo(TLo TLi)and Tima Hgh (THo s4 THI)
Progven &talusond (Pew) o la aq
The Pw On bh agisla. DF abo led al ag rgid
Oul ethase omly 6-5t3 e PSw uaistuns ase Ued and 3-83
Unued
A - l a s ove allad Math lag le) Condrtona)gs because

A Haas tadioa TsSome Conditions tiat esullk ahtoy an Iherudton

Nomtrd te) lamy 8lag dudbanty enty, pavily tlag Ond Overloo
Ro, ond Re, ave sed Jo chamge he banlk tagists
The Dho0 unUsed btk Cald
ae ues-dkinale lags
cy AcFo Re Rso Dv-P
POw7 9é Psw Psw-4 Pow 3PSw. 2 PSP. b
Cagg Co)
Ror pesRoming aikfnebte and ogie Oponertton p-hume sa
oyeaom e MSB (D7-Be than Cy-), otumoie C4-0
Camyag ey Can. be Aet o 4 04 0 dreetly by on Inafructton

Luth as 2eTB C and CLRe'

CLR C- lear Carv

Purperpming ditmalite and lgie opumlin pa Cay geotale

from Dto Da bit then Ac- , 0ThexeotteAc-0 (te easuy omlouwe
RS, 4R Rugiatu bamk &dneou
RS Reo Ras amt Aad
- 0tH
00H
0&H0FH
DH

18n-IF
FO Avalabe or uer or urnl popesc
 veFlbu Ca k d to daleel t tn Re Atpl
ged mumhet puartan edee-org
OV lag Stt Jb 4 i fhe othalocing Jupp Conditong
Occums PODN
PSW
hones o Coveyoom fo7 bu No Camy ou b A (oy-0)
5-hae ka Cormyou aom O CCy-) but Nlo Cprvy fon (Sg lb Sy bie

Oneton
-128 80 h O+6 E 100 0 0000

&+15-23-1
+(26
TO
vmDverPlod
OV-| betause Coyvyeutom 7 No Covog rom 1O b
OED
Posl swong be eausi Cpo Sho08 Onsus. as 12by(hezad of -BD

porlyla9 ndicals- pumbeL o s bsent o Aeatamudalor

Che mumbel o tn h aceumaulatos eddd tRen P-1,

e accumulalor k eVen then jD-0
1 e n be o
9p Ba0011000- P-01 mumbe bR a Dvem
2 D- 100o |1DO > P-i Numbe s asu bdd

The Oparalto ng o &o5) ae done by a group o Spoule Snfernd)

Ragisters, 2ath lalled a gpecia) tnekiop Register
oroama
Name RAMLaddea
CHee)
Acumulator
B Ari hmetfe DFO
DPH Adds psthg exteona) mem@st
PPL Addrsin extema mømeny
Itesrupt ehable Comto OA&
9nterupt psiontber
Po Post lato
PI 9/0 Peat latch 40
Po 9/o Pest latch AO
Ps o Polata 0B0
Poues Con)ro
pso gram &sa lis uooo ODD
 2cON orial pov Conthef
gpUF Qial por dala bujjax
gP &hack. peinl
THoD YinLAteunter modu lorho 89
TOon na tounler Contot
110 imer oloo byl gA
HOimcu Agh by
H TimeldJoobyu &
Trmat d high byta

The&o51 9harations hat do mat uge dhe totema 128 -by RaM
Oddsse 0 to h
The opuralHons oeo5T 0Ae done by a grnup speife ntenap
9ugisters 20ch eald a8pi) undtbo Reafster"gF
The 3FR May be attesed by ther names r by using oddregex

from &oh tFFh

Nol al Ae addrses om8oh to FFR a sed-for SFRs.e
apmpto use an addt es that not ned eT Lmphty vall
D th redieable Henulg

NoG ThePknu posk ok tte SFR and has mo tnerna) PeMadd

8houo-h Oootunete PSW ugikE aHbu He cxeuetton the

e llovethgInciraebions -
Mov A,9CH 2 t914
ADD A# 64 4

9cu QCH iooi100

64 0110100
100
100,
00 sD 12+th -l6 16-16-0 uffhaCant
bhu +9 6 6 16-16 0 ih a Lansy
00
)cyl: &inte Hhoat
1s a eop beyondha - bt

ACl: Stnt2 hont

a
Camy fom s b A btt
2inte h a00ltmuulatas thag ar OUn numbeu p
PD
s te e has ero de
Reo0 BgAclaulb Bank o &adoctud
R840
hante o.
t o 0 : Unttse,
O: sinte tRene k Canoy om o O and a (oovyoul-
6 OV

Paw.4-0 Not used henta-D

The ebntenls o p3! Mboobo0 ) CO

Shoo -h Conionk e he PSN ula olten hue additton t BFH

1BH In theolbcrg nstrueblon
Mov A,08F.
PDD 18A

BF LS:15+ l- 26 6-b-/o tolh a Cavoy

1 11+B (3
DAn
BFA o I1 i
B 000)1D1
(1611010
A e) Dey
Re br o Ral aRe 0s joleu
C0 ineeliee mo loy bypnd the Oy- br
) Bc:1: inteRoae g a Carsp om to a
to Ao D blb.
3) TD-0 Unased, lon Ce D.
Ra1 =0 By
dafoull, Bamk o 8deb
 ReD 0: By ouoult, Banko fs elele
6) DV-0 inte hoxe % No 2mo fo

)PaW.3-0 Not ued, hene o.

8Pol 8inte Rone t& an 0dd oumbet e ss in he atumulbt

The em En e the PsN t thus o100 DO0) Al

Memer 0Agomi ortten
laProgvamMan CRo) &o5pe
Cb) Sata Hae (Rm)
Soln
bDaa Lamo1tRp) Ruor hteamal RpMom peious poga
tgrom amy (RoM)
elasijed inlb
ges)
nterma) RoMRaber Iremal Romm previousPq
Ftma Rom -bft
Frtemal RoM
uta
pin %tompolad Ves
(ov (o) qround) 6okbyla
thunhe &o5) cam aepgs ortumal memol gfonttnga RoM
64kb
Dm addvp% 0o0oh to FFFFh RoM
No toooh
onl-chip RoM addoes 000o to OFFFh FFFh Akbyles
DFF Uip RoM addres
000e fo FFFFh Re
o00oL
EA-O PsN

Inerwcaions
PUSH dfreo ad drw
YOn cPtoo: Pugk Dne 8touke
DAChphtonTke k oinl thCtd by vne Te Conlenk
b he ihdRat varhabte k thon opleà ilotte
intumal
RPir docalion oddresed by -he tack
poinlz
lag alhad d: None
 Bates:2
eydus 3

erelhn:(3p) (p)+)
Siect Oddoes ing mode
th's &oppos& bol
Istuctron
he Inshruetbn uch as puSH O pucH R
A a
The
slegal behoctions
:PusA OS0h
wine Foh t e
Rnr addres belonging o Sogis
3) Pusay O8h
Bank4
whne 0gh s the Rpm addres t Rg
POP 9keel addrug
POp haom he &atk (ep) 6
oncoo
4 to by Sack pointer
Ouunphion:his Cepizs -ha byl pointi
addek tndeata4 and deoremet
he ocaton whee doeet
by 4.
gack poin Lu
lags a i l d None

Bys&
Cycles
purioton, Sp-p)- mod
dlseuk oddsesing
Not Thlehdrutiem &uppos bnly
R20 ilegl Indhuate
The Inshruettong &uoh as Pop A o Pop
Pop DEDh
uhune E0h k fhe Rem addvas belbnging fo ugtete A

Pop 08h
uene 0gh &he RarL addees e Re ef Bomkd.
SIACk pp&atk uheng oan arta Intma PeM Used by the
CPU to &love and etrive data quickly
laclee huglsfos used fo atass the Stack callec h.
Clate pönter (sp) ugicbur
The Stackk pointer a g.bit agka used by tt eo5t
held inBema Rom oddrus that k Called he Top o
an
tha &lnch
when &o51ReOE, the &ack Ponl sot 0th
to

Ron dala b be plated n -he Stack, the tnuk ponto

ntren.em behoie arung data o Re Gach ) h 9p+,
-hat he adk 9Aows up as dota red
As he data Aehed ome Mack,The byt& fs Saad om
&tack Ond then &P deurmonk (1) -8p-1 to Point t6 ine hecl
auallable bya o Aoved dato
Soung he dota onfo the Bock. Called a PusH
Raltiheving th brhenli te Badekeotad o Pop
Ro locatton 08k he ocatton used b the &TbCr
Ctoe t e data.

Mov RaBok
PuSH
Acume habt Jni HallyBank o 8oleTed ond Sp -DTh
Beve Feaurion. ARter neutton
OBA OBh
04A
09
08h 30 9p 08h
Sp-D
Spa-Ot+1
Spp08 h

&tock ponbz k n U Cmomted by ome fe p-3p+1,Pon

aHov Ra 80h
Nev R3 lhoh
Mev Ry, hlh.
PuCH 2
 PUgH3

PUSH
Agsume B o gledted and 2hack potnlai has nittally Oth
Ereaurho
Perove Exeour-tton AR PUSH 2 PUS 93 PuSH
OBh 0Bh OBh
0Bh OAh 0A 0Ph
0AA ogh 09hAo 09h Ao
04% 08h20 oaR20 0gA 30
ogh P-0Ah
08h p-09h

Up.&s umit o eck

be used or lack
go5t Ra Can
Ioortons 08htoFh 16 addresode
dph Fh Pem Ot otexved ov bit
Soo Jocbons
Qn mus mok be wed by glack doo- A
hmlmDAL
o1DrDgram, we meed mote ho 8 byts fogkb Fh-34M
t RPM
Pnokhen 0 Can Cng tack potnta tb poin
ovelfon oh Fh h18 dont b} te thsr ackton oy Sp x
Rov e#30h Noo p nitalned b 8ph
SETB PN.8 Bank 4 z hdad
Hov Ro,F 0F7 h
Hov B), OEEK
Lov , Olh
Pusa& dhseet addres et Ro bank 4)
PusH 4 digcb addnes ef Ri (ham )
PueH OE0h dfscer addsis ef A.
Bacfo e Fruutön Atr Feeultep
Resule: APhr PUSH
34h
3h
33h Addres Sata
99h FF
3lh 20
31hEE
90h FF 31
8P-20h Sp- 39h 83
PPpingsn gnck
inb Ra Bamko
7Pop pop dhadle
Pop3; Pop Stade inta Rs Banko
pop 9 Pop 8lack inl R oR Basko
Bapore Freuoo
ot6,
0eh FF-Sp-0Bh he detalt locolion of Ahauk&
0Ah A The progam mel Qan mdRy tte Sp
Indtroicétin
09h o Va/ebg uthg tte Hrv SptXxh
08h 3 0
eHov 8p # 9ch
ARtex Frtution Noo 8p:8oh

pop>&p- Op-) Etor Popa Apto pop

DBh "spp-) "SpSp-
eh 0Bh
Oph 0-9h
09h Ao Sp-09h 09h
opA 30k-h=0gh
0gh 0
(Ra-FFi
&O51 0sülaon and clock 6N

A bberma Operatfons tte 8o5l Syn chsonizad by the

0RL

Clock Pulses. These eloeck pnlges a 9amanoaA by ustng 0Rdlater kE.

Tie &opt poprtdles tPL4 d KTRL2 pins oCrnnetng a vsonan
abuoork b On Oxci|laloUa8 shouon tn
t8x1L2
C
Cayetal o) Coromb Resenado
19TL 19xTL
C
The ogallato Creuft Constat qguantz Oytnl copaulbrd
he Oxystal quan ty k tho boste nBmal elock Arcguny
o the mifero tenroltu
 munimum Maclmym bpenattn
he
One Jupicaly - a To 161a Sospectively
P P P Pa P
BPPa P B Pa
Bsalar
frguurty
LLTLI
8hab5ata
8tat 1 )at1 &tnts 1 &laty
95
S
0ne maChane Cyoe

Pldhus (oe)
olch Anable 80bl Ttm ing
numbene.d
8o51 O machine ycle Cbnsisk b 6 atales

ycle6&tates
machne
(te) 1ne

Congie eß ttoo 09alalor pulaes

9)Fach &tatu
TOnue Sate- 2 0scillalor Palses
aThe machine Cqele k dokined 08 tho 8mdllast Thkornal of
time noAedt oeeale (actompliah) any &tmpla nefruction

nehcong mop aqwned 6na, Jioo u n mathne Cydes

to o t l O n tnstructitons doponaling ona e upe ot

Inahraktops
lhua micsocomhrofls ReE, Is'ruukutbtons axe alehed&
utod by Bniesoontrolbr automatieally begintng. oik The
Instruetionoealed ab RoM menor addreK 000h
tme huded to nwuli an hstruCtoo Caleulaled Q

bina x2d

iossR dime toe lostrukion Js be exeurted

 8 the mumbe e machine yoles

3 h Oystel aqumy
yole, LEPRere 08 ttoo ALE Pulues per mathine Cud,
These PLe pulses axe Used es exenal mumaty atas

uru ctions wtleh aA Juoo Byti Jong lon be Ketded ond

n eulid bme m.achine Cyd
&ogkebut Ineru ckrons e mot pxeuld to a halh machine
Ccle howovtt &nge byli Instru ctonsbrow_ aucoy he.
0d byte.(tokPeh kthe byt efthe ut Instructon)
(The mex Ingtruetio jk then Ratthaol in ine oleioing math ine
Cyele ie io muat omathine yda)

Caleulatee maahne le he Cxyetaluquuny i

16442
D. 0. D62 Jecee
ol)Time pasfocd der ene pule lbx 16
0ne maeh1ne ele 1apulge
b maehone oyc time 0., 065 xlD
O.5Le0
ime pastod or bna palse 0,0833PLsee
xld
Ome machtra yel
pulkes
0ne madhine cyde tne 0. 0833 peC K|2=lpcec
)In an &ogl
8yslaro, dven by It.0592 HH elock, jnd
dabn an Inchutkion uhfch takes A machine ts -tine
nstCrlad
eydes
hx12
Tinsr-4-94140t
 WAle he havduoae guived 16
demultplox he addves DP&o5)
2M

Yo.o
Po.1
Po2
Po.3
Poay
Po.5
Po.b
PoM

bbdenssr
.Ag
Pa A1s

pest 0 Ao-A7 XDDo-D

Pot a 9W r9 a As A15

ALE Pule ALE atdk Atdnets

n &05 Rioroetolau, he porto Aal malbiplaxad oddres dala lacs

fe ADo-AD
8The ALt Atgnal is uged fo damultiplrted (oporaln)Jouoes orler
addoes bus (A,- Av)d data bugnal C9o-Dr)
wfun Aie , Proto tentains addses bus
bfun ALB:0, Poof o Comtatns data bus
So toz use YL9B73 to demultrpor addeesddata bus
 The M18378 oll be nabled uhun AE T& hi te
T9-L 373 has lbumer 0rdut add vex to - Ay Q4
Q4 o-Ay haGn În

Dra& Sehomate t htanhe ntimal Ro Ro o fop

HocD to acteyshem
M
Do-D
Posto Ao-7
Ap-Ais
Poat
ALe PULSE ALEatch Addnes
Extirmal Namo dddeas
PSeN Pulue P3eN
aabe Rom
Raading RytLyktngPler
RaPulse
00 1 Rd
Wsit pule TA We
Accesing ReM-Ung RD Enable
6r We
Nfe
h
Acesstng Rr
(9The &os @on Qddru po 84k-59la ertemal data maneru
The HevNe hsruabfon uped Jo atce tho enkernal data
TAHeve
memoly
The thternal dala momsa dindod inb

PnbuonalRa Addsus Aomae Ratybeark

Lou 19g-byl 00k-TFA Oodlcing 9agita, bit oddrexsable
Ye9ls t, Gunura Purpse Aogbta
Oppen 1a8 bya goh-Ffh SFe aghk
9he FR ugik lns 0e Qcuged by indie 0dbnustng bmly
JeaLl las-6ytu ae 0tunad ilkau by dinu addreing
by Jndinet oddrusig 07

Rpwe
RD, We Pins 034 us un a ptn Rht has 'b be aces
skn RD-0,a daln bp Cam be
Aeod rn a
Ra Ipoattn
ufun NR0, a data be tan be wvten tnlö a Rom loot
Do
RAM
Ao
A
ALS
ADDER

RD PAGE
Bins
WR 0E

Tq Accaping unnal data meney

ActeNg Rpu
n 8os, whon Re pio Oomnedled to Ve tia 8o51-
t kes addepsus boooh through OFFFh and ase dilub lo

JnTana RoML
() uwtin E==0 ( Glo te &o51 atchas 0ddiuso00ok. through
fFFFh 0Re divgcted o nkenal Ror/EPRoM
)Poto %a maltplhcu addros Aata bus
ukun ALE 1 Poat 0 tentaing addaus bus Ao-AY)
 ufn ALE 0, poxto ntains dala buu )
Thotu L8878 ued lo dmulliplex addas and addrus b
e t LS373 uill be onabled hen. ALE high, So oulput
YuL3373 Aas eusel ondar oddses -Ay s hoO

psogram &ore fnablePsEN) pih s an acttve Jouo pin

wtfchs sed b ativala pulrpne enabe gnal he
ONctional RoM /EPROM 8 Shoom inusa
Rm&ost has lo attas pegroo Code oomOm ntamal Rom,
PEN& Conneotad o-te anobl Pin (0E) Dha RoM dhip
oQltus eo9ram bdo, FA nmuwt be groumdad tRon
psEN 90 Jou), Jo enable tio entornal Rom to plan a
byt e progvan Cade bm Re daba buk

A RO/ EPRO
Ao)
ALET CAk Addr
A&
Pa o75auA p
Pronaum oiob
PseN DE

Accepsing atunal pogram matOD

 SURYA Gold
/Date Page

Embeddrd Micantenholea
uhiom a Compleli haadueaLe eqnlne4_to aun
apaalfeulag oppliattêopaovfdad on he
amfoa.cntrdlea chip, fl afezacd do as dn
Dmmlbedded ioaecenhiles embtdded mferocomhellor
my Aegaiae pouoea Suiet Cloe amd elock
2mbedded mienocmtelloas lommuntcalbTwti
oxtanal deufees om lz dtalal 2o phs

KTPL KTh
Grbedked paaalle4 o
Me
MM
Revel
Wee o i p t Cenbv
&d Piea
loinlzn Conh

En hetueun mtro dmtroleand mbeddtd ec

embiddedysem aAyem uedfoCocala

any automati dufce to t n t an mach.ines
uhg mioracontrelles EsImbeddtng ermbioing)
t toaae wi th haamdunae to makea sustem
Nicaotondsoles kdn totegralzd oredtthat ha
a DoCLKT mem.0 ime
iado

Ermbedkced kyslem
fr es on elestronelefeetto- nmethenical &yseo
deslgned o pesfatm a Apeiie netêo md k a
Cenbtoetteo befh handwaie oisl fismaate (kae)
 SURYA Gold
Date Page

InitndutktD o ES
Ccer tteface)

Embealdedhmpual
mpu &eRteas
Outpinf
Vaiabtex PHorcduane
Vaviables

nk to oikeu systm

Dnput dertc tutacing

s f v e r cPocu?lE
Praram
membsg
pouBea BuPplg
Rasek SufalComm
Orod m ports
6s6lais CToeufs
CPsc mesvap paaallel p
Cerntrolles

udpa ntaecing

ad tasb.aniin
hg)matt amera
Aatniattb apiplk Cau ianDheuutng ocop
ttome 0ppllamtes uOashsmq mAlhina
 Table 1.7.2
the
external 32 K EPROM and 32 K
RAM with
Example 1.7.1 Discuss interfacing of
microcontroller. Draw diagram and explain.
ne
address lines (Ag
-

A14).
Solution: To address 32 K EPROM and RAM needs 15 1s lowW
for selection of EPROM or RAM.
When A15
remaining address line Ag is used
EPROM is selected and when Ais is high RAM is selected.

RD
ALE

X P2.0
P2.7

32A
PO.0 K Ag-A15
Vcc PO.7 C
C (EPROM)
RST 8051 Do-D7

PSEN
PSEN -WR
EA WR
RD
ALE

Reset

OE D,Do AAo OE D-Do A12Ao WR

32 K (RAM)

CS CS
A15-

Fig. 1.7.8
Memory Map

femory As Au A3 Az A A0 Ag Ag Ay As As A4 Ag Az A An Address
Men *******************************.******ass
1000 0 0 0 0 00 0 0 0
0 0 8000H
********* * .... ********************* *********************************
*** -****** ******** ****.******.. (Start)
RAM
RAM 11 1 11 1 11
111 1 1 1 1 FEPH
*
..
***** ******* ******
******************************************* ******** ************* .......
. .......
(End)
0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000OH
*******'**** ****"**********i . inottspe ************************************"**********'*****'********r********** (Start)
ivdrveidiii

EPROM
0 1 11 1 1 1 11 1 1 1 1 1 1 1 TFFFH
End)
wwwwwweeee ww *

1.7.2 An An 8051
51 based system requires external memory of four 4 kbytes of SRAM
Example 1.7.2
eMch and two chips of EPROM of SIze 2 kbytes. The EPROM starts at address 2000H
SRAM address map follows EPROM map. Give the completeinterface

Solution: See Fig. 1.7.9.

AP2.0
P2.7

PO.0
PO.7 Ahns
B051

PSEN PSEN
WR
RD
ALE
Reset

OE D-Do AoAo OE DgD1s AA

OE D-Do AyrAoWA
4K(RAM) 2K(EPROM) 2K(EPROM)
S CS

EPROM 0 EPROM 1

RAM 1
RAM 2
A1 -REPROM
RAM3
RAM 4

RAM 1 -EPROM 1

RAM 2
RAM 3
IND
-RAM 4

Flg. 1.7.9
 BO

Microcontroller 1-28
Address
wwwwwwwwwwwwMwwwwwwwww.wwwwwwwwwwwwww
A Ao
wwwwwwwwwwwwwwwwww

As Ag Az
Ao Ag Ag Az A^ As 2000H
A15 A14 A3 Az A 0 0 0
00
EPROMO
0 0 1 0 0 0 0 0 0 0 0 27FFH
1 1
11 1
1 11 1 2800H
0 0 1 0 0 1 1
. .
*********"****** 00 EPROM1
wwww ******** *
0 0
0 0 10 10 0 0 0 0 00 2FFFH
1 1
11 1 **************

0 0 1 0 1 11 1 1 1 1 3000H
0 0 0 RAMO
0 0 0 0
0 1 1 0 0 0 0 0 3FFFH
0 1 1 1 1 1 1 1 1 1 1 1
*
1 11 r4000H
********* ******
11
*

0 0 0 0 RAM1
0 1 0 0 0 0 0 0
0 0 0 0
1 4FFFH
4FFFH
1 1 1 1
1 1 1 1 wwwe
0 0 0 1 11
********'***************** ***
* *ss******************************

***"***

0 0 0 5000H
0 1 0 1 0 0 0 0 0 0 0 0 0 RAM2
1 5FFFH
1
1 0 1 1 1 1 1 1 1 1 1 1

0 0 0 0 00 0 0 6000H
0 1 1 0 0 00 0 RAM3
1 1 1 1 1 6FFFH
0 1 1 0 1 1 11 1 1 1 oONOOtooo000ooO0o000000000o0000oooc

oooociotooo
 Example 1.7.4 Design a microcontroller system using 8051 microcontroller, 4 kbytes of ROM
and 8 kbytes of RAM interface the external memory such that the starting adäress o

VTU: Jan.-19,
Marks 8
ROM is 1000H and RAM is CO0OH
address
Solution: To address 4 kbytes ROM we need 12 address lines (A -A1) and
to
be used
8 kbytes RAM we need 13 address lines (Ag -A 12) remaining address lines
can

to generate chip select signals.

2 P2.0
P2.7

PO.0 AgA15
VcC PO.7
c
RST 8051 Dg-D7
PSEN
PSEN WR
WR
EA RD
RD ALE
ALE
Reset

OE D-Do A1AD OE D-Do A2Ao WR

ROM (4K) RAM (8K)

CS
A15 A15
A4 A4 D
A13
A3
An2-
Fig. 1.7.11
 1-31
Microcontroler
8051 licrocontroller
vwwww.dvvvev

Memory Map
****

Memory A15 Aj4A13 A12 A1 A 10 Ag Ag A7 A6 As AgjA3 A2 A Ag Address

wwe
eevveemern

0 0 0 10 0 0 00 0 0 0 0 0 0 0
ROM 1000H
0 0 0 1 1 1 1 1 1 1 11 1 1 11FFFH
******

RAM 1 1 0 00 0 0 0 0 0 0 0 0 0 00 CO00H
11 0 1 1 1 1 1 1 1 1 1 1 1 1
* *** vw.weedivii
1 D FFFH

Review Questions

1. Explain interfacing and timing diagrams for external program memory interfacing.
2. Explain interfacing and timing diagrams for external data memory interfacing.
3. Interface the external ROM and RAM to 8051. Explain how to access them.
VTU Dec.-11, June-13, July-18, Marks 6
4. Interface 8051 to 8K external RAM and 32K external ROM and explain how 8051 access them ?
VTU-: Jan.-16, Marks 8
5. With the help of diagram, explain how to
a
interface 8KB EPROM and 8KB RAM, to 8051
Microcontroller. VTU: June-16, Marks 6
6. Show how to interface external PROM and external RAM to 8051. Explain how 8051 access them.
VTU Jan.-18, Marks 10
Table 14-1: Powers of
2
2
10 1K
11 2K
12 4K
13 8K
14 16K
15 32K
16 64K

17 128K
18 256K

19 512K

20 1M

21 2M

22 4M

23 8M

24 16M

25 32M

64M
26
128M
27
Example 14-1

How many address lines are required for accessing the data in the following memory chips, while data is zed
as bytes in the first two cases and as nibbles in the last case?
Also find the memory capacity of each chip and the organization.
(a) 512 bytes RAM (b) 8 K RAM (c) 8 K ROM

Solution:
The memory in the first two cases is organized as bytes.
(a) 512 =2". So 9 address lines are required.
Memory capacity =512 x 8 = 4096bits.
The organization is 512 x 8.

(b) 1K 1024 210; 8 K

=
=23 x 210 213
So 13 address lines are required
Memory capacity =213 x 8 = 65,536 bits.
The organization is 8K x 8.

(c) Whether it is RAM or ROM, the calculation is the same.

8K 23 x 210 213,
Hence 13 address lines are needed.
Data is organized as 4 bits.
The memory capacity = 213 x 4 = 32,768 bits
The organization is 8 Kx 4.