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Subject Name: VLSI design Subject code: EC 701

ACROPOLIS INSTITUTE OF TECHNOLOGY AND RESEARCH,

INDORE

LABORATORY
JOURNAL VLSI LAB
MANUAL

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Name:

Class: 7th semester IV year

Branch: ECE

Subject: VLSI design ( EC701)

DEPARTMENT OF INFORMATION TECHNOLOGY

ACROPOLIS INSTITUTE OF TECHNOLOGY AND RESEARCH, INDORE

MANGLIA SQUARE, BYPASS ROAD 453771

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ACROPOLIS INSTITUTE OF TECHNOLOGY & RESEARCH, INDORE

Department of Information Technology

CERTIFICATE

This Is to Certify That the Experimental Work Entered In

This Journal As Per The B. Tech 4th Year Syllabus
Prescribed By The RGPV Was Done By Mr. / Ms.
B.Tech IV Year 7th Semester In The
Laboratory Of This Institute During
the Academic Year 2023- 2024

Date:

Signature of Head Signature of the Faculty

 Index

LIST OF EXPERIMENT
Date Page Date of Grade &
Exp Name of the Experiment
. of No. Submission Sign of
No. Exp. the
Faculty
1 Write a code to realize all the logic gates 8-10

2 Write a program for 2 to 4 decoders 11-12

3 Design 4-bit binary to gray converter 13-14

4 Write a code to realize Multiplexer 15

5 Write a code to realize Demultiplexer 16-17

6 Write Verilog codes to realize Comparator 18-20

7 Write a code to realize Full Adder using 21-23

three modeling styles.

8 Design Verilog code for flip-flops SR, D, 24-27

JK and T
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CONTENTS

List of Experiments:

Experiments can be conducted using any of the following or equivalent

design tools: Xilinx/Altera/ModelSim /Cadence/Synopsys/Mentor Graphics

Write HDL code and download the programs on a FPGA board such as Spartanor
equivalent and performance testing is to be done.

1. Write a code to realize all the logic gates.

2. Write a program for 2 to 4 decoders.

3. Design 4-bit binary to gray converter

4. Write a code to realize Multiplexer.

5.. Write a code to realize Demultiplexer.

6. Write Verilog codes to realize Comparator.

7. Write a code to realize Full Adder using three modeling styles.

8. Design Verilog code for flip-flops SR, D, JK and T

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INTRODUCTION TO HDL
VHDL stands for VHSIC (Very High-Speed Integrated Circuit) Hardware
Description Language. VHDL is a programming language that has been designed
and optimizedfor describing the behavior of digital systems.

VHDL has many features appropriate for describing the behavior of electronic
components ranging from simple logic gates to complete microprocessors and custom
chips. VHDL is also a general-purpose programming language: just as high-level
programming languages allow complex design concepts to be expressed as computer
programs, VHDL allows the behavior of complex electronic circuits to be captured into
a design system for automatic circuit synthesis or for system simulation.

One of the most important applications of VHDL is to capture the performance

specification for a circuit, in the form of what is commonly referred to as a test bench.
Test benches are VHDL descriptions of circuit stimuli and corresponding expected
outputs that verify the behavior of a circuit over time.
VHDL can describe a digital system at several different levels- Behavioral, Dataflow
and Structural.

A. Behavioral description: A digital circuit can be described at the behavioral level in

terms of its function or behavior, without giving any implementation details.
B. Data-flow description: A digital circuit can be described at the data-flow level by
giving the logic equation of that circuit.
C. Structural description: A digital circuit can be described at the structural level by
specifying the interconnection of the gates or flip-flops that comprise the circuit.

The basic design units used in VHDL.

Modules
Verilog provides the concept of a module. A module is the basic building block in
Verilog. A module can be an element or a collection of lower-level design blocks.
Typically, elements are grouped into modules to provide common functionality that is
used at many places in the design. A module provides the necessary functionality to
the higher-level block through its port interface (inputs and outputs) but hides the
internal implementation. This allows the designer to modify module internals without
affecting the rest of the design. In Verilog, a module is declared by the keyword.
module. A corresponding keyword endmodule must appear at the end of the module
definition.
Module <module_name> (module_terminal_list);
…..
<module internals>
…..
…endmodule
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>Entity: Entity is the basic design unit used in VHDL. It describes the external boundary
of the hardware.
General syntax of the entity is
entity entity-name is
port (list of ports: mode type; list of ports: mode type);
end [ entity ][entity-name]

List of ports: which includes all input and output ports

Mode type: This specifies the type of ports such as in, out & inout.

>Architecture: It describes the functionality/behavior of the entity. General syntax of the

architecture is architecture architecture-name of entity-name is
[ declarations
] begin
architecture
body.
end [architecture-name];

Note: 1. [ ] - square brackets indicate optional.

2. Signals and components are declared in the declaration part of the architecture.
3. The architecture body contains concurrent or sequential statements.

>Process (): A common way of modeling sequential logic in VHDL uses a process.
Generalsyntax of the process is
process (sensitivity-list)
begin
Sequential statements.
end process;

Sensitivity list contains a list of signals. Whenever one of the signals in the sensitivity list
changes the sequential statements in the process body are executed in sequence one time

>If statement: It is a commonly used sequential statement. The basic IF statement

has the form if (condition) then

Sequential statements1
Else
sequential statements2
end if;

The condition is a Boolean expression, which evaluates to TRUE or FALSE. If it is TRUE

sequential statements are executed otherwise sequential statements are executed.

>Elsif statement: Which is alternative way of writing nested IF statements. The most
general form of the ELSIF statement is
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if (condition) then
sequential statements
{ elsif (condition) then
sequential statements }
-- 0 or more elsif clauses may be
included. [else sequential statements

] end if;
The curly brackets indicate that any number of elsif clauses may be included, and the
square brackets indicate that the else clause is optional

>Case statement:

The case statement has the general form

case expression is
when choice1 => sequential
statements1 when choice2 =>
sequential statements2 … [ when others
=> sequential statements ] end case;

The expression is evaluated first. If it is equal to “choice1”, then “sequential statements”

are executed. If it is equal to “choice2”, then “sequential statements” are executed, etc.,
Note: All the possible values of the expression must be included in the choices. If all the
values are not explicitly given, a “when others” clause is required in the case statement
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EXPERIMENT NO:1

Aim: To write Verilog HDL codes to realize all the logic

gates.

Block Diagram:

Theory:
A logic gate is an elementary building block of a digital circuit. Most logic gates have
two inputs and one output. In digital logics AND, OR and NOT are called as basic
gates. NAND, NOR, XOR, XNOR are called complex gates. In these NOR and NAND
are called universal gates. Because the function of any gates can be done Using these
two gates. Using digital gates, we can implement all kinds of combinational circuits.
Each digital circuit output is a Boolean function of one or more Inputs. Boolean
functions are defined Using Boolean expressions.
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Truth Table:

Logic diagram:
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Verilog Code:

module all_gates (a, b, and_out, or_out, not_out, nand_out, nor_out, xor_out, xnor_out);
input a,b;
output and_out, or_out, not_out, nand_out, nor_out, xor_out, xnor_out;

assign and_out = a & b;

assign or_out = a | b;
assign not_out = ~ a ;
assign nand_out = ~(a & b);
assign nor_out = ~(a | b);
assign xor_out = a ^ b;
assign xnor_out = ~(a ^ b);
endmodule
Testbench waveform:
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EXPERIMENT No.2

Aim: Write Verilog program for the following combinational design along with test bench
to verify the design:

2 to 4 decoder realization using NAND gates only (structural model)

Theory:
Binary Decoders are the type of digital logic device that has inputs of 2-bit, 3-bit or 4-bit
codes depending upon the number of data input lines, so a decoder that has a set of
two or more bits will be defined as having an n-bit code, and therefore it will be possible
to represent 2n possible values. Thus, a decoder generally decodes a binary value into
a non-binary one by setting exactly one of its n outputs to logic “1”.
A standard combinational logic decoder is an n-to-m decoder, where m ≤ 2 n, and
whose output is dependent only on its present input states. In other words, a binary
decoder looks at its current inputs, determines which binary code or binary number is
present at its inputs and selects the appropriate output that corresponds to that binary
input.
A 2-to-4-line binary decoder can be used for decoding any 2-bit binary code to provide four
outputs, one for each possible input combination.

Truth Table:
Inputs outputs
A0 A1 D3 D2 D1 D0
X X z z z z
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
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Verilog Code:

module decoder2_4(D0, D1, D2, D3, A0, A1);

output D0,D1,D2,D3;
input A0,A1;
wire w1,w2,w3,w4,w5,w6;

nand x1(w1,A0,A0);
nand x2(w2,A1,A1);
nand x3(w3,w1,w2);
nand x4(w4,A0,w2);
nand x5(w5,w1,A1);
nand x6(w6,A0,A1);
nand x7(D0,w3,w3);
nand x8(D1,w4,w4);
nand x9(D2,w5,w5);
nand x10(D3,w6,w6);
endmodule

Testbench waveform:
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EXPERIMENT No:3

Aim: To write Verilog HDL codes to realize 4 Bit Binary To Gray code.

Theory:
Gray code is a form of binary that uses a different method of incrementing from one
number to the next. Gray code is the most popular absolute encoder output type
because its use prevents certain data errors which can occur with Natural Binary during
state changes.
This conversion method strongly follows the EX-OR gate operation between binary bits
.Binary to grey code conversion is done as below.
1. To convert binary to grey code, bring down the most significant digit of the
given binary number, because the first digit or most significant digit of the grey code
number is the same as the binary number.
2. To obtain the successive grey coded bits to produce the equivalent grey coded
number for the given binary, add the first bit or the most significant digit of binary to the
second one and write down the result next to the first bit of grey code, add the second
binary bit to third one and write down the result next to the second bit of grey code,
follow this operation until the last binary bit and write down the results based on EX-OR
logic to produce the equivalent grey coded binary.
Example:
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Truth Table:

Verilog Code:

module bin_gray(b,g); input[3:0] b;

output[3:0] g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1] ^b[0];
endmodule

TestBench waveform:
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EXPERIMENT 4

Aim: To write Verilog HDL codes to realize 8 to 1 multiplexer using case

statement and if statements

Theory
Multiplexer is also known as a data selector. It is a combinational circuit that has
2n inputs, ‘n’ selection lines and single output line. One of these data inputs will
be connected to the output based on the values of selection lines.

The figure shows the block diagram of a 8 to 1 multiplexer that consists of 8 inputs
,I0 to I7, three select inputs S2, S1 and S0 and one output from Y.

8 to 1 multiplexer using case statement

module mux8_1(Y,S,I); output Y;

input [2:0]S;
input[7:0]I;
reg Y;

always@(S,I)

begin
case(S)
3'b000:Y=I[0;
3'b001:Y=I[1];
3'b010:Y=I[2];
3'b011:Y=I[3];
3'b100:Y=I[4];
3'b101:Y=I[5];
3'b110:Y=I[6];
3'b111:Y=I[7];
endcase
end
endmodule

TestBench Waveform
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EXPERIMENT 5

Aim: To write Verilog HDL codes to realize 1 to 8 demultiplexer

Theory: A demultiplexer(or demux) is a device taking a single input and selecting one
of many data output lines, which is connected to a single input. A demultiplexer of 2 n
outputs has n select lines, which are used to select which output line to send the input.
A demultiplexer is also called a data distributor.Demultiplexers can be used to
implement general purpose logic. By setting the input to true, the demux behaves as a
decoder.
The figure shows the block diagram of a 1-to-8 demultiplexer that consists of a single
input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
Block Diagram:

Verilog Code:

module de_mux(d_in, sel,d_out);

input d_in;
input [2:0] sel;
output [7:0] d_out;
reg [7:0] d_out;
always@(sel,d_in)
begin

case(sel)
3'b000:d_out[0]=d_in;
3'b001:d_out[1]=d_in;
3'b010:d_out[2]=d_in;
3'b011:d_out[3]=d_in;
3'b100:d_out[4]=d_in;
3'b101:d_out[5]=d_in;
3'b110:d_out[6]=d_in;
3'b111:d_out[7]=d_in;
endcase
end
endmodule
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Testbench waveform:
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EXPERIMENT NO:6

Aim: To Write Verilog codes to realize Comparator

Theory: A digital comparator or magnitude comparator is a hardware electronics

device that takes two inputs in binary form and determines whether one number is
greater than , less than or equal to another number. Comparators are used in central
processing units(CPU) and microcontrollers. Examples of digital comparator include the
CMOS 4063 and 4585 and TTL 7485 and 74682-89
The analog equivalent of a digital comparator is the voltage comparator. Many
microcontrollers have analog comparators on some of their inputs that can be read or
trigger an input.

Truth table for 1-bit comparator

Input Output

a B a>b a=b a<b

0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0

Verilog code for 1-bit comparator.

module comparator_2 (a,b,agtb,altb,aeqb);

input a,b;
output agtb,altb,aeqb;
reg agtb,altb,aeqb;

always@(a,b)
begin
aeqb = ~(a ^b);
altb = (~a) & b;
agtb = a & (~b); end

endmodule
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RTL Schematics:

TestBench waveform:

Verilog codes to realize 4 Bit Comparator

module comparator_2 (a,b,agtb,altb,aeqb);

input [3:0] a,b;
output agtb,altb,aeqb;
reg agtb,altb,aeqb;

always@(a,b)
begin
if(a==b) aeqb=1’b1;
else if (a<b) altb=1’b1;
else agtb=1’b1;
end

endmodule
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RTL Schematics:

TestBench waveform:
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EXPERIMENT NO:7

Aim: To write Verilog HDL codes to describe the function of a Full Adder using
three modeling styles.
● Dataflow model
● Behavioral model
● Structural model

Circuit:

Truth Table:
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Theory:
The most basic arithmetic operation is addition of two binary digits. There are four possible
elementary operations, namely,
0+0=0
0+1=1
1+0=1
1+1=10
The first three operations produce a sum of length one digit,but when the last operation is
performed the sum is two digits. The higher significant bit of this result is called a carry
and the lower significant bit is called sum.
Half Adder:
A combinational circuit which performs the addition of two bits is called half adder. The
input variables designate the augend and the addend bit, whereas the output variables
produce the sum and carry bits.
Full Adder:
A combinational circuit which performs the arithmetic sum of three input bit is called full
adder. The three input bits include two significant bits and a previous carry bit. A full adder
circuit can be implemented with two half adders and on OR gate

Verilog code full adder using data flow description:

module fulladder_dataflow(a,b,c,sum,carry);
input a, b, c;
output sum, carry;

assign sum= a ^ b ^c;

assign carry =(a & b)| (b & c) | (c & a);

endmodule

Verilog code full adder using behavioral description:

Module FA_Behave(A,B,CIN,COUT,SUM);
input A,B,CIN;
output SUM,COUT;
reg SUM,COUT;

always@(A,B,CIN)
begin
SUM=(A^B^CIN);
COUT=(A&B)|(B&C)|(A&CIN);
End
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Verilog code full adder using structural description:

module fulladder(a, b, c, sum, carry);

input a,b, c;
output sum,carry;
wire temp1, temp2, temp3;

halfadder ha1 (a, b, temp1, temp2);

halfadder ha2 (c, temp1, sum, temp3);

assign carry= temp3 | temp2;

endmodule

module halfadder(a, b, s, c);

input a, b;
output s, c;

assign s= a^b;
assign c= a &b;

endmodule

RTL Schematics:

Testbench Waveform:
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EXPERIMENT NO:8

Aim: To write Verilog code for following flip-flops SR, D, JK and T

Theory: Flip-flop or latch is a circuit that has two stable states and can be used to store
state information. The circuit can be made to change state by signals applied to one or
more control inputs and will have one or two outputs. It is the basic storage element in
sequential logic. Flip-flops and latches are the fundamental building block of digital
electronics systems used in computers, communication and many other types of
systems.
SR flip-flop:
Theory: It is also known as SR latch, and can be considered as one of the most basic
sequential logic circuits possible. This simple flip-flop is basically a one-bit memory
bistable device that has two inputs, one which will “set” the device and is labeled as S
and another will “reset” which is labeled as R. Then the SR description stands for “Set-
Reset”. The reset input resets the flip-flop back to its original state with an output Q
that will either be at logic level “1” or level “0” depending upon set/reset condition.

Verilog Code:

module srff(sr,clk,q,qb);
input[1:0] sr;
input clk;
output q,qb;
reg q,qb;

always@ (posedge clk)

begin
case(sr)
2’b00: q=q;
2’b01:q=0;
2’b10:q=1;
2b’11: q=1’bz;
end case

assign qb=~q;
end

end module

RTL Schematic
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Testbench waveform:

D Flip-Flop:
Theory: The D flip-flop is also known as data or delay flip-flop.
The D flip-flop captures the value of the D-input at a definite portion of the clock
cycle(such as the rising edge of the clock). The captured value becomes the Q output. At
other times, the output Q does not change. The D flip-flop can be viewed as a memory
cell, a zero order hold or a delay line.

Verilog Code:

module dff(d,clk,reset,q,qbar)
input d,clk,reset;
output q,qb; reg q,qb;

always@(posedgeclk)
begin
if(reset)
q=d;
else q=0;
qbar=~q;
end

endmodule

RTL Schematics:

Testbench waveform:
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JK flip flop:
Theory: The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following
character of the clocked D flip-flop but has two inputs,traditionally labeled J and K in honor of
the inventor of the device, Jack Kilby. If J and K are different then the output Q takes the
value of J at the next clock edge
If J and K are both low then no change occurs. If J and K are both high at the clock
edge then the output will toggle from one state to the other. It can perform the functions
of the set/reset flip-flop and has the advantage that there are no ambiguous states. It
can also act as a T flip-flop to accomplish toggling action if J and K are tied together.
This toggle application finds extensive use in binary counters.

Verilog Code:
module jkff(clk,jk,q,qbar)
input clk;
input [1:0] jk; output q;
reg q; initial q=0;

always@(posedgeclk)
begin
case(jk);
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
2’b11:q=~q;
endcase
assign qbar=~q;
end

endmodule

RTL Schematics:

Testbench waveform:
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T Flip Flop
Theory: T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of an
intermediate state in SR flip – flop, we should provide only one input to the flip – flop
called Trigger input or Toggle input (T). Then the flip – flop acts as a Toggle switch.
Toggling means ‘Changing the next state output to complement the present state
output’.
T flip – flop can be designed by making simple modifications to the JK flip – flop. The T flip
– flop is a single input device and hence by connecting J and K inputs together and
giving them with single input called T we can convert a JK flip – flop into T flip – flop. So
a T flip – flop is sometimes called a single input JK flip – flop.

Verilog code

module tff(clk,t,reset, q,qbar);

input clk,t,reset;
output q,qbar;
reg q,qbar;

always @(posedgeclk)
begin
if(reset) q=~t;
else q=0;

qbar=~q;
end

endmodule

RTL Schematics:

TestBench waveform: