Unit -1

Basic concepts of computer

Unit-2
memory organization and CPU design
Unit-3
Input/output organization
Unit -4&5
Operating systems
TEXT BOOKS:
1. Computer Organization - Carl Hamacher, Zvonks Vranesic, SafeaZaky,
5th Edition,
McGraw Hill.
2. Computer System Architecture - M. moris mano, 3rd edition, Pearson
3. Operating System Concepts - Abreham Silberchatz, Peter B. Galvin,
Greg Gagne, 8th
Edition, John Wiley.
▣ Computer Organization and Architecture -
William Stallings 6th Edition, Pearson
▣ 2. Structured Computer Organization -
Andrew S. Tanenbaum, 4th Edition, PHI
 Basic Structure of Computers: Computer Types, Functional UNIT, Basic
 Operational Concepts, Bus, Structures, Software,
Performance, Multiprocessors and Multi computers
 Data Representation, Fixed Point Representation, Floating - Point
Representation.
 Register Transfer Language and Micro Operations: Register Transfer
Language, RegisterTransfer Bus and Memory Transfers, Arithmetic
Micro Operations, Logic Micro Operations,
 Shift Micro Operations, Arithmetic Logic Shift Unit, Instruction Codes,
Computer Registers
 Computer Instructions - Instruction Cycle. Memory -
Reference Instructions, Input - Output
 and Interrupt, STACK Organization, Instruction Formats, Addressing
Modes, DATA Transfer and Manipulation, Program Control, Reduced
Instruction Set Computer.
 INTRODUCTION TO COMPUTERS
 COMPUTER TYPES
 FUNCTIONAL BLOCK/UNIT OF
COMPUTER
 BASIC OPERATIONAL CONCEPTS
 BUS STRUCTURE
 SOFTWARE
 CISC VS RISC
 DATA REPRESENTSTION
What is a computer?

A) An electronic device which

performs multiple task
 Micro computer
 Laptop computer
 Workstation
 Super computers
 Main frame computers
 Hand held computers
 Multi core
Micro computers

Laptop computer

A portable, compact computer that can run on power

supply or a battery unit.
All components are integrated as one compact unit. It
is generally more expensive than a
comparable desktop. It is also called a Notebook.
 Commonly connected to LAN
 Used by one person at a time
 Engineering applications(3-d
mechanical design,
mathematical plots)
SUPER COMPUTER MAIN FRAME COMPUTER

Large expensive computer capable of

simultaneously processing data for
hundreds or thousands of users. Used
to store, manage, and process large
amounts of data that need to be
reliable, secure, and centralized.
HAND HELD COMPUTERS MULTICORE

Have Multiple Cores – parallel

It is also called a PDA (Personal computing platforms. Many
Digital Assistant). A computer Cores or computing elements in
that fits into a pocket, a single chip. Typical Examples:
runs on batteries, and is used Sony Play station, Core 2 Duo, i3,
while holding the unit in your i7 etc.
hand. Typically used as an
appointment book, address
book, calculator and notepad.
▣ COMPUTER HAVE 5 FUNCTIONAL UNTIS
example:

LOC A, R1
ADD R1,R0

 STEP 1: fetch instruction from

main memory to processor

 STEP 2: decode the operand

 STEP 3: add

 STEP 4: store and execute results

 MAR-Memory
address
register
 MDR-Memory data
register
 PC- Program counter
 Group of lines that serve as connecting
path for several devices is called a bus
(one bit per line).
Individual parts must communicate over a
communication line or path for
exchanging data, address and control
information.
Printer example – processor to printer. A
common approach is to use the concept
of buffer registers to hold the content
during the transfer.

Address line: contains address of device approaching processor

Control line: specify the task to be done
Data line: transfer the data from bus to one of the registers
 PERFORMANCE
T=(N*S)/R
T=execution time
N=number of instruction
S=average cycles per
second R=clock rate
 Software: any user wants to run program it
need system software
 Catching: commonly used data are copied to
on-processor memory to reduced access time

 Pipelining: it is set if data processing elements

connected in series where output of one
element is the input to other elements
System has more than one processor, with
common memory shared between processor.
System has more than one processor, where
have it own memory unit
 Information that a Computer is dealing with

* Data
- Numeric Data
Numbers( Integer, real)
- Non-numeric Data
Letters, Symbols

* Relationship between data elements

- Data Structures
Linear Lists, Trees, Rings, etc

* Program(Instruction)
 Data
Numeric data - numbers(integer, real)
Non-numeric data - symbols, letters

Number System
Nonpositional number system
- Roman number system
Positional number system
- Each digit position has a value called a weight
associated with it
- Decimal, Octal, Hexadecimal, Binary
Base (or radix) R number
- Uses R distinct symbols for each digit
- Example AR = an-1 an-2 ... a1 a0 .a-1…a-m
▣ Binary numbers(0’s and 1’s)
▣ Decimal numbers(base or radix as 10)(0-9)
▣ Octal decimal numbers(base or radix as 8)(0-8)
▣ Hexa decimal number(base or radix as 16)(0-16)

Examples: 1110011- binary number

(75)10- decimal number
(65)8- octa decimal number
(16𝐴)16-hexa decimal numbers
 Binary-decimal

1 1 0 0 1
23 22
21 20

1* 20=1
▣ 0* 2 =0 1+0+0+8+16=25
1

▣ 0*2 =0
2

▣ 1*2 =8
3

▣ 1*2 =16
4
Separate the number into its integer and
fraction parts and convert each part
separately.
- Convert integer part into the base R number
→ successive divisions by R and accumulation
of the remainders.
- Convert fraction part into the base R number
→ successive multiplications by R and
accumulation of integer digits
Convert 41.687510 to base 2. Fraction = 0.6875
Integer = 41 0.6875
x 2
2 41 1.3750
20 1 x 2
10 0 0.7500
5 0 x 2
2 1 1.5000
1 0 x 2
1.0000

(41)10 = (101001)2 (0.6875)10 = (0.1011)2

(41.6875)10 = (101001.1011)2
Exercise
Convert (63)10 to base 5: ANS: (223)5
Convert (1863)10 to base 8: ANS: (3507)8
Convert (0.63671875)10 to hexadecimal, binary: ANS:
10100011 (0.A3)16 30
Octal to decimal part
(736.4)8 = 6 x 80 + 3 x 81 + 7 x 82 + 4 x 8-1
= 7 x 64 + 3 x 8 + 6 x 1 + 4/8 = (478.5)10

Hexa to decimal
(F3)16 = 3*𝟏𝟔𝟎 +15*𝟏𝟔𝟏=3+240= (243)10
 Two types of complements for base R number system:

- R's complement and (R-1)'s complement

The (R-1)'s Complement

Subtract each digit of a number from (R-1)

Example
- 9's complement of 83510 is 16410
- 1's complement of 10102 is 01012(bit by bit complement operation)

The R's Complement

Add 1 to the low-order digit of its (R-1)'s complement

Example
- 10's complement of 83510 is 16410 + 1 = 16510
- 2's complement of 10102 is 01012 + 1 = 01102
 Numbers: Fixed Point Numbers and Floating Point Numbers
Binary Fixed-Point Representation

X = xnxn-1xn-2 ... x1x0. x-1x-2 ... x-m

Sign Bit(xn): 0 for positive - 1 for negative

Remaining Bits(xn-1xn-2 ... x1x0. x-1x-2 ... x-m)

Need to be able to represent both positive and negative numbers

- Following 3 representations

Signed magnitude representation

Signed 1's complement
representation Signed 2's complement
representation

Example: Represent +9 and -9 in 7 bit-binary number

Only one way to represent +9 ==> 0 001001

Three different ways to represent -9:
In signed-magnitude: 1 001001
In signed-1's complement: 1 110110
In signed-2's complement: 1 110111
Addition of two numbers in signed magnitude follows following steps:
1. If signs are same we add two magnitude and give
sum/result common sign
example: (+12) and (+15) 1
1
(+12) + (+15) = +(27) +12 0 1 1 0 0
+15 0 1 1 1 1
1 1 0 1 1== 0 11011
add- (-6),(-4) = (-6) + (-4) 0 1 1 0
0 100
1 0 1 0== 1 1010= -10
2) If sign are different ,we subtract smaller number from larger,
the sum/result will be given the sign of larger magnitude
Examples: add +6 & -9= -3 1 0 0 1
0110
0 0 1 1== 1 0011
Add -6 & +9==> 1 0 0 1
0110
0 0 1 1== 0 0011
Overflow occurs when we have extra bit which cannot be
accommodated for

example if we have 4-bit data and the result comes out as

5- bit data then overflow occurs

Overflow occurs in such cases where sign of both

magnitude are same

EXAMPLE: 9 + 9 or (-9) + (-9) 9 1001

+) 9 1001
overflow (1)0010
 Fixed Point Representations

Add the two numbers, including their sign bits.

- If there is a carry out of the most significant (sign) bit, the result is
incremented by 1 and the carry is discarded.

Example end-around carry

6 0 0110 -6 1 1001
+) -9 1 0110 +) 9 0 1001
(1) 0(1)0010
-3 1 1100
+) 1
3 0 0011

-9 1 0110 9 0 1001
+) -9 1 0110 +) 9 0 1001
1 (1)0010
(1)0 1100
+) 1
0 1101
overflow
39
Arithmetic Subtraction in 2’s complement

Take the complement of the

subtrahend (including the sign bit)
and add it to the minuend including the sign
bits.
(A)-(-B)=(A)+ B
(A)-B=(A)+( -B)
Has 3 parts
Signed bit=== 0(+ve) & 1(-ve)
Exponent bits(e)=== radix ®
Mantissa(M)==fraction part or integer
If you wants to represent 8-bit of data in
register then you can represent in the ways
shown below

EXPONENT MANTISSA

SIGN
=== Example: +6132. 786= 0.6132786*104
M *𝑟 𝑒

Fraction Exponent
+0.6132786 +04
EXAMPLE: floating point binary representation:

+1001.11 ===M *2𝑒==+(.1001110)2 * 2+4

Fraction Exponent
01001110 000100

Arithmetic operations with floating-point numbers are more

complicated than arithmetic operations with fixed-point numbers and
their execution takes longer and requires more complex hardware.
However, floating-point representation is a must for scientific
computations because of the scaling problems involved with fixed-
point computations. Many computers and all electronic calculators
have the built-in capability of performing floating-point arithmetic
operations
▣ Decimal BCD(8421) 2421 84-2-1 Excess-3
▣ 0 0000 0000 0000 0011
▣ 1 0001 0001 0111 0100 Note: 8,4,2,-2,1,-1 in this table is
the weight
▣ 2 0010 0010 0110 0101 associated with each bit position.
▣ 3 0011 0011 0101 0110
▣ 4 0100 0100 0100 0111
▣ 5 0101 1011 1011 1000
▣ 6 0110 1100 1010 1001
▣ 7 0111 1101 1001 1010
▣ 8 1000 1110 1000 1011
▣ 9 1001 1111 1111 1100
d3 d2 d1 d0: symbol in the codes
BCD: d3 x 8 + d2 x 4 + d1 x 2 + d0 x 1
 8421 code.
2421: d3 x 2 + d2 x 4 + d1 x 2 + d0 x 1
84-2-1: d3 x 8 + d2 x 4 + d1 x (-2) + d0 x (-1)
Excess-3: BCD + 3
decima g3 g2 g1 g0 b3 b2 b1 b0
l
G3=b3
0 0 0 0 0 0 0 0 0 AB AB
G2=b3  b2
1 0 0 0 1 0 0 0 1
G1=b2 b1 G0=b1 b0
2 0 0 1 1 0 0 1 0 0 0 0
3 0 0 1 0 0 0 1 1 0 1 1
4 0 1 1 0 0 1 0 0 1 0 1
5 0 1 1 1 0 1 0 1 1 1 0
6 0 1 0 1 0 1 1 0
7 0 1 0 0 0 1 1 1
8 1 1 0 0 1 0 0 0
9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0
13 1 0 1 1 1 1 0 1
14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1
▣ Character Binary code Character Binary code
▣ A 100 0001 0 011 0000
▣ B 100 0010 1 011 0001
▣ C 100 0011 2 011 0010
▣ D 100 0100 3 011 0011
▣ E 100 0101 4 011 0100
▣ F 100 0110 5 011 0101
▣ G 100 0111 6 011 0110
▣ H 100 1000 7 011 0111
▣ I 100 1001 8 011 1000
▣ J 100 1010 9 011 1001
▣ K 100 1011
▣ L 100 1100
▣ M 100 1101 Space 010 0000
▣ N 100 1110 . 010 1110
▣ O 100 1111 ( 010 1000
▣ P 101 0000 + 010 1011
▣ Q 101 0001 $ 010 0100
▣ R 101 0010 * 010 0100
▣ S 101 0011 ) 010 1001
▣ T 101 0100 - 010 1101
▣ U 101 0101 / 010 1111
▣ V 101 0110 , 010 1100
▣ W 101 0111 = 011 1101
▣ X 101 1000
▣ Y 101 1001
▣ Z 10 American Standard Code for Information Interchange (ASCII)
. Parity System
- Simplest method for error detection
- One parity bit attached to the information
- Even Parity and Odd Parity
Even Parity
- One bit is attached to the information so
that the total number of 1 bits is an even
number
1011001 0
1010010 1
Odd Parity
- One bit is attached to the information so
that the total number of 1 bits is an odd
number
1011001 1
1010010 0
Introduction :
Introduction to transfer language
What are micro-operations?
What is register transfer language?
The operations executed on data stored in registers are called
micro operations.

Examples of micro operations

 Shift
An elementary operation performed on data stored in on
 Load

 Clear

 Increment

 Count
▣ A register transfer language is system of expressing
in symbolic form which can perform micro operation
among registers of digital computers

▣ It is convenient tool for describing the internal

organization of digital computer in precise
manner.
▣ Computer registers are designated by capital letters
with numerals attached to it.
Examples( R1,R2)
MAR-memory address register
PC- program counter
IR- Instruction register
 R
1

Fig (a): REGISTER R1 Fig (b): SHOWING INDIVIDUAL BITS

7 6 5 4 3 2 1 0

Fig (c) :NUMBERING OF BITS REPRESENTING ON TOP

7 4 3 0

P(H)-HIGHER BITS P(L)-LOWER BITS

Fig (d): partitioning of register where (7-4) are higher bits and (0-3) are lower bits
Information transfer from one register to other is represented in symbolic form
shown below

R2 R1

In above representation the content of R1 is transferred to R2

We can also transfer data based on condition

Example if (p=1) then

R2 R1

P: R2 R1
It is assumed that all the transfer occurs during clock edge transition . The
actual
Transition occurs only when register is triggered by the positive transition of
the
clock
 Basic symbol of register transfer is shown in below box

SYMBOLS DESCRIPTION EXAMPLES

 Letter and numerals Denotes a register R2, R1, MAR

 Parenthesis ( ) Denotes part R2(0-7), R1(0-3)

of register
 Arrow R2 R1
Denotes transfer of
information P: R1 R2, MAR R2
if p=1 then the content of
 Comma , R2 is loaded in to R1
Separates two micro during same clock cycle
operations other instruction is also
executed ie R2 content is
loaded in to MAR
Colon indicates the
 Colon termination of control P: R1 R2
function
 A typical digital system has many registers.
If we want to transfer the information from one
register to another register we need paths
 Theses paths are provided by bus
 One of the way of constructing a common bus is
with multiplexers
 s0 s1 register
0 0 A
0 1 B
1 0 C
1 1 D

In general ,k registers with n bits

Requires n multiplexers
EX: common bus for 8 registers
With 16 bits requires 16 MUX

 For retrieving data of register A selection bits should be made zero

 For register B s0s1 should be one i.e 01
 For register C s0s1 should be two i.e 10
 For register D s0s1 should be three i.e 11
 Output
Y=A if C=1
High impedance(open circuit) if C=0
Normal input A

Control input C
 Output of four buffers are connected to form a single bus line
 Control input to the buffer which of the four normal inputs will communicate
with bus line
 At time one buffer can produce the output rest all will be in high
impedance state( open circuit)
 If s0s1=00 data of register A will be transfer to bus line
 If s0s1=01 data of register B will be transfer to bus line
 S0s1=10 register C data is transferred, s0s1=11 register D data will transfer
Most of the standard notations used for specifying operations on memory
transfer are stated below.
 The transfer of information from a memory unit to the user end is called a
Read operation.
 The transfer of new information to be stored in the memory is called a
Write operation.
 A memory word is designated by the letter M.
 We must specify the address of memory word while writing the
memory transfer operations.
 The address register is designated by AR and the data register by DR.
 read operation can be stated as:

Read: DR ← M [AR]

The Read statement causes a transfer of information into the data register (DR)
from the memory word (M) selected by the address register (AR).

write operation can be stated as:

Write: M [AR] ← R1

The Write statement causes a transfer of information from register R1 into the
memory word (M) selected by address register (AR).
Computer system micro operations are of four types:

1. Register transfer micro operations transfer binary

information from one register to another
2. Arithmetic micro operations perform arithmetic operations
on numeric data stored in registers.
3. Logic micro operations perform bit manipulation
operations on non numeric data stored in
registers.
4. Shift micro operations perform shift operations on
data stored in registers.
 The basic arithmetic micro operations are
 Addition
 Subtraction
 Increment
 Decrement
 The additional arithmetic micro operations are
 Add with carry
 Subtract with borrow
 Transfer/Load
 Etc……
Table: Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3

R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement
 4-bit binary adder
C4 C3 C2 C1

A3 A2 A1 A0
1 1 1 1
1 0 1 1
+
1 1 0 1 B0

1 0 0 0
S3 S2 S1 S0

 The bits (A) and (B) are inputs and designated by subscript numbers from right
to left, with subscript '0' denoting the low-order bit.
 The carry inputs starts from C0 to C3 connected in a chain through the full-adders
and given as an input to next full adder.
 C4 is the resultant output carry generated by the last full-adder circuit.
 The output carry from each full-adder is connected to the input carry of the
next- high-order full-adder.
 The sum outputs (S0 to S3) generates the required arithmetic sum
 4 –bit binary adder - subtractor

 If k=0 circuit act as

adder
 If k=1 circuit act
as subtractor

A-B= A+(B’+1)

B XOR 0 = B

B XOR 1= B’

The circuit consists of 4 full adders since we are performing operation on 4-bit
numbers. There is a control line K that holds a binary value of either 0 or 1 which
determines that the operation being carried out is addition or subtraction.
 4-bit Binary incrementer:

 A logic-1 is applied to one of the inputs of least significant half-adder, and

the other input is connected to the least significant bit of the number to
be incremented.
 The output carry from one half-adder is connected to one of the inputs of the
next-higher-order half-adder.
 The binary incrementer circuit receives the four bits from A0 through
A3, adds one to it, and generates the incremented output in S0 through
S3.
 The output carry C4 will be 1 only after incrementing binary 1111.
Example: increment of 0110 is
0110 +1=0111
 LOGIC MICROOPERATIONS

It specifies binary operations on the strings of bits stored

in registers.
 Logic micro operations are bit-wise operations, i.e.,
they work on the individual bits of data
 useful for bit manipulations on binary data
 useful for making logical decisions based on the bit value

There are, in principle, 16 different logic functions

that can be defined over two binary input variables
▣ Logic micro operations can be used to manipulate
individual bits or a portions of a word in a register
▣ Consider the data in a register A. In another register,
B, is bit data that will be used to modify the contents
of A
▣ Selective-set AA+B
◾ Selective-complement AAB
◾ Selective-clear A  A • B’
◾ Mask (Delete) AA•B
◾ Clear AAB
◾ Insert A  (A • B) + C
◾ Compare AAB
◾ ...
 Selective set
Rule: if the value(bit) in R2=1 ,then the result is = 1 otherwise
result is same as R1

EXAMPLE: R1= 1001, R2= 1010 R1 1 0 0 1

R2 1 0 1 0

1 0 1 1

Equivalent to OR operation
example 2 R1 1 1 0 0

R2 1 0 1 0

1 1 1 0
SELECTIVE COMPLEMENT

In a selective complement operation, the bit pattern in B is used to complement

certain bits in A

1100 At Equivalent to XOR operation

1010 B
0110 At+1 (A  A  B)

Rule: If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it is
unchanged
SELECTIVE CLEAR
In a selective clear operation, the bit pattern in B is used
to clear certain bits in A

1100 At
1010 B
0100 At+1 (A  A  B’)

RULE: If a bit in B is set to 1, that same position in A

gets set to 0, otherwise it is unchanged
MASK OPERATION:

In a mask operation, the bit pattern in B is used to clear

certain bits in A

1100 At
1010 B
1000 At+1 (A  A  B)

RULE: If a bit in B is set to 0, that same

position in A gets set to 0, otherwise it is
unchanged
CLEAR OPERATION
RULE: In a clear operation, if the bits in the
same position in A and B are the same,
they are cleared in A, otherwise they are
set in A

1 1 0 0 At
1010 B
0 1 1 0 At+1 (A  A  B)
INSERT OPERATION(MASKING +OR)
An insert operation is used to introduce a specific
bit pattern into A register, leaving the other bit
positions unchanged
This is done as
 A mask operation to clear the desired
bit positions, followed by
 An OR operation to introduce the new
bits into the desired positions
Example
Suppose you wanted to introduce 1010 into the low
order four bits of A: 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)

 Shift micro operations are used for serial transfer of data.
 The information transferred through the serial input
determines the type of shift. There are three types of shifts
o Logical shift
o Circular shift
o Arithmetic shift
RIGHT SHIFT

LEFT SHIFT
A right logical shift operation:
In a Register
Transfer Language,
the following
notation is used
shl - for a
logical shift left
Shr-for a
A left logical shift operation logical shift
right
Examples:
R2  shr R2
R2 shl R2
 Left circular shift
Right circular shift
 ARITHMETIC SHIFT
ARITHMETIC RIGHT SHIFT

An arithmetic shift is meant for signed binary numbers (integer)

 An arithmetic left shift multiplies a signed number by two
 An arithmetic right shift divides a signed number by two
 The main distinction of an arithmetic shift is that it must keep the sign of
the number the same as it performs the multiplication or division
In a RTL, the following notation is used
ashlfor an arithmetic shift left
ashrfor an arithmetic shift right
Examples:
R2  ashr R2
R3  ashl R3
 Instruction Codes

 Computer Registers

 Computer Instructions

 Timing and Control

 Instruction Cycle

 Memory Reference Instructions

 Input-Output and Interrupt

 Complete Computer Description

 Design of Basic Computer

 Design of Accumulator Logic

 Instruction Codes
 Every different processor type has its own design (different registers,
buses, micro operations, machine instructions, etc)
 Modern processor is a very complex device
 It contains
 Many registers
 Multiple arithmetic units, for both integer and floating
point calculations
 The ability to pipeline several consecutive instructions to speed
execution
 Etc.
 However, to understand how processors work, we will start with
a simplified processor model
 This is similar to what real processors were like ~25 years ago
 M. Morris Mano introduces a simple processor model he calls the Basic
Computer
 We will use this to introduce processor organization and the relationship
of the RTL model to the higher level computer processor
 THE BASIC COMPUTER

 The Basic Computer has two components, a

processor and memory
 The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory
 Each word is 16 bits long
RAM
CPU 0

15 0

4095
 INSTRUCTIONS
 Program:
A sequence of (machine) instructions

 (Machine) Instruction:
A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)

 The instructions of a program, along with any

needed data are stored in memory
 The CPU reads the next instruction from memory
 It is placed in an Instruction Register (IR)
 Control circuitry in control unit then translates the
instruction into the sequence of micro operations
necessary to implement it
 INSTRUCTION FORMAT
 A computer instruction is often divided into two parts
 An opcode (Operation Code) that specifies the operation for
that instruction
 An address that specifies the registers and/or locations in
memory to use for that operation
 In the Basic Computer, since the memory contains 4096 (= 2 12)
words, we needs 12 bit to specify which memory address this
instruction will use
 In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)

15 14 12 11 0

I OPCODE ADDRESS

I=0 (direct addressing)

Addressing mode
I=1(indirect addressing)
 ADDRESSING MODES

The address field of an instruction can represent either

 Direct address: the address in memory of the operand
is fetched directly
 Indirect address: Instruction needs two reference to fetch
an operand the first reference is used to read the operand
and second is for operand itself
▣ A processor has many registers to hold
instructions, addresses, data, etc
▣ The processor has a register, the Program Counter (PC)
that holds the memory address of the next instruction to
get
◾ Since the memory in the Basic Computer only has
4096 locations, the PC only needs 12 bits
▣ In a direct or indirect addressing, the processor needs
to keep track of what locations in memory it is
addressing: The Address Register (AR) is used for this
◾ The AR is a 12 bit register in the Basic Computer
▣ When an operand is found, using either direct or
indirect addressing, it is placed in the Data Register
(DR). The processor then uses this value as data for its
operation
▣ The Basic Computer has a single general purpose register –
the Accumulator (AC)
▣ The significance of a general purpose register is that it can be
referred to in instructions
◾ e.g. load AC with the contents of a specific memory location; store
the contents of AC into a specified memory location
▣ Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
▣ The Basic Computer uses a very simple model
of input/output (I/O) operations
◾ Input devices are considered to send 8 bits of character data to the
processor
◾ The processor can send 8 bits of character data to output devices
▣ The Input Register (INPR) holds an 8 bit character gotten from
an input device
▣ The Output Register (OUTR) holds an 8 bit character to be
send to an output device
S0 S1 S2
Three control lines, S2, S1, and S0 control which register the bus selects as its input

S2 S1 S0 Register
0 0 0x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory
BASIC COMPUTER INSTRUCTIONS
Symbol I=0 I=1 Description

AND 0xxx 8xxx AND memory word to AC

ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
▣ In Basic Computer, a machine instruction is executed
in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address
4. Execute the instruction

▣ After an instruction is executed, the cycle starts again

at step 1, for the next instruction
▣ Note: Every different processor has its own (different)
instruction cycle
▣ Control unit (CU) of a processor translates from machine
instructions to the control signals for the micro operations
that implement them
▣ Control units are implemented in one of two ways
▣ Hardwired Control
◾ CU is made up of sequential and combinational circuits to
generate the control signals
▣ Microprogrammed Control
◾ A control memory on the processor contains
microprograms that activate the necessary control signals
▣ We will consider a hardwired implementation of the control
unit for the Basic Computer
 TIMING SIGNALS

Generated by 4-bit sequence counter and 416 decoder

- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active
▣ In Basic Computer, a machine instruction is executed
in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address
4. Execute the instruction

▣ After an instruction is executed, the cycle starts again

at step 1, for the next instruction
▣ Note: Every different processor has its own (different)
instruction cycle
 REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when

- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop
 MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Decoder Symbolic Description
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

The effective address of the instruction is in AR and was placed

there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a
CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with
AC ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA
:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
 INPUT-OUTPUT AND INTERRUPT
A Terminal with a keyboard and a Printer
• Input-Output Configuration FGO

RECEIVER
PRINTER INTERFACE OUTR

AC

KEYBOARD TRANSMITTER INPR

INTERFACE

The terminal sends and receives serial difference between

information I/O device and the
- The serial info. from the keyboard is shifted computer
into INPR
- The serial info. for the printer is stored in the
OUTR
- INPR and OUTR communicate with the
terminal serially and with the AC in
parallel.
- The flags are needed to synchronize the timing
 FGI
INPR Input register - 8 bits OUTR Output register
- 8 bits FGI Input flag - 1 bit
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit
 INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from
SKI pB9: if(FGI = 1) then (PC  PC + 1) AC Skip on input
SKO pB8: if(FGO = 1) then (PC  PC + 1) flag Skip on output
ION pB7: IEN  1 flag Interrupt enable
IOF pB6: IEN  0 on Interrupt enable
off
 Open communication only when some data has to be passed -->
interrupt.

 The I/O interface, instead of the CPU, monitors the I/O device.


 When the interface founds that the I/O device is ready for data
transfer, it generates an interrupt request to the CPU

 Upon detecting an interrupt, the CPU stops momentarily the task it is

doing, branches to the service routine to process the data transfer, and
then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop

- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted
REGISTER STACK ORGANIZATION
MEMORY STACK ORGANIZATION

Stack start
 REVERSE POLISH NOTATION

Reverse Polish notation (RPN) is a method for conveying

mathematical expressions without the use of separators such as
brackets and parentheses. In this notation, the operators follow
their operands, hence removing the need for brackets to define
evaluation priority.

It is like post fix notations that all the operators are moving
towards right

For example: A + B

In RPN it is written as AB+

P+Q-R/S

P+Q -RS/
PQ+ - RS/==== PQ+RS/-
EXAMPLE: (A+B)*(C-D)

AB+ * CD-

AB+CD-*
 INSTRUCTION FORMAT
 OP-code field - specifies the operation to be performed
 Address field - designates memory address(es) or a processor register(s)
 Mode field - specifies the way the operand or the
 effective address is determined
 The number of address fields in the instruction format
 depends on the internal organization of CPU
-The three most common CPU organizations:
Instruction Format
Single accumulator organization:
 ADD X /* AC ← AC + M[X] */
 General register organization:
 ADD R1, R2, R3 /* R1 ← R2 + R3 */
 ADD R1, R2 /* R1 ← R1 + R2 */
 MOV R1, R2 /* R1 ← R2 */
 ADD R1, X /* R1 ← R1 + M[X] */
 Stack organization:
 PUSH X /* TOS ← M[X] */
 ADD
 Instruction Fields
 THREE, AND TWO-ADDRESS INSTRUCTIONS
Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

ADD R1, A, B /* R1 ← M[A] + M[B] */

ADD R2, C, D /* R2 ← M[C] + M[D] */
MUL X, R1, R2 /* M[X] ← R1 * R2 */
- Results in short programs
- Instruction becomes long(many bits)
Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1 ← M[A] */

ADD R1, B /* R1 ← R1 + M[A]
*/ MOV R2, C /* R2 ← M[C] */
ADD R2, D /* R2 ← R2 + M[D] */
MUL R1, R2 /* R1 ← R1 * R2 */
MOV X, R1 /* M[X] ← R1 */
- Computers with two-address instructions are most common
 ONE, AND ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
Instruction Format
LOAD A /* AC ← M[A] */
ADD B /* AC ← AC + M[B] */
STORE T /* M[T] ← AC */
LOAD C /* AC ← M[C] */
ADD D /* AC ← AC + M[D] */
MUL T /* AC ← AC * M[T] */
STORE X /* M[X] ← AC */

Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS ←A */
PUSH B /* TOS ←B */
ADD /* TOS ← (A + B) */
PUSH C /* TOS ←C */
PUSH D /* TOS ←D */
ADD /* TOS ← (C + D) */
MUL /* TOS ← (C + D) * (A + B)
*/
POP X /* M[X] ← TOS */
 ADDRESSING MODES
The operation field of an instruction specifies the operation to be performed.
This operation must be executed on some data stored in computer registers or
memory words. The way the operands are chosen during program execution
in dependent on the addressing mode of the instruction.
The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is actually referenced.

Computers use addressing mode techniques for the purpose of accommodating

one or both of the following provisions:

 To give programming versatility to the user by providing such facilities as

pointers to Memory, counters for loop control, indexing of data, and program
relocation.
 To reduce the number of bits in the addressing field of the instruction.
 The availability of the addressing modes gives the experienced
assembly language programmer flexibility for writing programs that
are more efficient with respect to the number of instructions and
execution time.
1. Implied Addressing Mode-
In this addressing mode,
• The definition of the instruction itself specify the operands
implicitly.
• It is also called as implicit addressing mode.
Examples-
• The instruction “Complement Accumulator” is an implied
mode instruction.
• In a stack organized computer, Zero Address Instructions are
implied mode instructions.(since operands are always
implied to be present on the top of the stack)
2 Immediate Mode:
Instead of specifying the address of the operand,operand itself
is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

Examples-

ADD 10 will increment the value stored in the accumulator by 10.

MOV R #20 initializes register R to a constant value 20.
 3. Direct Addressing Mode-

In this addressing mode,

• The address field of the instruction contains the effective address of the operand.
• Only one reference to memory is required to fetch the operand.
• It is also called as absolute addressing mode.
EXAMPLE: ADD X will
increment the value stored
in the accumulator by the
value stored at memory
location X.
AC ← AC + [X]

4. Indirect Addressing Mode-

In this addressing mode,

• The address field of the instruction specifies the address of memory location that
contains the effective address of the operand. Example-
• Two references to memory are required to fetch the operand.
ADD X will increment
the value stored in the
accumulator by the
value stored at
memory location
specified by X. AC ←
AC + [[X]]
5. Register direct Addressing Mode-
In this addressing mode,
The operand is contained in a register set.
The address field of the instruction refers to a CPU register that contains the operand.
No reference to memory is required to fetch the operand.

note-
This addressing mode is similar
to indirect addressing mode.
The only difference is address
field of the instruction refers to a
CPU register. Example: AC ← AC +
[R]

6. Register Indirect Addressing Mode-

In this addressing mode,
The address field of the instruction refers to a CPU register that contains the effective
address of the operand.
Only one reference to memory is required to fetch the operand.

note-
This addressing mode is similar to
indirect addressing mode.
The only difference is address field of
the instruction refers to a CPU
register. Example: AC ← AC + [[R]]
7. Relative Addressing Mode-

In this addressing mode,

•Effective address of the operand is obtained by adding the content of program counter with the
address part of the instruction.
Effective Address
= Content of Program Counter + Address part of the instruction

NOTE-

• Program counter (PC) always contains the address of the next instruction to be executed.
• After fetching the address of the instruction, the value of program counter immediately
increases.
• The value increases irrespective of whether the fetched instruction has completely executed or
not.
8. Indexed Addressing Mode-
In this addressing mode,
•Effective address of the operand is obtained by adding the content of index register with the
address part of the instruction.

Effective Address
= Content of Index Register + Address part of the
instruction
9. Base Register Addressing Mode-
In this addressing mode,
•Effective address of the operand is obtained by adding the content of base register with the
address part of the instruction.

Effective Address
= Content of Base Register + Address part of the instruction
 10. Auto-Increment Addressing Mode-
•This addressing mode is a special case of Register Indirect Addressing Mode where-
In this addressing mode,
•After accessing the operand, the content of the register is automatically incremented by step
size ‘d’.
•Step size ‘d’ depends on the size of operand accessed.
•Only one reference to memory is required to fetch the operand.

Assume operand size = 2

bytes. Here,
After fetching the operand 6B, the instruction register RAUTO will be automatically
incremented by 2.
Then, updated value of RAUTO will be 3300 + 2 = 3302.
At memory address 3302, the next operand will be found.
NOTE-
In auto-increment addressing
mode, First, the operand value is
fetched.
Then, the instruction register RAUTO value is incremented by step size ‘d’.
11.Auto-Decrement Addressing Mode-
This addressing mode is again a special case of Register Indirect Addressing
Mode where-
In this addressing mode,
• First, the content of the register is decremented by step size ‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• After decrementing, the operand is read.
• Only one reference to memory is required to fetch the operand.

Assume operand size = 2

bytes. Here,
First, the instruction register RAUTO will be decremented by 2.
Then, updated value of RAUTO will be 3302 – 2 =
3300. At memory address 3300, the operand will be
found.
NOTE-
In auto-decrement addressing mode,
First, the instruction register RAUTO value is decremented by step size ‘d’.
Then, the operand value is fetched.
DATA TRANSFER INSTRUCTIONS
DATA MANIPULATION INSTRUCTIONS
PROGRAM CONTROL INSTRUCTIONS

3. Bit Z (zero) is set to 1 if the output of the ALU

contains all 0's
4. Bit V (overflow) is set to 1 if the exclusive-
OR of the last two carries is equal to 1, and
Cleared to 0 otherwise

The four status bits are symbolized

by C, S, Z, and V. The bits are set or
cleared as a result of an operation
performed in the ALU.
1. Bit C (carry) is set to 1 if the end
carry C8 is 1. It is cleared to 0 if the
carryy is 0 .
2. Bit S (sign) is set to 1 if the highest-
order bit F? is 1. It is set to 0 if the bit
is0.
CONDITIONAL BRANCH INSTRUCTIONS
 SUBROUTINE CALL AND RETURN

 A subroutine is a self-contained sequence of instructions that performs a

given computational task.
 The instruction that transfers program control to a subroutine is known by
different names. The most common names used are call subroutine, jump to
subroutine, branch to subroutine, or branch and save address

Some store the return address in the first memory

location of the subroutine, some store it in a fixed
location in memory, some store it in a processor
register, and some store it in a memory stack. The
most efficient way is to store the return address in a
memory stack. The advantage of using a stack for the
return address is that when a succession of
subroutines is called, the sequential return addresses
can be pushed into the stack. The return from
subroutine instruction causes the stack to pop and the
contents of the top of the stack are transferred to the
program counter.
 PROGRAM INTERRUPT
Types of Interrupts
1. External interrupts
2. Internal interrupts
3. Software Interrupts
External interrupts: External Interrupts initiated from the outside of CPU and
Memory

Examples: I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
- Operator

Internal interrupts (traps):

Internal Interrupts are caused by the currently running program
Examples :Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer
HW. Software Interrupts are initiated by the executing an instruction.
-Examples: Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of
operations which are not allowed in the user
mode
 Typical characteristics of RISC

For any given level of general performance, a RISC chip will typically have far fewer
transistors dedicated to the core logic which originally allowed designers to increase
the size of the register set and increase internal parallelism

Other features, which are typically found in RISC architectures are:

 Uniform instruction format, using a single word with the op code in the same
bit positions in every instruction, demanding less decoding;
 Identical general purpose registers, allowing any register to be used in any context,
simplifying compiler design (although normally there are separate floating point
registers);
 Simple addressing modes. Complex addressing performed via sequences
of arithmetic and/or load-store operations

 RISC designs are also more likely to feature a Harvard memory model, where the
instruction stream and the data stream are conceptually separated; this means that
modifying the memory where code is held might not have any effect on the
instructions executed by the processor (because the CPU has a separate instruction
and data cache