M60a-4gb-8gb-16gb-Ecc-Nand - 29F4G08BA

Micron Confidential and Proprietary
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Features
NAND Flash Memory

MT29F4G08ABADAH4, MT29F4G08ABADAWP, MT29F4G08ABBDAH4,
MT29F4G08ABBDAHC, MT29F4G16ABADAH4, MT29F4G16ABADAWP,
MT29F4G16ABBDAH4, MT29F4G16ABBDAHC, MT29F8G08ADADAH4,
MT29F8G08ADBDAH4, MT29F8G16ADADAH4, MT29F8G16ADBDAH4,
MT29F16G08AJADAWP
Features • First block (block address 00h) is valid when ship-

ped from factory with ECC. For minimum required
• Open NAND Flash Interface (ONFI) 1.0-compliant1 ECC, see Error Management.
• Single-level cell (SLC) technology • Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-
• Organization cles are less than 1000
– Page size x8: 2112 bytes (2048 + 64 bytes) • RESET (FFh) required as first command after pow-
– Page size x16: 1056 words (1024 + 32 words) er-on
– Block size: 64 pages (128K + 4K bytes) • Alternate method of device initialization (Nand_In-
– Plane size: 2 planes x 2048 blocks per plane it) after power up (contact factory)
– Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks • Internal data move operations supported within the
16Gb: 16,384 blocks plane from which data is read
• Asynchronous I/O performance • Quality and reliability
– tRC/tWC: 20ns (3.3V), 25ns (1.8V) – Data retention: 10 years
• Array performance – Endurance: 100,000 PROGRAM/ERASE cycles
– Read page: 25µs 3 • Operating voltage range
– Program page: 200µs (TYP: 1.8V, 3.3V)3 – VCC: 2.7–3.6V
– Erase block: 700µs (TYP) – VCC: 1.7–1.95V
• Command set: ONFI NAND Flash Protocol • Operating temperature:
• Advanced command set – Commercial: 0°C to +70°C
– Program page cache mode4 – Industrial (IT): –40°C to +85°C
– Read page cache mode 4 – Automotive Industrial (AIT): –40°C to +85°C
– One-time programmable (OTP) mode – Automotive (AAT): –40°C to +105°C
– Two-plane commands 4 • Package
– Interleaved die (LUN) operations – 48-pin TSOP type 1, CPL 2
– Read unique ID – 63-ball VFBGA
– Block lock (1.8V only)
Notes: 1. The ONFI 1.0 specification is available at
– Internal data move
www.onfi.org.
• Operation status byte provides software method for
2. CPL = Center parting line.
detecting
3. See Program and Erase Characteristics for
– Operation completion tR_ECC and tPROG_ECC specifications.
– Pass/fail condition
4. These commands supported only with ECC
– Write-protect status
disabled.
• Ready/Busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: Write protect entire device
PDF: 09005aef83b25735
m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. R 02/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

Features
Part Numbering Information

Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Marketing Part Number Chart
MT 29F 4G 08 A B A D A WP IT ES :D
Micron Technology Design Revision (shrink)
Product Family Production Status

29F = NAND Flash memory Blank = Production
ES = Engineering sample
Density MS = Mechanical sample
4G = 4Gb QS = Qualification sample
8G = 8Gb
16G = 16Gb Special Options
Blank
Device Width X = Product longevity program (PLP)
08 = 8-bit
16 = 16-bit Operating Temperature Range
Blank = Commercial (0°C to +70°C)
Level IT = Industrial (–40°C to +85°C)
A = SLC AIT = Automotive Industrial (–40°C to +85°C)
AAT = Automotive (–40°C to +105°C)
Classification
Mark Die nCE RnB I/O Channels
B 1 1 1 1 Speed Grade
D 2 1 1 1 Blank
J 4 2 2 1
Package Code
Operating Voltage Range WP = 48-pin TSOP Type 1
A = 3.3V (2.7–3.6V) HC = 63-ball VFBGA (10.5 x 13 x 1.0mm)
B = 1.8V (1.7–1.95V) H4 = 63-ball VFBGA (9 x 11 x 1.0mm)
Feature Set Interface

D = Feature set D A = Async only
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Features
Contents
Important Notes and Warnings ......................................................................................................................... 8
General Description ......................................................................................................................................... 9
Signal Descriptions ........................................................................................................................................... 9
Signal Assignments ......................................................................................................................................... 10
Package Dimensions ....................................................................................................................................... 13
Architecture ................................................................................................................................................... 16
Device and Array Organization ........................................................................................................................ 17
Asynchronous Interface Bus Operation ........................................................................................................... 21
Asynchronous Enable/Standby ................................................................................................................... 21
Asynchronous Commands .......................................................................................................................... 21
Asynchronous Addresses ............................................................................................................................ 23
Asynchronous Data Input ........................................................................................................................... 24
Asynchronous Data Output ......................................................................................................................... 25
Write Protect# ............................................................................................................................................ 26
Ready/Busy# .............................................................................................................................................. 27
Device Initialization ....................................................................................................................................... 31
Command Definitions .................................................................................................................................... 32
Reset Operations ............................................................................................................................................ 35
RESET (FFh) ............................................................................................................................................... 35
Identification Operations ................................................................................................................................ 36
READ ID (90h) ............................................................................................................................................ 36
READ ID Parameter Tables .............................................................................................................................. 37
READ PARAMETER PAGE (ECh) ...................................................................................................................... 40
Parameter Page Data Structure Tables ............................................................................................................. 41
NAND Component Parameter Page Data Structure Tables ................................................................................ 46
READ UNIQUE ID (EDh) ................................................................................................................................ 49
Feature Operations ......................................................................................................................................... 50
SET FEATURES (EFh) .................................................................................................................................. 51
GET FEATURES (EEh) ................................................................................................................................. 52
Status Operations ........................................................................................................................................... 55
READ STATUS (70h) ................................................................................................................................... 56
READ STATUS ENHANCED (78h) ................................................................................................................ 56
Column Address Operations ........................................................................................................................... 58
RANDOM DATA READ (05h-E0h) ................................................................................................................ 58
RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 59
RANDOM DATA INPUT (85h) ...................................................................................................................... 60
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 61
Read Operations ............................................................................................................................................. 63
READ MODE (00h) ..................................................................................................................................... 65
READ PAGE (00h-30h) ................................................................................................................................ 65
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 66
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 67
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 69
READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 70
Program Operations ....................................................................................................................................... 72
PROGRAM PAGE (80h-10h) ......................................................................................................................... 73
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 73
PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 76
Erase Operations ............................................................................................................................................ 78
ERASE BLOCK (60h-D0h) ............................................................................................................................ 78
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Features
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 79

Internal Data Move Operations ....................................................................................................................... 80
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 81
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 82
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 83
Block Lock Feature ......................................................................................................................................... 84
WP# and Block Lock ................................................................................................................................... 84
UNLOCK (23h-24h) .................................................................................................................................... 84
LOCK (2Ah) ................................................................................................................................................ 87
LOCK TIGHT (2Ch) ..................................................................................................................................... 88
BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 89
One-Time Programmable (OTP) Operations .................................................................................................... 91
Legacy OTP Commands .............................................................................................................................. 91
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 92
RANDOM DATA INPUT (85h) ...................................................................................................................... 93
OTP DATA PROTECT (80h-10) ..................................................................................................................... 94
OTP DATA READ (00h-30h) ......................................................................................................................... 96
Two-Plane Operations .................................................................................................................................... 98
Two-Plane Addressing ................................................................................................................................ 98
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 107
Error Management ........................................................................................................................................ 108
Internal ECC and Spare Area Mapping for ECC ............................................................................................... 110
Electrical Specifications ................................................................................................................................. 112
Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 114
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 116
Electrical Specifications – Program/Erase Characteristics ................................................................................ 119
Asynchronous Interface Timing Diagrams ...................................................................................................... 120
Revision History ............................................................................................................................................ 132
Rev. R – 02/18 ............................................................................................................................................ 132
Rev. Q – 04/14 ............................................................................................................................................ 132
Rev. P – 02/14 ............................................................................................................................................ 132
Rev. O – 08/13 ............................................................................................................................................ 132
Rev. N – 10/12 ............................................................................................................................................ 132
Rev. M – 02/12 ........................................................................................................................................... 132
Rev. L – 1/12 .............................................................................................................................................. 132
Rev. K – 11/11 ............................................................................................................................................ 132
Rev. J – 09/11 ............................................................................................................................................. 132
Rev. I – 07/11 ............................................................................................................................................. 132
Rev. H – 12/10 ............................................................................................................................................ 133
Rev. G – 10/10 ............................................................................................................................................ 133
Rev. F – 06/10 ............................................................................................................................................ 133
Rev. E – 05/10 ............................................................................................................................................ 133
Rev. D – 03/10 ............................................................................................................................................ 133
Rev. C – 01/10 ............................................................................................................................................ 133
Rev. B – 10/09 ............................................................................................................................................ 133
Rev. A – 07/09 ............................................................................................................................................ 134
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Features
List of Tables
Table 1: Signal Definitions ............................................................................................................................... 9
Table 2: Array Addressing – MT29F4G08 (x8) .................................................................................................. 17
Table 3: Array Addressing – MT29F4G16 (x16) ................................................................................................. 18
Table 4: Array Addressing – MT29F8G08 and MT29F16G08 (x8) ....................................................................... 19
Table 5: Array Addressing – MT29F8G16 ( x16) ................................................................................................ 20
Table 6: Asynchronous Interface Mode Selection ............................................................................................ 21
Table 7: Command Set .................................................................................................................................. 32
Table 8: Two-Plane Command Set .................................................................................................................. 34
Table 9: READ ID Parameters for Address 00h ................................................................................................. 37
Table 10: READ ID Parameters for Address 20h ............................................................................................... 39
Table 11: Parameter Page Data Structure ........................................................................................................ 41
Table 12: Parameter Page Data Structure ........................................................................................................ 46
Table 13: Feature Address Definitions ............................................................................................................. 50
Table 14: Feature Address 90h – Array Operation Mode ................................................................................... 51
Table 15: Feature Addresses 01h: Timing Mode ............................................................................................... 53
Table 16: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 54
Table 17: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 54
Table 18: Status Register Definition ................................................................................................................ 55
Table 19: Block Lock Address Cycle Assignments ............................................................................................ 86
Table 20: Block Lock Status Register Bit Definitions ........................................................................................ 89
Table 21: Error Management Details ............................................................................................................. 108
Table 22: Absolute Maximum Ratings ............................................................................................................ 112
Table 23: Recommended Operating Conditions ............................................................................................. 112
Table 24: Valid Blocks ................................................................................................................................... 112
Table 25: Capacitance ................................................................................................................................... 113
Table 26: Test Conditions .............................................................................................................................. 113
Table 27: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 114
Table 28: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 115
Table 29: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 116
Table 30: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 116
Table 31: AC Characteristics: Normal Operation (3.3V) .................................................................................. 117
Table 32: AC Characteristics: Normal Operation (1.8V) .................................................................................. 117
Table 33: Program/Erase Characteristics ....................................................................................................... 119
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Features
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP – Type 1 (Top View) ...................................................................................................... 10
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 11
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 12
Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 13
Figure 6: 63-Ball VFBGA (10.5mm x 13mm) .................................................................................................... 14
Figure 7: 63-Ball VFBGA (9mm x 11mm) ......................................................................................................... 15
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 16
Figure 9: Array Organization – MT29F4G08 (x8) .............................................................................................. 17
Figure 10: Array Organization – MT29F4G16 (x16) .......................................................................................... 18
Figure 11: Array Organization – MT29F8G08 and MT29F16G08 (x8) ................................................................. 19
Figure 12: Array Organization – MT29F8G16 (x16) .......................................................................................... 20
Figure 13: Asynchronous Command Latch Cycle ............................................................................................ 22
Figure 14: Asynchronous Address Latch Cycle ................................................................................................ 23
Figure 15: Asynchronous Data Input Cycles .................................................................................................... 24
Figure 16: Asynchronous Data Output Cycles ................................................................................................. 25
Figure 17: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 26
Figure 18: READ/BUSY# Open Drain .............................................................................................................. 28
Figure 19: tFall and tRise (3.3V V CC) ................................................................................................................ 28
Figure 20: tFall and tRise (1.8V V CC) ................................................................................................................ 29
Figure 21: IOL vs. Rp (VCC = 3.3V V CC) .............................................................................................................. 29
Figure 22: IOL vs. Rp (1.8V V CC) ....................................................................................................................... 30
Figure 23: TC vs. Rp ....................................................................................................................................... 30
Figure 24: R/B# Power-On Behavior ............................................................................................................... 31
Figure 25: RESET (FFh) Operation .................................................................................................................. 35
Figure 26: READ ID (90h) with 00h Address Operation .................................................................................... 36
Figure 27: READ ID (90h) with 20h Address Operation .................................................................................... 36
Figure 28: READ PARAMETER (ECh) Operation .............................................................................................. 40
Figure 29: READ UNIQUE ID (EDh) Operation ............................................................................................... 49
Figure 30: SET FEATURES (EFh) Operation .................................................................................................... 51
Figure 31: GET FEATURES (EEh) Operation .................................................................................................... 52
Figure 32: READ STATUS (70h) Operation ...................................................................................................... 56
Figure 33: READ STATUS ENHANCED (78h) Operation ................................................................................... 57
Figure 34: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 58
Figure 35: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 59
Figure 36: RANDOM DATA INPUT (85h) Operation ........................................................................................ 60
Figure 37: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 62
Figure 38: READ PAGE (00h-30h) Operation ................................................................................................... 66
Figure 39: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 66
Figure 40: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 67
Figure 41: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 68
Figure 42: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 69
Figure 43: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 71
Figure 44: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 73
Figure 45: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 75
Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 75
Figure 47: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 76
Figure 48: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 78
Figure 49: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 79
Figure 50: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 81
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Features
Figure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 81
Figure 52: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 82
Figure 53: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 82
Figure 54: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 82
Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 83
Figure 56: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation .................................... 83
Figure 57: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 85
Figure 58: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 85
Figure 59: UNLOCK Operation ....................................................................................................................... 86
Figure 60: LOCK Operation ............................................................................................................................ 87
Figure 61: LOCK TIGHT Operation ................................................................................................................. 88
Figure 62: PROGRAM/ERASE Issued to Locked Block ...................................................................................... 89
Figure 63: BLOCK LOCK READ STATUS .......................................................................................................... 89
Figure 64: BLOCK LOCK Flowchart ................................................................................................................ 90
Figure 65: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 93
Figure 66: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ... 94
Figure 67: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 95
Figure 68: OTP DATA READ ........................................................................................................................... 96
Figure 69: OTP DATA READ with RANDOM DATA READ Operation ................................................................. 97
Figure 70: TWO-PLANE PAGE READ .............................................................................................................. 99
Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ ................................................................... 100
Figure 72: TWO-PLANE PROGRAM PAGE ...................................................................................................... 100
Figure 73: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 101
Figure 74: TWO-PLANE PROGRAM PAGE CACHE MODE ............................................................................... 102
Figure 75: TWO-PLANE INTERNAL DATA MOVE ........................................................................................... 103
Figure 76: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ............................ 104
Figure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT ............................................... 105
Figure 78: TWO-PLANE BLOCK ERASE ......................................................................................................... 106
Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ........................................................................ 106
Figure 80: Spare Area Mapping (x8) ............................................................................................................... 110
Figure 81: Spare Area Mapping (x16) ............................................................................................................. 111
Figure 82: RESET Operation .......................................................................................................................... 120
Figure 83: READ STATUS Cycle ..................................................................................................................... 120
Figure 84: READ STATUS ENHANCED Cycle .................................................................................................. 121
Figure 85: READ PARAMETER PAGE ............................................................................................................. 121
Figure 86: READ PAGE .................................................................................................................................. 122
Figure 87: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 123
Figure 88: RANDOM DATA READ .................................................................................................................. 124
Figure 89: READ PAGE CACHE SEQUENTIAL ................................................................................................ 125
Figure 90: READ PAGE CACHE RANDOM ...................................................................................................... 126
Figure 91: READ ID Operation ...................................................................................................................... 127
Figure 92: PROGRAM PAGE Operation .......................................................................................................... 127
Figure 93: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 128
Figure 94: PROGRAM PAGE Operation with RANDOM DATA INPUT .............................................................. 128
Figure 95: PROGRAM PAGE CACHE .............................................................................................................. 129
Figure 96: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 129
Figure 97: INTERNAL DATA MOVE ............................................................................................................... 130
Figure 98: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 130
Figure 99: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ................. 131
Figure 100: ERASE BLOCK Operation ............................................................................................................ 131
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Important Notes and Warnings
Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
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General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
See Internal ECC and Spare Area Mapping for ECC for more information.
Signal Descriptions
Table 1: Signal Definitions
Signal1 Type Description2

ALE Input Address latch enable: Loads an address from I/O[7:0] into the address register.
CE# Input Chip enable: Enables or disables one or more die (LUNs) in a target.
CE#2 For the 16Gb device, CE# controls the first 8Gb of memory; CE2# controls the second 8Gb
of memory.
CLE Input Command latch enable: Loads a command from I/O[7:0] into the command register.
LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the
BLOCK LOCK, connect LOCK to VSS during power-up, or leave it disconnected (internal
pull-down).
RE# Input Read enable: Transfers serial data from the NAND Flash to the host system.
WE# Input Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash.
WP# Input Write protect: Enables or disables array PROGRAM and ERASE operations.
I/O[7:0] (x8) I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and command infor-
I/O[15:0] (x16) mation.
R/B# Output Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.
R/B#2 This signal indicates target array activity.
For the 16Gb device, R/B# indicates the status of the first 8Gb of memory; R/B# indicates
the status of the second 8Gb of memory.
VCC Supply VCC: Core power supply
VSS Supply VSS: Core ground connection
NC – No connect: NCs are not internally connected. They can be driven or left unconnected.
DNU – Do not use: DNUs must be left unconnected.
Notes: 1. See Device and Array Organization for detailed signal connections.
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Signal Assignments
2. See Asynchronous Interface Bus Operation for detailed asynchronous interface signal
descriptions.
Signal Assignments
Figure 2: 48-Pin TSOP – Type 1 (Top View)
x16 x8 x8 x16
NC NC 1 48 VSS1 VSS
NC NC 2 47 DNU I/O15
NC NC 3 46 NC I/O14
NC NC 4 45 NC I/O13
NC NC 5 44 I/O7 I/O7
R/B#23 R/B2#3 6 43 I/O6 I/O6
R/B# R/B# 7 42 I/O5 I/O5
RE# RE# 8 41 I/O4 I/O4
CE# CE# 9 40 NC I/O12
CE2#3 CE2#3 10 39 VCC1 VCC
NC NC 11 38 DNU2 DNU2
VCC VCC 12 37 VCC VCC
VSS VSS 13 36 VSS VSS
NC NC 14 35 NC NC
NC NC 15 34 VCC1 VCC
CLE CLE 16 33 NC I/O11
ALE ALE 17 32 I/O3 I/O3
WE# WE# 18 31 I/O2 I/O2
WP# WP# 19 30 I/O1 I/O1
NC NC 20 29 I/O0 I/O0
NC NC 21 28 NC I/O10
NC NC 22 27 NC I/O9
NC NC 23 26 DNU I/O8
NC NC 24 25 VSS1 VSS
Notes: 1. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
2. For the 3V device, pin 38 is DNU. For the 1.8V device, pin 38 is LOCK.
3. R/B2# and CE2# are available on 16Gb devices only. They are NC for other configura-
tions.
PDF: 09005aef83b25735

Signal Assignments
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View)
1 2 3 4 5 6 7 8 9 10
A NC NC NC NC
B NC NC NC
C WP# ALE Vss CE# WE# R/B#
D Vcc2 RE# CLE NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC Vss2 NC
G DNU Vcc2 LOCK1 NC NC DNU
H NC I/O0 NC NC NC Vcc
J NC I/O1 NC Vcc I/O5 I/O7
K Vss I/O2 I/O3 I/O4 I/O6 Vss
L NC NC NC NC
M NC NC NC NC
Notes: 1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V de-
vice.
2. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
PDF: 09005aef83b25735

Signal Assignments
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)
1 2 3 4 5 6 7 8 9 10
A NC NC NC NC
B NC NC NC
C WP# ALE Vss CE# WE# R/B#
D Vcc RE# CLE NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC Vss NC
G DNU Vcc LOCK1 I/O13 I/O15 DNU
H I/O8 I/O0 I/O10 I/O12 I/O14 Vcc
J I/O9 I/O1 I/O11 Vcc I/O5 I/O7
K Vss I/O2 I/O3 I/O4 I/O6 Vss
L NC NC NC NC
M NC NC NC NC
Note: 1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V de-
vice.
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Package Dimensions
Package Dimensions
Figure 5: 48-Pin TSOP – Type 1, CPL
0.25 Mold compound:

20.00 ±0.25 for reference only Epoxy novolac
0.50 TYP Plated lead finish:
18.40 ±0.08 for reference 100% Sn
48 only
1
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
12.00 ±0.08
0.27 MAX
0.17 MIN
24 25
0.25
0.10 Gage
+0.03 plane
0.15 See detail A
-0.02
1.20 MAX +0.10
0.10
-0.05
0.50 ±0.1
0.80
Detail A
Note: 1. All dimensions are in millimeters.
PDF: 09005aef83b25735

Package Dimensions
Figure 6: 63-Ball VFBGA (10.5mm x 13mm)
0.65 ±0.05
Seating
plane
A
0.12 A
63X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu). Ball A1 ID Ball A1 ID
Dimensions apply to 10 9 8 7 6 5 4 3 2 1
solder balls post-
reflow on Ø0.4 SMD
ball pads.
A
B
C
D
E
F
8.8 CTR 13 ±0.1
G
H
J
K
L
0.8 TYP
M
0.8 TYP 1.0 MAX

7.2 CTR 0.25 MIN
10.5 ±0.1 Bottom side saw fiducials may or

may not be covered with soldermask.
PDF: 09005aef83b25735

Package Dimensions
Figure 7: 63-Ball VFBGA (9mm x 11mm)
Seating
plane
A
0.1 A
63X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.4 SMD
ball pads. Ball A1 ID
Solder ball material: (covered by SR) Ball A1 ID
10 9 8 7 6 5 4 3 2 1
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
A
B
C
D
E
F
8.8 CTR 11 ±0.1
G
H
J
K
L
0.8 TYP
M
0.8 TYP 1.0 MAX
7.2 CTR 0.25 MIN
9 ±0.1
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Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row de-
coder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word
by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput. The status register reports
the status of die operations.
Figure 8: NAND Flash Die (LUN) Functional Block Diagram
VCC VSS
I/Ox I/O
control Address register
Status register
Command register
CE#
CLE Column decode
ALE Control
Row decode
WE# logic NAND Flash

RE# array
WP# (2 planes)
LOCK1
Data register
R/B#
Cache register
ECC
Note: 1. The LOCK pin is used on the 1.8V device.
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Device and Array Organization
Figure 9: Array Organization – MT29F4G08 (x8)
2112 bytes 2112 bytes

DQ7
Cache Register 2048 2048
64 64 DQ0
Data Register 2048 64 2048 64
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 64 pages

2048 blocks
= (128K + 4K) bytes
per plane 1 block 1 block
1 plane = (128K + 4K) bytes x 2048 blocks
4096 blocks
= 2112Mb
per device
1 device = 2112Mb x 2 planes
= 4224Mb
Plane of Plane of
even-numbered blocks odd-numbered blocks
(0, 2, 4, 6, ..., 4092, 4094) (1, 3, 5, 7, ..., 4093, 4095)
Table 2: Array Addressing – MT29F4G08 (x8)
Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Fifth LOW LOW LOW LOW LOW LOW BA17 BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column ad-
dress; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be 0.
3. BA6 controls plane selection.
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1056 words 1056 words

DQ15
Cache Register 1024 32 1024 32 DQ0
Data Register 1024 32 1024 32
1 page = (1K + 32 words)
1 block = (1K + 32) words x 64 pages

2048 blocks = (64K + 2K) words
per plane 1 block 1 block
1 plane = (64K + 2K) words x 2048 blocks
4096 blocks = 2112Mb
per device
1 device = 2112Mb x 2 planes
= 4224Mb
Plane of Plane of
even-numbered blocks odd-numbered blocks
(0, 2, 4, 6, ..., 4092, 4094) (1, 3, 5, 7, ..., 4093, 4095)
Table 3: Array Addressing – MT29F4G16 (x16)
Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00
First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8
Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Fifth LOW LOW LOW LOW LOW LOW LOW BA17 BA16
2. If CA10 = 1, then CA[9:5] must be 0.
3. BA6 controls plane selection.
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Figure 11: Array Organization – MT29F8G08 and MT29F16G08 (x8)
Die 0 Die 1
2112 bytes 2112 bytes 2112 bytes 2112 bytes

I/O7
Cache Register 2048 64 2048 64 2048 64 2048 64 I/O0
Data Register 2048 64 2048 64 2048 64 2048 64

1 page = (2K + 64 bytes)
2048 blocks 1 block = (2K + 64) bytes x 64 pages

per plane = (128K + 4K) bytes
1 block 1 block 1 block 1 block
per die
1 die = 2112Mb x 2 planes
= 4224Mb
1 device = 4224Mb x 2 die

Plane 0: even- Plane 1: odd- Plane 0: even- Plane 1: odd-
= 8448Mb
numbered blocks numbered blocks numbered blocks numbered blocks
(0, 2, 4, 6, ..., (1, 3, 5, 7, ..., (4096, 4098, ..., (4097, 4099, ...,
4092, 4094)1 4093, 4095) 8188, 8190) 8189, 8191)
Note: 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1.

Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1.
Table 4: Array Addressing – MT29F8G08 and MT29F16G08 (x8)
Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Fifth LOW LOW LOW LOW LOW BA183 BA17 BA16
Notes: 1. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be 0.
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
PDF: 09005aef83b25735

Die 0 Die 1
1056 words 1056 words 1056 words 1056 words

I/O7
Cache Register 1024 32 1024 32 1024 32 1024 32 I/O0
Data Register 1024 32 1024 32 1024 32 1024 32

1 page = (1K + 32 words)
2048 blocks 1 block = (1K + 32) words x 64 pages

per plane = (64K + 2K) words
1 block 1 block 1 block 1 block
per die
1 die = 2112Mb x 2 planes
= 4224Mb
1 device = 4224Mb x 2 die

Plane 0: even- Plane 1: odd- Plane 0: even- Plane 1: odd-
= 8448Mb
numbered blocks numbered blocks numbered blocks numbered blocks
(0, 2, 4, 6, ..., (1, 3, 5, 7, ..., (4096, 4098, ..., (4097, 4099, ...,
4092, 4094)1 4093, 4095) 8188, 8190) 8189, 8191)
Note: 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1.

Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1.
Table 5: Array Addressing – MT29F8G16 ( x16)
Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/O0
First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8
Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 PA8
Fifth LOW LOW LOW LOW LOW LOW BA183 BA17 BA16
2. If CA10 = 1, then CA[9:5] must be 0.
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
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Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the
same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and
commands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address input
cycles, and one or more data cycles, either READ or WRITE.
Table 6: Asynchronous Interface Mode Selection
Mode1 CE# CLE ALE WE# RE# I/Ox WP#

Standby2 H X X X X X 0V/VCC
Command input L H L H X H
Address input L L H H X H
Data input L L L H X H
Data output L L L H X X
Write protect X X X X X X L
Notes: 1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
2. WP# should be biased to CMOS LOW or HIGH for standby.
Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the ris-
ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a command
is issued.
PDF: 09005aef83b25735

Figure 13: Asynchronous Command Latch Cycle
CLE
tCLS tCLH
tCS tCH
CE#
tWP
WE#
tALS tALH
ALE
tDS tDH
I/Ox COMMAND
Don’t Care
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Asynchronous Addresses
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, like ad-
dress cycles that follow the READ STATUS ENHANCED (78h) command.
Figure 14: Asynchronous Address Latch Cycle
CLE
tCLS
tCS
CE#
tWC
tWP tWH
WE#
tALS
tALH
ALE
tDS tDH
I/Ox Col Col Row Row Row

add 1 add 2 add 1 add 2 add 3
Don’t Care Undefined
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Asynchronous Data Input

Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is
written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW,
and the device is not busy.
Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
Figure 15: Asynchronous Data Input Cycles
CLE
tCLH
CE#
tALS tCH
ALE
tWC
tWP tWP tWP
WE#
tWH
tDS tDH tDS tDH tDS tDH
I/Ox DIN M DIN M+1 DIN N
Don’t Care
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Asynchronous Data Output

Data can be output from a die (LUN) if it is in a READY state. Data output is supported
following a READ operation from the NAND Flash array. Data is output from the cache
register of the selected die (LUN) to I/O[7:0] on the falling edge of RE# when CE# is
LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.
If the host controller is using a tRC of 30ns or greater, the host can latch the data on the
rising edge of RE# (see the figure below for proper timing). If the host controller is using
a tRC of less than 30ns, the host can latch the data on the next falling edge of RE#.
Using the READ STATUS ENHANCED (78h) command prevents data contention follow-
ing an interleaved die (multi-LUN) operation. After issuing the READ STATUS EN-
HANCED (78h) command, to enable data output, issue the READ MODE (00h) com-
mand.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-
er, it is possible to output data from the status register even when a die (LUN) is busy by
first issuing the READ STATUS or READ STATUS ENHANCED (78h) command.
Figure 16: Asynchronous Data Output Cycles
tCEA
CE#
tCHZ
tREA tREA tREA
tRP tREH tCOH
RE#
tRHZ tRHZ
tRHOH
I/Ox DOUT DOUT DOUT
tRR tRC
RDY
Don’t Care
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Figure 17: Asynchronous Data Output Cycles (EDO Mode)
CE#
tRC tCHZ
tRP tREH tCOH
RE#
tREA tREA tRHZ
tCEA tRLOH tRHOH
I/Ox DOUT DOUT DOUT
tRR
RDY
Don’t Care
Write Protect#
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations
to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When
WP# is HIGH, PROGRAM and ERASE operations are enabled. When WP# is LOW or tog-
gled LOW during a READ operation, read will be performed as normal. It is recommen-
ded that the host drive WP# LOW during power-on until V CC is stable to prevent inad-
vertent PROGRAM and ERASE operations (see Device Initialization for additional de-
tails).
If WP# is toggled during PROGRAM or ERASE (while RB# is LOW), then the following
will occur
• The PROGRAM or ERASE operation is aborted
• In asynchronous mode, toggling WP# LOW during a NAND PROGRAM or ERASE op-
eration will act like a RESET (FFh) command. In synchronous mode, it will act like a
SYNCHRONOUS RESET (FCh) command
• The data that was being programmed or erased (targeted page or block) is not valid
anymore
• The status register will be set to 60h until a RESET, new operation, or new power up
command is given
After a command sequence is complete and the target is ready, WP# can be transi-
tioned. After WP# is transitioned, the host must wait tWW before issuing a new com-
mand.
The WP# signal is always an active input, even when CE# is HIGH. This signal should
not be multiplexed with other signals.
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Ready/Busy#
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-
get is ready or busy. A target is busy when one or more of its die (LUNs) are busy
(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each
die (LUN) contains a status register, it is possible to determine the independent status
of each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-
tus Operations for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an
interrupt pin on the system controller.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing re-
quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10%
and 90% points on the R/B# waveform, the rise time is approximately two time con-
stants (TC).
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 23 (page 30).
The minimum value for Rp is determined by the output drive capability of the R/B# sig-
nal, the output voltage swing, and V CC.
V (MAX) - VOL (MAX)

Rp = CC
IOL + ΣIL
Where ΣIL is the sum of the input currents of all devices tied to the R/B# pin.
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Figure 18: READ/BUSY# Open Drain
Rp
VCC
R/B#
Open drain output
IOL
VSS
Device
Figure 19: tFall and tRise (3.3V VCC)
3.50
3.00
2.50 tFall tRise

2.00
V
1.50
1.00
0.50
0.00
–1 0 2 4 0 2 4 6
TC VCC 3.3V
Notes: 1. tFall and tRise calculated at 10% and 90% points.

2. tRise dependent on external capacitance and resistive loading and output transistor im-
pedance.
3. tRise primarily dependent on external pull-up resistor and external capacitive loading.
4. tFall = 10ns at 3.3V.
5. See TC values in Figure 23 (page 30) for approximate Rp value and TC.
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Figure 20: tFall and tRise (1.8V VCC)
3.50
3.00
2.50
tFall tRise
2.00
V
1.50
1.00
0.50
0.00
-1 0 2 4 0 2 4 6
TC VCC1.8V
1. tFall and tRise are calculated at 10% and 90% points.

Notes:
2. tRise is primarily dependent on external pull-up resistor and external capacitive loading.
3. tFall ≈ 7ns at 1.8V.
4. See TC values in Figure 23 (page 30) for TC and approximate Rp value.
Figure 21: IOL vs. Rp (VCC = 3.3V VCC)

3.50
3.00
2.50
2.00
I (mA)
1.50
1.00
0.50
0.00
0 2000 400 0 6000 8000 10,000 12,000
Rp (Ω)
IOL at VCC (MAX)
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Figure 22: IOL vs. Rp (1.8V VCC)

3.50
3.00
2.50
2.00
I (mA)
1.50
1.00
0.50
0.00
0 2000 4000 6000 8000 10,000 12,000
Rp (Ω)
IOL at VCC (MAX)
Figure 23: TC vs. Rp
1200
1000
800
TC (ns)
600
400
200
0
0 2000 4000 6000 8000 10,000 12,000
Rp (W) IOL at VCC (MAX)
RC = TC
C = 100pF
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Device Initialization
Device Initialization
Micron NAND Flash devices are designed to prevent data corruption during power
transitions. V CC is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping V CC, use the following procedure
to initialize the device:
1. Ramp V CC.
2. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target. The R/B# signal becomes valid when 50µs has elapsed since the begin-
ning the V CC ramp, and 10µs has elapsed since V CC reaches V CC,min.
3. If not monitoring R/B#, the host must wait at least 100µs after V CC reaches V CC,min.
If monitoring R/B#, the host must wait until R/B# is HIGH.
4. The asynchronous interface is active by default for each target. Each LUN draws
less than an average of 10mA (IST) measured over intervals of 1ms until the RESET
(FFh) command is issued.
5. The RESET (FFh) command must be the first command issued to all targets (CE#s)
after the NAND Flash device is powered on. Each target will be busy for 1ms after a
RESET command is issued. The RESET busy time can be monitored by polling
R/B# or issuing the READ STATUS (70h) command to poll the status register.
6. The device is now initialized and ready for normal operation.
Figure 24: R/B# Power-On Behavior
50µs (MIN)
VCC = VCC (MIN)

VCC
10µs
(MAX)
R/B#
VCC ramp 100µs (MAX) Reset (FFh)

starts is issued
Invalid
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Command Definitions
Command Definitions
Table 7: Command Set
Number of
Valid Data Valid While Valid While
Command Address Input Command Selected LUN Other LUNs
Command Cycle #1 Cycles Cycles Cycle #2 is Busy1 are Busy2 Notes
Reset Operations
RESET FFh 0 – – Yes Yes
Identification Operation
READ ID 90h 1 – – No No
READ PARAMETER PAGE ECh 1 – – No No
READ UNIQUE ID EDh 1 – – No No
Feature Operations
GET FEATURES EEh 1 – – No No
SET FEATURES EFh 1 4 – No No
Status Operations
READ STATUS 70h 0 – – Yes
READ STATUS EN- 78h 3 – – Yes Yes
HANCED
Column Address Operations
RANDOM DATA READ 05h 2 – E0h No Yes
RANDOM DATA INPUT 85h 2 Optional – No Yes
PROGRAM FOR 85h 5 Optional – No Yes 3
INTERNAL DATA MOVE
READ OPERATIONS
READ MODE 00h 0 – – No Yes
READ PAGE 00h 5 – 30h No Yes
READ PAGE CACHE SE- 31h 0 – – No Yes 4, 5
QUENTIAL
READ PAGE CACHE 00h 5 – 31h No Yes 4, 5
RANDOM
READ PAGE CACHE LAST 3Fh 0 – – No Yes 4, 5
Program Operations
PROGRAM PAGE 80h 5 Yes 10h No Yes
PROGRAM PAGE CACHE 80h 5 Yes 15h No Yes 4, 6
Erase Operations
ERASE BLOCK 60h 3 – D0h No Yes
Internal Data Move Operations
READ FOR INTERNAL 00h 5 – 35h No Yes 3
DATA MOVE
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Command Definitions
Table 7: Command Set (Continued)
Number of
Valid Data Valid While Valid While
Command Address Input Command Selected LUN Other LUNs
Command Cycle #1 Cycles Cycles Cycle #2 is Busy1 are Busy2 Notes
PROGRAM FOR INTER- 85h 5 Optional 10h No Yes
NAL DATA MOVE
Block Lock Operations
BLOCK UNLOCK LOW 23h 3 – – No Yes
BLOCK UNLOCK HIGH 24h 3 – – No Yes
BLOCK LOCK 2Ah – – – No Yes
BLOCK LOCK-TIGHT 2Ch – – – No Yes
BLOCK LOCK READ 7Ah 3 – – No Yes
STATUS
One-Time Programmable (OTP) Operations
OTP DATA LOCK BY 80h 5 No 10h No No 7
PAGE (ONFI)
OTP DATA PROGRAM 80h 5 Yes 10h No No 7
(ONFI)
OTP DATA READ (ONFI) 00h 5 No 30h No No 7
Notes: 1. Busy means RDY = 0.

2. These commands can be used for interleaved die (multi-LUN) operations (see Interleaved
Die (Multi-LUN) Operations (page 107)).
3. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and
PROGRAM for INTERNAL DATA MOVE.
4. These commands supported only with ECC disabled.
5. Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy
(RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h)
or READ PAGE CACHE series command; otherwise, it is prohibited.
6. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE
(80h-15h) command; otherwise, it is prohibited.
7. OTP commands can be entered only after issuing the SET FEATURES command with the
feature address.
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Command Definitions
Table 8: Two-Plane Command Set

Note 4 applies to all parameters and conditions
Number of Number of
Com- Valid Com- Valid Com- Valid While Valid While
mand Address mand Address mand Selected Other LUNs
Command Cycle #1 Cycles Cycle #2 Cycles Cycle #3 LUN is Busy are Busy Notes
READ PAGE TWO- 00h 5 00h 5 30h No Yes
PLANE
READ FOR TWO- 00h 5 00h 5 35h No Yes 1
PLANE INTERNAL
DATA MOVE
RANDOM DATA 06h 5 E0h – – No Yes 2
READ TWO-PLANE
PROGRAM PAGE 80h 5 11h-80h 5 10h No Yes
TWO-PLANE
PROGRAM PAGE 80h 5 11h-80h 5 15h No Yes
CACHE MODE TWO-
PLANE
PROGRAM FOR 85h 5 11h-85h 5 10h No Yes 1
TWO-PLANE INTER-
NAL DATA MOVE
BLOCK ERASE TWO- 60h 3 D1h-60h 3 D0h No Yes 3
PLANE
Notes: 1. Do not cross plane boundaries when using READ FOR INTERNAL DATA MOVE TWO-
PLANE or PROGRAM FOR TWO-PLANE INTERNAL DATA MOVE.
2. The RANDOM DATA READ TWO-PLANE command is limited to use with the PAGE READ
TWO-PLANE command.
3. D1h command can be omitted.
4. These commands supported only with ECC disabled.
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Reset Operations
Reset Operations
RESET (FFh)
The RESET command is used to put the memory device into a known condition and to
abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy
state. The contents of the memory location being programmed or the block being
erased are no longer valid. The data may be partially erased or programmed, and is in-
valid. The command register is cleared and is ready for the next command. The data
register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the
command register.
The RESET command must be issued to all CE#s as the first command after power-on.
The device will be busy for a maximum of 1ms.
Figure 25: RESET (FFh) Operation
Cycle type Command
I/O[7:0] FF
tWB tRST
R/B#
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Identification Operations
Identification Operations
READ ID (90h)
The READ ID (90h) command is used to read identifier codes programmed into the tar-
get. This command is accepted by the target only when all die (LUNs) on the target are
idle.
Writing 90h to the command register puts the target in read ID mode. The target stays in
this mode until another valid command is issued.
When the 90h command is followed by an 00h address cycle, the target returns a 5-byte
identifier code that includes the manufacturer ID, device configuration, and part-spe-
cific information.
When the 90h command is followed by a 20h address cycle, the target returns the 4-byte
ONFI identifier code.
Figure 26: READ ID (90h) with 00h Address Operation
Cycle type Command Address DOUT DOUT DOUT DOUT DOUT

tWHR
I/O[7:0] 90h 00h Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Note: 1. See READ ID Parameter tables for byte definitions.
Figure 27: READ ID (90h) with 20h Address Operation
Cycle type Command Address DOUT DOUT DOUT DOUT

tWHR
I/O[7:0] 90h 20h 4Fh 4Eh 46h 49h
Note: 1. See READ ID Parameter tables for byte definitions.
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READ ID Parameter Tables
Table 9: READ ID Parameters for Address 00h

b = binary; h = hexadecimal
Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value
Byte 0 – Manufacturer ID
Manufacturer Micron 0 0 1 0 1 1 0 0 2Ch
Byte 1 – Device ID
MT29F4G08ABADA 4Gb, x8, 3.3V 1 1 0 1 1 1 0 0 DCh
MT29F4G16ABADA 4Gb, x16, 3.3V 1 1 0 0 1 1 0 0 CCh
MT29F4G08ABBDA 4Gb, x8, 1.8V 1 0 1 0 1 1 0 0 ACh
MT29F4G16ABBDA 4Gb, x16, 1.8V 1 0 1 1 1 1 0 0 BCh
MT29F8G08ADBDA 8Gb, x8, 1.8V 1 0 1 0 0 0 1 1 A3h
MT29F8G16ADBDA 8Gb, x16, 1.8V 1 0 1 1 0 0 1 1 B3h
MT29F8G08ADADA 8Gb, x8, 3.3V 1 1 0 1 0 0 1 1 D3h
MT29F8G16ADADA 8Gb, x16, 3.3V 1 1 0 0 0 0 1 1 C3h
MT29F16G08AJADA 16Gb, x8, 3.3V 1 1 0 1 0 0 1 1 D3h
Byte 2
Number of die per CE 1 0 0 00b
2 0 1 01b
Cell type SLC 0 0 00b
Number of simultaneously 2 0 1 01b
programmed pages
Interleaved operations be- Not supported 0 0b
tween multiple die
Cache programming Supported 1 1b
Byte value MT29F4G08ABADA 1 0 0 1 0 0 0 0 90h
MT29F4G16ABADA 1 0 0 1 0 0 0 0 90h
MT29F4G08ABBDA 1 0 0 1 0 0 0 0 90h
MT29F4G16ABBDA 1 0 0 1 0 0 0 0 90h
MT29F8G08ADBDA 1 1 0 1 0 0 0 1 D1h
MT29F8G16ADBDA 1 1 0 1 0 0 0 1 D1h
MT29F8G08ADADA 1 1 0 1 0 0 0 1 D1h
MT29F8G16ADADA 1 1 0 1 0 0 0 1 D1h
MT29F16G08AJADA 1 1 0 1 0 0 0 1 D1h
Byte 3
Page size 2KB 0 1 01b
Spare area size (bytes) 64B 1 1b
Block size (without spare) 128KB 0 1 01b
Organization x8 0 0b
x16 1 1b
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Table 9: READ ID Parameters for Address 00h (Continued)

b = binary; h = hexadecimal
Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value
Serial access 1.8V 25ns 0 0 0xxx0b
(MIN) 3.3V 20ns 1 0 1xxx0b
MT29F4G16ABADA 1 1 0 1 0 1 0 1 D5h
MT29F4G08ABBDA 0 0 0 1 0 1 0 1 15h
MT29F4G16ABBDA 0 1 0 1 0 1 0 1 55h
MT29F8G08ADBDA 0 0 0 1 0 1 0 1 15h
MT29F8G16ADBDA 0 1 0 1 0 1 0 1 55h
MT29F8G08ADADA 1 0 0 1 0 1 0 1 95h
MT29F8G16ADADA 1 1 0 1 0 1 0 1 D5h
MT29F16G08AJADA 1 0 0 1 0 1 0 1 95h
Byte 4
Internal ECC level 4-bit ECC/512 (main) + 1 0 10b
4 (spare) + 8 (parity)
bytes
Planes per CE# 2 0 1 01b
4 1 0 10b
Plane size 2Gb 1 0 1 101b
Internal ECC ECC disabled 0 0b
ECC enabled 1 1b
MT29F4G16ABADA 0 1 0 1 0 1 1 0 56h
MT29F4G08ABBDA 0 1 0 1 0 1 1 0 56h
MT29F4G16ABBDA 0 1 0 1 0 1 1 0 56h
MT29F8G08ADBDA 0 1 0 1 1 0 1 0 5Ah
MT29F8G16ADBDA 0 1 0 1 1 0 1 0 5Ah
MT29F8G08ADADA 0 1 0 1 1 0 1 0 5Ah
MT29F8G16ADADA 0 1 0 1 1 0 1 0 5Ah
MT29F16G08AJADA 0 1 0 1 1 0 1 0 5Ah
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Table 10: READ ID Parameters for Address 20h

h = hexadecimal
Byte Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value
0 “O” 0 1 0 0 1 1 1 1 4Fh
1 “N” 0 1 0 0 1 1 1 0 4Eh
2 “F” 0 1 0 0 0 1 1 0 46h
3 “I” 0 1 0 0 1 0 0 1 49h
4 Undefined X X X X X X X X XXh
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READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE (ECh)

The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page
programmed into the target. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing ECh to the command register puts the target in read parameter page mode. The
target stays in this mode until another valid command is issued.
When the ECh command is followed by an 00h address cycle, the target goes busy for tR.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode. Use of the
READ STATUS ENHANCED (78h) command is prohibited while the target is busy and
during data output.
To insure data integrity, x8 devices contain at least eight copies of the parameter page,
and x16 devices contain at least four copies of the parameter page. Each parameter
page is 256 bytes. If the initial READ PARAMETER PAGE (ECh) command fails to retrieve
a correct copy of the parameter page, the command can be reissued until a correct copy
is retrieved. If desired, the RANDOM DATA READ (05h-E0h) command can be used to
change the location of data output.
Figure 28: READ PARAMETER (ECh) Operation
Cycle type Command Address DOUT DOUT DOUT DOUT DOUT DOUT
I/O[7:0] ECh 00h P00 P10 … P01 P11 …

tWB tR tRR
R/B#
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Parameter Page Data Structure Tables
Table 11: Parameter Page Data Structure
Byte Description Value

0–3 Parameter page signature 4Fh, 4Eh, 46h, 49h
4–5 Revision number 02h, 00h
6–7 Features supported MT29F4G08ABBDAH4 18h, 00h
MT29F4G08ABBDAHC 18h, 00h
MT29F4G16ABBDAHC 19h, 00h
MT29F4G16ABBDAH4 19h, 00h
MT29F8G08ADBDAH4 1Ah, 00h
MT29F8G16ADBDAH4 1Bh, 00h
MT29F4G08ABADAWP 18h, 00h
MT29F4G08ABADAH4 18h, 00h
MT29F4G16ABADAWP 19h, 00h
MT29F4G16ABADAH4 19h, 00h
MT29F8G08ADADAH4 1Ah, 00h
MT29F8G16ADADAH4 1Bh, 00h
MT29F16G08AJADAWP 1Ah, 00h
8–9 Optional commands supported 3Fh, 00h
10–31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
32–43 Device manufacturer 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h,
20h
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Table 11: Parameter Page Data Structure (Continued)

44–63 Device model MT29F4G08ABBDAH4 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F4G08ABBDAHC 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h
MT29F4G16ABBDAHC 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h
MT29F4G16ABBDAH4 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F8G08ADBDAH4 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h,
42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F8G16ADBDAH4 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h,
42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F4G08ABADAWP 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 20
MT29F4G08ABADAH4 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F4G16ABADAWP 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 20h
MT29F4G16ABADAH4 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F8G08ADADAH4 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h,
41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F8G16ADADAH4 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h,
41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F16G08AJADAWP 4Dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 41h,
4Ah, 41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h
64 Manufacturer ID 2Ch
65–66 Date code 00h, 00h
00h, 00h
80–83 Number of data bytes per page 00h, 08h, 00h, 00h
84–85 Number of spare bytes per page 40h, 00h
86–89 Number of data bytes per partial page 00h, 02h, 00h, 00h
90–91 Number of spare bytes per partial page 10h, 00h
92–95 Number of pages per block 40h, 00h, 00h, 00h
96–99 Number of blocks per unit 00h, 10h, 00h, 00h
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100 Number of logical units MT29F4G08ABBDAH4 01h
MT29F4G08ABBDAHC 01h
MT29F4G16ABBDAHC 01h
MT29F4G16ABBDAH4 01h
MT29F8G08ADBDAH4 02h
MT29F4G08ABADAWP 01h
MT29F4G08ABADAH4 01h
MT29F4G16ABADAWP 01h
MT29F4G16ABADAH4 01h
MT29F8G08ADADAH4 02h
MT29F16G08AJADAWP 04h
101 Number of address cycles 23h
102 Number of bits per cell 01h
103–104 Bad blocks maximum per unit 50h, 00h
105–106 – –
107 Guaranteed valid blocks at beginning of target 01h
108–109 Block endurance for guaranteed valid blocks 00h, 00h
110 Number of programs per page 04h
111 Partial programming attributes 00h
112 Number of bits ECC bits 04h
113 Number of interleaved address bits 01h
114 Interleaved operation attributes 0Eh
00h, 00h
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128 I/O pin capacitance MT29F4G08ABBDAH4 0Ah
MT29F4G08ABBDAHC 0Ah
MT29F4G16ABBDAHC 0Ah
MT29F4G16ABBDAH4 0Ah
MT29F4G08ABADAWP 0Ah
MT29F4G08ABADAH4 0Ah
MT29F4G16ABADAWP 0Ah
MT29F4G16ABADAH4 0Ah
MT29F16G08AJADAWP 28h
129–130 Timing mode support MT29F4G08ABBDAH4 1Fh, 00h
MT29F4G08ABBDAHC 1Fh, 00h
MT29F4G16ABBDAH4 1Fh, 00h
MT29F8G08ADBDAH4 1Fh, 00h
MT29F4G08ABADAWP 3Fh, 00h
MT29F4G08ABADAH4 3Fh, 00h
MT29F8G08ADADAH4 3Fh, 00h
MT29F16G08AJADAWP 3Fh, 00h
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131–132 Program cache timing MT29F4G08ABBDAH4 1Fh, 00h
mode support MT29F4G08ABBDAHC 1Fh, 00h
MT29F4G16ABBDAH4 1Fh, 00h
MT29F16G08AJADAWP 3Fh, 00h
133–134 tPROG (MAX) page program time 58h, 02h
135–136 tBERS (MAX) block erase time B8h, 0Bh
137–138 tR (MAX) page read time 19h, 00h
139–140 tCCs (MIN) 64h, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164–165 Vendor-specific revision number 01h, 00h
166–253 Vendor-specific 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h,
01h,0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h
254–255 Integrity CRC Set at test
256–511 Value of bytes 0–255
768+ Additional redundant parameter pages
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NAND Component Parameter Page Data Structure Tables
Table 12: Parameter Page Data Structure

0–3 Parameter page signature 4Fh, 4Eh, 46h, 49h
4–5 Revision number 02h, 00h
6–7 Features supported MT29F4G08ABBDA3W 18h, 00h
MT29F4G16ABBDA3W 19h, 00h
MT29F8G08ADBDA3W 1Ah, 00h
MT29F8G16ADBDA3W 1Bh, 00h
MT29F4G08ABADA3W 18h, 00h
MT29F4G16ABADA3W 19h, 00h
MT29F8G08ADADA3W 1Ah, 00h
MT29F8G16ADADA3W 1Bh, 00h
8–9 Optional commands supported 3Fh, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
32–43 Device manufacturer 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h,
20h
44–63 Device model MT29F4G08ABBDA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G16ABBDA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F8G08ADBDA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h,
42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F8G16ADBDA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h,
42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G08ABADA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G16ABADA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F8G08ADADA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h,
41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F8G16ADADA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h,
41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
64 Manufacturer ID 2Ch
65–66 Date code 00h, 00h
00h, 00h
80–83 Number of data bytes per page 00h, 08h, 00h, 00h
84–85 Number of spare bytes per page 40h, 00h
86–89 Number of data bytes per partial page 00h, 02h, 00h, 00h
90–91 Number of spare bytes per partial page 10h, 00h
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92–95 Number of pages per block 40h, 00h, 00h, 00h
96–99 Number of blocks per unit 00h, 10h, 00h, 00h
100 Number of logical units MT29F4G08ABBDA3W 01h
MT29F4G16ABBDA3W 01h
MT29F8G08ADBDA3W 02h
MT29F4G08ABADA3W 01h
MT29F4G16ABADA3W 01h
MT29F8G08ADADA3W 02h
101 Number of address cycles 23h
102 Number of bits per cell 01h
103–104 Bad blocks maximum per unit 50h, 00h
105–106 Block endurance 01h, 05h
107 Guaranteed valid blocks at beginning of target 01h
108–109 Block endurance for guaranteed valid blocks 00h, 00h
110 Number of programs per page 04h
111 Partial programming attributes 00h
112 Number of bits ECC bits 04h
113 Number of interleaved address bits 01h
114 Interleaved operation attributes 0Eh
00h, 00h
128 I/O pin capacitance MT29F4G08ABBDA3W 0Ah
MT29F4G16ABBDA3W 0Ah
MT29F4G08ABADA3W 0Ah
MT29F4G16ABADA3W 0Ah
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129–130 Timing mode support MT29F4G08ABBDA3W 1Fh, 00h
MT29F4G16ABBDA3W 1Fh, 00h
MT29F8G08ADBDA3W 1Fh, 00h
MT29F4G08ABADA3W 3Fh, 00h
MT29F8G08ADADA3W 3Fh, 00h
131–132 Program cache timing MT29F4G08ABBDA3W 1Fh, 00h
mode support MT29F4G16ABBDA3W 1Fh, 00h
133–134 tPROG (MAX) page program time 58h, 02h
135–136 tBERS (MAX) block erase time B8h, 0Bh
137–138 tR (MAX) page read time 19h, 00h
139–140 tCCs (MIN) 64h, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164–165 Vendor-specific revision number 01h, 00h
166–253 Vendor-specific 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h,
01h,0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h
254–255 Integrity CRC Set at test
768+ Additional redundant parameter pages
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READ UNIQUE ID (EDh)
READ UNIQUE ID (EDh)

The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed
into the target. This command is accepted by the target only when all die (LUNs) on the
target are idle.
Writing EDh to the command register puts the target in read unique ID mode. The tar-
get stays in this mode until another valid command is issued.
When the EDh command is followed by an 00h address cycle, the target goes busy for
tR.If the READ STATUS (70h) command is used to monitor for command completion,
the READ MODE (00h) command must be used to re-enable data output mode.
After tR completes, the host enables data output mode to read the unique ID. When the
asynchronous interface is active, one data byte is output per RE# toggle.
Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The
first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple-
ment of the first 16 bytes. The host should XOR the first 16 bytes with the second 16
bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In
the event that a non-FFh result is returned, the host can repeat the XOR operation on a
subsequent copy of the unique ID data. If desired, the RANDOM DATA READ (05h-E0h)
command can be used to change the data output location.
The upper eight I/Os on a x16 device are not used and are a “Don’t Care” for x16 devi-
ces.
Figure 29: READ UNIQUE ID (EDh) Operation
Cycle type Command Address DOUT DOUT DOUT DOUT DOUT DOUT
I/O[7:0] EDh 00h U00 U10 … U01 U11 …

tWB tR tRR
R/B#
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Feature Operations
Feature Operations
The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the
target's default power-on behavior. These commands use a one-byte feature address to
determine which subfeature parameters will be read or modified. Each feature address
(in the 00h to FFh range) is defined in below. The SET FEATURES (EFh) command
writes subfeature parameters (P1–P4) to the specified feature address. The GET FEA-
TURES command reads the subfeature parameters (P1–P4) at the specified feature ad-
dress.
When a feature is set, by default it remains active until the device is power cycled. It is
volatile. Unless otherwise specified in the features table, once a device is set it remains
set, even if a RESET (FFh) command is issued. GET/SET FEATURES commands can be
used after required RESET to enable features before system BOOT ROM process.
Internal ECC can be enabled/disabled using SET FEATURES (EFh). The SET FEATURES
command (EFh), followed by address 90h, followed by four data bytes (only the first da-
ta byte is used) will enable/disable internal ECC.
The sequence to enable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)-
08h(data)-00h(data)-00h(data)-00h(data)-wait(tFEAT).
The sequence to disable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)-
00h(data)-00h(data)-00h(data)-00h(data)-wait(tFEAT). The GET FEATURES command
is EEh.
Table 13: Feature Address Definitions
Feature Address Definition

00h Reserved
01h Timing mode
02h–7Fh Reserved
80h Programmable output drive strength
81h Programmable RB# pull-down strength
82h–FFh Reserved
90h Array operation mode
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Feature Operations
Table 14: Feature Address 90h – Array Operation Mode
Subfeature
Parameter Options 1/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
P1
Operation Normal Reserved (0) 0 00h 1
mode option OTP Reserved (0) 1 01h
operation
OTP Reserved (0) 1 1 03h
protection
Disable ECC Reserved (0) 0 0 0 0 00h 1
Enable ECC Reserved (0) 1 0 0 0 08h 1
P2
Reserved Reserved (0) 00h
P3
P4
Note: 1. These bits are reset to 00h on power cycle.
SET FEATURES (EFh)

The SET FEATURES (EFh) command writes the subfeature parameters (P1–P4) to the
specified feature address to enable or disable target-specific features. This command is
accepted by the target only when all die (LUNs) on the target are idle.
Writing EFh to the command register puts the target in the set features mode. The target
stays in this mode until another command is issued.
The EFh command is followed by a valid feature address. The host waits for tADL before
the subfeature parameters are input. When the asynchronous interface is active, one
subfeature parameter is latched per rising edge of WE#.
After all four subfeature parameters are input, the target goes busy for tFEAT. The READ
STATUS (70h) command can be used to monitor for command completion.
Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to
modify the interface type, the target will be busy for tITC.
Figure 30: SET FEATURES (EFh) Operation
Cycle type Command Address DIN DIN DIN DIN

tADL
I/O[7:0] EFh FA P1 P2 P3 P4
tWB tFEAT
R/B#
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Feature Operations
GET FEATURES (EEh)

The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the
specified feature address. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing EEh to the command register puts the target in get features mode. The target
stays in this mode until another valid command is issued.
When the EEh command is followed by a feature address, the target goes busy for tFEAT.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode.
After tFEAT completes, the host enables data output mode to read the subfeature pa-
rameters.
Figure 31: GET FEATURES (EEh) Operation
Cycle type Command Address DOUT DOUT DOUT DOUT
I/Ox EEh FA P1 P2 P3 P4
tWB tFEAT tRR
R/B#
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Feature Operations
Table 15: Feature Addresses 01h: Timing Mode
Subfeature
Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
P1
Timing mode Mode 0 Reserved (0) 0 0 0 00h 1, 2
(default)
Mode 1 Reserved (0) 0 0 1 01h 2
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Notes: 1. The timing mode feature address is used to change the default timing mode. The timing
mode should be selected to indicate the maximum speed at which the device will re-
ceive commands, addresses, and data cycles. The five supported settings for the timing
mode are shown. The default timing mode is mode 0. The device returns to mode 0
when the device is power cycled. Supported timing modes are reported in the parame-
ter page.
2. Supported for both 1.8V and 3.3V.
3. Supported for 3.3V only.
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Feature Operations
Table 16: Feature Addresses 80h: Programmable I/O Drive Strength
Subfeature
P1
I/O drive strength Full (default) Reserved (0) 0 0 00h 1
Three-quarters Reserved (0) 0 1 01h
One-half Reserved (0) 1 0 02h
One-quarter Reserved (0) 1 1 03h
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Note: 1. The programmable drive strength feature address is used to change the default I/O
drive strength. Drive strength should be selected based on expected loading of the
memory bus. This table shows the four supported output drive strength settings. The
default drive strength is full strength. The device returns to the default drive strength
mode when the device is power cycled. AC timing parameters may need to be relaxed if
I/O drive strength is not set to full.
Table 17: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
Subfeature
P1
R/B# pull-down Full (default) 0 0 00h 1
strength Three-quarters 0 1 01h
One-half 1 0 02h
One-quarter 1 1 03h
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength
should be selected based on the expected loading of R/B#. Full strength is the default,
power-on value.
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Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target
through its 8-bit status register.
After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,
status register output is enabled. The contents of the status register are returned on I/
O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (tR) is complete, the host must issue the READ MODE (00h)
command to disable the status register and enable data output (see Read Operations).
The READ STATUS (70h) command returns the status of the most recently selected die
(LUN). To prevent data contention during or following an interleaved die (multi-LUN)
operation, the host must enable only one die (LUN) for status output by using the READ
STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations).
With internal ECC enabled, a READ STATUS command is required after completion of
the data transfer (tR_ECC) to determine whether an uncorrectable read error occurred.
Table 18: Status Register Definition
SR Program Program Page Page Read

Bit Page Cache Mode Page Read Cache Mode Block Erase Description
7 Write protect Write protect Write protect Write protect Write protect 0 = Protected
1 = Not protected
6 RDY RDY1 cache RDY RDY1 cache RDY 0 = Busy
1 = Ready
5 ARDY ARDY2 ARDY ARDY2 ARDY Don't Care
4 – – – – – Don't Care
3 – – Rewrite – – 0 = Normal or uncorrectable
recommended3 1 = Rewrite recommended
2 – – – – – Don't Care
1 FAILC (N - 1) FAILC (N - 1) Reserved – – Don't Care
0 FAIL FAIL (N) FAIL4 – FAIL 0 = Successful PROGRAM/
ERASE/READ
1 = Error in PROGRAM/
ERASE/READ
Notes: 1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
2. Status register bit 5 is 0 during the actual programming operation. If cache mode is
used, this bit will be 1 when all internal operations are complete.
3. A status register bit defined as Rewrite Recommended signifies that the page includes
acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-
writeof this page is recommended. (Up to a 4-bit error has been corrected if internal
ECC was enabled.)
4. A status register bit defined as FAIL signifies that an uncorrectable READ error has oc-
curred.
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Status Operations
READ STATUS (70h)

The READ STATUS (70h) command returns the status of the last-selected die (LUN) on
a target. This command is accepted by the last-selected die (LUN) even when it is busy
(RDY = 0).
If there is only one die (LUN) per target, the READ STATUS (70h) command can be used
to return status following any NAND command.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select the die (LUN) that should report status. In this situation, using
the READ STATUS (70h) command will result in bus contention, as two or more die
(LUNs) could respond until the next operation is issued. The READ STATUS (70h) com-
mand can be used following all single-die (LUN) operations.
Figure 32: READ STATUS (70h) Operation
Cycle type Command DOUT

tWHR
I/O[7:0] 70h SR
READ STATUS ENHANCED (78h)

The READ STATUS ENHANCED (78h) command returns the status of the addressed die
(LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die
(LUNs), even when they are BUSY (RDY = 0).
Writing 78h to the command register, followed by three row address cycles containing
the page, block, and LUN addresses, puts the selected die (LUN) into read status mode.
The selected die (LUN) stays in this mode until another valid command is issued. Die
(LUNs) that are not addressed are deselected to avoid bus contention.
The selected LUN's status is returned when the host requests data output. The RDY and
ARDY bits of the status register are shared for all planes on the selected die (LUN). The
FAILC and FAIL bits are specific to the plane specified in the row address.
The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for
data output. To begin data output following a READ-series operation after the selected
die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data
output. If the host needs to change the cache register that will output data, use the
RANDOM DATA READ TWO-PLANE (06h-E0h) command after the die (LUN) is ready.
Use of the READ STATUS ENHANCED (78h) command is prohibited during the power-
on RESET (FFh) command and when OTP mode is enabled. It is also prohibited follow-
ing some of the other reset, identification, and configuration operations. See individual
operations for specific details.
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Status Operations
Figure 33: READ STATUS ENHANCED (78h) Operation
Cycle type Command Address Address Address DOUT

tWHR
I/Ox 78h R1 R2 R3 SR
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The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for man-
aging data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
RANDOM DATA READ (05h-E0h)

The RANDOM DATA READ (05h-E0h) command changes the column address of the se-
lected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles containing
the column address, followed by the E0h command, puts the selected die (LUN) into
data output mode. After the E0h command cycle is issued, the host must wait at least
tWHR before requesting data output. The selected die (LUN) stays in data output mode
until another valid command is issued.

In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
issued prior to issuing the RANDOM DATA READ (05h-E0h). In this situation, using the
RANDOM DATA READ (05h-E0h) command without the READ STATUS ENHANCED
(78h) command will result in bus contention because two or more die (LUNs) could
output data.
Figure 34: RANDOM DATA READ (05h-E0h) Operation
Cycle type DOUT DOUT Command Address Address Command DOUT DOUT DOUT
tRHW tWHR
I/O[7:0] Dn Dn + 1 05h C1 C2 E0h Dk Dk + 1 Dk + 2
SR[6]
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RANDOM DATA READ TWO-PLANE (06h-E0h)

The RANDOM DATA READ TWO-PLANE (06h-E0h) command enables data output on
the addressed die’s (LUN’s) cache register at the specified column address. This com-
mand is accepted by a die (LUN) when it is ready (RDY = 1; ARDY = 1).
Writing 06h to the command register, followed by two column address cycles and three
row address cycles, followed by E0h, enables data output mode on the address LUN’s
cache register at the specified column address. After the E0h command cycle is issued,
the host must wait at least tWHR before requesting data output. The selected die (LUN)
stays in data output mode until another valid command is issued.
Following a two-plane read page operation, the RANDOM DATA READ TWO-PLANE
(06h-E0h) command is used to select the cache register to be enabled for data output.
After data output is complete on the selected plane, the command can be issued again
to begin data output on another plane.
In devices with more than one die (LUN) per target, after all of the die (LUNs) on the
target are ready (RDY = 1), the RANDOM DATA READ TWO-PLANE (06h-E0h) command
can be used following an interleaved die (multi-LUN) read operation. Die (LUNs) that
are not addressed are deselected to avoid bus contention.
In devices with more than one die (LUN) per target, during interleaved die (multi-LUN)
operations where more than one or more die (LUNs) are busy (RDY = 1; ARDY = 0 or
RDY = 0; ARDY = 0), the READ STATUS ENHANCED (78h) command must be issued to
the die (LUN) to be selected prior to issuing the RANDOM DATA READ TWO-PLANE
(06h-E0h). In this situation, using the RANDOM DATA READ TWO-PLANE (06h-E0h)
command without the READ STATUS ENHANCED (78h) command will result in bus
contention, as two or more die (LUNs) could output data.
If there is a need to update the column address without selecting a new cache register
or LUN, the RANDOM DATA READ (05h-E0h) command can be used instead.
Figure 35: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation
Cycle
DOUT DOUT Command Address Address Address Address Address Command DOUT DOUT DOUT
type
tRHW tWHR
I/O[7:0] Dn Dn + 1 06h C1 C2 R1 R2 R3 E0h Dk Dk + 1 Dk + 2
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RANDOM DATA INPUT (85h)

The RANDOM DATA INPUT (85h) command changes the column address of the selec-
ted cache register and enables data input on the last-selected die (LUN). This command
is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also ac-
cepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles containing
the column address, puts the selected die (LUN) into data input mode. After the second
address cycle is issued, the host must wait at least tADL before inputting data. The se-
lected die (LUN) stays in data input mode until another valid command is issued.
Though data input mode is enabled, data input from the host is optional. Data input
begins at the column address specified.
The RANDOM DATA INPUT (85h) command is allowed after the required address cycles
are specified, but prior to the final command cycle (10h, 11h, 15h) of the following com-
mands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
CACHE (80h-15h), PROGRAM FOR INTERNAL DATA MOVE (85h-10h), and PROGRAM
FOR TWO-PLANE INTERNAL DATA MOVE (85h-11h).
In devices that have more than one die (LUN) per target, the RANDOM DATA INPUT
(85h) command can be used with other commands that support interleaved die (multi-
LUN) operations.
Figure 36: RANDOM DATA INPUT (85h) Operation
As defined for PAGE As defined for PAGE

(CACHE) PROGRAM (CACHE) PROGRAM
Cycle type DIN DIN Command Address Address DIN DIN DIN
tADL
I/O[7:0] Dn Dn + 1 85h C1 C2 Dk Dk + 1 Dk + 2
RDY
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PROGRAM FOR INTERNAL DATA INPUT (85h)

The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address
(block and page) where the cache register contents will be programmed in the NAND
Flash array. It also changes the column address of the selected cache register and ena-
bles data input on the specified die (LUN). This command is accepted by the selected
die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die
(LUN) during cache programming operations (RDY = 1; ARDY = 0).
Write 85h to the command register. Then write two column address cycles and three
row address cycles. This updates the page and block destination of the selected device
for the addressed LUN and puts the cache register into data input mode. After the fifth
address cycle is issued the host must wait at least tADL before inputting data. The selec-
ted LUN stays in data input mode until another valid command is issued. Though data
input mode is enabled, data input from the host is optional. Data input begins at the
column address specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command is allowed after the re-
quired address cycles are specified, but prior to the final command cycle (10h, 11h, 15h)
of the following commands while data input is permitted: PROGRAM PAGE (80h-10h),
PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), PRO-
GRAM FOR INTERNAL DATA MOVE (85h-10h), and PROGRAM FOR TWO-PLANE IN-
TERNAL DATA MOVE (85h-11h). When used with these commands, the LUN address
and plane select bits are required to be identical to the LUN address and plane select
bits originally specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command enables the host to mod-
ify the original page and block address for the data in the cache register to a new page
and block address.
In devices that have more than one die (LUN) per target, the PROGRAM FOR INTERNAL
DATA INPUT (85h) command can be used with other commands that support inter-
leaved die (multi-LUN) operations.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with the
RANDOM DATA READ (05h-E0h) or RANDOM DATA READ TWO-PLANE (06h-E0h)
commands to read and modify cache register contents in small sections prior to pro-
gramming cache register contents to the NAND Flash array. This capability can reduce
the amount of buffer memory used in the host controller.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM FOR
INTERNAL DATA MOVE command sequence to modify one or more bytes of the origi-
nal data. First, data is copied into the cache register using the 00h-35h command se-
quence, then the RANDOM DATA INPUT (85h) command is written along with the ad-
dress of the data to be modified next. New data is input on the external data pins. This
copies the new data into the cache register.
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Figure 37: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation
Cycle type DIN DIN Command Address Address Address Address Address Command DIN DIN DIN
tADL
I/O[7:0] Dn Dn + 1 85h C1 C2 R1 R2 R3 10h Dk Dk + 1 Dk + 2
RDY
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Read Operations
Read Operations
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the
NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data in
the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands
can be used to output data from the cache register while concurrently copying a page
from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash ar-
ray to its corresponding cache register using the READ PAGE (00h-30h) command.
R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After
tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
• READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential page from the
NAND Flash array to the data register
• READ PAGE CACHE RANDOM (00h-31h) – copies the page specified in this command
from the NAND Flash array to its corresponding data register
After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next page begins copying data from the array to the data register. After tRCBSY,
R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy
with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and
the page requested in the READ PAGE CACHE operation is transferred to the data regis-
ter. At this point, data can be output from the cache register, beginning at column ad-
dress 0. The RANDOM DATA READ (05h-E0h) command can be used to change the col-
umn address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an addi-
tional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ
PAGE CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied
into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and
ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.
Data can then be output from the cache register, beginning at column address 0. The
RANDOM DATA READ (05h-E0h) command can be used to change the column address
of the data being output.
For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands
during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h,
78h), READ MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA
READ (05h-E0h), and RESET (FFh).
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Read Operations
Two-Plane Read Operations

Two-plane read page operations improve data throughput by copying data from more
than one plane simultaneously to the specified cache registers. This is done by pre-
pending one or more READ PAGE TWO-PLANE (00h-00h-30h) commands in front of
the READ PAGE (00h-30h) command.
When the die (LUN) is ready, the RANDOM DATA READ TWO-PLANE (06h-E0h) com-
mand determines which plane outputs data. During data output, the following com-
mands can be used to read and modify the data in the cache registers: RANDOM DATA
READ (05h-E0h) and RANDOM DATA INPUT (85h).
Two-Plane Read Cache Operations
Two-plane read cache operations can be used to output data from more than one cache
register while concurrently copying one or more pages from the NAND Flash array to
the data register. This is done by prepending READ PAGE TWO-PLANE (00h-00h-30h)
commands in front of the PAGE READ TWO-PLANE CACHE (00h-00h-31h) command.
To begin a two-plane read page cache sequence, begin by issuing a READ PAGE TWO-
PLANE operation using the READ PAGE TWO-PLANE (00h-00h-30h) and READ PAGE
(00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy
(RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these
commands:
• READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential pages from the
previously addressed planes from the NAND Flash array to the data registers.
• READ PAGE TWO-PLANE (00h-00h-30h) [in some cases, followed by READ PAGE
TWO-PLANE CACHE (00h-00h-31h)] – copies the pages specified from the NAND
Flash array to the corresponding data registers.
After the READ PAGE CACHE series (31h, 00h-00h-31h) command has been issued,
R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY
while the next pages begin copying data from the array to the data registers. After
tRCBSY,
R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with a
cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pa-
ges requested in the READ PAGE CACHE operation are transferred to the data registers.
Issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which
cache register will output data. After data is output, the RANDOM DATA READ TWO-
PLANE (06h-E0h) command can be used to output data from other cache registers. Af-
ter a cache register has been selected, the RANDOM DATA READ (05h-E0h) command
can be used to change the column address of the data output.
After outputting data from the cache registers, either an additional TWO-PLANE READ
CACHE series (31h, 00h-00h-31h) operation can be started or the READ PAGE CACHE
LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are cop-
ied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1,
indicating that the cache registers are available and that the die (LUN) is ready. Issue the
RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which cache
register will output data. After data is output, the RANDOM DATA READ TWO-PLANE
(06h-E0h) command can be used to output data from other cache registers. After a
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Read Operations
cache register has been selected, the RANDOM DATA READ (05h-E0h) command can
be used to change the column address of the data output.
For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands
during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h,
78h), READ MODE (00h), two-plane read cache series (31h, 00h-00h-30h, 00h-00h-31h),
RANDOM DATA READ (06h-E0h, 05h-E0h), and RESET (FFh).
READ MODE (00h)

The READ MODE (00h) command disables status output and enables data output for
the last-selected die (LUN) and cache register after a READ operation (00h-30h,
00h-3Ah, 00h-35h) has been monitored with a status operation (70h, 78h). This com-
mand is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accep-
ted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
must be used to select only one die (LUN) prior to issuing the READ MODE (00h) com-
mand. This prevents bus contention.
READ PAGE (00h-30h)

The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its
respective cache register and enables data output. This command is accepted by the die
(LUN) when it is ready (RDY = 1, ARDY = 1).
To read a page from the NAND Flash array, write the 00h command to the command
register, then write n address cycles to the address registers, and conclude with the 30h
command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is
transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) can be used. If the status opera-
tions are used to monitor the LUN's status, when the die (LUN) is ready
(RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing
the READ MODE (00h) command. When the host requests data output, output begins
at the column address specified.
During data output the RANDOM DATA READ (05h-E0h) command can be issued.
When internal ECC is enabled, the READ STATUS (70h) command is required after the
completion of the data transfer (tR_ECC) to determine whether an uncorrectable read
error occured. (tR_ECC is the data transferred with internal ECC enabled.)
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) prior to the issue of the READ MODE (00h)
command. This prevents bus contention.
The READ PAGE (00h-30h) command is used as the final command of a two-plane read
operation. It is preceded by one or more READ PAGE TWO-PLANE (00h-00h-30h) com-
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Read Operations
mands. Data is transferred from the NAND Flash array for all of the addressed planes to
their respective cache registers. When the die (LUN) is ready
(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane
addressed in the READ PAGE (00h-30h) command. When the host requests data output,
output begins at the column address last specified in the READ PAGE (00h-30h) com-
mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enable
data output in the other cache registers.
Figure 38: READ PAGE (00h-30h) Operation
Cycle type Command Address Address Address Address Address Command DOUT DOUT DOUT
I/O[7:0] 00h C1 C2 R1 R2 R3 30h Dn Dn+1 Dn+2

tWB tR tRR
RDY
Figure 39: READ PAGE (00h-30h) Operation with Internal ECC Enabled
tR_ECC
RDY
I/O[7:0] 00h Address Address Address Address Address 30h 70h Status 00h DOUT (serial access)
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
READ PAGE CACHE SEQUENTIAL (31h)

The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page
within a block into the data register while the previous page is output from the cache
register. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE
(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is is-
sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After
tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point, data can
be output from the cache register beginning at column address 0. The RANDOM DATA
READ (05h-E0h) command can be used to change the column address of the data being
output from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block
boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the
last page of a block is read into the data register, the next page read will be the next logi-
cal block in which the 31h command was issued. Do not issue the READ PAGE CACHE
SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE
CACHE LAST (3Fh) command.
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Read Operations
Figure 40: READ PAGE CACHE SEQUENTIAL (31h) Operation
Cycle type Command Address x5 Command Command DOUT DOUT DOUT Command DOUT
I/O[7:0] 00h Page Address M 30h 31h D0 … Dn 31h D0

tWB tR RR tWB tRCBSY tRR tWB tRCBSY tRR
RDY
Page M Page M+1
READ PAGE CACHE RANDOM (00h-31h)

The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and
page into the data register while the previous page is output from the cache register.
This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is
also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
To issue this command, write 00h to the command register, then write n address cycles
to the address register, and conclude by writing 31h to the command register. The col-
umn address in the address specified is ignored. The die (LUN) address must match the
same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applica-
ble, the previous READ PAGE CACHE RANDOM (00h-31h) command.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy
with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is availa-
ble and that the specified page is copying from the NAND Flash array to the data regis-
ter. At this point, data can be output from the cache register beginning at column ad-
dress 0. The RANDOM DATA READ (05h-E0h) command can be used to change the col-
umn address of the data being output from the cache register.
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command fol-
lowed by the READ MODE (00h) command must be used to select only one die (LUN)
and prevent bus contention.
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Read Operations
Figure 41: READ PAGE CACHE RANDOM (00h-31h) Operation
Cycle type Command Address x5 Command Command Address x5 Command DOUT DOUT DOUT Command
I/O[7:0] 00h Page Address M 30h 00h Page Address N 31h D0 … Dn 00h
tWB tR RR tWB tRCBSY tRR
RDY
Page M
1
Cycle type DOUT Command Address x5 Command DOUT
I/O[7:0] Dn 00h Page Address P 31h D0

tWB tRCBSY tRR
RDY
Page N
1
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Read Operations
READ PAGE CACHE LAST (3Fh)

The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and
copies a page from the data register to the cache register. This command is accepted by
the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN)
during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command reg-
ister. After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is
ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, be-
ginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be
used to change the column address of the data being output from the cache register.
In devices that have more than one LUN per target, during and following interleaved die
(multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by
the READ MODE (00h) command must be used to select only one die (LUN) and pre-
vent bus contention.
Figure 42: READ PAGE CACHE LAST (3Fh) Operation
As defined for
READ PAGE CACHE
(SEQUENTIAL OR RANDOM)
Cycle type Command DOUT DOUT DOUT Command DOUT DOUT DOUT
I/O[7:0] 31h D0 … Dn 3Fh D0 … Dn

tWB tRCBSY tRR tWB tRCBSY tRR
RDY
Page Address N Page N
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Read Operations
READ PAGE TWO-PLANE 00h-00h-30h

The READ PAGE TWO-PLANE (00h-00h-30h) operation is similar to the PAGE READ
(00h-30h) operation. It transfers two pages of data from the NAND Flash array to the da-
ta registers. Each page must be from a different plane on the same die.
To enter the READ PAGE TWO-PLANE mode, write the 00h command to the command
register, and then write five address cycles for plane 0 (BA6 = 0). Next, write the 00h
command to the command register, and five address cycles for plane 1 (BA6 = 1). Final-
ly, issue the 30h command. The first-plane and second-plane addresses must meet the
two-plane addressing requirements, and, in addition, they must have identical column
addresses.
After the 30h command is written, page data is transferred from both planes to their re-
spective data registers in tR. During these transfers, R/B# goes LOW. When the transfers
are complete, R/B# goes HIGH. To read out the data from the plane 0 data register,
pulse RE# repeatedly. After the data cycle from the plane 0 address completes, issue a
RANDOM DATA READ TWO-PLANE (06h-E0h) command to select the plane 1 address,
then repeatedly pulse RE# to read out the data from the plane 1 data register.
Alternatively, the READ STATUS (70h) command can monitor data transfers. When the
transfers are complete, status register bit 6 is set to 1. To read data from the first of the
two planes, the user must first issue the RANDOM DATA READ TWO-PLANE (06h-E0h)
command and pulse RE# repeatedly.
When the data cycle is complete, issue a RANDOM DATA READ TWO-PLANE (06h-E0h)
command to select the other plane. To output the data beginning at the specified col-
umn address, pulse RE# repeatedly.
Use of the READ STATUS ENHANCED (78h) command is prohibited during and follow-
ing a PAGE READ TWO-PLANE operation.
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Read Operations
Figure 43: READ PAGE TWO-PLANE (00h-00h-30h) Operation
CLE
WE#
ALE
RE#
Page address M Page address M
00h Col Col Row Row Row 00h Col Col Row Row Row 30h
I/Ox add 1 add 2 add 1 add 2 add 3 add 1 add 2 add 1 add 2 add 3
Column address J Plane 0 address Column address J Plane 1 address tR
R/B#
CLE
WE#
ALE
RE#
I/Ox DOUT 0 DOUT 1 DOUT 06h Col Col Row Row Row E0h DOUT 0 DOUT 1 DOUT
Plane 0 data Plane 1 address Plane 1 data
R/B#
1
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Program Operations
Program Operations
Program operations are used to move data from the cache or data registers to the NAND
array. During a program operation the contents of the cache and/or data registers are
modified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant page
address to the most significant page address (0, 1, 2, ….., 63). During a program opera-
tion, the contents of the cache and/or data registers are modified by the internal control
logic.
Program Operations
The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE
TWO-PLANE (80h-11h) command, programs one page from the cache register to the
NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should
check the FAIL bit to verify that the operation has completed successfully.
Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program op-
eration system performance. When this command is issued, the die (LUN) goes busy
(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,
and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. While
the contents of the data register are moved to the NAND Flash array, the cache register
is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE
(80h-10h) command.
For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busy
times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are
status operations (70h, 78h) and reset (FFh). When RDY = 1 and ARDY = 0, the only valid
commands during PROGRAM PAGE CACHE series (80h-15h) operations are status op-
erations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h),
RANDOM DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RE-
SET (FFh).
Two-Plane Program Operations
The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve pro-
gram operation system performance by enabling multiple pages to be moved from the
cache registers to different planes of the NAND Flash array. This is done by prepending
one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands in front of the PRO-
GRAM PAGE (80h-10h) command.
Two-Plane Program Cache Operations
The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve pro-
gram cache operation system performance by enabling multiple pages to be moved
from the cache registers to the data registers and, while the pages are being transferred
from the data registers to different planes of the NAND Flash array, free the cache regis-
ters to receive data input from the host. This is done by prepending one or more PRO-
GRAM PAGE TWO-PLANE (80h-11h) commands in front of the PROGRAM PAGE
CACHE (80h-15h) command.
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Program Operations
PROGRAM PAGE (80h-10h)

The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache reg-
ister, and moves the data from the cache register to the specified block and page ad-
dress in the array of the selected die (LUN). This command is accepted by the die (LUN)
when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy
with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block and
page address specified, write 80h to the command register. Unless this command has
been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h
to the command register clears all of the cache registers' contents on the selected target.
Then write n address cycles containing the column address and row address. Data input
cycles follow. Serial data is input beginning at the column address specified. At any time
during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR IN-
TERNAL DATA INPUT (85h) commands may be issued. When data input is complete,
write 10h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tPROG as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) may be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The PROGRAM PAGE (80h-10h) command is used as the final command of a two-plane
program operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE
(80h-11h) commands. Data is transferred from the cache registers for all of the ad-
dressed planes to the NAND array. The host should check the status of the operation by
using the status operations (70h, 78h).
When internal ECC is enabled, the duration of array programming time is tPROG_ECC.
During tPROG_ECC, the internal ECC generates parity bits when error detection is com-
plete.
Figure 44: PROGRAM PAGE (80h-10h) Operation
Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command Command DOUT
tADL
I/O[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 10h

tPROG
70h Status
or
tWB tPROG_ECC
RDY
PROGRAM PAGE CACHE (80h-15h)

The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the se-
lected die (LUN). After the data is copied to the data register, the cache register is availa-
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Program Operations
ble for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die
(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when
busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page
address specified, write 80h to the command register. Unless this command has been
preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to
the command register clears all of the cache registers' contents on the selected target.
Then write n address cycles containing the column address and row address. Data input
cycles follow. Serial data is input beginning at the column address specified. At any time
during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR IN-
TERNAL DATA INPUT (85h) commands may be issued. When data input is complete,
write 15h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a pre-
vious program cache operation, to copy data from the cache register to the data register,
and then to begin moving the data register contents to the specified page and block ad-
dress.
To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, al-
ternatively, the status operations (70h, 78h) can be used. When the LUN’s status shows
that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should
check the status of the FAILC bit to see if a previous cache operation was successful.
If, after tCBSY, the host wants to wait for the program cache operation to complete,
without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor AR-
DY until it is 1. The host should then check the status of the FAIL and FAILC bits.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
used to select only one die (LUN) for status output. Use of the READ STATUS (70h) com-
mand could cause more than one die (LUN) to respond, resulting in bus contention.
The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a
two-plane program cache operation. It is preceded by one or more PROGRAM PAGE
TWO-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred
from the cache registers to the corresponding data registers, then moved to the NAND
Flash array. The host should check the status of the operation by using the status opera-
tions (70h, 78h).
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Program Operations
Figure 45: PROGRAM PAGE CACHE (80h–15h) Operation (Start)
Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command
tADL
I/O[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 15h

tWB tCBSY
RDY
tADL
I/O[7:0]
80h C1 C2 R1 R2 R3 D0 D1 … Dn 15h
tWB tCBSY
RDY
Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (End)
As defined for
PAGE CACHE PROGRAM
tADL
I/O[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 15h

tWB tCBSY
RDY
tADL
I/O[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 10h

tWB tLPROG
RDY
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Program Operations
PROGRAM PAGE TWO-PLANE (80h-11h)

The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input data
to the addressed plane's cache register and queue the cache register to ultimately be
moved to the NAND Flash array. This command can be issued one or more times. Each
time a new plane address is specified that plane is also queued for data transfer. To in-
put data for the final plane and to begin the program operation for all previously
queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM
PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the
NAND Flash array. This command is accepted by the die (LUN) when it is ready
(RDY = 1).
To input a page to the cache register and queue it to be moved to the NAND Flash array
at the block and page address specified, write 80h to the command register. Unless this
command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command,
issuing the 80h to the command register clears all of the cache registers' contents on the
selected target. Write five address cycles containing the column address and row ad-
dress; data input cycles follow. Serial data is input beginning at the column address
specified. At any time during the data input cycle, the RANDOM DATA INPUT (85h) and
PROGRAM FOR INTERNAL DATA INPUT (85h) commands can be issued. When data
input is complete, write 11h to the command register. The selected die (LUN) will go
busy (RDY = 0, ARDY = 0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal or,
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1), additional PROGRAM PAGE TWO-PLANE (80h-11h)
commands can be issued to queue additional planes for data transfer. Alternatively, the
PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be is-
sued.
When the PROGRAM PAGE (80h-10h) command is used as the final command of a two-
plane program operation, data is transferred from the cache registers to the NAND
Flash array for all of the addressed planes during tPROG. When the die (LUN) is ready
(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the
planes to verify that programming completed successfully.
When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command
of a program cache two-plane operation, data is transferred from the cache registers to
the data registers after the previous array operations finish. The data is then moved
from the data registers to the NAND Flash array for all of the addressed planes. This oc-
curs during tCBSY. After tCBSY, the host should check the status of the FAILC bit for
each of the planes from the previous program cache operation, if any, to verify that pro-
gramming completed successfully.
For the PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PRO-
GRAM PAGE CACHE (80h-15h) commands, see Two-Plane Operations for two-plane ad-
dressing requirements.
Figure 47: PROGRAM PAGE TWO-PLANE (80h–11h) Operation
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Program Operations
Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address
tADL
I/O[7:0] 80h C1 C2 R1 R2 R3 D0 … Dn 11h 80h ...
tWB tDBSY
RDY
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Erase Operations
Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to
prepare its pages for program operations.
Erase Operations
The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK
TWO-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the
die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that
this operation completed successfully.
TWO-PLANE ERASE Operations
The ERASE BLOCK TWO-PLANE (60h-D1h) command can be used to further system
performance of erase operations by allowing more than one block to be erased in the
NAND array. This is done by prepending one or more ERASE BLOCK TWO-PLANE (60h-
D1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Two-Plane
Operations for details.
ERASE BLOCK (60h-D0h)

The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash
array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To erase a block, write 60h to the command register. Then write three address cycles
containing the row address; the page address is ignored. Conclude by writing D0h to the
command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS
while the block is erased.
To determine the progress of an ERASE operation, the host can monitor the target's
R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The ERASE BLOCK (60h-D0h) command is used as the final command of an erase two-
plane operation. It is preceded by one or more ERASE BLOCK TWO-PLANE (60h-D1h)
commands. All blocks in the addressed planes are erased. The host should check the
status of the operation by using the status operations (70h, 78h). See Two-Plane Opera-
tions for two-plane addressing requirements.
Figure 48: ERASE BLOCK (60h-D0h) Operation
Cycle type Command Address Address Address Command
I/O[7:0] 60h R1 R2 R3 D0h

tWB tBERS
RDY
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Erase Operations
ERASE BLOCK TWO-PLANE (60h-D1h)

The ERASE BLOCK TWO-PLANE (60h-D1h) command queues a block in the specified
plane to be erased in the NAND Flash array. This command can be issued one or more
times. Each time a new plane address is specified, that plane is also queued for a block
to be erased. To specify the final block to be erased and to begin the ERASE operation
for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This
command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To queue a block to be erased, write 60h to the command register, then write three ad-
dress cycles containing the row address; the page address is ignored. Conclude by writ-
ing D1h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY =
0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal, or
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK TWO-PLANE (60h-
D1h) commands can be issued to queue additional planes for erase. Alternatively, the
ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks.
For two-plane addressing requirements for the ERASE BLOCK TWO-PLANE (60h-D1h)
and ERASE BLOCK (60h-D0h) commands, see Two-Plane Operations.
Figure 49: ERASE BLOCK TWO-PLANE (60h–D1h) Operation
Cycle type Command Address Address Address Command Command Address
I/O[7:0] 60h R1 R2 R3 D1h 60h ...

tWB tDBSY
RDY
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Internal data move operations make it possible to transfer data within a device from
one page to another using the cache register. This is particularly useful for block man-
agement and wear leveling.
The INTERNAL DATA MOVE operation is a two-step process consisting of a READ FOR
INTERNAL DATA MOVE (00h-35h) and a PROGRAM FOR INTERNAL DATA MOVE
(85h-10h) command. To move data from one page to another on the same plane, first
issue the READ FOR INTERNAL DATA MOVE (00h-35h) command. When the die (LUN)
is ready (RDY = 1, ARDY = 1), the host can transfer the data to a new page by issuing the
PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command. When the die (LUN) is
again ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this
operation completed successfully.
To prevent bit errors from accumulating over multiple INTERNAL DATA MOVE opera-
tions, it is recommended that the host read the data out of the cache register after the
READ FOR INTERNAL DATA MOVE (00h-35h) completes and prior to issuing the PRO-
GRAM FOR INTERNAL DATA MOVE (85h-10h) command. The RANDOM DATA READ
(05h-E0h) command can be used to change the column address. The host should check
the data for ECC errors and correct them. When the PROGRAM FOR INTERNAL DATA
MOVE (85h-10h) command is issued, any corrected data can be input. The PROGRAM
FOR INTERNAL DATA INPUT (85h) command can be used to change the column ad-
dress.
It is not possible to use the READ FOR INTERNAL DATA MOVE operation to move data
from one plane to another or from one die (LUN) to another. Instead, use a READ PAGE
(00h-30h) or READ FOR INTERNAL DATA MOVE (00h-35h) command to read the data
out of the NAND, and then use a PROGRAM PAGE (80h-10h) command with data input
to program the data to a new plane or die (LUN).
Between the READ FOR INTERNAL DATA MOVE (00h-35h) and PROGRAM FOR INTER-
NAL DATA MOVE (85h-10h) commands, the following commands are supported: status
operations (70h, 78h) and column address operations (05h-E0h, 06h-E0h, 85h). The RE-
SET operation (FFh) can be issued after READ FOR INTERNAL DATA MOVE (00h-35h),
but the contents of the cache registers on the target are not valid.
In devices that have more than one die (LUN) per target, once the READ FOR INTER-
NAL DATA MOVE (00h-35h) is issued, interleaved die (multi-LUN) operations are pro-
hibited until after the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is
issued.
Two-Plane Read for Internal Data Move Operations
Two-plane internal data move read operations improve read data throughput by copy-
ing data simultaneously from more than one plane to the specified cache registers. This
is done by issuing the READ PAGE TWO-PLANE (00h-00h-30h) command or the READ
FOR INTERNAL DATA MOVE (00h-00h-35h) command.
The INTERNAL DATA MOVE PROGRAM TWO-PLANE (85h-11h) command can be used
to further system performance of PROGRAM FOR INTERNAL DATA MOVE operations
by enabling movement of multiple pages from the cache registers to different planes of
the NAND Flash array. This is done by prepending one or more PROGRAM FOR INTER-
NAL DATA MOVE (85h-11h) commands in front of the PROGRAM FOR INTERNAL DA-
TA MOVE (85h-10h) command. See Two-Plane Operations for details.
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READ FOR INTERNAL DATA MOVE (00h-35h)

The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to
the READ PAGE (00h-30h) command, except that 35h is written to the command regis-
ter instead of 30h.
Though it is not required, it is recommended that the host read the data out of the de-
vice to verify the data prior to issuing the PROGRAM FOR INTERNAL DATA MOVE
(85h-10h) command to prevent the propagation of data errors.
If internal ECC is enabled, the data does not need to be toggled out by the host to be
corrected and moving data can then be written to a new page without data reloading,
which improves system performance.
Figure 50: READ FOR INTERNAL DATA MOVE (00h-35h) Operation
I/O[7:0] 00h C1 C2 R1 R2 R3 35h Dn Dn+1 Dn+2

tWB tR tRR
RDY
Figure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h)
I/O[7:0] 00h C1 C2 R1 R2 R3 35h D0 … Dj + n

tWB tR tRR
RDY
Cycle type Command Address Address Command DOUT DOUT DOUT

tWHR
I/O[7:0] 05h C1 C2 E0h Dk Dk + 1 Dk + 2
RDY
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Figure 52: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled
tR_ECC tPROG_ECC
R/B#
I/O[7:0] 00h Address 35h 70h Status 00h DOUT 85h Address 10h 70h Status 00h
(5 cycles) (5 cycles)
Source address DOUT is optional Destination address
SR bit 0 = 0 READ successful SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error SR bit 1 = 0 READ error
Figure 53: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled
tR_ECC tPROG_ECC
R/B#
I/O[7:0] 00h Address 35h 70h Status 00h DOUT 85h Address Address
(5 cycles) (5 cycles) Data 85h (2 cycles) Data 10h 70h
Source address SR bit 0 = 0 READ successful DOUT is optional Destination address
SR bit 1 = 0 READ error Column address 1, 2
(Unlimitted repetitions are possible)
PROGRAM FOR INTERNAL DATA MOVE (85h–10h)

The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally iden-
tical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the
command register, cache register contents are not cleared.
Figure 54: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation
Cycle type Command Address Address Address Address Address Command
I/O[7:0] 85h C1 C2 R1 R2 R3 10h

tWB tPROG
RDY
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Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h)
Cycle type Command Address Address Address Address Address DIN DIN
tWHR
I/O[7:0] 85h C1 C2 R1 R2 R3 Di Di + 1
RDY
Cycle type Command Address Address DIN DIN DIN Command

tWHR
I/O[7:0] 85h C1 C2 Dj Dj + 1 Dj + 2 10h

tWB tPROG
RDY
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h)

The PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) command is func-
tionally identical to the PROGRAM PAGE TWO-PLANE (85h-11h) command, except that
when 85h is written to the command register, cache register contents are not cleared.
See Program Operations for further details.
Figure 56: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation
Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address
tADL
I/O[7:0] 85h C1 C2 R1 R2 R3 D0 … Dn 11h 85h ...
tWB tDBSY
RDY
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Block Lock Feature
Block Lock Feature

The block lock feature protects either the entire device or ranges of blocks from being
programmed and erased. Using the block lock feature is preferable to using WP# to pre-
vent PROGRAM and ERASE operations.
Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if
LOCK is LOW, all BLOCK LOCK commands are disabled. However if LOCK is HIGH at
power-on, the BLOCK LOCK commands are enabled and, by default, all the blocks on
the device are protected, or locked, from PROGRAM and ERASE operations, even if WP#
is HIGH.
Before the contents of the device can be modified, the device must first be unlocked.
Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE
operations complete successfully only in the block ranges that have been unlocked.
Blocks, once unlocked, can be locked again to protect them from further PROGRAM
and ERASE operations.
Blocks that are locked can be protected further, or locked tight. When locked tight, the
device’s blocks can no longer be locked or unlocked.
WP# and Block Lock

The following is true when the block lock feature is enabled:
• Holding WP# LOW locks all blocks, provided the blocks are not locked tight.
• If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command
must be issued to unlock blocks.
UNLOCK (23h-24h)
By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from
PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a
range of blocks. Unlocked blocks have no protection and can be programmed or erased.
The UNLOCK command uses two registers, a lower boundary block address register and
an upper boundary block address register, and the invert area bit to determine what
range of blocks are unlocked. When the invert area bit = 0, the range of blocks within
the lower and upper boundary address registers are unlocked. When the invert area bit
= 1, the range of blocks outside the boundaries of the lower and upper boundary ad-
dress registers are unlocked. The lower boundary block address must be less than the
upper boundary block address. The figures below show examples of how the lower and
upper boundary address registers work with the invert area bit.
To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appro-
priate address cycles that indicate the lower boundary block address. Then issue the
24h command followed by the appropriate address cycles that indicate the upper boun-
dary block address. The least significant page address bit, PA0, should be set to 1 if set-
ting the invert area bit; otherwise, it should be 0. The other page address bits should be
0.
Only one range of blocks can be specified in the lower and upper boundary block ad-
dress registers. If after unlocking a range of blocks the UNLOCK command is again is-
sued, the new block address range determines which blocks are unlocked. The previous
unlocked block address range is not retained.
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Block Lock Feature
Figure 57: Flash Array Protected: Invert Area Bit = 0
Protected
Block 4095 area
Block 4094
Block 4093
Block 4092 FFCh Upper block boundary Unprotected
Block 4091 area
Block 4090
Block 4089
Block 4088 FF8h Lower block boundary
Block. 4087
..
.. Protected
.. area
..
..
..
.
Block 0002
Block 0001
Block 0000
Figure 58: Flash Array Protected: Invert Area Bit = 1
Unprotected
Block 4095 Area
Block 4094
Block 4093
Block 4092 FFCh Upper block boundary Protected
Block 4091 area
Block 4090
Block 4089
Block 4088 FF8h Lower block boundary
Block. 4087
..
.. Unprotected
..
.. area
..
..
.
Block 0002
Block 0001
Block 0000
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Block Lock Feature
Table 19: Block Lock Address Cycle Assignments
ALE Cycle I/O[15:8]1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
First LOW BA7 BA6 LOW LOW LOW LOW LOW Invert area bit2
Second LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Third LOW LOW LOW LOW LOW LOW LOW BA17 BA16
Notes: 1. I/O[15:8] is applicable only for x16 devices.

2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h com-
mand.
Figure 59: UNLOCK Operation
WP#
CLE
CE#
WE#
ALE
RE#
I/Ox 23h Block Block Block 24h Block Block Block

add 1 add 2 add 3 add 1 add 2 add 3
Unlock Lower boundary Upper boundary
R/B#
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Block Lock Feature
LOCK (2Ah)
By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from
PROGRAM and ERASE operations. If portions of the device are unlocked using the UN-
LOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The
LOCK command locks all of the blocks in the device. Locked blocks are write-protected
from PROGRAM and ERASE operations.
To lock all of the blocks in the device, issue the LOCK (2Ah) command.
When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for
tLBSY. The
PROGRAM or ERASE operation does not complete. Any READ STATUS com-
mand reports bit 7 as 0, indicating that the block is protected.
The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is
locked tight.
Figure 60: LOCK Operation
CLE
CE#
WE#
I/Ox 2Ah
LOCK command
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Block Lock Feature
LOCK TIGHT (2Ch)

The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and al-
so prevents unlocked blocks from being locked. When this command is issued, the UN-
LOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level
of protection against inadvertent PROGRAM and ERASE operations to locked blocks.
To implement LOCK TIGHT in all of the locked blocks in the device, verify that WP# is
HIGH and then issue the LOCK TIGHT (2Ch) command.
When a PROGRAM or ERASE operation is issued to a locked block that has also been
locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not
complete. The READ STATUS (70h) command reports bit 7 as 0, indicating that the
block is protected. PROGRAM and ERASE operations complete successfully to blocks
that were not locked at the time the LOCK TIGHT command was issued.
After the LOCK TIGHT command is issued, the command cannot be disabled via a soft-
ware command. Lock tight status can be disabled only by power cycling the device or
toggling WP#. When the lock tight status is disabled, all of the blocks become locked,
the same as if the LOCK (2Ah) command had been issued.
The LOCK TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.
Figure 61: LOCK TIGHT Operation
LOCK
WP#
CLE
CE#
WE#
I/Ox 2Ch
LOCK TIGHT
command
R/B#
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Block Lock Feature
Figure 62: PROGRAM/ERASE Issued to Locked Block
LBSY
t
R/B#
I/Ox PROGRAM or ERASE Add ress/data input CONFIRM 70h 60h
Locked block READ STATUS
BLOCK LOCK READ STATUS (7Ah)

The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection
status of individual blocks. The address cycles have the same format, as shown below,
and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output
the block lock status register, which contains the information on the protection status
of the block.
Table 20: Block Lock Status Register Bit Definitions
Block Lock Status Register Definitions I/O[7:3] I/O2 (Lock#) I/O1 (LT#) I/O0 (LT)
Block is locked tight X 0 0 1
Block is locked X 0 1 0
Block is unlocked, and device is locked tight X 1 0 1
Block is unlocked, and device is not locked tight X 1 1 0
Figure 63: BLOCK LOCK READ STATUS
CLE
CE#
WE#
tWHR
ALE
RE#
7Ah Add 1 Add 2 Add 3 Status

I/Ox
BLOCK LOCK Block address
READ STATUS
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Block Lock Feature
Figure 64: BLOCK LOCK Flowchart
Power-up
Power-up with Power-up with
LOCK HIGH LOCK LOW
(default)
Entire NAND Flash BLOCK LOCK function

array locked disabled
LOCK TIGHT Cmd

with WP# and
LOCK HIGH
Entire NAND Flash

array locked tight
UNLOCK Cmd with

invert area bit = 1
UNLOCK Cmd with

invert area bit = 0
WP# LOW Unlocked range WP# LOW Locked range

>100ns or >100ns or UNLOCK Cmd with
LOCK Cmd LOCK Cmd invert area bit = 0
Locked range Unlocked range
UNLOCK Cmd with invert area bit = 1
Unlocked range UNLOCK Cmd with invert area bit = 0 Locked range
UNLOCK Cmd
with invert area LOCK TIGHT Cmd LOCK TIGHT Cmd
bit = 1 with WP# and with WP# and
LOCK HIGH LOCK HIGH
Unlocked range Locked tight range
Locked tight range Unlocked range
Unlocked range Locked-tight range
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This Micron NAND Flash device offers a protected, one-time programmable NAND
Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on
the device, and the entire range is guaranteed to be good. The OTP area is accessible
only through the OTP commands. Customers can use the OTP area any way they
choose; typical uses include programming serial numbers or other data for permanent
storage.
The OTP area leaves the factory in an unwritten state (all bits are 1s). Programming or
partial-page programming enables the user to program only 0 bits in the OTP area. The
OTP area cannot be erased, whether it is protected or not. Protecting the OTP area pre-
vents further programming of that area.
Micron provides a unique way to program and verify data before permanently protect-
ing it and preventing future changes. The OTP area is only accessible while in OTP oper-
ation mode. To set the device to OTP operation mode, issue the SET FEATURE (EFh)
command to feature address 90h and write 01h to P1, followed by three cycles of 00h to
P2-P4. For parameters to enter OTP mode, see Features Operations.
When the device is in OTP operation mode, all subsequent PAGE READ (00h-30h) and
PROGRAM PAGE (80h-10h) commands are applied to the OTP area. The OTP area is as-
signed to page addresses 02h-1Fh. To program an OTP page, issue the PROGRAM PAGE
(80h-10h) command. The pages must be programmed in the ascending order. Similarly,
to read an OTP page, issue the PAGE READ (00h-30h) command.
Protecting the OTP is done by entering OTP protect mode. To set the device to OTP pro-
tect mode, issue the SET FEATURE (EFh) command to feature address 90h and write
03h to P1, followed by three cycles of 00h to P2-P4.
To determine whether the device is busy during an OTP operation, either monitor R/B#
or use the READ STATUS (70h) command.
To exit OTP operation or protect mode, write 00h to P1 at feature address 90h.
Legacy OTP Commands

For legacy OTP commands, OTP DATA PROGRAM (A0h-10h), OTP DATA PROTECT
(A5h-10h), and OTP DATA READ (AFh-30h), refer to the MT29F4GxxAxC data sheet.
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OTP DATA PROGRAM (80h-10h)

The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within
the OTP area. An entire page can be programmed at one time, or a page can be partially
programmed up to eight times. Only the OTP area allows up to eight partial-page pro-
grams. The rest of the blocks support only four partial-page programs. There is no
ERASE operation for OTP pages.
PROGRAM PAGE enables programming into an offset of an OTP page using two bytes of
the column address (CA[12:0]). The command is compatible with the RANDOM DATA
INPUT (85h) command. The PROGRAM PAGE command will not execute if the OTP
area has been protected.
To use the PROGRAM PAGE command, issue the 80h command. Issue n address cycles.
The first two address cycles are the column address. For the remaining cycles, select a
page in the range of 02h-00h through 1Fh-00h. Next, write from 1–2112 bytes of data.
After data input is complete, issue the 10h command. The internal control logic auto-
matically executes the proper programming algorithm and controls the necessary tim-
ing for programming and verification.
R/B# goes LOW for the duration of the array programming time (tPROG). The READ
STATUS (70h) command is the only valid command for reading status in OTP operation
mode. Bit 5 of the status register reflects the state of R/B#. When the device is ready,
read bit 0 of the status register to determine whether the operation passed or failed (see
Status Operations). Each OTP page can be programmed to 8 partial-page programming.
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RANDOM DATA INPUT (85h)

After the initial OTP data set is input, additional data can be written to a new column
address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT
command can be used any number of times in the same page prior to the OTP PAGE
WRITE (10h) command being issued.
Figure 65: OTP DATA PROGRAM (After Entering OTP Operation Mode)
CLE
CE#
tWC
WE#
tWB tPROG
ALE
RE#
I/Ox 80h Col Col OTP 00h 00h DIN DIN 10h 70h Status
add 1 add 2 page1 n m
OTP DATA INPUT 1 up to m bytes PROGRAM READ STATUS
command OTP address1 serial input command command
R/B#
x8 device: m = 2112 bytes OTP data written
x16 device: m = 1056 words (following good status confirmation)
Don’t Care
Note: 1. The OTP page must be within the 02h–1Fh range.
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Figure 66: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Opera-
tion Mode)
CLE
CE#
tWC tADL tADL
WE#
tWB tPROG
ALE
RE#
Col Col OTP DIN DIN Col Col DIN DIN

I/Ox 80h
add1 add2 page1
00h 00h
n n+1
85h
add1 add2 n n+1
10h 70h Status
SERIAL DATA Serial input RANDOM DATA Column address Serial input PROGRAM READ STATUS
INPUT command INPUT command command command
R/B#
Don‘t Care
OTP DATA PROTECT (80h-10)

The OTP DATA PROTECT (80h-10h) command is used to prevent further programming
of the pages in the OTP area. To protect the OTP area, the target must be in OTP opera-
tion mode.
To protect all data in the OTP area, issue the 80h command. Issue n address cycles in-
cluding the column address, OTP protect page address and block address; the column
and block addresses are fixed to 0. Next, write 00h data for the first byte location and
issue the 10h command. R/B# goes LOW for the duration of the array programming
time, tPROG.
After the data is protected, it cannot be programmed further. When the OTP area is pro-
tected, the pages within the area are no longer programmable and cannot be unprotec-
ted.
The READ STATUS (70h) command is the only valid command for reading status in OTP
operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of
the READ STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine if the oper-
ation passed or failed.
If the OTP DATA PROTECT (80h-10h) command is issued after the OTP area has already
been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
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Figure 67: OTP DATA PROTECT Operation (After Entering OTP Protect Mode)
CLE
CE#
tWC
WE#
tWB tPROG
ALE
RE#
I/Ox Col Col OTP Status

80h 00h 00h page 00h 00h DIN 10h 70h
OTP DATA PROGRAM READ STATUS
PROTECT command command command
OTP address
R/B#
OTP data protected1
Don’t Care
Note: 1. OTP data is protected following a good status confirmation.
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OTP DATA READ (00h-30h)

To read data from the OTP area, set the device to OTP operation mode, then issue the
PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area
whether the area is protected or not.
To use the PAGE READ command for reading data from the OTP area, issue the 00h
command, and then issue five address cycles: for the first two cycles, the column ad-
dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h
through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE
command is not supported on OTP pages.
R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The
READ STATUS (70h) command is the only valid command for reading status in OTP op-
eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-
tions).
Normal READ operation timings apply to OTP read accesses. Additional pages within
the OTP area can be selected by repeating the OTP DATA READ command.
The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)
command.
Only data on the current page can be read. Pulsing RE# outputs data sequentially.
Figure 68: OTP DATA READ
CLE
CE#
WE#
ALE
RE#
I/Ox Col Col OTP DOUT DOUT DOUT

00h 00h 00h 30h
add 1 add 2 page1 n n+1 m
tR
OTP address
Busy
R/B#
Don’t Care
Note: 1. The OTP page must be within the 02h–1Fh range.
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Figure 69: OTP DATA READ with RANDOM DATA READ Operation
CLE
t CLR
CE#
WE#
t WB
t AR t WHR
ALE
t RC t REA
RE#
t RR
Col Col OTP DOUT DOUT Col Col DOUT DOUT

I/Ox 00h add 1 add 2 page 1 00h 00h 30h
n n+1
05h add 1 add 2 E0h
m m+1
tR
Column addressn Column addressm
Busy
R/B#
Don’t Care
Note: 1. The OTP page must be within the range 02h–1Fh.
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Two-Plane Operations
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. The
planes are addressed via the low-order block address bits. Specific details are provided
in Device and Array Organization.
Two-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Two-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing two-plane program or erase operations, use the READ STATUS (70h)
command and check whether the previous operation(s) failed. If the READ STATUS
(70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the
READ STATUS ENHANCED (78h) command to determine which plane operation failed.
Two-Plane Addressing
Two-plane commands require multiple, five-cycle addresses, one address per opera-
tional plane. For a given two-plane operation, these addresses are subject to the follow-
ing requirements:
• The LUN address bit(s) must be identical for all of the issued addresses.
• The plane select bit, BA[6], must be different for each issued address.
• The page address bits, PA[5:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following two-plane program page
and erase block operations on a single die (LUN).
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Figure 70: TWO-PLANE PAGE READ
CLE
WE#
ALE
RE#
Page address M Page address M
00h Col Col Row Row Row 00h Col Col Row Row Row 30h
I/Ox add 1 add 2 add 1 add 2 add 3 add 1 add 2 add 1 add 2 add 3
Column address J Plane 0 address Column address J Plane 1 address tR
R/B#
CLE
WE#
ALE
RE#
I/Ox DOUT 0 DOUT 1 DOUT 06h Col Col Row Row Row E0h DOUT 0 DOUT 1 DOUT
Plane 0 data Plane 1 address Plane 1 data
R/B#
1
Notes: 1. Column and page addresses must be the same.

2. The least significant block address bit, BA6, must be different for the first- and second-
plane addresses.
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Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ
tR
R/B#
RE#
Address
I/Ox 00h Address (5 cycles) 00h Address (5 cycles) 30h Data output 05h (2 cycles) E0h Data output
Plane 0 address Plane 1 address Plane 0 data Plane 0 data
R/B#
RE#
Address
I/Ox 06h Address (5 cycles) E0h Data output 05h (2 cycles) E0h Data output
Plane 1 address Plane 1 data Plane 1 data
Figure 72: TWO-PLANE PROGRAM PAGE
tDBSY tPROG
R/B#
I/Ox 80h Address (5 cycles) Data input 11h 80h Address (5 cycles) Data input 10h 70h Status
1st-plane address 2nd-plane address
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Figure 73: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT
tDBSY
R/B#
I/Ox 80h Address (5 cycles) Data input 85h Address (2 cycles) Data input 11h 80h Address (5 cycles) Data input
1st-plane address Different column 2nd-plane address
address than previous
5 address cycles, for 1
1st plane only
Unlimited number of repetitions
tPROG
R/B#
I/Ox 85h Address (2 cycles) Data input 10h

Different column
address than previous
1 5 address cycles, for
2nd plane only
Unlimited number of repetitions
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Figure 74: TWO-PLANE PROGRAM PAGE CACHE MODE
tDBSY tCBSY
R/B#
I/Ox 80h Address/data input 11h 80h Address/data input 15h
1st plane 2nd plane

1
tDBSY tCBSY
R/B#
1st plane 2nd plane

1
2
tDBSY tLPROG
R/B#
1st plane 2nd plane

2
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Figure 75: TWO-PLANE INTERNAL DATA MOVE
tR tDBSY
R/B#
I/Ox 00h Address (5 cycles) 00h Address (5 cycles) 35h 85h Address (5 cycles) 11h
1st-plane source 2nd-plane source 1st-plane destination
tPROG
R/B#
I/Ox 85h Address (5 cycles) 10h 70h Status

2nd-plane destination
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Figure 76: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ
tR
R/B#
RE#
I/Ox 00h Address (5 cycles) 00h Address (5 cycles) 35h Data output 06h Address (5 cycles) E0h
1st-plane source 2nd-plane source Data from 1st-plane source 2nd-plane source address 1
R/B#
RE#
I/Ox Data output 05h Address (2 cycles) E0h Data output

Data from 2nd-plane Data from 2nd-plane source
1 2nd-plane source source column address from new column address
2
Optional
tDBSY tPROG
R/B#
RE#
I/Ox
85h Address (5 cycles) 11h 85h Address (5 cycles) 10h 70h Status
1st-plane destination 2nd-plane destination
2
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Figure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT
tR
R/B#
I/Ox 00h Address (5 cycles) 00h Address (5 cycles) 35h 85h Address (5 cycles) Data 85h Address (2 cycles) Data 11h
1st-plane source 2nd-plane source 1st-plane destination

Optional Unlimited number
of repetitions
tDBSY tPROG
R/B#
I/Ox 85h Address (5 cycles) Data 85h Address (2 cycles) Data 10h 70h Status
Optional
2nd-plane destination Unlimited number
of repetitions
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Figure 78: TWO-PLANE BLOCK ERASE
CLE
CE#
WE#
ALE
tDBSY tBERS
R/B#
RE#
I/Ox 60h Address input (3 cycles) D1h 60h Address input (3 cycles) D0h 70h Status
1st plane 2nd plane or 78h
Optional Don‘t Care
Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle
CE#
CLE
WE#
tAR
ALE
RE#
tWHR tREA
I/Ox 78h Address (3 cycles) Status output
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Interleaved Die (Multi-LUN) Operations
Interleaved Die (Multi-LUN) Operations

In devices that have more than one die (LUN) per target, it is possible to improve per-
formance by interleaving operations between the die (LUNs). An interleaved die (multi-
LUN) operation is one that is issued to an idle die (LUN) (RDY = 1) while another die
(LUN) is busy (RDY = 0).
Interleaved die (multi-LUN) operations are prohibited following RESET (FFh), identifi-
cation (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of
the die (LUNs) on the target.
During an interleaved die (multi-LUN) operation, there are two methods to determine
operation completion. The R/B# signal indicates when all of the die (LUNs) have finish-
ed their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes
HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the
READ STATUS ENHANCED (78h) command can report the status of each die (LUN) in-
dividually.
If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h),
then the die (LUN) is able to accept the data for another cache operation when status
register bit 6 is 1. All operations, including cache operations, are complete on a die
when status register bit 5 is 1.
During and following interleaved die (multi-LUN) operations, the READ STATUS (70h)
command is prohibited. Instead, use the READ STATUS ENHANCED (78h) command to
monitor status. This command selects which die (LUN) will report status. When two-
plane commands are used with interleaved die (multi-LUN) operations, the two-plane
commands must also meet the requirements in Two-Plane Operations.
See Command Definitions for the list of commands that can be issued while other die
(LUNs) are busy.
During an interleaved die (multi-LUN) operation that involves a PROGRAM series
(80h-10h, 80h-15h) operation and a READ operation, the PROGRAM series operation
must be issued before the READ series operation. The data from the READ series opera-
tion must be output to the host before the next PROGRAM series operation is issued.
This is because the 80h command clears the cache register contents of all cache regis-
ters on all planes.
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Error Management
Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks
(NVB) of the total available blocks. This means the die (LUNs) could have blocks that
are invalid when shipped from the factory. An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum required ECC.
Additional blocks can develop with use. However, the total number of available blocks
per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used
quite reliably in systems that provide bad block management and error-correction algo-
rithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad block mark into every loca-
tion in the first page of each invalid block. It may not be possible to program every loca-
tion with the bad block mark. However, the first spare area location in each bad block is
guaranteed to contain the bad block mark. This method is compliant with ONFI Factory
Defect Mapping requirements. See the following table for the first spare area location
and the bad block mark.
System software should check the first spare area location on the first page of each
block prior to performing any PROGRAM or ERASE operations on the NAND Flash de-
vice. A bad block table can then be created, enabling system software to map around
these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks could be marginal, it may not be possible to recover this information if the block
is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Always check status after a PROGRAM or ERASE operation
• Under typical conditions, use the minimum required ECC (see table below)
• Use bad block management and wear-leveling algorithms
The first block (physical block address 00h) for each CE# is guaranteed to be valid
with ECC when shipped from the factory.
Table 21: Error Management Details
Description Requirement
Minimum number of valid blocks (NVB) per LUN 4016
Total available blocks per LUN 4096
First spare area location x8: byte 2048
x16: word 1024
Bad-block mark x8: 00h
x16: 0000h
Minimum required ECC 4-bit ECC per 528 bytes
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Error Management
Table 21: Error Management Details (Continued)
Description Requirement
Minimum ECC with internal ECC enabled 4-bit ECC per 516 bytes (user data) + 8
bytes (parity data)
Minimum required ECC for block 0 if PROGRAM/ 1-bit ECC per 528 bytes
ERASE cycles are less than 1000
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Internal ECC and Spare Area Mapping for ECC

Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256
words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the spare
area. The metadata II area, which consists of two bytes (x8) and one word (x16), is not
ECC protected. During the busy time for PROGRAM operations, internal ECC generates
parity bits when error detection is complete.
During READ operations the device executes the internal ECC engine (5-bit detection
and 4-bit error correction). When the READ operaton is complete, read status bit 0 must
be checked to determine whether errors larger than four bits have occurred.
Following the READ STATUS command, the device must be returned to read mode by
issuing the 00h command.
Limitations of internal ECC include the spare area, defined in the figures below, and
ECC parity areas that cannot be written to. Each ECC user area (referred to as main and
spare) must be written within one partial-page program so that the NAND device can
calculate the proper ECC parity. The number of partial-page programs within a page
cannot exceed four.
Figure 80: Spare Area Mapping (x8)
Max Byte Min Byte

Address Address ECC Protected Area Description
1FFh 000h Yes Main 0 User data
801h 800h No Reserved
803h 802h No User metadata II
807h 804h Yes Spare 0 User metadata I
80Fh 808h Yes Spare 0 ECC for main/spare 0
817h 814h Yes Spare 1 User metadata I Bad Block ECC User Data
81Fh 818h Yes Spare 1 ECC for main/spare 1 Information Parity (Metadata)
821h 820h No Reserved 2 bytes 8 bytes 6 bytes
831h 830h No User data
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Figure 81: Spare Area Mapping (x16)
Max word Min word

Address Address ECC Protected Area Description
407h 404h Yes Spare 0 ECC for main/spare 0
40Bh 40Ah Yes Spare 1 User metadata I Bad Block ECC User Data
40Fh 40Ch Yes Spare 1 ECC for main/spare 1 Information Parity (Metadata)
410h 410h No Reserved 1 word 4 words 3 words
417h 414h Yes Spare 2 ECC for main/spare 2
418h 418h No User data
41Bh 41Ah Yes Spare 3 User metadata I
41Fh 41Ch Yes Spare 3 ECC for main/spare 3
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Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not guar-
anteed. Exposure to absolute maximum rating conditions for extended periods can af-
fect reliability.
Table 22: Absolute Maximum Ratings

Voltage on any pin relative to Vss
Parameter/Condition Symbol Min Max Unit
Voltage input 1.8V VIN –0.6 2.4 V
3.3V –0.6 4.6 V
VCC supply voltage 1.8V VCC –0.6 2.4 V
3.3V –0.6 4.6 V
Storage temperature TSTG –65 150 °C
Short circuit output current, I/Os – – 5 mA
Table 23: Recommended Operating Conditions
Parameter/Condition Symbol Min Typ Max Unit

Operating temperature Commercial TA 0 – 70 °C
Industrial –40 – 85 °C
VCC supply voltage 1.8V VCC 1.7 1.8 1.95 V
3.3V 2.7 3.3 3.6 V
Ground supply voltage VSS 0 0 0 V
Table 24: Valid Blocks
Parameter Symbol Device Min Max Unit Notes

Valid block NVB MT29F4G 4016 4096 Blocks 1, 2
number MT29F8G 8032 8192 Blocks 1, 2, 3
Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad
blocks upon shipment. Additional bad blocks may develop over time; however, the total
number of available blocks will not drop below NVB during the endurance life of the
device. Do not erase or program blocks marked invalid by the factory.
2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the
factory.
3. Each 4Gb section has a maximum of 80 invalid blocks.
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Table 25: Capacitance

Notes 1–3 apply to all parameters and conditions
Description Symbol Max Unit
Input capacitance CIN 10 pF
Input/output capacitance (I/O) CIO 10 pF
Notes: 1. These parameters are verified in device characterization and are not 100% tested.
2. Test conditions: TC = 25°C; f = 1 MHz; VIN = 0V.
3. Capacitance (CIN = CIO = 20pF) for MT29F8G and (CIN = CIO = 40pF) for MT29F16G.
Table 26: Test Conditions
Parameter Value Notes

Input pulse levels 0.0V to VCC
Input rise and fall times 1.8V 2.5ns
3.3V 5.0ns
Input and output timing levels VCC/2
Output load 1 TTL GATE and CL = 30pF (1.8V) 1
1 TTL GATE and CL = 50pF (3.3V)
Output load 1 TTL GATE and CL = 30pF (1.8V) 1
1 TTL GATE and CL = 50pF (3.3V)
Note: 1. Verified in device characterization, not 100% tested.
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Electrical Specifications – DC Characteristics and Operating
Conditions
Electrical Specifications – DC Characteristics and Operating Conditions
Table 27: DC Characteristics and Operating Conditions (3.3V)
Parameter Conditions Symbol Min Typ Max Unit Notes

Sequential READ current tRC = tRC(MIN); CE# = VIL; ICC1 – 25 35 mA
IOUT = 0mA
PROGRAM current – ICC2 – 25 35 mA
ERASE current – ICC3 – 25 35 mA
Standby current (TTL) CE# = VIH; ISB1 – – 1 mA 1
WP# = 0V/VCC
Standby current (CMOS) CE# = VCC - 0.2V; ISB2 – 20 100 µA
WP# = 0V/VCC
Staggered power-up cur- Rise time = 1ms IST – – 10 per die mA 2
rent Line capacitance = 0.1µF
Input leakage current VIN = 0V to VCC ILI – – ±10 µA
Output leakage current VOUT = 0V to VCC ILO – – ±10 µA
Input high voltage I/O[7:0], I/O[15:0], VIH 0.8 x VCC – VCC + 0.3 V
CE#, CLE, ALE, WE#, RE#,
WP#
Input low voltage, all in- – VIL –0.3 – 0.2 x VCC V
puts
Output high voltage IOH = –400µA VOH 0.67 x VCC – – V 3
Output low voltage IOL = 2.1mA VOL – – 0.4 V 3
Output low current VOL = 0.4V IOL (R/B#) 8 10 – mA 4
Notes: 1. ISB1 = 15mA if operating temperature is 105°C.

2. Measurement is taken with 1ms averaging intervals and begins after VCC reaches
VCC(MIN).
3. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
4. IOL (R/B#) may need to be relaxed if R/B pull-down strength is not set to full.
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Electrical Specifications – DC Characteristics and Operating
Conditions
Table 28: DC Characteristics and Operating Conditions (1.8V)
Parameter Conditions Symbol Min Typ Max Unit Notes

Sequential READ current tRC = tRC(MIN); CE# = VIL; ICC1 – 13 20 mA 1, 2
IOUT = 0mA
PROGRAM current – ICC2 – 10 20 mA 1, 2
ERASE current – ICC3 – 10 20 mA 1, 2
Standby current (TTL) CE# = VIH; ISB1 – – 1 mA
WP# = 0V/VCC
Standby current (CMOS) CE# = VCC - 0.2V; ISB2 – 10 50 µA
WP# = 0V/VCC
Staggered power-up cur- Rise time = 1ms IST – – 10 per die mA 3
rent Line capacitance = 0.1µF
Input leakage current VIN = 0V to VCC ILI – – ±10 µA
Output leakage current VOUT = 0V to VCC ILO – – ±10 µA
Input high voltage I/O[7:0], I/O[15:0], VIH 0.8 x VCC – VCC + 0.3 V
CE#, CLE, ALE, WE#, RE#,
WP#
Input low voltage, all in- – VIL –0.3 – 0.2 x VCC V
puts
Output high voltage IOH = –100µA VOH VCC - 0.1 – – V 4
Output low voltage IOL = +100µA VOL – – 0.1 V 4
Output low current (R/B#) VOL = 0.2V IOL (R/B#) 3 4 – mA 5
Notes: 1. Typical and maximum values are for single-plane operation only. If device supports dual-
plane operation, values are 20mA (TYP) and 40mA (MAX).
2. Values are for single-die operations. Values could be higher for interleaved-die opera-
tions.
3. Measurement is taken with 1ms averaging intervals and begins after VCC reaches
VCC(MIN).
4. Test conditions for VOH and VOL.
5. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full.
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Electrical Specifications – AC Characteristics and Operating
Conditions
Electrical Specifications – AC Characteristics and Operating Conditions
Table 29: AC Characteristics: Command, Data, and Address Input (3.3V)

Note 1 applies to all
Parameter Symbol Min Max Unit Notes
ALE to data start tADL 70 – ns 2
ALE hold time tALH 5 – ns
ALE setup time tALS 10 – ns
CE# hold time tCH 5 – ns
CLE hold time tCLH 5 – ns
CLE setup time tCLS 10 – ns
CE# setup time tCS 15 – ns
Data hold time tDH 5 – ns
Data setup time tDS 7 – ns
WRITE cycle time tWC 20 – ns 2
WE# pulse width HIGH tWH 7 – ns 2
WE# pulse width tWP 10 – ns 2
WP# transition to WE# LOW tWW 100 – ns
Notes: 1. Operating mode timings meet ONFI timing mode 5 parameters.

2. Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends
with the first rising edge of WE# for data input.
Table 30: AC Characteristics: Command, Data, and Address Input (1.8V)

ALE to data start tADL 70 – ns 2
ALE hold time tALH 5 – ns
ALE setup time tALS 10 – ns
CE# hold time tCH 5 – ns
CLE hold time tCLH 5 – ns
CLE setup time tCLS 10 – ns
CE# setup time tCS 20 – ns
Data hold time tDH 5 – ns
Data setup time tDS 10 – ns
WRITE cycle time tWC 25 – ns 2
WE# pulse width HIGH tWH 10 – ns 2
WE# pulse width tWP 12 – ns 2
WP# transition to WE# LOW tWW 100 – ns
Notes: 1. Operating mode timings meet ONFI timing mode 4 parameters.

2. Timing for tADL begins in the address cycle on the final rising edge of WE#, and ends
with the first rising edge of WE# for data input.
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Conditions
Table 31: AC Characteristics: Normal Operation (3.3V)

ALE to RE# delay tAR 10 – ns
CE# access time tCEA – 25 ns
CE# HIGH to output High-Z tCHZ – 50 ns 2
CLE to RE# delay tCLR 10 – ns
CE# HIGH to output hold tCOH 15 – ns
Output High-Z to RE# LOW tIR 0 – ns
READ cycle time tRC 20 – ns
RE# access time tREA – 16 ns
RE# HIGH hold time tREH 7 – ns
RE# HIGH to output hold tRHOH 15 – ns
RE# HIGH to WE# LOW tRHW 100 – ns
RE# HIGH to output High-Z tRHZ – 100 ns 2
RE# LOW to output hold tRLOH 5 – ns
RE# pulse width tRP 10 – ns
Ready to RE# LOW tRR 20 – ns
Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 µs 3
WE# HIGH to busy tWB – 100 ns
WE# HIGH to RE# LOW tWHR 60 – ns
Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will
go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5µs.
Table 32: AC Characteristics: Normal Operation (1.8V)

ALE to RE# delay tAR 10 – ns
CE# access time tCEA – 25 ns
CE# HIGH to output High-Z tCHZ – 50 ns 2
CLE to RE# delay tCLR 10 – ns
CE# HIGH to output hold tCOH 15 – ns
Output High-Z to RE# LOW tIR 0 – ns
READ cycle time tRC 25 – ns
RE# access time tREA – 22 ns
RE# HIGH hold time tREH 10 – ns
RE# HIGH to output hold tRHOH 15 – ns
RE# HIGH to WE# LOW tRHW 100 – ns
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Conditions
Table 32: AC Characteristics: Normal Operation (1.8V) (Continued)

RE# HIGH to output High-Z tRHZ – 65 ns 2
RE# LOW to output hold tRLOH 3 – ns
RE# pulse width tRP 12 – ns
Ready to RE# LOW tRR 20 – ns
Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 µs 3
WE# HIGH to busy tWB – 100 ns
WE# HIGH to RE# LOW tWHR 80 – ns
Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will
be busy for a maximum of 1ms. Thereafter, the device is busy for a maximum of 5µs.
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Electrical Specifications – Program/Erase Characteristics
Electrical Specifications – Program/Erase Characteristics
Table 33: Program/Erase Characteristics
Parameter Symbol Typ Max Unit Notes

Number of partial-page programs NOP – 4 cycles 1
BLOCK ERASE operation time tBERS 0.7 3 ms
Busy time for PROGRAM CACHE operation tCBSY 3 600 µs 2
Cache read busy time tRCBSY 3 25 µs
Busy time for SET FEATURES and GET FEATURES operations tFEAT – 1 µs
Busy time for OTP DATA PROGRAM operation if OTP is pro- tOBSY – 30 µs
tected
Busy time for PROGRAM/ERASE on locked blocks tLBSY – 3 µs
PROGRAM PAGE operation time, internal ECC disabled tPROG 200 600 µs 8
PROGRAM PAGE operation time, internal ECC enabled tPROG_ECC 220 600 µs 3, 8
Data transfer from Flash array to data register, internal ECC tR – 25 µs 6, 7
disabled
Data transfer from Flash array to data register, internal ECC tR_ECC 45 70 µs 3, 5
enabled
Busy time for OTP DATA PROGRAM operation if OTP is pro- tOBSY_ECC – 50 µs
tected, internal ECC enabled
Busy time for TWO-PLANE PROGRAM PAGE or TWO-PLANE tDBSY 0.5 1 µs
BLOCK ERASE operation
Notes: 1. Four total partial-page programs to the same page. If ECC is enabled, then the device is
limited to one partial-page program per ECC user area, not exceeding four partial-page
programs per page.
2. tCBSY MAX time depends on timing between internal program completion and data-in.
3. Parameters are with internal ECC enabled.
4. Typical is nominal voltage and room temperature.
5. Typical tR_ECC is under typical process corner, nominal voltage, and at room tempera-
ture.
6. Data transfer from Flash array to data register with internal ECC disabled.
7. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
8. Typical program time is defined as the time within which more than 50% of the pages
are programmed at nominal voltage and room temperature.
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Asynchronous Interface Timing Diagrams
Figure 82: RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
I/O[7:0] FFh
RESET
command
Figure 83: READ STATUS Cycle
tCLR
CLE tCLS tCLH
tCS
CE#
tWP tCH
WE#
tCEA tCHZ
tWHR tRP tCOH
RE#
tRHZ
tRHOH
tDS tDH tIR tREA
I/O[7:0] Status
70h output
Don’t Care
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Figure 84: READ STATUS ENHANCED Cycle
tCS
CE#
tCLS tCLH
CLE
tWC
tWP tWP tWH tCH
WE#
tCHZ
tCEA
tALH tALS tALH tAR tCOH
ALE
RE#
tRHZ
tDS tDH tWHR tRHOH

tREA
I/O[7:0] 78h Row add 1 Row add 2 Row add 3 Status output
Don’t Care
Figure 85: READ PARAMETER PAGE
CLE
WE#
tWB
ALE
tRC
RE#
tRR
tRP
I/O[7:0] ECh 00h P00 P10 P2550 P01
tR or tR_ECC
R/B#
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Figure 86: READ PAGE
CLE
tCLR
CE#
tWC
WE#
tWB
tAR
ALE
tRC tRHZ
tR or tR_ECC
RE#
tRR tRP
I/Ox Col Col Row Row Row 30h DOUT DOUT DOUT
00h
add 1 add 2 add 1 add 2 add 3 N N+1 M
RDY Busy
Don’t Care
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Figure 87: READ PAGE Operation with CE# “Don’t Care”
CLE
CE#
RE#
ALE
tR or tR_ECC
RDY
WE#
I/Ox 00h Address (5 cycles) 30h Data output
tCEA
CE#
tREA tCHZ
RE# tCOH
Don’t Care
I/Ox Out
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Figure 88: RANDOM DATA READ
CLE
tCLR
CE#
WE#
tRHW
tWHR
ALE
tRC tREA
RE#
I/Ox DOUT DOUT 05h Col Col E0h DOUT DOUT

N-1 N add 1 add 2 M M+1
Column address M
RDY
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Figure 89: READ PAGE CACHE SEQUENTIAL
CLE
tCLS tCLS tCLH
tCLH
tCH tCS
tCS tCH
CE#
tWC
WE#
tCEA tRHW
ALE
tRC
RE# tWB
tDH
tREA
tDS
tDS tWB tR tRR tDH
I/Ox 00h Col Col Row Row Row 30h 31h Dout Dout Dout 31h
add 1 add 2 add 1 add 2 add 3 0 1
Column address Page address tRCBSY Page address

00h M M
RDY
Column address 0
CLE
tCLS tCLH
tCS
tCH
CE#
WE#
tRHW tRHW
tCEA
ALE
tRC tRC
RE# tWB
tREA tDS tRR
tDH tREA
Dout Dout Dout Dout Dout Dout

I/Ox 0 1
Dout 31h 0 1
Dout 3Fh
0 1
Dout
Page address tRCBSY Page address tRCBSY Page address

M M+1 M+2
RDY
Column address 0 Column address 0 Column address 0
1 Don’t Care
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Figure 90: READ PAGE CACHE RANDOM
CLE
tCLS
tCLH
tCH
tCS
CE#
tWC
WE#
ALE
RE#
tDH
tWB tR
tDS
Col Col Row Row Row Col Col Row Row

I/Ox 00h add 1 add 2 add 1 add 2 add 3
30h 00h add 1 add 2 add 1 add 2
Column address Page address Column address Page address

00h M 00h N
RDY
CLE tCLS
tCLH
tCS
tCH
CE#
WE# tCEA tRHW
ALE
tRC
tWB
RE# tDS tRR

tDH tREA
Col Col Row Row Row 31h Dout Dout Dout 3Fh Dout Dout Dout
add 1 add 2 add 1 add 2 add 3 0 1 0 1
I/Ox
Column address Page address tRCBSY Page address tRCBSY Page address
00h N M N
RDY Column address 0 Column address 0
1 Don’t Care
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Figure 91: READ ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tWHR tREA
I/Ox 90h 00h or 20h Byte 0 Byte 1 Byte 2 Byte 3 Byte 4

Address, 1 cycle
Figure 92: PROGRAM PAGE Operation
CLE
CE#
tWC tADL
WE#
tWB tPROG or tWHR

tPROG_ECC
ALE
RE#
Col Col Row Row Row DIN DIN

I/Ox 80h add 1 add 2 add 1 add 2 add 3 10h 70h Status
N M
1 up to m byte
serial Input
RDY
Don’t Care
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Figure 93: PROGRAM PAGE Operation with CE# “Don’t Care”
CLE
CE#
WE#
ALE
I/Ox 80h Address (5 cycles) Data input Data input 10h
tCS tCH
CE#
tWP
WE#
Don’t Care
Figure 94: PROGRAM PAGE Operation with RANDOM DATA INPUT
CLE
CE#
tWC tADL tADL

WE#
tPROG or
tWB tPROG_ECC tWHR
ALE
RE#
Col Col Row Row Row DIN DIN Col Col DIN DIN
I/Ox 80h add 1 add 2 add 1 add 2 add 3 85h add 1 add 2 Q
10h 70h Status
M N P
CHANGE WRITE Column address READ STATUS
Serial input COLUMN command Serial input command
RDY
Don’t Care
PDF: 09005aef83b25735

Figure 95: PROGRAM PAGE CACHE
CLE
CE#
tWC tADL
WE#
tWB tCBSY tWB tLPROG tWHR
ALE
RE#
I/Ox 80h Col Col Row Row Row Din Din 15h 80h Col Col Row Row Row Din Din 10h 70h Status
add 1 add 2 add 1 add 2 add 3 N M add 1 add 2 add 1 add 2 add 3 N M
Serial input
RDY
Last page - 1 Last page
Don’t Care
Figure 96: PROGRAM PAGE CACHE Ending on 15h
CLE
CE#
tWC tADL tADL
WE#
tWHR tWHR
ALE
RE#
I/Ox 80h Col Col Row Row Row Din Din 15h 70h Status 80h Col Col Row Row Row Din Din 15h 70h Status 70h Status
add 1 add 2 add 1 add 2 add 3 N M add 1 add 2 add 1 add 2 add 3 N M
Serial input
Last page – 1 Last page

Poll status until: To verify successful completion of the last 2 pages:
I/O6 = 1, Ready I/O5 = 1, Ready
I/O0 = 0, Last page PROGRAM successful
I/O1 = 0, Last page – 1 PROGRAM successful
Don’t Care
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Figure 97: INTERNAL DATA MOVE
CLE
CE#
tWC tADL
WE#
tWB tWB tPROG tWHR
ALE
RE#
tR
I/Ox 00h Col Col Row Row Row 35h 85h Col Col Row Row Row Data Data 10h 70h Status
add 1 add 2 add 1 add 2 add 3 (or 30h) add 1 add 2 add 1 add 2 add 3 1 N
READ STATUS
Busy Busy command
RDY
Data Input Don’t Care

Optional
Figure 98: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled
tR_ECC tPROG_ECC
R/B#
I/O[7:0] 00h Address 35h 70h Status 00h DOUT 85h Address 10h 70h Status 00h
(5 cycles) (5 cycles)
Source address DOUT is optional Destination address
SR bit 0 = 0 READ successful SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error SR bit 1 = 0 READ error
PDF: 09005aef83b25735

Figure 99: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled
tR_ECC tPROG_ECC
R/B#
I/O[7:0] 00h Address 35h 70h Status 00h DOUT 85h Address Address
(5 cycles) (5 cycles) Data 85h (2 cycles) Data 10h 70h
Source address SR bit 0 = 0 READ successful DOUT is optional Destination address
SR bit 1 = 0 READ error Column address 1, 2
(Unlimitted repetitions are possible)
Figure 100: ERASE BLOCK Operation
CLE
CE#
WC
t
WE#
WB
t
WHR
t
ALE
RE#
BERS
t
Row Row Row

I/O[7:0] 60h add 1 add 2 add 3 D0h 70h Status
Row address READ STATUS

command
Busy
RDY
I/O0 = 0, Pass
I/O0 = 1, Fail
Don’t Care
PDF: 09005aef83b25735

Revision History
Revision History
Rev. R – 02/18
• Added Important Notes and Warnings section for further clarification aligning to in-
dustry standards
Rev. Q – 04/14
• Updated the ONFI statement in the READ PARAMETER PAGE (ECh) section
• Updated the LOCK TIGHT command section
Rev. P – 02/14
• Added information for automotive grade and automotive industrial grade parts
Rev. O – 08/13
• Updated Block Lock Feature and Lock Tight in Block Lock Feature
Rev. N – 10/12
• Updated part number chart with option X for product longevity program (PLP) under
Special Options
Rev. M – 02/12
• Updated ISB2 spec in 3.3V DC Characteristics and Operating Conditions table
Rev. L – 1/12
• Updated 63-ball package dimension drawing
• Corrected the P1 values in the Feature Addresses 01h: Timing Mode table
Rev. K – 11/11
• Command Definitions topic, Command Set table: Changed OTP DATA LOCK BY
BLOCK (ONFI) to OTP DATA LOCK BY PAGE (ONFI); fixed unresolved xref to c_inter-
leaved_die_multi-lun_operations.dita in note 2
• One-Time Programmable (OTP) Operations topic, OTP DATA PROTECT (80h-10) sec-
tion: Updated content
Rev. J – 09/11
• Deleted OCPL notation from 48-Pin TSOP – Type 1 figure
• Removed former 48-Pin TSOP – Type 1, CPL figure
Rev. I – 07/11
• Added 16Gb and 16Gb part numbers to document
• Updated part number chart to include 16Gb
• Added 16Gb density to Device and Array Organization
• Clarification to Notes for Electrical Specifications table
PDF: 09005aef83b25735

Revision History
Rev. H – 12/10
• Updated status bit 1 under Program Page in Status Operations
Rev. G – 10/10
• Removed the words "or by factory (always enabled)" from the General Description
Rev. F – 06/10
• Replaced blank with 3 for number of valid address cycles on Block Erase Two-Plane in
the Two-Plane Command Set Table
Rev. E – 05/10
• Changed status to Production
• Added part numbers to document
• Removed Endurance spec from Features and Parameter Page Data Structure Table
• Filled in missing values to READ ID Table
• Changed tBERS from .5 to .7 in Electrical Specifications – Program/Erase Characteris-
tics
• Replaced Status Register Definition table with the correct one for ECC
Rev. D – 03/10
• Updated value for byte 113 to 01h; value for byte 114 to 0Eh in Parameter Page Data
Structure Tables
• Updated note 6 in Electrical Specifications - Program/Erase Characteristics to say
"disabled"
• Fixed note typo in Features
• Updated OTP Protect - changed to protect by block; removed protect by page
• Updated 1.8V Active Current specs for single die and fixed typos in DC tables
Rev. C – 01/10
• Updated READ ID Tables to include the following value changes: Byte 1 –
MT29F4G08ABBDA (4Gb, x8, 1.8V) Value: ACh, MT29F4G16ABBDA (4Gb, x16, 1.8V)
Value: BCh; Byte 2 – MT29F4G08ABBDA Value: 90h, MT29F4G16ABBDA Value: 90h;
Byte 3 – MT29F4G08ABBDA Value: 15h, MT29F4G16ABBDA Value: 55h; Byte 4 –
MT29F4G08ABBDA Value: 56h, MT29F4G16ABBDA Value: 56h; Removed H4 from
part numbers
• Added Bare Die Parameter Page Data Structure Table
• Removed Boot Block
Rev. B – 10/09
• Removed part numbers: MT29F4G08ABBDAWP and MT29F4G16ABBDAWP
• Updated "Internal Data Move with Internal ECC Enabled" graphic spec from tR to
tR_ECC
• Updated "Internal Data Move with Random Data Input with Internal ECC Enabled"
graphic spec from tR to tR_ECC
• Updated Boot Block Operation to include dual-plane restrictions
PDF: 09005aef83b25735

Revision History
• Added tRCBSY spec to Electrical Specifications - Program/Erase Characteristics

• Added note for tPROG and tPROG_ECC specifications to Electrical Specifications -
Program/Erase Characteristics
• Moved note from tRHW to tRHZ in AC Characteristics and Operating Conditions
Rev. A – 07/09
• Initial release; Advance status
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
PDF: 09005aef83b25735

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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

NAND Flash Memory

Features • First block (block address 00h) is valid when ship-

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Part Numbering Information

Figure 1: Marketing Part Number Chart

Micron Technology Design Revision (shrink)

Product Family Production Status

Feature Set Interface

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 79

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Important Notes and Warnings

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Table 1: Signal Definitions

Signal1 Type Description2

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 2: 48-Pin TSOP – Type 1 (Top View)

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View)

C WP# ALE Vss CE# WE# R/B#

D Vcc2 RE# CLE NC NC NC

G DNU Vcc2 LOCK1 NC NC DNU

J NC I/O1 NC Vcc I/O5 I/O7

K Vss I/O2 I/O3 I/O4 I/O6 Vss

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)

C WP# ALE Vss CE# WE# R/B#

D Vcc RE# CLE NC NC NC

G DNU Vcc LOCK1 I/O13 I/O15 DNU

H I/O8 I/O0 I/O10 I/O12 I/O14 Vcc

J I/O9 I/O1 I/O11 Vcc I/O5 I/O7

K Vss I/O2 I/O3 I/O4 I/O6 Vss

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 5: 48-Pin TSOP – Type 1, CPL

0.25 Mold compound:

Note: 1. All dimensions are in millimeters.

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 6: 63-Ball VFBGA (10.5mm x 13mm)

0.8 TYP 1.0 MAX

10.5 ±0.1 Bottom side saw fiducials may or

Note: 1. All dimensions are in millimeters.

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 7: 63-Ball VFBGA (9mm x 11mm)

0.8 TYP 1.0 MAX

7.2 CTR 0.25 MIN

Note: 1. All dimensions are in millimeters.

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Figure 8: NAND Flash Die (LUN) Functional Block Diagram

WE# logic NAND Flash

Note: 1. The LOCK pin is used on the 1.8V device.

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Device and Array Organization