Chapter 2

Combinational Logic
Circuits
M. Morris Mano, Charles R. Kime. (2015). Logic and computer design fundamentals (5th ed.). Pearson.

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Contents

1. Binary Logic and Gates

2. Boolean Algebra
3. Standard Forms
4. Karnaugh Map (K Map)
5. Exclusive-Or Operation and Gates
6. HDL Representation - Verilog

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1. Binary Logic and Gates

• Digital circuits are hardware components that manipulate binary

information.
• The circuits are implemented using transistors and interconnections in complex
semi-conductor devices called integrated circuits.
• Each basic circuit is referred to as a logic gate.
• For simplicity in design, we model the transistor-based electronic circuits as
logic gates.
• Thus, the designer need not be concerned with the internal electronics of the individual
gates, but only with their external logic properties.
• Each gate performs a specific logical operation.
• The outputs of gates are applied to the inputs of other gates to form a digital circuit

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Binary Logic

• Binary logic deals with binary variables, which take on two

discrete values, and with the operations of mathematical
logic applied to these variables.
• Logical operators operate on binary values and binary
variables.
• Basic logical operators are the logic functions AND, OR and NOT.

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Binary Variables

• Two binary values have different names:

• True/False
• On/Off
• Yes/No
• 1/0
• We use 1 and 0 to denote the two values.
• Variable identifier examples:
• A, B, C, X, Y, Z
• RESET, START_IT, or ADD1

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Logical Operations

• The three basic logical operations are:

• AND : represented by a dot (.) or by the absence of an operator
• Z = X.Y or Z = XY is read “Z is equal to X AND Y.”
• OR : represented by a plus symbol (+)
• Z = X + Y is read “Z is equal to X OR Y.”
• NOT : represented by a bar over the variable (¯), a single quote
mark (') after, or (~) before the variable.
• Z = X is read “Z is equal to NOT X”

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Logical Operations

• AND operation OR operation NOT operation

0.0=0 0+0=0 0=1
0.1=0 0+1=1 1=0
1.0=0 1+0=1
1.1=1 1+1=1

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Logical Operations

• A truth table for an operation is a table of combinations of the

binary variables showing the relationship between the values
that the variables take on and the values of the result of the
operation.

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Logic Gates

• Logic gates are electronic circuits that operate on one or more

input signals to produce an output signal.
• Voltage-operated circuits respond to two separate voltage ranges that
represent a binary variable equal to logic 1 or logic 0.
• The input terminals of logic gates accept binary signals within the
allowable range and respond at the output terminals with binary signals
that fall within a specified range.
• The intermediate regions between the allowed ranges in the figure are
crossed only during changes from 1 to 0 or from 0 to 1.
• These changes are called transitions.

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Logic Gates

• Each gate has another very

important property called gate
delay, the length of time it takes
for an input change to result in the
corresponding output change.

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Logic Gates

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Commonly Used Logic Gates

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Commonly Used Logic Gates

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Logic Gates

• If we consider the inverter as a

degenerate version of NAND and NOR
gates with just one input, NAND gates
alone or NOR gates alone can
implement any Boolean function.
• Thus, these gate types are much more
widely used than AND and OR gates in
actual logic circuits. As a consequence,
actual circuit implementations are often
done in terms of these gate types.

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HDL Representations of Gates

• While schematics using the basic logic gates are sufficient

for describing small circuits, they are impractical for
designing more complex digital systems.
• In contemporary computer systems design, HDL (Hardware
Description Language) has become intrinsic to the design
process.
• VHDL
• Verilog
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HDL Representations of Gates

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HDL Representations of Gates

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2. Boolean Algebra

• The Boolean algebra is an algebra dealing with binary variables and logic
operations.
• The variables are designated by letters of the alphabet.
• The three basic logic operations are AND, OR, and NOT.
• A Boolean expression is an algebraic expression formed by using
• Binary variables
• Constants 0 and 1
• Logic operation symbols
• Parentheses.
• Boolean function
𝐿 𝐷, 𝑋, 𝐴 = 𝐷𝑋ത + 𝐴

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2. Boolean Algebra

• A Boolean function can be represented by a truth table.

• A truth table for a function is a list of all combinations of 1s and
0s that can be assigned to the binary variables and a list that
shows the value of the function for each binary combination.
• The number of rows in a truth table is 2n, where n is the number
of variables in the function.
• The binary combinations for the truth table are the n-bit binary numbers
that correspond to counting in decimal from 0 through 2n - 1.

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2. Boolean Algebra

• Function 𝐿 𝐷, 𝑋, 𝐴 = 𝐷𝑋ത + 𝐴

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2. Boolean Algebra

• Function 𝐿 𝐷, 𝑋, 𝐴 = 𝐷𝑋ത + 𝐴

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Boolean Algebra

• Circuit gates are interconnected by wires that carry logic

signals. Logic circuits of this type are called combinational
logic circuits, since the variables are “combined” by the
logical operations.
• There is only one way that a Boolean function can be
represented in a truth table. However, when the function is
in algebraic equation form, it can be expressed in a variety
of ways.
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Basic Identities of Boolean Algebra

• The dual of an algebraic expression is

obtained by interchanging OR and AND
operations and replacing 1s by 0s and 0s
Dual by 1s.

Dual

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Basic Identities of Boolean ALgebra

• DeMorgan’s theorem can be extended to three or more

variables.

• For example

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Basic Identities of Boolean Algebra

• Using truth tables to prove the logical equivalence

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Algebraic Manipulation

• Boolean algebra is a useful tool for simplifying digital

circuits.

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Algebraic Manipulation

• Each circuit implements the same function, but the

one with fewer gates and/or fewer gate inputs is
preferable because it requires fewer components 27
Algebraic Manipulation

• When a Boolean equation is implemented with

logic gates, each term requires a gate, and each
variable within the term designates an input to the
gate. We define a literal as a single variable within a
term that may or may not be complemented.
• Figure 2-8(a): 3 terms, 8 literals
• Figure 2-8(b): 2 terms, 4 literals
• By reducing the number of terms, the number of
literals, or both in a Boolean expression, it is often
possible to obtain a simpler circuit. Boolean algebra
is applied to reduce an expression for the purpose
of obtaining a simpler circuit.

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Algebraic Manipulation

• Some useful equalities

Dual

• Consensus theorem

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Complement of a Function

• 1. The complement of a function can be derived algebraically by

applying DeMorgan’s theorem.
• 2. A simpler method for deriving the complement of a function is
to take the dual of the function equation and complement each
literal.
• 3. The complement representation for a function F, 𝐹,ത obtained
from an interchange of 1s to 0s and 0s to 1s for the values of F in
the truth table.

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Complement of a Function

• 1. Complementing a function by applying DeMorgan’s

theorem

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Complement of a Function

• 3. Complementing
a function by using
dual

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Complement of a Function

• 3. The complement representation for a function F, 𝐹,ത obtained from an

interchange of 1s to 0s and 0s to 1s for the values of F in the truth table.
D X A ഥ+𝑨
𝑳 = 𝑫𝑿 𝑳ത
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 0
1 1 0 0 1
1 1 1 1 0 33
3. Standard Forms

• The standard forms facilitate the simplification procedures for Boolean

expressions and, in some cases, may result in more desirable
expressions for implementing logic circuits.
• The standard forms contain product terms and sum terms.
• Product term: This is a logical product consisting of an AND operation among
three literals.

• Sum term: This is a logical sum consisting of an OR operation among the literals.

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Minterms and Maxterms

• Minterm: A product term in which all the variables appear

exactly once, either complemented or uncomplemented, is
called a minterm.
• Maxterm: A sum term that contains all the variables in
complemented or uncomplemented form is called a
maxterm.

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 Minterms and Maxterms

• n is the number of variable -> 2n minsterms, 2n maxterms

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Minterms and Maxterms

• 2n maxterms

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Minterms and Maxterms

• A Boolean function can be represented algebraically from a

given truth table by
• A sum of minterms
• A product of maxterms

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Standard Forms • 1. Sum-of-Products Form
• sum of all the minterms that produce a 1 in
the function

2. Product-of-Sums Form
product of all the maxterms that produce a 0 in
the function
F

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Minterms and Maxterms

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Sum of Products

• The AND gates followed by the

OR gate form a circuit
configuration referred to as a
two-level implementation or
two-level circuit.

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Sum of Products

• The decision as to whether to

use a two-level or multiple-level
(three levels or more)
implementation is complex.
• Among the issues involved are
the number of gates, number
of gate inputs, and the amount
of delay between the time the
input values are set and the
time the resulting output values
appear. Two-level
implementations are the natural
form for certain
implementation technologies.
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Cost Criteria

• Cost Criteria:
• To formalize the way of measuring the simplicity of a logic circuit
• Literal cost and gate-input cost
• Literal cost
• The number of literal appearances in a Boolean expression
corresponding exactly to the logic diagram

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 Literal Cost
Literal cost 5 6

• Literal cost has the advantage that it is very simple to

evaluate by counting literal appearances.
• It does not, however, represent circuit complexity accurately
in all cases, even for the comparison of different
implementations of the same logic function.

Literal cost 8 8
But, the first equation has two terms and the second has four. This suggests
that the first equation has a lower cost than the second. 44
 Gate-Input Cost

• Gate-input cost is the number of inputs to the gates in the implementation

corresponding exactly to the given equation or equations.
• 1. all literal appearances,
• 2. the number of terms excluding terms that consist only of a single literal, and,
optionally,
• 3. the number of distinct complemented single literals

Gate-Input cost 8+2+4 8+4+4

Gate-input cost is currently a good measure for contemporary logic
implementations, since it is proportional to the number of transistors
and wires used in implementing a logic circuit
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4. Karnaugh Map (K Map)

• The K map is a graphical tool

• Simplify a logic expression
• Convert a truth table into a simple one
• Each case in the truth table corresponds to a square in the K map.
• Horizontally or vertically, adjacent square differs only in ONE
variable.
• Once a K map has been filled with 0s and 1s, the sum-of-products
expression for the output X can be obtained by ORing together those
squares that contain a 1.

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Two-Variable K Map

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Two-Variable K Map

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Three-Variable K Map

BC BC BC BC

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Three-Variable K Map

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Four-Variable K Map

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Karnaugh Map

• Looping: The expression for the output X can be simplified

by properly combining those squares in the K map that
contain 1s. The process for combining these 1s is called
“looping”.

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Looping Groups of Two (pairs)

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Looping Groups of Two (pairs)

• Looping a pair of adjacent 1s in

a K map eliminates the variable
that appears in complemented
and un-complemented form.
• The two 1s in the top row are
horizontally adjacent.
• The leftmost column and the
rightmost column of squares
are considered to be adjacent.

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Looping Groups of Two (pairs)

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Looping Groups of Four (Quads)

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 Looping Groups of Four (Quads)

• Looping a quad of adjacent

1s eliminates the two
variables that appear in
both complemented and
un-complemented form.

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 Looping Groups of Eight (Octets)

• Looping an eight of
adjacent 1s eliminates
the three variables
that appear in both
complemented and
un-complemented
form.

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 Looping Groups of Eight (Octets)

• Looping an eight of
adjacent 1s eliminates
the three variables
that appear in both
complemented and
un-complemented
form.

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 Karnaugh Map

• Simplification process
1. Construct the K map and place 1s in those squares corresponding to the 1s in the truth
table. Place 0s in the other squares.
2. Examine the map for adjacent 1s and loop those 1s that are not adjacent to any other 1s.
These are called isolated 1s.
3. Next, look for those 1s that are adjacent to only one other 1. Loop any pair containing such
a 1.
4. Loop any octet even if it contains some 1s that have already been looped.
5. Loop any quad that contains one or more 1s that have not already been looped, making
sure to use the minimum number of loops.
6. Loop any pairs necessary to include any 1s that have not yet been looped, making sure to
use the minimum number of loops.
7. Form the OR sum of all the terms generated by each loop.

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Karnaugh Map

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Karnaugh Map

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Karnaugh Map

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Karnaugh Map

• Filling a K Map from an Output Expression

• 1. Get the expression into SOP form if it is not already in that form.
• 2. For each product term in the SOP expression, place a 1 in each
K-map square whose label contains the same combination of input
variables. Place a 0 in all other squares.

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 Karnaugh Map

• Use a K map to simplify

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Karnaugh Map

• Use a K map to simplify

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Karnaugh Map

• Product-of-Sum Optimization
• Simplify the following Boolean function in product-of-sums form:

The squares marked with 0s represent the minterms not included

in F and therefore denote the complement of F.
Combining the squares marked with 0s, we obtain the optimized
complemented function

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 Don’t-Care Conditions

• Some logic circuits can be

designed so that we “don’t
care” whether the output is 1
or 0.
• The x represents the don’t-
care condition.
• A circuit designer is free to
make the output for any
don’t-care condition either a
0 or a 1 to produce the
simplest output expression.
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5. Exclusive-Or Operation and Gates

𝑋⨁𝑌 = 𝑋𝑌ത + 𝑋𝑌
ത

𝑋⨁𝑌 = 𝑋𝑌ത + 𝑋𝑌
ത = 𝑋ത + 𝑌 𝑋 + 𝑌ത = 𝑋𝑌 + 𝑋ത 𝑌ത

• The following identities apply to the exclusive-OR operation:

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5. Exclusive-Or Operation and Gates

• Exclusive-OR operation is both commutative and

associative:

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6. HDL Representation - Verilog

• A Two-bit greater-than comparator A > B

• A>B : The output is 1
• Otherwise: The output is 0

• A = A1A0 : A 2-digit binary number A

• A1: The most significant bit (MSB)
• A0: The lest significant bit (LSB)
• B = B1B0 : A 2-digit binary number B
• B1: The most significant bit (MSB)
• B0: The lest significant bit (LSB)

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A1 A0 B1 B0 A is greater than B
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
A_greater_than_B = 𝐴1 𝐴0 𝐵1 𝐵0 + 𝐴1 𝐴0 𝐵1 𝐵0
0 1 0 0 1 𝐴1 𝐴0 𝐵1 𝐵0 + 𝐴1 𝐴0 𝐵1 𝐵0 +𝐴1 𝐴0 𝐵1 𝐵0
0 1 0 1 0 + 𝐴1 𝐴0 𝐵1 𝐵0 +𝐴1 𝐴0 𝐵1 𝐵0
0 1 1 0 0 B1B0
0 1 1 1 0 00 01 11 10
1 0 0 0 1 𝐴1 𝐴0 𝐵1 𝐵0 00
1 0 0 1 1 𝐴1 𝐴0 𝐵1 𝐵0 A1A0 01 1

1 0 1 0 0 11 1 1 1
10 1 1
1 0 1 1 0
1 1 0 0 1 𝐴1 𝐴0 𝐵1 𝐵0 A_greater_than_B= 𝐴1 𝐵1 + 𝐴0 𝐵1 𝐵0 + 𝐴1 𝐴0 𝐵0
1 1 0 1 1 𝐴1 𝐴0 𝐵1 𝐵0
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1 1 1 0 1 𝐴1 𝐴0 𝐵1 𝐵0
1 1 1 1 0
Two-Bit Greater-Than Circuit

A_greater_than_B= 𝐴1 𝐵1 + 𝐴0 𝐵1 𝐵0 + 𝐴1 𝐴0 𝐵0

and0_out

B1_n

and1_out

and2_out
B0_n
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Two-Bit Greater-Than Circuit
and0_out

B1_n
and1_out

and2_out
B0_n

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 Structural Verilog Description of Two-Bit
Greater-Than Circuit and0_out

B1_n
• Equivalent to the circuit schematic and1_out

• Gate-level modeling
and2_out
B0_n

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• // : Single line comment
• /* .. : Multiline comment
*/
• input [1:0] A, B;
• A and B are vectors with a width of two, with the most significant (leftmost) bit numbered 1 and
least significant (rightmost) bit numbered 0. A[1] A[0] B[1] B[0]
A B

• In Verilog, wire is the default net type. Notably, input and output ports have the
default type wire. 76
77
Dataflow Verilog Description

• A dataflow description describes a circuit in terms of

function rather than structure and is made up of concurrent
assignment statements or their equivalent.
• Concurrent assignment statements are executed
concurrently (i.e., in parallel) whenever one of the values on
the right-hand side of the statement changes.
• For example, whenever a change occurs in a value on the right-
hand side of a Boolean equation, the left-hand side is evaluated.

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 and0_out

B1_n
and1_out

• Dataflow Modeling
and2_out
B0_n

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• The order of execution of the assignment statements does not depend upon
the order of their appearance in the model description, but rather on the order
of changes of signals on the right-hand side of the assignment statements.

• The description would have exactly the same

behavior even if the assignment statements were
listed in some other order, e.g., if lines 10 and 15
were interchanged. 80
Behavioral Verilog Description

• Dataflow models using concurrent assignments are

considered to be behavioral descriptions, because they
describe the function of the circuit without describing its
structure.
• Verilog provides ways to describe circuits at levels higher
than the logic level.

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Behavioral Verilog Description

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Testbenches

• A testbench is an HDL
model whose purpose is
to test another model,
often called the Device
Under Test (DUT), by
applying stimuli to the
inputs.
• More complex testbenches
will also analyze the output
of the DUT for correctness.

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Testbenches

• $display : print the immediate values

• $strobe : print the values at the end of the current timestep
• $monitor : print the values at the end of the current
timestep if any values changed.
• $monitor can only be called once; sequential call will override the
previous.

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