Shift Reegisters
Shift Reegisters
The simplest possible shift register is one that uses only flip-flops, as shown in Fig.
Each clock pulse shifts the contents of the register one bit position to the right.
The serial input determines what goes into the leftmost flip-flop during the shift.
The serial output is taken from the output of the rightmost flip-flop.
Following are the four types of shift registers based on applying inputs and accessing of outputs.
Serial In − Serial Out shift register
Serial In − Parallel Out shift register
Parallel In − Serial Out shift register
Parallel In − Parallel Out shift register
Serial In − Serial Out (SISO) shift register
The shift register, which allows serial input and produces serial output is known as Serial In – Serial
Out (SISO) shift register.
This block diagram consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop
is connected as the input of next D flip-flop.
All these flip-flops are synchronous with each other since, the same clock signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is
also called as serial input.
For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we can
receive the bits serially from the output of right most D flip-flop. Hence, this output is also called as serial
output.
101
Serial In − Parallel Out (SIPO) shift register
The shift register, which allows serial input and produces parallel output is known as Serial In –
Parallel Out (SIPO) shift register.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence,
this input is also called as serial input.
For every positive edge triggering of clock signal, the data shifts from one stage to the next.
In this case, we can access the outputs of each D flip-flop in parallel. So, we will get parallel
outputs from this shift register.
101
Parallel In − Serial Out (PISO) shift register
In the "Parallel In Serial Out" register, the data is entered in a parallel way, and the outcome
comes serially.
The shift mode and the load mode are the two modes in which the "PISO" circuit works.
Parallel In − Parallel Out (PIPO) shift register
In "Parallel In Parallel Out", the inputs and the outputs come in a parallel way in the register.
The inputs B0, B1, B2, and B3, are directly passed to the data inputs D0, D1, D2, and D3 of the
respective flip flop.
The bits of the binary input is loaded to the flip flops when the negative clock edge is applied. The
clock pulse is required for loading all the bits. At the output side, the loaded bits appear.
Input
Bidirectional Shift Register
Below is the diagram of 4-bit "bidirectional" shift register where DR is the "serial right shift data
input", DL is the "left shift data input", and M is the "mode select input".
(L/R)
M
Universal Shift Register
A shift-right control to enable the shift operation and the serial input and output lines associated with the shift right.
A shift-left control to enable the shift operation and the serial input and output lines associated with the shift left.
A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer.
If the Shift register has the capability of
Serial In − Serial Out
Serial In − Parallel Out
Parallel In − Serial Out
Parallel In − Parallel Out
and act as Bidirectional shift register is referred as a universal shift register.
Shift registers are often used to interface digital system situated remotely from each other. If the distance is far, it
will be expensive to use n lines to transmit the n bits in parallel.
Transmitter performs a parallel-to-serial conversion of data and the receiver does a serial-to-parallel conversion.
R/L
SH/LOAD
Universal Shift Register using MUX
Serial
input for
shift-left
Typical ICs for Shift register