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EIOT UNIT 1 - Interrupt Handling

The document discusses interrupt handling in 8051 microcontrollers. It describes the interrupt service routine and six interrupt sources of 8051 including timers, external interrupts, and serial port. It also covers interrupt priorities and how to program external interrupts as either level-triggered or edge-triggered.

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Aiswarya Ilango
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42 views14 pages

EIOT UNIT 1 - Interrupt Handling

The document discusses interrupt handling in 8051 microcontrollers. It describes the interrupt service routine and six interrupt sources of 8051 including timers, external interrupts, and serial port. It also covers interrupt priorities and how to program external interrupts as either level-triggered or edge-triggered.

Uploaded by

Aiswarya Ilango
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Timers and Serial Port

Interrupt Handling
Interrupt Service Routine
Interrupt Service Routine (ISR) is a specialized

subroutine that handles interrupts generated by

external events or internal conditions, allowing the

microcontroller to respond promptly to asynchronous

events without halting its main execution flow.

3
Six Interrupts of 8051
RESET
Timers 0 and Timer 1
INT0 and INT1
Serial Port

4
Interrupt Priorities of 8051

SOURCE LOCATION PRIORITY LEVEL


INT0 0003H Highest
T0 000BH
INT1 0013H
T1 001BH
Serial Port 0023H Lowest
Interrupt Enable Register
Interrupt Priority Register of 8051
8051 has five sources of interrupts
⚫ INT0 and INT1 are two external interrupt inputs.
⚫ Edge sensitive interrupts programmed with IT0 and IT1
in register TCON. Interrupts are processed by IE0 and IE1.
Flags are automatically cleared after the control is
transferred.
⚫ Level sensitive interrupts where the flags are controlled
by external interrupt sources.
⚫ The TIMER0 and TIMER1 interrupt sources are generated
by TF0 and TF1 bits of the register TCON. When
interrupts are generated, the respective flags are
generated. 8
Programming External
Hardware Interrupts
The external interrupts of 8051 are INT0 and INT1. The
TCON register is Time Control, bit addressable having
address 88H.
It is used to program external interrupts to edge or level
triggered.

9
Level Triggered Interrupt
Level-Triggered Interrupt INTO and INT I pins are normally
high.
If a low-level signal is applied to them, it triggers the
interrupt.
The microcontroller stops whatever it is doing and jumps to
the interrupt vector table to service that interrupt.
The low-level signal at the INT pin must be removed before
the execution of the last instruction of the ISR, RETI .
Otherwise, another interrupt will be generated. This is
called a level-triggered or level-activated interrupt and is the
default mode upon reset
10
Level Triggered Interrupt

11
Edge Triggered Interrupt
To make INTO and INT I edge-triggered interrupts, we
must program the bits of the TCON register The TCON
register holds the IT0 and IT1 flag bits that determine
level- or edge-triggered mode of the hardware interrupt
ITO and IT I are bits D0 and D2 of TCON They are also
referred to asTCON.0 and TCON.2 since the TCON
register is bit-addressable

12
D1 and D3 of TCON determines whether level triggered
or edge triggered mode of interrupt. they are also
referred to as TCON.1 and TCON.3

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