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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2764903, IEEE
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A Bi-Directional Series Z-Source Circuit Breaker

Daniel J. Ryan, Student Member, IEEE, Hugh D. Torresan, Member, IEEE, and Behrooz Bahrani, Member, IEEE

Abstract— A Z-Source series circuit breaker topology, which semiconductor junctions, lack galvanic isolation, and have
allows bi-directional power flow, and has the ability to au- low fault current capability. Thus, there has been significant
tonomously disconnect DC faults is introduced. This topology research effort to address these issues.
allows current flow in the forward and reverse directions
through the use of a diode bridge. The diode bridge allows In order to increase the efficiency of PECBs, use of custom
response to faults on either the source or load side with only silicon [13] or wide band-gap semiconductors [14]–[17] has
a single controlled switch. No additional passive components been investigated. However, currently the availability of these
are required when compared with the uni-directional series Z- semiconductor devices is limited, particularly at high voltage
Source circuit breaker topology. Analysis is performed to find and current levels. Another alternative can be hybrid circuit
the fault conditions that cause the bi-directional circuit breaker
to trip when operating in a single load power system. Then, breakers, which combine an ACB and PECB in parallel [18]–
using the simulation platform Matlab/Simulink, operation of [23]. Hybrid circuit breakers provide efficiency similar to
the bi-directional circuit breaker is evaluated for both source ACBs. However, they are costly and have increased response
and load side faults. To experimentally validate the findings, an time compared with PECBs. This makes managing fault
experimental prototype has been implemented. This prototype is currents in the semiconductor switch difficult.
used to confirm the circuit breaker’s function in both the forward
and reverse directions in addition to its response to source side Additionally, the fault detection and control system required
faults. for PECBs increases response time, increases cost, and adds
a point of failure. To address this, Z-Source circuit break-
Index Terms—Bi-directional Circuit Breaker, DC Systems,
Power Electronic Circuit Breaker, Protection Systems, Z-Source ers (ZCBs), a type of PECB that autonomously respond to
Circuit Breaker faults, are proposed [24], [25]. Autonomous operation lowers
response time, reduces sensing and processing electronics, and
limits fault current. Additionally, passive components used in
I. I NTRODUCTION ZCBs limit the peak current in the semiconductor switch,
so that it is not required to withstand high fault currents.
R ECENTLY, there has been a trend towards using direct
current (DC) in power systems. Applications being in-
vestigated are: electric ships [1], high-voltage DC (HVDC)
Thus, ZCBs address two of the four issues mentioned above.
Furthermore, in order to lower loss in a ZCB, it is possible
networks [2], micro-grids [3], [4], data-centres [5], battery to integrate modern semiconductor devices into the ZCB [13].
energy storage [6], and wind farms [7]. However, viability of Moreover, a simple no-load switch can be used to provide
applications that use medium voltage DC (MVDC) is limited galvanic isolation for safety reasons, opening once the fault
by current DC circuit breaker technology. current is broken.
Protection of low-voltage DC (LVDC) systems is commonly In order to improve upon the first proposed ZCBs, the series
achieved using arc-based circuit breakers (ACBs). However, ZCB topology, shown in Fig. 1, is proposed in [26], [27].
DC systems lack a natural zero-current crossing, which in- When compared with other ZCBs, it maintains a common
creases the difficulty of extinguishing the arc generated when neutral between the input and output. Additionally, its transfer
the ACB opens [8]. Thus, as voltage and fault current in- function is that of a second-order low-pass filter, which is
crease, the size and cost of such ACBs become prohibitive. suitable for input filtering of power electronic converters. This
Thus, medium-voltage DC (MVDC) systems require a novel allows the CB to serve two purposes: (1) fault protection and
solution. (2) filtering. Integrating the CB into the input filter of power
Power electronic circuit breakers (PECBs) are an alternative electronic converters reduces the number of components and
to ACBs, which use semiconductors rather than mechanical cost of a DC power system. Furthermore, the peak source
switches. The series and parallel connection of semiconductor current during fault interruption is reduced compared to some
devices provides scalability. This allows PECBs to operate in other ZCB topologies.
MVDC systems, which operate at higher voltage and fault In [28], a modified series ZCB is proposed for discrimination
current levels than are feasible for ACBs [9]. Additionally, between load steps and faults. In [29], a series ZCB with
PECBs can limit fault currents, due to their high operating mutually-coupled inductors is proposed for reduced volume
speed [10]–[12]. and weight. However, none of the proposed series ZCBs
Although PECBs provide these advantages, they require addi- allow bi-directional power flow. The capability of operating
tional sensing and control circuitry, have power loss in the with bi-directional power flow is an increasingly common
requirement for modern power systems. Driving this increase
D. Ryan and B. Bahrani are with the Department of Electrical and Computer is the expanding use of energy storage systems, redundant
Systems Engineering, Monash University, Melbourne 3800, Australia (e-mail: network structures such as the ring-bus, and grid-connected
[email protected]; [email protected]).
H. Torresan is with the Defence Science and Technology Group, Melbourne micro-grids, which may either absorb or supply power from
3207, Australia their point of common-coupling (PCC). System protection

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C1
if,ZCB D5 L1
D1 D3
L1 T1 L2 LL
T1
D1 D2 if,C IL
D2 C1 D4
VS C2 if CL RL D6 L2
VS CL RL

C2

Fig. 1. Fault current path of uni-directional series ZCB [27].

Fig. 2. Steady-state current flow of the proposed topology.

must take this requirement into account.
This paper introduces a bi-directional series ZCB, which is
scalable for MVDC systems. The proposed ZCB retains the fringe cases for fault detection. They also define the maxi-
advantages of the series ZCB including common neutral, mum allowable load current slew rate and load step change.
reduced peak source current, and a low-pass filter frequency In the analysis performed, it is assumed C1 = C2 = CZCB
response characteristic. In this paper, the performance of the and L1 = L2 = L. The investigation is undertaken with bi-
proposed ZCB in a simple power system is theoretically ana- directional series ZCB in a simple power system, which is
lyzed, and several expressions for various operating scenarios shown in Fig. 2. In this system, the ZCB is protecting an
of the ZCB are developed. The expressions derived are vali- RC load, which is being supplied by an ideal DC voltage
dated with simulated results. Additionally, experimental results source and a line with inductance LL . The load capacitance CL
of the bi-directional series ZCB are presented, which validate represents the typically large input capacitance of a voltage-
its operation in both the forward and reverse directions, and fed power electronic converter. In order for the CB to switch
its response to source side faults. from the off-state to the on-state, T1 is gated on. The gating
This paper is structured as follows. Section II describes signal can be released once the CB reaches a steady-state.
the introduced bi-directional series ZCB topology and its
operational principles, and provides an analysis of various A. On-state Operation
fault conditions. Section III provides a comparison of the In the on-state (Fig. 2), the line inductance LL , L1 , and L2
proposed bi-directional series ZCB topology with competing pass the steady-state load current IL , and the voltage drop
bi-directional Z-Source topologies. In Section IV, the perfor- across the inductances is zero. D1 and D4 are conducting
mance of the proposed ZCB is validated through simulation while D2 and D3 are in the reverse-blocking state. Assuming
and experimental results. Section V concludes the paper. ideal components, the load voltage is VS , C2 is charged to VS ,
and C1 is discharged. If the source and load connections are
II. B IDIRECTIONAL S ERIES Z-S OURCE C IRCUIT B REAKER swapped, the CB behaves in the same manner. However, D2
T OPOLOGY and D3 are in the forward conducting state, while D1 and D4
are in the reverse-blocking state.
The proposed bi-directional series ZCB is shown in Fig. 2. In an application such as protection of energy storage, where
The full-bridge arrangement of diodes allows load current to the power flow may gradually change from one direction to
flow in either direction while retaining the same conduction another, T1 may switch off when the current flow direction
path through the Z-Source inductors and thyristor. Thus, reverses. This is because as the power flow direction reverses,
the CB limits and interrupts fault current regardless of the the load current must drop momentarily to zero. The thyristor
direction of power flow. Additionally, the CB responds to has a specified turn-off time tq and holding current iH . If
faults on either set terminals. the thyristors current is allowed to fall below iH for a period
A description of the CB’s on-state operation is given in longer than tq , it switches to the blocking state. To avoid this,
Subsection II-A. Subsection II-B gives a description of the the CB’s control system must provide a gating signal to T1
CB’s response to output faults. This is followed by a derivation when the power flow direction changes.
of the CB’s minimum output fault conductance in Subsec-
tion II-C, and minimum detectable output fault ramp-rate
(Frr) in Subsection II-D. Subsection II-E gives a description B. Response to Output Faults
of the CB’s response to input faults. This is followed by When a fault is applied to the CB’s output, while it is
a derivation of the CB’s minimum input fault conductance operating in the on-state, the fault current flows through the
in Subsection II-F, and minimum detectable input Frr in red path shown in Fig. 3(a). The fault current is divided into
Subsection II-G. Finally, in Subsection II-H the maximum if,ZCB and if,C ; if,ZCB flows through the Z-Source capacitors,
voltage and current stresses for the components of the circuit and if,C flows through the load capacitance. When the fault
breaker are tabulated. first occurs, the Z-Source inductors resist a change in current,
The minimum detectable Frr and fault conductance are re- thus, their currents remain at their pre-fault level IL . Inspecting
quired in selection of the CB’s passive components to find the the node (a) current, as shown in Fig. 3(a), when if,ZCB rises

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D5 D5
L1 L1
D1 R1 D3 D1 R1 D3 if,C
LL LL
T1 T1
(a) if,S (a)
D2 D6 C1 D4 if D2 D6 C1 D4
R2 L2 R2 L2 if,C
VS CL RL VS if CL RL

C2 if,ZCB if,C C2 if,ZCB

(a) Fault on output. (b) Fault on input.

Fig. 3. Fault current flow of the proposed topology for a: (a) fault on the input, and (b) fault on the output.

to IL , iT is zero causing T1 to commutate off. Once T1 turns Through analysis of the fault node, where load current and
off, two series LC circuits are formed: (1) through L1 , C1 , and inductor current are assumed to be equal, it is found that
the fault, and (2) through L2 , C2 , and the fault. With typical
if (t) = if,ZCB (t) + if,C (t). (2)
component values, both circuits have under-damped resonant
responses, which are decoupled when fault impedance is zero. Assuming C1 = C2 = CZCB and substituting for iF from (1)
The initial conditions for resonance are determined by the in (2) result in:
steady-state operating point of the circuit.
CZCB dvf (t) dvf (t)
When these circuits begin to resonate, vC2 falls, and vC1 rises. Gf vf (t) = − − CL . (3)
When vC1 rises above VS , the inductor voltages fall below zero 2 dt dt
and are clamped by the diodes D5 and D6 . This restricts the Assuming a loss-less CB, CL is charged to VS during steady-
thyristor voltage from rising above the source voltage, which state operation. Thus, the initial condition is
lowers the forward blocking voltage requirement of T1 to VS . vf (0) = VS . (4)
The inductor current is clamped at the current peak of the
LC circuit, thus, the circuits stored energy is dissipated in the Through solving (3) with the initial condition (4),
clamping diodes (D5 & D6 ). In practice, a resistor could be 2 Gf
added in series with the clamping diode as shown in Fig. 3(a) − t
vf (t) = VS e CZCB + 2CL . (5)
in order to dissipate the stored energy more quickly. However,
the resistor’s voltage drop increases the blocking requirement Thus, using
of the thyristor.
dvC (t) CZCB dvf (t)
During the resonance, the output diode (D2 or D4 ) current iC (t) = C = , (6)
is the sum of the current in the two series LC circuits. The dt 2 dt
input diode (D1 or D3 ) current is only that of one series LC it is found that
circuit, thus, it is half of the output diode current. Note that 2 Gf
CZCB Gf − t
reverse recovery time of the diodes does not affect the CB’s if,ZCB (t) = VS e CZCB + 2CL . (7)
operation, thus, low-loss standard recovery diodes are suitable. CZCB + 2CL
Additionally, the forward voltage drop of a diode is generally From (7), if,ZCB (t) is a decaying exponential. Thus, it is
lower than that of an equivalently-rated thyristor. maximum for t = 0 µs. For iT1 to fall to zero, the ZCB fault
current must overcome the steady-state load current. Therefore
to trip, if,ZCB must be larger than IL . The steady-state load
C. Minimum Detectable Fault Conductance - Output current (IL ) is
The CB’s response to a fault depends on the characteristics VS
IL = . (8)
of the fault and the power system within which it is operating. RL
For the CB to operate autonomously, these characteristics must Thus, Gf,min,out is found where i1 (0) = IL and is described
be such that the current through T1 falls to zero subsequent to as follows
a fault. The requirements for autonomous operation, in the case 
2CL
 
1

where a fault with conductance Gf is applied at t = 0 µs at the Gf,min,out = 1 + · . (9)
CZCB RL
CB’s output, are investigated for the power system shown in
Fig. 3(a). Thus, the minimum fault conductance (Gf,min,out ), Gf,min,out decreases as CZCB increases relative to CL . This
which causes the CB to trip, is derived. Assuming a fault at is because a larger portion of the initial fault current flows
the CB output, the fault current can be written as through the Z-Source capacitors. Gf,min,out also decreases as
RL increases. This is due to a decrease in steady-state load
if (t) = vf (t)Gf . (1) current, which reduces the magnitude of if,ZCB required to

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commutate T1 off. When CL is zero, Gf,min,out is equal E. Response to Input Faults

to the load conductance GL . Assuming the load capacitance The proposed CB is also able to operate autonomously for
is known, which is likely for power electronic loads, and faults on its input, regardless of initial current flow direction.
taking the maximum steady-state load (worst case), (9) allows This allows rapid and autonomous isolation of faulted lines
the selection of C1 and C2 to meet a required minimum from a DC power system. If the CB is in the on-state and a
Gf,min,out . fault is applied across its input, some of the initial fault current
is supplied by the Z-Source capacitors. The response of other
D. Minimum Detectable Fault Ramp Rate - Output components is dependent on the load capacitance as described
In this section, the minimum detectable output Frr, below.
Krr,min,out , is derived. The fault conductance, Gf , is dependent 1) RC Load: In the case where a short circuit fault occurs
on time t with a linear gradient of Krr , thus, and there is a load capacitance, fault current flows as shown in
Fig. 3(b). The initial fault current is the sum of if,ZCB , if,C , and
if (t) = Gf (t)vf (t) = Krr t · vf (t). (10)
if,S . In this case, the collapsing input voltage causes D1 and D4
A linearly-increasing conductance approximates the behaviour to turn off, and D3 and D2 to turn on. The initial fault current
of an inductor as follows: supplied by the DC source (if,S ) is limited to IL by the line
1 t inductance. Similarly, the initial fault current (if,C ) supplied
Z
iL (t) = VL dt + iL (0). (11) by CL is limited to IL by the Z-Source inductors. Additionally,
L 0
the Z-Source capacitance supplies the fault current if,ZCB .
With a constant applied voltage VL and zero initial current Inspecting the cathode current of T1 , when i1 is equal to IL
iL = 0 A, the inductor characteristic is reduced to (the current through L2 ), T1 current falls to zero commutating
1 it off. When T1 turns off, two series LC resonant circuits are
∆iL (t) = VL ∆t. (12)
L formed: (1) through C2 , L2 and the fault, and (2) through
Substituting for Gf from (10) in (3) results in C1 , CL , L1 and the fault. These circuits are decoupled when
CZCB dvf dvf fault impedance is zero. The initial conditions for resonance
Krr tvf (t) = − − CL . (13) are determined by the steady-state operating point of the
2 dt dt
circuit, and the response is similar to that of described in
Solving (13) for the initial conditions defined in (4) gives
Subsection II-B for an output fault. However, in this case, the
Krr response of one LC circuit is affected by the load capacitance.
− t2
vf (t) = VS e CZCB + 2C L . (14) 2) Resistive Load: In the case where a short circuit fault
occurs and CL = 0 µF , the initial fault current is the sum of
Substituting for vf (t) from (14) in (6) results in
if,ZCB and if,S . In this case, the voltage at both the input and
Krr output collapse immediately. The initial fault current supplied
CZCB Krr − t2
if,ZCB (t) = VS te ZCB + 2CL .
C (15) by the DC source (if,S ) is limited to IL by the line inductance
CZCB + 2CL LL . This means that the Z-Source capacitance provides current
Thus, the instant at which if,ZCB (t) has its maximum is found to both the fault and load, i.e., it sees the fault in parallel with
as follows: r the load resistance. Thus, when the fault is a short circuit,
2CL + CZCB the load resistance could be neglected. The thyristor current
tmax = . (16)
2Krr is forced to zero by if,ZCB turning it off. After T1 has turned
The minimum Frr Krr,min is therefore found where off, L1 current is clamped by D5 , and a series LC resonant
if,ZCB (ti1 ,max ) is equal to the steady-state load current IL . circuit is formed through C2 , L2 , and the fault. The initial
Thus, conditions for resonance are determined by the steady-state
CZCB + 2CL operating point of the circuit, and the response is similar to that
Krr,min,out = 2e . (17)
RL 2 CZCB 2 of described in Subsection II-B for an output fault. However,
In [27], an expression for the minimum detectable Frr of a uni- in this case, there is only one LC resonant circuit.
directional series Z-Source CB feeding an RC load is derived.
This is equivalent to the expression (17) of the bi-directional F. Minimum Detectable Fault Conductance - Input
series Z-Source CB. Similarly to Gf,min,out , Krr,min,out is
dependent on RL . In both cases, the minimum value of RL In this section, the minimum detectable input fault conduc-
represents the worst case scenario where the CB is least likely tance, Gf,min,in , is derived for the cases both with and without
to trip. Additionally, nuisance tripping may be caused by high load capacitance.
slew rates of load current. Thus, a restriction of 1) RC Load: For the case where there is a load capaci-
tance, when the input fault with conductance Gf occurs, the
diload
< Vout Krr,min,out , (18) CB responds as described in Subsection II-E. The Z-Source
dt capacitors provide an initial fault voltage of VS . Therefore,
is placed on the current slew-rate of the load. This stops through analysis of the input node, the initial fault current is
unwanted tripping of the CB. Equation (18) is equivalent to found to be
stating that a change in load conductance must have a ramp
rate less than Krr,min,out . if (0) = if,ZCB (0) + if,C (0) + if,S (0). (19)

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The initial fault current is defined in terms of the fault

conductance and fault voltage as iL if iC
if (0) = VS Gf . (20) Leq,1 +
Because the initial current in inductors, L1 , L2 , and LS , is Lf,in CZ vf
equal to the steady-state load current, it is known that VS -
VS
if,C (0) = if,S (0) = IL = . (21)
RL
Thus, through substituting for if (0) from (20), and for if,S (0) Fig. 4. Circuit model used to analyze Krr,min,in .
and if,C (0) from (21) into (19), it is found that
VS
if,ZCB (0) = VS Gf − 2 . (22) of Lf lower than Lf,min,in . To find Krr,min,in , the current
RL
through thyristor T1 during the fault is analyzed. The circuit
The minimum current if,ZCB (0) that the CB requires to switch configuration used for analysis is the same as that shown in
off is equal to the steady-state load current IL . Therefore, Fig. 3(b). In this case, it is assumed that CL is large enough
3 so that the output voltage is assumed to be constant during
Gf,min,in =
. (23)
RL the turn-off period. This represents the worst scenario for
2) Resistive Load: For the case where there is no load Krr,min,in . The analysis of current through T1 can be broken
capacitance, when an input fault of conductance Gf occurs, into two time periods after the fault occurs at t = 0 µs. The
the CB responds as described in Subsection II-E. However, in first period is between t = 0 µs and t = t1 . During this period,
this case, load resistance cannot be neglected, and the load is D2 and D3 switch on, and the fault voltage is maintained at
supplied with current iL (0). The Z-Source capacitors provide VS as the source and CB current are commutated to the fault.
an initial fault voltage of VS . Therefore, through analysis of Because the fault voltage is constant, the fault current increases
the input node, according to

if (0) = if,ZCB (0) + if,S (0) − iL (0). (24) VS

if (t) = t for 0 < t < t1 . (29)
Lf,in
Because the initial voltages across capacitors C1 and C2 is
equal to their steady-state voltages, it is known that The thyristor current is maintained, thus,

vC1 (0) + vC2 (0) VS VS

iL (0) = = . (25) iT (t) = for 0 < t < t1 . (30)
RL RL RL
Thus, through substituting for if (0), if,S (0), and iL (0) from, It is assumed that the change of if,S and if,C is small over the
(20), (21) and, (25) respectively, into (24), time period 0 ≤ t ≤ t1 , thus,
VS VS if (t1 ) = 2IL . (31)
if,ZCB (0) = VS · Gf + − . (26)
RL RL
Through equating (29) and (31), and substituting for IL from
The minimum current if,ZCB (0) that the CB requires to switch (21), it is found that
off is equal to the steady-state load current IL . Therefore,
2Lf,in
1 t1 = . (32)
.
Gf,min,in = (27) RL
RL
At t = t1 , D1 and D4 are turned off. The second period is
The minimum input fault conductance required to trip the CB
defined as t1 ≤ t ≤ t2 . During this period, the circuit is
is larger for the case where there is load capacitance, when
modelled as shown in Fig. 4, where
compared with the case where there is no load capacitance.
In the case where there is no load capacitance, Gf,min,in = LZCB = L1 = L2 , (33)
Gf,min,out .  −1
1 1
CZ = + , (34)
G. Minimum Detectable Fault Ramp Rate - Input C1 C2
−1
In this section, the minimum detectable input Frr, Krr,min,in ,

1 1
is derived. In this case, the fault conductance Gf is dependent Leq,1 = + , (35)
Lf,in L1 + L 2
on time t as described in (10). To perform the numerical
−1
analysis, the fault impedance is taken to be an inductance (Lf )

1 1 1
where Leq,2 = + + . (36)
1 Lf,in 2LZCB Lf
Lf,in ≈ . (28)
Krr,in The differential equation
This approximation is described further in Subsection II-D. In d2 vf (t) 1 VS
a given system, the ZCB only trips autonomously for values 2
+ vf (t) = for t1 < t ≤ t2 (37)
dt Leq,2 CZ Leq,1 CZ

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0 350
300
-10
250
IT,min,in [A]

-20

tT,off [μs]
200
-30 150
100
-40
50
-50
0
0 1.0 2.0 3.0 4.0 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0
Lf [mH] Lf [mH]

Fig. 5. Finding Lf,max,in numerically as the inductance for which Fig. 6. Time taken for the thyristor current to fall to zero, tT,off , versus fault
IT,min,in = 0 A. inductance Lf .

TABLE I
describes the fault voltage during this period. Solving this with P EAK C URRENT AND VOLTAGE IN C OMPONENTS
initial conditions
Component Peak Current Peak Voltage Comment
dvf
vf (t1 ) = VS and (t1 ) = 0 (38) C1 & C2 ipeak VS Z-Source Capacitors
dt L1 & L 2 ipeak VS Z-Source Inductors
results in T1 IL VS Thyristor
Leq,2 + (Leq,1 − Leq,2 )cos( √ t ) D1 & D3 ipeak VS Input Diodes
Leq,2 CZ D2 & D4 2 ipeak VS Output Diodes
vf (t) = VS . (39)
Leq,1
Note to solve (37), it is assumed t1 = 0 to simplify analysis.
where,
Once vf (t) is found, the thyristor current is derived to be r
RL C
t Q= . (43)
VS p (Leq,1 − Leq,2 )cos( √Leq,2 CZ ) 2 L
iT (t) = − VS CZ p These expression are used to find the peak currents in the
RL Leq,1 Leq,2
proposed topology. Table I shows the peak currents and
(Leq,1 − Leq,2 )( CZ Leq,2 sin( √ t
p
) − t) voltages across components during a short circuit fault. This
Leq,2 CZ
− VS . (40) table assumes R1 = R2 = 0, and ideal semiconductors.
Leq,1 (L1 + L2 )
Then, tmin,in at which iT is minimum is found to be
  III. E VALUATION OF C OMPETING P ROPOSALS
p −1 Leq,2 This section provides an evaluation of existing ZCB topolo-
tmin,in = Leq,2 CZ cos . (41)
Leq,1 + (L1 + L2 ) gies and comparison with the proposed topology. In this
Through substituting for CZ , Leq,1 , Leq,2 , and tmin,in from section, three existing bi-directional ZCBs, which are shown
(34), (35), (36), and (41), respectively, in (40), iT,min,in is in Figs. 7, 8, and 9, are described.
found as a function of Lf . Fig. 5 shows iT,min,in (Lf ) for the
parameters in Table III. The value of Lf where iT,min,in = 0 A A. Bi-Directional Topologies
is Lf,max,in for which the CB turns off. This is found numer-
Several ZCBs that allow bi-directional power flow have been
ically to be Lf,max,in = 3.05 mH. Thus, taking into account
proposed [30]–[32]. However, these have some disadvantages
the initial assumption of (28), Krr,min,in = 327.87 (Ωs)−1 .
when compared with the proposed ZCB.
The time taken for the thyristor current to fall to zero, (tT,off ),
In [31], two bi-directional ZCBs are introduced. These are
is also plotted for various values of Lf in Fig. 6. For values of
shown in Figs. 7 and 8. Both of these topologies are modifi-
Lf less than Lf,max,in , the relationship between Lf and tT,off
cations of the classical ZCB [25]. As such, they do not have a
is approximately linear with a gradient of 106 µs.mH −1 .
common neutral or low-pass frequency response characteristic.
A third bi-directional ZCB is introduced in [30]. It is shown
H. Component Maximum Currents and Voltages in Fig. 9. Its design has a combination of the characteristics
The peak current and voltage stress on components occurs of the series [26], and the parallel [24] ZCB topologies.
when the circuit breaker is operating at maximum load, and a
short circuit fault occurs. The peak current and voltage stress B. Topology Comparison
are required for selection of components.
The comparison of the proposed bi-directional series ZCB
The peak inductor, diode, and capacitor currents occur during
with existing bi-directional ZCBs is given in Table II. It
the post fault resonance. The peak inductor current for the
is seen that the proposed ZCB has a low number of pas-
uni-directional series ZCB is derived in [27] as follows
p sive components compared with other bi-directional ZCBs,
ipeak = IL 1 + 4Q2 , (42) which reduces size. Additionally, it has the fewest controlled

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L1 T1 L3

D1 T2 D3

C1 C2 C3 C4
VS CL RL

T3T4T1T2VSL1L2C1C2RLCL
Fig. 8. Bi-directional ZCB topology presented in [24].
L2 L4

D2 D4

Fig. 7. Bi-directional ZCB topology presented in [24].

TABLE II
B I - DIRECTIONAL ZCB S COMPARISON

Category Fig. 7 [31] Fig. 8 [31] Fig. 9 [30] Proposed Fig. 2

1 Number of Passive Components 8 4 5 4
2 Number of Controlled Switches 2 4 2 1
3 Common Neutral No No Yes Yes
4 Suitable for Input Filtering of Power Converters No No No Yes
5 Peak Forward-Blocking Voltage of Thyristor VS > VS > VS VS
6 Input Current Spike due to Reverse Recovery of Thyristor Yes Yes Yes No
7 Limited Peak Thyristor Reverse Resonance Voltage No No Yes No
8 Magnitude of Reflected Fault Current Zero Zero High Moderate

C1 limited in the proposed circuit breaker and is approximately

C2 equal to the source voltage. However, for the topology in
T1 T2 Fig. 9, anti-parallel diodes across each thyristor limit the
L1 L2
reverse voltage of the thyristor during commutation, which
D1 D2
increases its turn-off time (tq ).
One disadvantage of the proposed topology is that it reflects a
VS CL RL portion of the fault current to the source when interrupting a
C0 fault at its output. However, in [29], it is shown the reflected
fault current can be reduced to zero by replacing the inductors
with mutually-coupled ones. Though, this in turn requires a
lower thyristor turn-off time.
Fig. 9. Bi-directional ZCB topology presented in [30].

IV. P ERFORMANCE E VALUATION

switches, reducing unit cost and complexity. The proposed This section presents simulation and experimental results
ZCB is the only bi-directional ZCB that has a low pass filter that validate the aforementioned operation of the proposed
voltage transfer function, which allows it to be used for input ZCB topology. Subsection IV-A presents detailed simulation
filtering of power converters. Furthermore, the peak forward- results and discussion of the proposed ZCB topology over a
blocking thyristor voltage is clamped in the proposed topology, range of different fault conditions. Additionally, in Subsec-
which reduces component stress and cost compared with other tion IV-B, using an experimental setup, the performance of
topologies. Also, the proposed ZCB has a common neutral, the proposed ZCB is experimentally validated.
which is required for earthed systems to limit current flowing
through alternate return paths. Other topologies, without a
common neutral, are unsuitable for earthed systems. A. Simulation Results
In ZCBs, a current spike occurs in the thyristor when it com- To evaluate the performance of the proposed CB, a test sys-
mutates off. This is due to its reverse recovery characteristic. If tem as shown in Fig. 2 is simulated in the MATLAB/Simulink
the current spike is propagated to the input of the ZCB, it may environment. The parameters of the simulated system are set
cause issues with circuit breaker co-ordination. The proposed according to Table III except where explicitly stated otherwise.
ZCB does not propagate this spike to its input, while the other The simulated system is used to evaluate the performance of
bi-directional topologies do. the proposed ZCB and to verify the expressions presented in
The reverse voltage applied to the thyristor assists causes it Section II. In all simulation tests, the CB is in steady-state
to commutate off. With low reverse voltages, the turn-off time before the fault is applied.
of the thyristor is increased [33]. The reverse voltage is not

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(a) (a)
60
iT, Gf = 1.05 (Ω) -1
i L1 & i L2 [A]

20 iT, Gf = 1.00 (Ω)-1

i T [A]
30
i L1
i L2 0
0
(b)
(b)
500 15
50
iIN, Gf = 1.05 (Ω) -1
v T [V]

i T [A]
iIN, Gf = 1.00 (Ω)-1

i IN [A]
0 0 25
vT
iT
-500 -15 0

(c) 0 100 200 300 400 500

120 time [μs]
i IN
[A]

iOUT
OUT

Fig. 11. Simulation results for output faults Gf = 1.05 (Ω)−1 and Gf =
60 1.00 (Ω)−1 , where CL = 500 µF : (a) thyristor currents and (b) input
i IN & i

currents.
0
0 100 200 300 400 500 (a)
time [μs]
iT, Gf = 0.034 (Ω) -1
20
Fig. 10. Simulation results for a bolted fault on CB output: (a) inductor iT, Gf = 0.032 (Ω)-1
i T [A]
currents, (b) thyristor voltage and current, and (c) input and output currents.

1) Infinite Fault Conductance: Firstly, a bolted fault is

applied to the CB’s output at t = 0 µs, for the case where
(b)
LL = 0 mH. This provides a base case of the CB’s operation. 50
The CB’s response to the fault is shown in Fig. 10. This re- iIN, Gf = 0.034 (Ω)-1
sponse is consistent with the description given in Section II-B. iIN, Gf = 0.032 (Ω)-1
i IN [A]

25
After the fault occurs, iT , as shown in Fig. 10(b), falls to
zero immediately due the fault current supplied by the Z-
0
Source capacitance, if,ZCB . The LC resonant response of the
inductors and capacitors occurs between 0 < t < 260 µs. At 0 100 200 300 400 500
time [μs]
t = 260 µs, the inductor currents are clamped by D5 and
D6 . Thus, the inductor currents, shown in Fig. 10(a), decay
Fig. 12. Simulation results for output faults Gf = 0.034 (Ω)−1 and Gf =
rapidly through the clamping diodes and resistors. When the 0.032 (Ω)−1 , where CL = 0 µF : (a) thyristor currents and (b) input currents.
inductors are clamped, the input and output currents, shown
in Fig. 10(c), rapidly fall to zero.
It is also observed that the peak output current is twice the a) Output: This simulation test is performed to vali-
peak input current. Thus, the peak current in D4 is twice that date the expression for minimum output fault conductance
of D1 . After the thyristor is disconnected, both LC resonant as expressed in (9). The calculated minimum fault conduc-
circuits are connected in series with the output. Thus, the tance for the component values in Table III is Gf,min,out =
output current is the summation of their individual currents. 1.043 (Ω)−1 . Therefore, simulation tests are carried out for
Conversely, only the LC circuit containing L1 and C1 is values slightly above and below the minimum fault conduc-
connected in series with the input. tance, Gf = 1.05 (Ω)−1 and Gf = 1.00 (Ω)−1 , respectively.
The reverse resonance time (trr ) is the time for which the The thyristor and input currents are shown in Fig. 11.
thyristor remains reverse-biased during turn off. In this sim- As shown in Fig. 11(a), for Gf = 1.05 (Ω)−1 , before the
ulation, it is measured as trr,out,sim = 158.9 µs. In order fault, iT is at a steady-state value of 10 A. When the fault
for the thyristor to remain off, trr must be greater than the occurs at t = 0 µs, iT is rapidly forced to zero. Thus, the CB
thyristor’s turn-off time (tq ). A line inductance LL = 1 mH switches off. As shown in Fig. 11(b), iIN is also at a steady-
is added to the model, and the simulation is repeated with state value of 10 A before the fault. When the fault occurs,
the fault induced on the CB’s input terminals. In this case, iIN begins to rise and reaches a peak value of 16.9 A. This
trr,in,sim = 159.3 µs. The two measured values are close to peak input current is lower than the case where there is no
the value calculated, trr,calc = 159.0 µs, using the expression fault impedance, due to damping of the resonant response of
derived in [27] for the series ZCB. the series LC circuits. Additional damping is created by the
series fault resistance.
2) Minimum Fault Conductance:

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For the case where Gf = 1.00 (Ω)−1 , iT is shown in (a)

Fig. 11(a). Prior to the fault, iT is at a steady-state value of iT, Gf = 0.105 (Ω)-1
10 A. When the fault occurs at t = 0 µs, the fault current 20 iT, Gf = 0.095 (Ω)-1

i T [A]
flowing through the Z-Source capacitors is not enough to
overcome the steady-state load current and to force iT to zero.
Thus, the CB does not trip, and the fault current continues to 0

increase through the thyristor. As shown in Fig. 11(b), iIN is

also at a steady-state value of 10 A before the fault. When the
fault occurs at t = 0 µs, because the CB does not turn off, (b)
25
iIN rises. This response is dominated by the characteristics of iIN, Gf = 0.105 (Ω)-1
the Z-Source inductance. iIN, Gf = 0.095 (Ω)-1

i IN [A]
The simulation test is then repeated with CL = 0 µF . The 0
minimum fault conductance calculated using (9) in this case
is Gf,min,out = 0.033 (Ω)−1 . Two simulation tests are carried
out for Gf = 0.034 (Ω)−1 and Gf = 0.032 (Ω)−1 . The -25
0 100 200 300 400 500
thyristor and input currents are shown in Fig. 12. time [μs]
For the case where Gf = 0.034 (Ω)−1 , iT is shown in
Fig. 12(a). Prior to the fault, iT is at a steady-state value of Fig. 13. Simulation results for input faults Gf = 0.105 (Ω)−1 and Gf =
10 A. When the fault occurs at t = 0 µs, iT falls rapidly 0.095 (Ω)−1 , where CL = 500 µF : (a) thyristor currents and (b) input
currents.
to zero. Thus, the CB switches off. As shown in Fig. 12(b),
iIN is also at a steady-state value of 10 A before the fault. (a)
When the fault occurs, iIN begins to fall immediately. In this
case, there is no resonant response of iIN . The reason is that i T [A] iT, Gf = 0.034 (Ω)-1
20
the large fault resistance over-damps the series LC circuits iT, Gf = 0.032 (Ω)-1
created when the CB opens.
For the case where for Gf = 0.032 (Ω)−1 , iT is shown in 0

Fig. 12(a). Prior to the fault, iT is at a steady-state value of

10 A. The fault occurs at t = 0 µs, however, current flowing
(b)
through the Z-Source capacitors is not enough to overcome
the steady-state load current. Thus, the CB does not trip. As iIN, Gf = 0.034 (Ω) -1
20
shown in Fig. 12(b), iIN is also at a steady-state value of iIN, Gf = 0.032 (Ω)-1
i IN [A]

10 A before the fault. When the fault occurs at t = 0 µs,

because the CB does not turn off, iIN rises. This response is 0
dominated by the characteristics of the Z-Source inductance.
0 100 200 300 400 500
The case where there is no load capacitance defines a time [μs]
fundamental limit on minimum output fault conductance,
which is equal to the load conductance. The CB cannot be Fig. 14. Simulation results for input faults Gf = 0.034 (Ω)−1 and Gf =
designed to trip autonomously for fault conductance less than 0.032 (Ω)−1 , where CL = 0 µF : (a) thyristor currents and (b) input currents.
the load conductance.

b) Input: A simulation test is carried out for faults while a fault conductance of Gf = 0.032 (Ω)−1 does not.
on the CB’s input. The minimum fault conductances
for cases both with and without a load capacitance are 3) Minimum Fault Ramp Rate:
calculated according to (23) and (27). With a load capacitance a) Output: The minimum output Frr, which causes the
CL = 500 µF , Gf,min,in = 0.1 (Ω)−1 , and with a load CB to switch off, is also investigated through simulation. To
capacitance CL = 0 µF , Gf,min,in = 0.033 (Ω)−1 . The do this, an inductance Lf is placed in series with the fault.
simulation tests are carried out for both Gf = 0.105 (Ω)−1 This approximates the characteristics of a conductance with
and Gf = 0.095 (Ω)−1 with CL = 500 µF . The results are ramp Krr , as described in Subsection II-D. The minimum Frr
shown in Fig. 13. It is noted that when Gf = 0.105 (Ωs)−1 , that trips the CB is calculated using (17) to be Krr,min,in =
the thyristor switches off. However, the input current 5730 (Ωs)−1 . In Fig. 15, the simulated thyristor current is
continues to rise. Although this is true for the time period shown for the cases where faults with inductances of Lf =
shown, the current decays after t = 500 µs. For the case 167.8 µH and Lf = 181.8 µH are applied to the CB’s output.
where Gf = 0.095 (Ω)−1 , the thyristor current does not drop These values correspond to fault conductance ramp rates of
below zero, thus, the circuit breaker does not trip. Krr = 5500 (Ωs)−1 and Krr = 5960 (Ωs)−1 , respectively.
Additionally, simulation tests are carried out for For the case where Lf = 167.8 µH, iT falls gradually to
Gf = 0.032 (Ω)−1 and Gf = 0.034 (Ω)−1 , with CL = 0 µF . zero, and the thyristor switches off. However, for the case
The results are shown in Fig. 14. As expected, a fault where Lf = 181.8 µH, the thyristor current does not fall to
conductance of Gf = 0.034 (Ω)−1 switches the thyristor off, zero, thus, the thyristor remains in the conducting state, and

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15 TABLE III
E XPERIMENTAL S ETUP C OMPONENT VALUES
10
Parameter Value Comment
5
iT [A]

C1 = C2 = C 33 µF Z-Source Capacitors
0 iT, Lf= 167.8 μH L1 = L 2 = L 1 mH Z-Source Inductors
iT, Lf= 181.8 μH RL 30 Ω Load Resistance
-5
0 100 200 300 400 500 VS 300 V Source Voltage
time [μs] RC 1Ω Clamping Resistor
LL 5 mH Line Inductance
Fig. 15. Simulation of thyristor current during output faults with inductances
CL 480 uF Load Capacitance
Lf = 167.8 µH and Lf = 181.8 µH, where CL = 500 µF .

The Experimental Prototype

(a)
15
10
iT [A]

5 iT,Simulated, Lf= 3.0 mH

0 iT,Analytical, Lf= 3.0 mH
-5
External
(b)
Thyristor
15
to Induce Fault
10
iT [A]

5 iT,Simulated, Lf= 3.2 mH

0 iT,Analytical, Lf= 3.2 mH
-5 MCB for Input Fault Protection Manual Thyristor Control
0 100 200 300 400 500
time [μs]
Fig. 17. The experimental prototype.
Fig. 16. Simulation results for input fault, Lf = 3 mH and Lf = 3.2 mH,
where CL = 500 µF , compared with analytically modelled equations (40)- (a)
(41). 60
iL1 & iL2 [A]

30
iL1
the circuit breaker does not trip. iL2
0
b) Input: A simulation is used to to evaluate the ana-
lytical modelling in Subsection II-G. In Subsection II-G, a (b)
500 80
method is presented for finding Lf,max,in . For the component
values in Table III, Lf,max,in = 3.05 mH. Therefore, the
vT [V]

iT [A]
0 0
circuit breaker system is simulated to find the thyristor current vT
(iT,Simulated ) with input faults of inductances Lf = 3 mH iT
and Lf = 3.2 mH. These correspond to inductances below -500 -80
and above the maximum input fault inductance. The analytical (c)
120
thyristor current (iT,Analytical ) is also found using (40) for iIN
iIN & iOUT [A]

the two inductance values. This allows a comparison of the iOUT

iT,Analytical with iT,Simulated to be made in Fig. 16. In 60

Fig. 16(a) iT,Simulated and iT,Analytical are shown for the case
where Lf = 3 mH. It is seen that the simulated and analytical 0
results match closely. Fig. 16(a) also shows that the circuit 0 100 200 300 400 500
time [μs]
breaker trips (i.e., iT,Simulated and iT,Analytical fall to/below
0 A), which is expected for the fault inductance below Fig. 18. Experimental results for a direct fault on the output with the ZCB in
Lf,max,in . It is noted that iT,Analytical rises again after falling to the forward direction: (a) inductor currents, (b) thyristor voltage and current,
zero.This is because the non-linear switching of the thyristor is and (c) input and output current.
not part of the analytical model. In Fig. 16(b) iT,Simulated and
iT,Analytical are shown for the case where Lf = 3.2 mH, it
is seen that the simulated and analytical results match closely. B. Experimental Results
Fig. 16(b) also shows that the circuit breaker does not trip To experimentally validate the findings, an experimental
(i.e. iT,Simulated and iT,Analytical do not fall to/below 0 A), prototype is implemented with the selected component values
which is expected for the fault inductance above Lf,max,in . shown in Table III. A photo of the implemented ZCB is
These results confirm the analytical model and the method for shown in Fig. 17.
finding Lf,max,in presented in Subsection II-G.

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1) Output Fault: To demonstrate the prototype’s bi- (a)

60
directional capability, it is tested in both the forward and

iL1 & iL2 [A]

reverse directions. Initially, one pair of input terminals is
connected to a DC voltage source, and the other is connected 30
iL1
to a resistive load. In the first test, the initial steady-state iL2
operating current is 10 A. At t = 50 µs, a fault is applied 0
across the load. The inductor currents, thyristor voltage, (b)
thyristor current, input current, and output current are shown 500 80
in Fig. 18. In Fig. 18(a) it is seen that both inductor currents

vT [V]

iT [A]
increase gradually when the fault occurs, then begin to decay 0 0
vT
as they are clamped by their reverse-biased clamping diodes.
iT
The thyristor current and voltage in Fig. 18(b) show that -500 -80
immediately after the fault, the thyristor switches off and
(c)
remains reverse biased for trr . However, a negative voltage 120
spike is observed in the thyristor current that is not observed iIN

iIN & iOUT [A]

in simulation. This is due to the thyristor reverse recovery iOUT
60
characteristic. The peak of this spike is dependent on the
reverse recovery charge of the thyristor and rate of current 0
fall [33]. Although this spike is propagated through the 0 100 200 300 400 500
CB capacitors, the thyristor, and the output diode, it is not time [μs]
experienced on the input. Thus, the reverse recovery current
spike of the main thyristor switch does not have any impact Fig. 19. Experimental results for a direct fault on the output with the ZCB in
the reverse direction: (a) inductor currents, (b) thyristor voltage and current,
on co-ordination with upstream CBs. In Fig. 18(c), the circuit and (c) input and output current.
breaker input and output currents are shown. It is seen that
the reverse recovery current spike is propagated to the circuit (a)
breakers output, though it is lower in magnitude than the 300 50
maximum output current.
[V]

iT [A]
The experiment described above is then repeated after 0 0
T

vT
v

switching the source and load terminals of the CB. The

iT
inductor currents are shown in Fig.19(a), thyristor voltage and -300 -50
thyristor current are shown in Fig.19(b), and input current (b)
and output current are shown in Fig.19(c). It is observed that 300 50
these results closely match those with the circuit breaker the
v T [V]

iT [A]
forward direction, confirming that the CB’s response is not 0 0
dependent on its orientation. vT
iT
The reverse resonance time trr for forward and reverse- -300 -50
oriented cases described above is measured to be 132.6 µs 0 100 200 300 400 500 600
time [μs]
and 132.0 µs, respectively, which is lower than the time
expected from simulation. This can be explained by the Fig. 20. Experimental results for a resistive fault on the output of the ZCB:
de-rating of inductors L1 and L2 due to the large DC bias (a) thyristor voltage and current, where Gf,out = 1.136 (Ω)−1 , and (b)
current. Therefore, the inductance values are de-rated by thyristor voltage and current, where Gf,out = 0.833 (Ω)−1 .
30%. The reverse resonance time with this lower inductance
is calculated to be 137.0 µs using the expression derived in
[27], which is in agreement with the experimental results. Gf > Gf,min,out , the thyristor current falls to zero, and its
This effect is observed due to core non-linearity, which causes forward voltage increases (forward blocking). Thus, the circuit
inductance to decrease at high DC bias currents. A DC bias breaker is tripped. While, for Gf < Gf,min,out , the thyristor
de-rating is also observed in an experimental prototype of the current continues to rise, and its forward voltage stays low
uni-directional series ZCB in [27]. (forward conducting). Thus, the circuit breaker is not tripped.
One discrepancy between the experimental results in Fig. 20
2) Resistive Output Fault: To verify Equation (9), a 480 µF and simulation results shown in Fig. 11 is noted. For the case
capacitance is added in parallel with the resistive load. Thus, where Gf < Gf,min,out , the thyristor current did fall briefly to
according to (9), Gf,min,out = 1.003 (Ω)−1 . Therefore, faults zero. Additionally, there is significant ringing in the thyristor
with conductances of 1.136 (Ω)−1 and 0.833 (Ω)−1 , respec- current. This occurs due to parasitic inductance between the
tively, are applied to the circuit breakers output. Initially, the circuit breaker and load capacitor. As the parasitic inductance
steady-state operating current is 10 A. At t = 50 µs, the fault decreases the minimum fault conductance, Equation (9) is con-
is applied across the load. The thyristor current and voltage servative when the parasitic inductance is taken into account.
during these tests are shown in Fig. 20. 3) Input Fault: For this test, the system is re-configured
These results verify the expression (9). It is seen that for through adding an additional 5 mH inductance between the

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(a) flow capability and ability to break fault currents for faults on
80
iL1 either the load or source side.
iL1 & iL2 [A]

iL2
40
ACKNOWLEDGEMENT
0 The authors thank the Defence Science and Technology
(b) Group (DST-Group), Australia, for supporting this work.
500 80
vT [V]

iT [A]
0 0 R EFERENCES
vT
iT [1] B. Zahedi and L. E. Norum, “Modeling and simulation of all-electric
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2764903, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 13

[18] H. Polman, J. A. Ferreira, M. Kaanders, B. H. Evenblij, and P. V. Gelder, Daniel Ryan Daniel Ryan received a BE (hons.)
“Design of a bi-directional 600 v/6 ka zvs hybrid dc switch using in Electrical and Computer Systems engineering in
igbts,” in Conference Record of the 2001 IEEE Industry Applications 2015, from Monash University, Melbourne, Aus-
Conference. 36th IAS Annual Meeting (Cat. No.01CH37248), vol. 2, tralia. Currently, he is pursuing a Ph.D. at Monash
Conference Proceedings, pp. 1052–1059 vol.2. University. His research interests include protection
[19] J. M. Meyer and A. Rufer, “A dc hybrid circuit breaker with ultra-fast of DC power systems, grid integration of energy
contact opening and integrated gate-commutated thyristors (igcts),” IEEE storage, and power system dynamics and control.
Transactions on Power Delivery, vol. 21, no. 2, pp. 646–651, 2006.
[20] A. Hassanpoor, J. Hfner, and B. Jacobson, “Technical assessment of
load commutation switch in hybrid hvdc breaker,” IEEE Transactions
on Power Electronics, vol. 30, no. 10, pp. 5393–5400, 2015.
[21] X. Song, C. Peng, and A. Huang, “A medium voltage hybrid dc circuit
breaker; part i: Solid state main breaker based on 15 kv sic emitter turn-
off (eto) thyristor,” IEEE Journal of Emerging and Selected Topics in
Power Electronics, vol. PP, no. 99, pp. 1–1, 2016. Hugh Torresan Hugh Torresan received a BE
[22] D. Dring, D. Ergin, K. Wrflinger, J. Dorn, F. Schettler, and E. Spahic, (hons.) in Electrical and Computer Systems engi-
“System integration aspects of dc circuit breakers,” IET Power Electron- neering in 2002, and Masters of Engineering Science
ics, vol. 9, no. 2, pp. 219–227, 2016. (research) in 2005, from Monash University, Mel-
[23] D. Bsche, E. D. Wilkening, H. Kpf, and M. Kurrat, “Hybrid dc circuit bourne, Australia. In 2008 he completed the Sub-
breaker feasibility study,” IEEE Transactions on Components, Packaging marine Design and Procurement course at University
and Manufacturing Technology, vol. 7, no. 3, pp. 354–362, 2017. College London, and qualified for chartered engineer
[24] K. A. Corzine and R. W. Ashton, “A new z-source dc circuit breaker,” status with the Royal Institution of Naval Archi-
IEEE Transactions on Power Electronics, vol. 27, no. 6, pp. 2796–2804, tect (RINA) and the British Engineering Council in
2012. 2011.
[25] ——, “A new z-source dc circuit breaker,” in 2010 IEEE International He led DST-Group’s contribution to The Technical
Symposium on Industrial Electronics, 2010, Conference Proceedings, pp. Co-operation Program (TCCP) on Power and Energy Materials and Systems
585–590. from 2006 to 2015, culminating in 5 years as panel chair. Currently, he is
[26] A. H. Chang, A. T. Avestruz, S. B. Leeb, and J. L. Kirtley, “Design of dc a Senior Electrical Research Engineer with the Maritime Division of DST-
system protection,” in 2013 IEEE Electric Ship Technologies Symposium Group, and chair of the Victorian Section of RINA.
(ESTS), 2013, Conference Proceedings, pp. 500–508. Hugh leads DST-Group’s science program on maritime batteries, and
[27] A. H. Chang, B. R. Sennett, A. T. Avestruz, S. B. Leeb, and J. L. provides research support to both the Royal Australian Navy’s in-service fleet,
Kirtley, “Analysis and design of dc system protection using z-source as well as new-build projects. His research interests include deep-learning
circuit breaker,” IEEE Transactions on Power Electronics, vol. 31, no. 2, for battery performance prediction, statistical models of large-format battery
pp. 1036–1049, 2016. installations and novel application of imbricated cell inverters.
[28] A. Maqsood, A. Overstreet, and K. Corzine, “Modified z-source dc
circuit breaker topologies,” IEEE Transactions on Power Electronics,
vol. PP, no. 99, pp. 1–1, 2015.
[29] A. Maqsood and K. Corzine, “Z-source dc circuit breakers with coupled
inductors,” in Energy Conversion Congress and Exposition (ECCE), Behrooz Bahrani Behrooz Bahrani received the
2015 IEEE, 2015, Conference Proceedings, pp. 1905–1909. B.Sc. degree from Sharif University of Technology,
[30] D. Keshavarzi, T. Ghanbari, and E. Farjah, “A z-source based bidirec- Tehran, Iran, the M.Sc. degree from the University of
tional dc circuit breaker with fault current limitation and interruption Toronto, Toronto, ON, Canada, and the Ph.D. degree
capabilities,” IEEE Transactions on Power Electronics, vol. PP, no. 99, from the Ecole Polytechnique Fédérale de Lausanne
pp. 1–1, 2016. (EPFL), Lausanne, Switzerland, all in electrical en-
[31] A. Maqsood and K. Corzine, “The z-source breaker for fault protection gineering, in 2006, 2008, and 2012, respectively.
in ship power systems,” in Power Electronics, Electrical Drives, Au- From September 2012 to September 2015, he was a
tomation and Motion (SPEEDAM), 2014 International Symposium on, Postdoctoral Fellow at several institutions including
2014, Conference Proceedings, pp. 307–312. EPFL, Purdue University, West Lafayette, IN, USA,
[32] A. Maqsood, L. Lu, and K. A. Corzine, “Low-voltage dc testbed design Georgia Institute of Technology, Atlanta, GA, USA,
for a z-source breaker based protection scheme,” in 2016 Clemson and Technical University of Munich, Munich, Germany. Currently, he is a
University Power Systems Conference (PSC), 2016, Conference Proceed- lecturer at Monash University, Melbourne, Australia. His research interests
ings, pp. 1–6. include control of power electronic systems, applications of power electronics
[33] A. Wintrich, U. Nicolai, W. Tursky, and T. Reimann, Application Manual in power and traction systems, and grid integration of renewable energy
Power Semiconductors, 2nd ed., Semikron International, Sigmundstrasse resources.
200, 90431 Nuremberg, Germany, 2015.

0885-8993 (c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.