Mackey 2017
Mackey 2017
Mackey 2017
3765
as L0 which has a value L. The source inductor is smaller in
magnitude compared to the impedance network inductors L1
and L2 . When the fault initiates, current through the Z-source
inductors cannot change instantly. However, low inductance
of L0 allows transient current to go through it towards the
capacitive path via the two capacitors C1 and C2 in the
impedance network. The breaker observes a negative current
generating the forced zero current crossings.
Fig. 6: Mechanically Switched Z-source Circuit Breaker To model the current supplied from the source during this
Schematic without Source Inductor first two zero crossings in the DCCB current, it is assumed
that current through the Z-source inductors does not change
within this time. The analysis assumes zero pre-fault current.
An approximate equivalent circuit for this period is shown
in Fig. 9. The line parameters are ignored for this analysis
since the line lengths in the distribution system are assumed
to be short. Even if the lines introduce a small resistance to
the system, they can be lumped with the load and thus will
not affect the transient behavior significantly. The model is
comprised of the series connection of LEQ and CEQ . Here,
LEQ depicts the source inductor and CEQ depicts the series
connection of impedance network capacitors C1 and C2 as
seen by the transient current during bolted fault. Therefore,
LEQ has value L and if we assume both C1 and C2 has value
Fig. 7: Switch Current without Source Inductor C, then CEQ = C2 . The fault is initiated at t = 0.
The current from the source, IL (t) and the voltage
across the equivalent capacitor, VC (t) is related to each
between time available before zero-current crossing during a other by the following equation IL (t) = C2 dVdt C (t)
. source
bolted fault is determined. This analytical approach gives the Voltage is VS therefore applying Kirchhoffs voltage law,
relationship between the available time window and the values L (t)
L dIdt + VC (t) = VS . Replacing IL (t) and simplifying it is
for the passive components. This helps the design of circuit 2
parameters for a given system and also the development of reduced to d VdtC2(t) + LC
2 2
VC (t) = LC VS . Analysis is for zero
control and protection algorithm for isolating the source from pre-fault current therefore applying initial condition VC (t) = 0
C (t)
the fault in fastest possible time with minimum stress on the and dVdt = 0 for t = 0. The final results for capacitor
mechanical switch. voltage (Eq. 1) and inductor current (Eq. 2) can be derived
based on these assumptions and the source current derivative
A. System Dynamics during Fault is given by Eq. 3.
System dynamics during the fault have been derived and
an approximate analytical formulation is presented here. The 2
VC (t) = −VS ∗ cos ∗t + VS (1)
timing of the inductive transient must be coordinated to LC
facilitate the UFMS opening corresponding to a zero-crossing
√
time [18–20] The source inductor shown in Fig. 3 is depicted VS C 2
IL (t) = √ ∗ sin ∗t (2)
2L LC
3766
load changes from Ri to Rf where Rf = Rni . During the
VS 2 transient period, the current will flow through the source
IL (t) = ∗ cos ∗t (3)
L LC inductor and the impedance network capacitors as the large
impedance network inductors do not allow sudden change in
This solution is only applicable to time period for the current through them. The capacitors can be assumed to act
first two zero current crossings as shown in Fig. 8 because like a short circuit to this transient current. It can be shown
the assumption that current through the Z-source inductors that the source current during this step change is given by
remain constant is not strictly valid after that. However, this Eq. 4 and the derivative of current is given by Eq. 5.
is the most significant time window and of interest because
to utilize the ultra-fast opening of the mechanical switch, the VS VS VS −Rf t
IL (t) = − − ∗ exp (4)
optimum signal initiating time is shortly before the second zero Rf Rf Ri L
crossing. This ensures that the mechanical switch interrupts
very low current as well as it will be subject to a zero- Rf VS VS −Rf t
IL (t) = − ∗ exp (5)
crossing immediately which minimizes the arcing followed L Rf Ri L
by the breaking operation. If this is not done accordingly, Evaluating this at t = 0, it can be shown that the peak value
the source current keeps on increasing in a rising√ sinusoidal of the derivative is VLS ∗ (1 − n1 ). For a bolted fault, n = ∞.
manner. The peak of the current is given by V√ S C
2L
for a zero- In that case, the peak value of derivative will be VLS which
pre-fault current for this time window. If the pre-fault current matches with Eq. 3. This relationship is later used to develop
is I0 , the
√ peak current for this period can be expressed as by a control scheme that can differentiate between the transients
I0 + 2L . The peak current value as well as the width of
V√S C
created due to step change in load and the transients due to
this time window is directly related to the passive component fault thereby preventing false operation of the breaker. Also,
values. it helps set the tolerable threshold for the rate of change in
Fig. 10 shows the PSCAD simulation results when the current with a particular pre-fault current as this threshold will
pre-fault current is 0 A and 20 A respectively for a system vary with the pre-fault current. Based on that, a tripping signal
with the parameters shown in Table 1. For a 0 A pre-fault is sent to the breaker to isolate the source from the fault.
current, the model gives a value of 110.27 A for source
current peak whereas the simulation gives 111.3 A. For a 20 C. Zero-Crossing Time Calculation
A pre-fault current, the model gives a peak of 130.27 A in
If there is a bolted fault, the current through the mechanical
this case whereas the simulation gives 131.3 A. Therefore,
breaker experiences zero-crossing as shown in Fig. 8. Evalu-
the simulations shows that the approximated model gives
ating those zero-crossing time is essential to determine when
fairly accurate results as simulation for this time window
to turn off the breaker. It ensures that the breaker sees a zero-
of concern thereby validating the analytical approach. This
crossing during resulting in safe interruption of current. If the
simple analytical model provides a way to choose the passive
pre-fault current is given by Ipre , then we define parameter r
components for a given system and develop the optimum I
as r = Ipre Here, Ip is given by Eq. 6.
control system. p
√
VS C
Ip = √ (6)
2L
Equating (2) with Ipre we get two solutions for zero-
crossings which are denoted as t1 in Eq. 7 and t2 in Eq. 8
respectively.
−1 LC
t1 = sin (r) ∗ (7)
2
−1
LC
t2 = π − sin (r) ∗ (8)
2
Fig. 10: Source Current during Bolted Fault Here, t2 denotes the second zero-crossing. The goal is to
open the switch before this time. However, these solutions are
derived assuming that current through the impedance network
B. Step Change in Load does not change during the fault. However, there will be
If there is a step change in load for a system with this some deviation from this assumption because by the time the
breaker arrangement, the derivative of the current is dictated breaker current reaches second zero-crossing, there will be
by the supply voltage and source inductance. Let us assume, some change in the current through the impedance network
the initial current is Ii and the final current is If and they inductors. So, a correction factor is applied to t2 . The modified
are related as If = n ∗ Ii . It happens when the resistive equation for second zero-crossing is given as Eq. 9.
3767
Vs Ip Ipre t2 (ms) t2 (ms) t2s (ms)
L 200 87.178 40 1.16 1.04 1.01
t2 = t2 ∗ 1 − (9)
L 1 + L2 300 130.767 50 1.2 1.08 1.05
The analytical results show that the impedance network 400 174.356 40 1.26 1.13 1.11
parameters and source inductance contribute significantly to It can be seen that with the correction applied, the zero-
the negative current peak and zero-crossing time. Depending crossing time can be calculated quite accurately using the
on the range of voltage and current of a system, it is possible analytical model. It ensures that the breaker can be opened in
to optimize the inductors and capacitors accordingly. Fig. 11 the vicinity of zero-crossing to minimize arcing if the tripping
shows the second zero-crossing time variation with the ratio of signal is sent utilizing this timing information.
source inductance to impedance network capacitor values. The
curves illustrated in Fig. 11 allow a system designer to select E. Test Prototype Validation
the ideal inductor and capacitor values to coordinate the se- In addition to simulation validation of the analytical method,
lected UFMS control for the voltage and current specifications a mechanical Z-source DCCB test prototype has been con-
of the system. structed and tested under load as shown in Fig. 12. The
experimental results validating the theory and simulation
analysis are given in Fig. 13. The experimental data with
the test prototype reconciles with the analytical model and
simulation through validation of timing, zero crossing and
system dynamics during transient. It shows that the zero-
crossing time is dictated by the passive components and the
current derivative changes as a function of supply voltage and
source inductance.
D. Simulation Validation
Analytical results for zero-crossing are validated with simu-
lation for the two different set of inductor and capacitor values Fig. 12: Z-source Circuit Breaker Test Prototype
which are given in Table. 2 and Table. 3. Here, t2s denotes
the zero-crossing time as obtained from simulation.
Fig. 12 shows the preliminary test prototype rated for 400
V and 20 A. The test load applied was a combination of pure
resistive loading in the form of wire wound, ceramic core re-
sistors and a 5.2 kW programmable load operating in constant
current mode to allow for a precise load current control. A
metal-oxide varistor is used to protect the mechanical switch
from over voltage during interruption. The parameter values
of the test prototype were given earlier in Table 1.
TABLE III: Simulation Results for Fig. 13: Z-source Circuit Breaker Test Prototype Waveform
L = 1 mH, L1 = L2 = 5 mH and C = 380 μF
3768
III. C ONTROL AND P ROTECTION L OGIC
The control logic is implemented via the flow chart shown in
Fig. 14. A delay is provided during the start to avoid tripping
due to inrush current. IT hreshold and IT hreshold depict the
threshold value for the current and rate of current change
respectively. The IT hreshold is set dynamically based on the
steady state current of the system. The status of the transient is
determined from the current derivative calculated in the digital
signal processor based on the feedback from the from the
current and voltage sensors. The controller logic differentiates
between a fault current and normal operation load change
using the current derivative information. This allows for a Fig. 15: Comparison of Various Direct Current Circuit Break-
highly customizable circuit breaker control to provide optimal ers
protection with minimal spurious trips.
3769
Fig. 16: Bi-directional, Ultra-Fast Mechanically Switched, Z-source Circuit Breaker Schematic
3770