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Lock-Up Latch

Lock-up latches are inserted between flip-flops in scan chains to address timing issues caused by clock delays or mismatches. They hold data temporarily to ensure it is captured, allowing scan chains to function properly during testing. While lock-up latches fix timing problems, they also segment scan chains and limit optimization of chain length.

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0% found this document useful (0 votes)
260 views15 pages

Lock-Up Latch

Lock-up latches are inserted between flip-flops in scan chains to address timing issues caused by clock delays or mismatches. They hold data temporarily to ensure it is captured, allowing scan chains to function properly during testing. While lock-up latches fix timing problems, they also segment scan chains and limit optimization of chain length.

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LOCK UP

LATCH
What are Lock-up Latches​

Lock-up latches are basic transparent latches (like D latches) used in scan chains. They're
inserted between regular flip-flops that have a high chance of failing to hold data due to long
clock delays (skew) or mismatched clock domains.​

These latches essentially act as temporary storage points. They hold the data for a short period,
ensuring it's captured by the next flip-flop even with significant clock skew. This allows scan chains
to function properly during testing, regardless of clock domain differences, by improving hold time
margins.

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DFT tool should have control over the enable pin of the latch from a clock or from PI.​

If above condition met, then tool will consider latches as Transparent Latch else it will be Non-
Transparent Latch​

Latches placed by the designer during the design phase typically aren't included in the scan chain
used for testing. ​

In contrast, lock-up latches inserted by the Design for Testability (DFT) engineer specifically to
address challenges with mixing clock edges (positive and negative) or clock domains become
part of the scan chain.​

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Lock up Latch uses​
EDGE MIXING​
KEEPING BOTH POSITIVE EDGE AND NEGATIVE EDGE TRIGGERED FLOPS IN SAME SCAN CHAIN.​

1. Positive Positive​

2. Negative Negative​

3. Negative Positive​

4. Positive Negative This will create a Problem​​

DOMAIN MIXING​
KEEPING FLOPS WITH DIFFERENT SCAN CLOCKS IN SAME SCAN CHAIN​​.

1. CLK A & CLK B arrive at same time​

2. CLK B arrive early​

3. CLK A arrive early This will create a Problem​


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Case 1 : Pos - Pos​

Q1 changes to high at the 1st active edge of its clock.​


Q2 changes to high at 2nd active edge of its clock​

Normal Operation​

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Case 2 : Neg - Neg​

Q1 changes to high at the 1st active edge of its clock.​


Q2 changes to high at 2nd active edge of its clock​

Normal Operation​

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Case 3 : Neg - Pos

Q1 changes to high at the 1st active edge of its clock.​


Q2 changes to high at 2nd active edge of its clock​

Normal Operation​

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Case 4 : Pos - Neg

Q1 is becoming high at the 1st active edge of its clock​


Q2 is also becoming high at 1st active edge of its clock​


Problem – 2 shifts in the same clock pulse​

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Case 4 : Pos - Neg ( Resolved )

Q1 changes to high at the 1st active edge of its clock.​


Q2 changes to high at the 2nd active edge of its clock​


PROBLEM RESOLVED​

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Why Positive Negative will create problem ?​
Mixing positive and negative flip-flops can be tricky. ​

Imagine a bucket brigade where you want to grab water (capture data) and then pass it on (shift data).
You can't do both at once!​

But if your design needs a positive flop followed by a negative one, use a special "lock-up latch" to make it
work even with a slightly wonky clock.​

Scan Chain Order and Clock Type:​

The order of flops also depends on your clock signal:​

Return-to-Zero (RTZ) Clock : Put negative flops first, then positive ones (negedge posedge)​

Non-RTZ Clock : Reverse the order (posedge negedge).​

This stops data from accidentally jumping between flops in the same clock cycle.​

Following these tips keeps your scan chain working smoothly, even with mixed flops!​

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Case 1 – CLK A & CLK B arrives at same time​

Q1 changes to high at the 1st active edge of


its clock.​

Q2 changes to high at 2nd active edge of its


clock​


Normal Operation​

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Case 2 – CLK B arrives early​

Q1 changes to high at the 1st active edge of


its clock.​


Q2 changes to high at 2nd active edge of its
clock​

Normal Operation​

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Case 3 – CLK A arrives at early​

Q1 changes to high at the 1st active edge of its


clock.​


Q2 also changes to high at 1st active edge of its
clock​


PROBLEM​

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Case 3 – CLK A arrives at early ( Resolved )​

Q1 changes to high at the 1st active edge of its


clock.​

Q2 changes to high at 2nd active edge of its


clock​

PROBLEM RESOLVED​

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Issues of Lock-up Latches

Lock-up latches are a double-edged sword in scan chains.​

The good: They fix timing issues by ensuring data is captured correctly despite clock delays.​

The bad: They act like roadblocks that prevent efficient chain optimization.​

Imagine a long scan chain like a data highway. Lock-up latches are like tollbooths. They make
sure data arrives on time, but they also break the highway into smaller sections. This limits how
much engineers can rearrange the chain for optimal length.​

The consequence: Longer scan chains mean more wires and potentially higher power
consumption.​

In short: Lock-up latches are helpful but can make scan chains less efficient.​


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