High-Efficiency Class-F-1 Power Amplifier Design with

Input Harmonic Manipulation

Lei Dong, Songbai He, Fei You, and Qi Lei

Department of circuit and system, University of Electronic Science and Tech. of China,
Chengdu, 611731, China

Abstract — This paper presents the design and realization the realization of output harmonic manipu lation while
of a high-efficiency Class-F-1 power amplifier, in which the neglecting the significance of input harmonic control .
input second harmonic effect is emphasized for the efficiency This paper highlights the further improvement of Class -
enhancement. Through the numerical analysis and device -
model-based simulation, the optimum manipulation of input F-1 PAs efficiency by properly setting input harmonic
and output harmonic terminations are carried out. Following impedance. To provide a better guidance to design in
this knowledge, a 3.5-GHz Class-F-1 power amplifier with an physical world, all of analysis and simulat ion is perfo rmed
accurate input harmonic control was fabricated using a based on a practical device, the Cree ’s CGH40010. The
commercial high power GaN HEMT. The experimental full design method is detailed in Section II, involving best
results show that a maximum power-added-efficiency (PAE)
of 76.7% with 39.9dBm output power (Pout) and 12.9dB gain schemes in terms of input harmonic man ipulation as well
is achieved. as output matching network, Section III presents the
Index Terms — Class-F-1 power amplifier, High Efficiency, experimental validation. With a sight tuning employed,
GaN, Input Harmonic Manipulation. the manufactured Class-F-1 amplifier exh ibits over 70%
PAE and around 10W Pout under drive of a continuous
wave signal. Finally, in Section IV, so me conclusions are
I. INT RODUCTION
drawn.
The enhancement of power-added-efficiency (PA E) is
one key target for base-station power amplifiers (PAs)
II. CLASS-F-1 DESI GN M ET HODOLOGY
design. A good PAE performance allows for less pressure
on the thermal management and power supply. Vgg Vdd
Various strategies to obtain very high-efficiency PAs I ds  g mVgs
have been proposed and experimentally validated [1]-[4]; IMN
 OMN

among which, the wavefo rm engineering approach [5] is

widely seen as the most promising candidates. As a classic 50ohm Vgs 50ohm
example of waveform shaping, the Class -F-1 amplifier Cgs  Cds
operation requires the output termination having zero
impedance at odd harmonics and infinite impedance at
even harmonics, thus generating a square output voltage
waveform and a half-sinusoid output current waveform. In
Fig.1. Simplified circuit model of FET amplifier
this scenario, null power is dissipated on the transistor
since no overlap between voltage and current waveform,
The cru x of Class-F-1 amp lifier design lies in
hence 100% efficiency is theoretically achieved.
engineering output current and voltage to exhibit the
In previous, the limitation on breakdown voltage of
correct waveforms. Since the FET output can be treated as
transistors was a bottleneck for the Class-F-1 amplifier
a voltage-controlled current source, specifically controlled
development, due to its essential large drain voltage swing.
by gate-source voltage as shown in Fig.1, the exact
With the emergency of wide band gap semiconductors,
behavior of gate-source voltage inherently determines
especially GaN, Class-F-1 PAs operating at high efficiency
output current waveform. Many factors have an effect on
become available. In addition, some papers [6] [7] have
gate-source voltage, such as incident signal, gate bias,
reported that in practical design, Class -F-1 amplifiers even
input fundamental and harmonic terminations. Given that,
have better efficiency than its inverse mode, Class-F
all these parameters should be carefully devised for Class -
amp lifiers. Therefo re, the Class -F-1 gains much popularity
F-1 operation. On the other side, the output voltage is
fro m the industry. Up to now, Nu merous successful cases
generated from the output current. Thus, in order to obtain
[4, 8, 9] have been published for Class -F-1 amplifiers with
ideal output voltage waveform, one needs to adjust load
high efficiency. But most of these cases merely emphasize
impedance on the basis of output current. Obviously,

978-1-4577-1121-3/12/$26.00 © Institute
Authorized licensed use limited to: Indian 2012 IEEEof Space Science And Technology.1Downloaded on May 15,2024 at 19:07:03 UTC from IEEE Xplore. PAWRapply.
Restrictions 2012
 current waveform control has the equal importance as the output current. For simplicity, input voltage is
voltage waveform control. supposed to contain only fundamental and second
harmonic. In analysis, set Vgg =-2.6V, introducing 5% Idss ,
A. Current waveform engineering
The generation of output current can be summarized as Vgs 1 =5.6V, 1 =0, and Vt is about -3V for CGH40010. All
follow: under the impact of nonlinear gate-source magnitude value is normalized with Vgs1 . Fig.3 reflects the
capacitance [5], the original incident signal is no longer a
result of numerical analysis.
pure sinusoid wave with harmonics addit ion. Fo r this
reason, a variation o f harmon ic input terminations results 1

in different input voltage at a gate node. And if a constant 1.4

0.9

transconductance assumed, the output current waveform is 0.8

1.2
just similar to the truncated input voltage waveform. Fig.2 0.7

mag(Ids3)/mag(Ids1)
1
illustrates this procedure and the relationship between 0.6
input voltage and output current is given by 0.8
X: 180
Y: 0.4167
0.5
0.6
Vgs 0  Vgs1 cos t  1  
Z: 0.3469
0.4

gm   ,Vgs  t  Vt ;
0.4

I ds (t )    Vgs 2 cos t  1   " 

0.3
0.2
0.2
(1)
  
0

 0 V gs t Vt . 1
0.8 100
200 0.1
0.6 0
0.4 -100
0.2
-200
0

Where Vt denotes the cutoff voltage of transistor. Normalized mag(Vgs2) phase(Vgs2)-phase(Vgs1)

Fig.3. M agnitude ratio of output 3nd harmonic to fundamental

components of Vgs

1
1st
2nd current versus amplitude and phase of input 2 nd harmonic voltage
0
Since the best ratio of third harmonic to fundamental is
-1 1/3 for Class-F-1 current, it can be concluded from Fig.3
Time
that where input second harmonic has nearly a normalized
2 amp litude of 0.7 and a phase difference between -100°
1 and 100° makes an available design space. Plus, Class -F-1
Vgs

0 operation requires fundamental current in phase with third

harmonic current. Hence optimu m operation for input
-1
Time second harmonic needs selected from the aforementioned
2
space. Based on the load-pull simu lation, the second
harmonic termination is decided to fix at 1.4-j*64 Ω
Ids

1
finally. A 6% increase of PAE can be obtained when input
0 second harmonic termination applied, as revealed by Fig.4.
Time
80 1,000

Fig.2. Generation of output current waveform

Magnitude of Input 2nd Harmonic Impedance

79 872

78 745
It is not hard to observe that to obtain a standard
squared Class-F-1  current, the gate-source voltage is 77 616

unnecessarily squared. One only with flattened peak, as

PAE(%)

76 488

shown in Fig.2, can be an alternate waveform because

75 360
sharp trough is intrinsically t runcated by transconductance
behavior. Through simu lation, we find that this kind of 74 232

waveform can be produced just by adding proper second 73 104

harmonic co mponent. This also gives a direct explanation

to why class-F-1 efficiency is very sensitive to the input
72 -24
-200 -150 -100 -50 0 50 100 150 200
Phase of Input 2nd Harmonic Reflection Coefficient
second harmonic, which is described by several papers [9]
[10]. According to the classic Class -F-1 theory [11], the Fig.4. PAE and magnitude of input 2nd harmonic impedance
third harmon ic contributes mostly to the formation of a versus phase of input 2nd harmonic reflection coefficient,
squared waveform. As a consequence, we further exp lore magnitude of input 2nd harmonic reflection coefficient is 0.9
how the input second harmonic affects third harmon ic o f

Authorized licensed use limited to: Indian Institute of Space Science And Technology.2Downloaded on May 15,2024 at 19:07:03 UTC from IEEE Xplore. Restrictions apply.
 B. Voltage waveform engineering strategy leads to the fact that second-order harmonic
impedance only depending on two sections of
Theoretically, an open circu it for output second
harmonic together with a short circu it fo r third can deliver transmission lines (T1, S1), thus simplify ing the post-
a quasi half-sinusoid wave, thus achieving high efficiency. tuning. This topology synthesizes DC bias and matching
In the real design, it is demonstrated that to tune the network. Therefore C match , wh ich gives a short circuit to
second harmonic load is much more crucial for voltage fundamental frequency, is incorporated. The ult imate
waveform engineering. The third harmonic load just needs simu lation shows a peak PA E o f 81.1% at 41.5d Bm P out .
escaping from the “danger zone” as depicted in Fig.5. The simulated drain current and voltage waveform at the
package plane, given by Fig.7, proves Class -F-1 operation.
82 1000
60 1.5

80 796
50 1

Magnitude of Output 3rd Impedance

78 592

Drain Voltage(V)

Drain Current(A)
40 0.5
PAE(%)

76 388
30 0

74 184
20 -0.5

72 -20 10 -1
-200 -150 -100 -50 0 50 100 150 200
0 1 2 3 4 5 6
Phase of Output 3rd Harmonic Reflection Coefficient
Time(sec) -10
x 10

Fig.5. PAE and magnitude of output 3rd harmonic impedance Fig.7. Simulated drain voltage and current waveform at the
versus phase of output 3rd harmonic reflection coefficient, package plane
magnitude of output 3rd harmonic reflection coefficient is 0.9
III. EXPERIMENTAL VALIDATION
Using efficiency-oriented load-pull simu lation, it is easy
to find the optimu m load condit ion: the fundamental, To verify the analysis and simulat ion results, a practical
second and third harmonic load impedance is expected at Class-F-1 was fabricated on 0.508-mm Duriod (  r = 2.22)
15.3+ j*5, 1.3+j* 4.5, 7.5-j*110 respectively. Then, the substrate, as shown in Fig.8. Measurements show that the
remained task is to design a topology to realize the operating frequency for best performance slightly shifts
particular load condition. fro m 3.5 GHz to 3.48 GHz, mainly because of EM effects.
And the DC bias is set up at the same values in simulat ion:
Vdd
I dd =150mA, Vgg =29.5V.
1S
S1(λ/8)

Cmatch
S3

3S
T1 T2 T3
2S
S2(λ/12)

Rout Cout 50ohm

impedance manipulating plane

Fig.6. Proposed output topology

Fig.6 exh ibits the proposed output topology. The Fig.8. Photo of fabricated Class-F-1, dimensions: 89˜58mm2
harmonic -tuned circuit for second-order is designed in
front of third-order for the sake of less insertion loss [12].
Fig.9 gives both simulated and measured results with
And the other reason for this arrangement is to provide
respect to drain efficiency, PA E, Pout and power gain. The
convenience for post-tuning. Considered the tolerance of
maximu m drain efficiency respectively reaches up to
fabrication, post-tuning is probably needed. In post-tuning,
81.1% and 80.9%; PA E equals to 77.2% and 76.7%. The
to focus on the adjustment of second harmonic circuit is
fabricated circuit can deliver 39.4dBm Pout with 13.4d B
one important rule. The “second-harmonic-control-first”

Authorized licensed use limited to: Indian Institute of Space Science And Technology.3Downloaded on May 15,2024 at 19:07:03 UTC from IEEE Xplore. Restrictions apply.
 gain, co mpared to the simu lated 39.9dBm Pout with IV. CONCLUSION
12.9d B gain. In Fig.10, utilizing a 2.5M Hz modulat ion-
This paper expects an enhancement of Class -F-1
bandwidth signal with a PA R of 8.9dB, linearity and
efficiency by proper input harmonic manipulation. In
efficiency of the PA are evaluated. The measured ACPR is
order to achieve it, the input second harmonic effect is
lower than -27 dBc and over 50% d rain efficiency is
stressed and analyzed using the numeric approach. Based
achieved. In Table I, the performance co mparison is given
on the practical device simu lation, a fu lly design of 3.5 -
between recently reported PAs with waveform
GHz Class-F-1 is carried out. The fulfilled PA delivers a
engineering and this work.
peak PA E of 76.7% at Pout of 39.9d Bm, wh ich shows a
41 100
good agreement with simu lation results.
38 90

35 80
Output Power(dBm)&Power Gain(dB)

A CKNOWLEDGEMENT

PAE(%)&Drain Efficiency(%)
32 70

29 simulated DE
simulated PAE
measured PAE
60 This work is supported by the National Natural Science
measured DE
26 50 Foundation of China under Grant 61001032/F010501 and
23
simulated Pout
simulated Gain 40 General Research Foundation for .ey Universit ies under
20
measured Pout
30 Grant ZYGX2010Z005.
measured Gain
17 20

14 10 REFERENCES
11 0
13 16 19 22 25 28 [1] F. You, S. B. He, X. Tang, and X. Deng, “High-efficiency
Input Power(dBm)
single-ended class-E/F power amplifier with finite dc feed
inductor,” IEEE Trans. Microw. Theory & Tech., vol.
Fig.9. Simulated and measured drain efficiency, PAE, output
MTT-58, pp. 32–40, Jan. 2010.
power and power gain versus input power [2] A. Grebennikov, “High efficiency class E/F lumped and
transmission-Line power amplifiers”, IEEE Trans. Microw.
56 -14
Theory & Tech, 2011 (online version).
50 Drain Efficiency -18 [3] J. M oon, “Investigation of a Class-J power amplifier with a
44
PAE
-22
nonlinear Cou t for optimized operation”, IEEE Trans.
Higher ACPR Microw. Theory & Tech., Vol.58, pp.2800-2811, 2011.
PAE(%)&Drain Efficiency(%)

Lower ACPR
38 -26 [4] K. kuroda, “Parasitic compensation design technique for a C
band GaN HEM T class-F amplifier,” IEEE Trans. Microw.
ACPR(dBc)

32 -30
Theory & Tech., Vol.58, pp.2741-2750,Oct.2010.
26 -34 [5] S.C.Cripps, RF Power Amplifiers for Wireless
20 -38 Communications, Norwood, M A: ArtechHouse, 2006.
[6] A. Inoue, and A. Ohta. M atsuda,“The efficiency of class-F
14 -42
and inverse class-F amplifiers,“ IEEE MTT-S Int.
8 -46 Microwave Symp., pp. 1947–1950, Dig., June 2004.
[7] Y. Woo, “Efficiency comparison between highly efficient
2 -50
24 25 26 27 28 29 30 31 32 33 34 35 36 class-F and inverse class-F power amplifiers,” IEEE,
Output Power(dBm)
Microw. Magazine,vol.8, pp.100-110,June 2007.
Fig.10. M easured ACPR and efficiency versus output power [8] P. Wright, et al., “Highly efficient operation modes in GaN
power transistors delivering upwards of 81% efficiency and
12W output power,” 2008 MTT-S Int. Symp Dig.,pp.1147-
TABLE I 1150,Jun 2008.
PERFORMANCE COMPARISON AMONG RECENTLY [9] D.Wu, “10W GaN inverse class-F PA with input/output
REPORTED W AVEFORM ENGINEERED PA S harmonic termination for high efficiency WiM AX
transmitter,” IEEE 10th Wireless and Microwave
Technology Conference, pp.1-4, April 2009.
Ref F/GHz Pout/W DE*/% PAE/% Class Year [10] S. Goto, et al, “Effect of bias condition and input harmonic
termination on high efficiency inverse class-F amplifiers,”
[2] 2.14 20 73.7 70 E/F 2011 IEEE 31s t European Microwave Conf., vol. 3, pp. 113–116,
[3] 2.14 11.5 79.5 77.3 J 2011 Sept. 2001.
[11] A. Grebennikov, RF and Microwave Power Amplifier
[4] 5.7 2.2 79.9 71.4 F 2010 Design M cGraw-Hill,2004.
[12] M . Helaoui, “Optimizing losses in distributed
[9] 2.5 12.7 76.5 73.3 Inv F 2009 multiharmonic matching networks applied to the design of
This 3.48 9.77 81.1 76.7 Inv F 2011 an RF GaN power amplifier with higher than 80% power-
added efficiency,” IEEE Trans. MTT, Vol.57,pp.314-
Work
322,Jan.2009.
*DE: Drain Efficiency

Authorized licensed use limited to: Indian Institute of Space Science And Technology.4Downloaded on May 15,2024 at 19:07:03 UTC from IEEE Xplore. Restrictions apply.