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Vlsi Lab Report

The document describes simulations of various digital CMOS circuits using Ngspice and Magic layout tool. It includes the design and analysis of an inverter, NAND, NOR, transmission gate, pass transistor logic gates and a D flip-flop with reset using Ngspice transient analysis plots and Magic layout diagrams.

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Sathvick Batchu
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59 views26 pages

Vlsi Lab Report

The document describes simulations of various digital CMOS circuits using Ngspice and Magic layout tool. It includes the design and analysis of an inverter, NAND, NOR, transmission gate, pass transistor logic gates and a D flip-flop with reset using Ngspice transient analysis plots and Magic layout diagrams.

Uploaded by

Sathvick Batchu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Batchu Sathvick

19BEC009 .

VLSI Lab Report


(1) CMOS Inverter

1.1 Aim
In this experiment, we analyzing the CMOS inverter circuit using ng spice and designing the layout of the
CMOS inverter using magic.

1.2 Stick diagram

1.3 Magic layout


1.4 Magic-Spice

1.5 (a) NGSpice code


.title Inverter(ngspice)
.include techfile130.txt
vdd vdd 0 1.2
* Inputs to transistors
vin vi 0 PULSE(0 1.2 2NS 2NS 2NS 100NS 200NS)
******************MOSFETs drain gate source body
Mp vout vi vdd vdd pmos l=120n w=240n
Mn vout vi 0 0 nmos l=120n w=120n
Cload vout 0 200f
.dc vin 0 1.2 0.1
//.tran 0.1n 500n 0 0.1n
.control
run
plot v(vi) v(vout)
.endc
.end
(b) Transient analysis code
.title Inverter(ngspice)
.include techfile130.txt
vdd vdd 0 1.2
* Inputs to transistors
vin vi 0 PULSE(0 1.2 2NS 2NS 2NS 100NS 200NS)
******************MOSFETs drain gate source body
Mp vout vi vdd vdd pmos l=120n w=240n
Mn vout vi 0 0 nmos l=120n w=120n
Cload vout 0 200f
//.dc vin 0 1.2 0.1
.tran 0.1n 500n 0 0.1n
.control
run
plot v(vi) v(vout)
.endc
.end
1.6 NGSpice plot

(a) Dc Analysis

(b) Transieant Analysis


(2) 2-Input Static CMOS NAND

2.1 Aim
In this experiment, we try to implement the static CMOS 2 input NAND circuit using ngspice and design
the layout of SCMOS 2 input NAND using magic.

2.2 Stick diagram

2.3 Magic layout


2.4 Magic-Spice

2.5 NGSpice code


.title 2 input NAND ckt
.include techfile130.txt
*****************MOs d g s b
MP1 Y A Vdd Vdd pmos w=390n l=130n
MP2 Y B Vdd vdd pmos w=390n l=130n
Mn1 Y A n1 0 nmos w=390n l=130n
Mn2 n1 B 0 0 nmos w=390n l=130n
CL Y 0 0.5p
Vdd Vdd 0 1.2
VA A 0 PULSE (0 1.2 0 1n 1n 100n 200n)
VB B 0 PULSE (0 1.2 0 1n 1n 198n 400n)
.tran 0.1n 500n 0 0.1n
.control
run
plot V(Y) V(A) V(B)
.endc
.end
2.6 NGSpice plot
(3) 3-Input Static CMOS NAND
3.1 Aim
In this experiment, we try to implement the static CMOS 3 input NAND circuit using ngspice and design
the layout of SCMOS 3 input NAND using magic.

3.2 Stick diagram

3.3 Magic layout


3.4 Magic-Spice

3.5 NGSpice code


.title 3 input NAND ckt
.include techfile130.txt
*****************MOs d g s b
MP1 Y A Vdd Vdd pmos w=390n l=130n
MP2 Y B Vdd vdd pmos w=390n l=130n
MP3 Y C Vdd vdd pmos w=390n l=130n
Mn1 Y A n1 0 nmos w=390n l=130n
Mn2 Y B n2 0 nmos w=390n l=130n
Mn3 Y C 0 0 nmos w=390n l=130n
CL Y 0 0.5p
Vdd Vdd 0 1.2
VA A 0 PULSE (0 1.2 0 1n 1n 100n 200n)
VB B 0 PULSE (0 1.2 0 1n 1n 198n 400n)
VC C 0 PULSE (0 1.2 0 1n 1n 400n 800n)
.tran 0.1n 900n 0 0.1n
.control
run
plot V(Y) V(A) V(B) V(C)
.endc
.end
3.6 NGSpice plot
(4) 2-Input Static CMOS NOR
4.1 Aim
In this experiment, we try to implement the static CMOS 2 input NOR circuit using ngspice and design
the layout of SCMOS 2 input NOR using magic.

4.2 Stick diagram

4.3 Magic layout


4.4 Magic-Spice

4.5 NGSpice code


.title 2 input NOR ckt
.include techfile130.txt
MP1 n1 A Vdd Vdd pmos w=520n l=130n
MP2 Y B n1 Vdd pmos w=520n l=130n
Mn1 Y A 0 0 nmos w=130n l=130n
Mn2 Y B 0 0 nmos w=130n l=130n
CL Y 0 50f
Vdd Vdd 0 1.2
VA A 0 PULSE (0 1.2 0 1n 1n 100n 200n)
VB B 0 PULSE (0 1.2 0 1n 1n 200n 400n)
.tran 0.1n 500n 0 0.1n
.control
run
plot V(Y) V(A) V(B)
.endc
4.6 NGSpice plot
(5) 3-Input Static CMOS NOR
5.1 Aim
In this experiment, we try to implement the static CMOS 3 input NOR circuit using ngspice and design
the layout of SCMOS 3 input NOR using magic.

5.2 Stick diagram

5.3 Magic layout


5.4 Magic-Spice

5.5 NGSpice code


.title 3 input NOR ckt
.include techfile130.txt
**********mos d g s b
MP1 n1 A Vdd Vdd pmos w=200n l=130n
MP2 n2 B n1 Vdd pmos w=260n l=130n
MP3 Y C n2 Vdd pmos w=260n l=130n
Mn1 Y A 0 0 nmos w=130n l=130n
Mn2 Y B 0 0 nmos w=130n l=130n
Mn3 Y c 0 0 nmos w=130n l=130n
*CL Y 0 1p
Vdd Vdd 0 1.2
VA A 0 PULSE (0 1.2 0 1n 1n 100n 200n)
VB B 0 PULSE (0 1.2 0 1n 1n 200n 400n)
VC C 0 PULSE (0 1.2 0 1n 1n 400n 800n)
.tran 0.1n 900n 0 0.1n
.control
run
plot V(Y) V(A) V(B) V(C)
.endc
5.6 NGSpice plot
(6) Transmission Gate
6.1 Aim
In this experiment, we try to implement the transmission gate circuit using ngspice and design the layout
of transmission gate using magic.

6.2 Stick diagram

6.3 Magic layout


6.4 Magic-Spice

6.5 NGSpice code


.title transmissiongate
.include techfile130.txt
Vdd vdd 0 1.2
vA A 0 PULSE (0 1.2 0 1n 1n 100n 200n)
Mp1 Y 0 A Vdd pmos l=130n w=260n
Mn1 Y Vdd A 0 nmos l=130n w=130n
CL Y 0 100f
.tran 0.1n 500n
.control
run
plot v(Y) v(A)
.endc
.end

6.6 NGSpice plot


(7) Pass Transistor AND
7.1 Aim
In this experiment, we try to implement the pass transistor AND circuit using ngspice and design the
layout of pass transistor AND using magic.

7.2 Stick diagram

7.3 Magic layout


7.4 Magic-Spice

7.5 NGSpice code


.title passtransistorAND
.include techfile130.txt
vdd vdd 0 1.2
* Inputs to transistors
vA A 0 PULSE(0 1.2 0NS 1NS 1NS 100NS 200NS) //(vi vf td tr tf tw T)
vB B 0 PULSE(0 1.2 0NS 1NS 1NS 200NS 400NS)
******************MOSFETs drain gate source body
Mp Bbar B vdd vdd pmos l=130n w=520n
Mn Bbar B 0 0 nmos l=130n w=260n
Mn1 Y B A 0 nmos l=130n w=260n
Mn2 Y Bbar B 0 nmos l=130n w=260n
C1 Y 0 1p
.tran 0.1NS 500NS
.control
run
plot v(Y) v(A) v(B)
.endc
.end
7.6 NGSpice plot
(8) Pass Transistor OR
8.1 Aim
In this experiment, we try to implement the pass transistor OR circuit using ngspice and design the layout
of pass transistor OR using magic.

8.2 Stick diagram

8.3 Magic layout


8.4 Magic-Spice

8.5 NGSpice code


.title passtransistorOR
.include techfile130.txt
vdd vdd 0 1.2
* Inputs to transistors
vA A 0 PULSE(0 1.2 0NS 1NS 1NS 100NS 200NS) //(vi vf td tr tf tw T)
vB B 0 PULSE(0 1.2 0NS 1NS 1NS 200NS 400NS)
******************MOSFETs drain gate source body
Mp Bbar B vdd vdd pmos l=130n w=520n
Mn Bbar B 0 0 nmos l=130n w=260n
Mn1 Y Bbar A 0 nmos l=130n w=260n
Mn2 Y B vdd 0 nmos l=130n w=260n
C1 Y 0 1p
.tran 0.1NS 500NS
.control
run
plot v(Y) v(A) v(B)
.endc
.end
8.6 NGSpice plot
(9) D-Flipflop with reset
9.1 Aim
In this experiment, we try to implement the D-flipflop with reset circuit using ngspice and design the
layout of D-flipflop with reset using magic.

9.2 Stick diagram

9.3 Magic layout


9.4 Magic-Spice

9.5 NGSpice code


.title DFF
.include techfile130.txt
.include Invert.lib
.include 2Nor.lib
.include Trans.lib
Vdd Vdd 0 1.2
Vd D 0 PULSE(0 1.2 10NS 1NS 1NS 50NS 100NS)
Vclk clk PULSE(0 1.2 0NS 1NS 1NS 50NS 100NS)
Vr R 0 PULSE(0 1.2 0NS 1NS 1NS 10NS 100NS)
X5 clk clk_bar Vdd Inv
X1 D clk n1 Vdd Trans
X2 n1 n2 Vdd Inv
X3 n2 n3 Vdd Inv
X4 n3 clk_bar n1 Vdd Trans
X6 n2 R Q Vdd 2Nor
C1 Y 0 1p
.tran 0.1NS 500NS
.control
run
plot v(Y) v(D) v(R) v(clk)
.endc
.end

9.6 NGSpice plot


(10) Footed dynamic NAND

10.1 Aim
In this experiment, we are analyzing the footed dynamic nand using ngspice.

10.2 NGSpice code


.title footedDynamicNand
.include techfile130.txt
vdd vdd 0 1.2
va A 0 PULSE (0 1.2 0 1n 1n 10n 20n)
vb B 0 PULSE (0 1.2 0 1n 1n 20n 40n)
vc C 0 PULSE (0 1.2 0 1n 1n 40n 80n)
vd Clk 0 PULSE (0 1.2 0 1n 1n 10n 20n)
Mp1 Y Clk Vdd Vdd pmos w=130n l=130n
Mn1 Y A n1 0 nmos w=260n l=130n
Mn2 n1 B n2 0 nmos w=260n l=130n
Mn3 n2 C n3 0 nmos w=260n l=130n
Mn4 n3 Clk 0 0 nmos w=260n l=130n
CL Y 0 1p
.tran 0.1n 300n
.control
run
plot v(Y) v(A) v(B) v(C)
.endc
.end

10.3 NGSpice plot

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