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DLD Assignment 4

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29 views

DLD Assignment 4

Uploaded by

INAM FAZAL
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Spring 2024

Instructor: Dr. Ghufran Shafiq

EEE 241 – Digital Logic Design

Assignment # 04
CLO4

Due Date: 30/05/2024

Total Marks: 50

Department of ECE, COMSATS University Islamabad


EEE 241 – Digital Logic Design
Assignment 4

Question1 (25 Marks)

Design a sequential circuit with two JK flip-flops 𝐴 and 𝐵 and two inputs 𝐸 and 𝐹. If 𝐸 =
0, the circuit remains in the same state regardless of the value of 𝐹. When 𝐸 = 1 and
𝐹 = 1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back to
00, and repeats. When 𝐸 = 1 and 𝐹 = 0, the circuit goes through the state transitions
from 00 to 11, to 10, to 01, back to 00, and repeats.

Question2 (15 Marks)

Using JK flip‐flops,
a) Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6.
b) Draw the logic diagram of the counter design in part (a).

Question3 (10 Marks)

Design the same counter as designed in question 2 by 4-bit binary counter. Use block
diagram of a 4-bit binary counter and required additional logic gates. Draw the logic
diagram only.

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