SEMESTER: WINTER, SESSION: 2022-2023

Examination & Semester: 2nd Semester M.Tech. + JRF + B.Tech. ECE[DEJ, Mid-Semester

Time: 2 Hours Max Marks: 60

Subject: MOS Device Physics and Modelling (ECD569)
Instructions: Answer all the questions.
(The right side numbers are representing the marks of the corresponding question.)
1.
Consider an n-type semiconductor at temperature T=300 Kwith doping concentration
Na=1015 cm and intrinsic carrier concentration n= 1.5x1010 cm-, in non-equilibrium 10
the excess carrier concentration is öp=10!3 cm3, Calculate the quasi-Fermi energy
levels. Sketch the energy band diagram for the equilibrium and non-equilibrium
conditions. Mark all the calculated levels clearly.
2.
In ap-type semiconductor at T=300 K, the Fermi level Er lies 0.08 eV above the
valence band.
(a) lf the temperature is increased to 350 K, then find the new position of the Fermi 5
level. Show the corresponding energy band diagram for both the temperatures.
(b) If thedoping concentration of the acceptor atoms is doubled at T-300 K, then
find the position of the Fermi level. Show the corresponding energy band
diagrams.
3. (a) Obtain the expression for the thermal-equilibrium concentration of electrons in the
conduction band and holes in the valence band for a non-degenerate semiconductor. 10
Perform both the derivations with all the steps. [Use : o Vxexp'-*) dx =]
(b) Findout the relation of intrinsic Fermi level with Ee and Ey by mentioning all the
steps. Using this, obtain the equation for the concentration of electrons in terms of 10
intrinsic carrier concentration. Show all the steps clearly.

4. Consider a semiconductor that is non-uniformly doped with donor impurity atoms

ND(x). Show that the induced electric field E(x) in the semiconductor in thermal
equilibrium is given by:
1 dNp (*)
E(x) = - Np (x) dx

5 The total current in asemiconductor is constant and is composed of electron drift

current and hole diffusion current. The electron concentration is constant and equal to 15
101 cm3, The hole concentration in terms of distance x' is given by:
p(*) = 1015 exp(-*/)cm-3
Where L= 12 um. The hole diffusion coefficient is D,=12 cm²/s and the electron
mobility is ui=1000 cm²/Vs. The total current density is J=4.8 Alcm². Sketch (a) the
hole diffusion current density versus (b) the electron current density versus x and
(c) the electric field versus x. Clearly mark the x intercept and y intercept.
(Take x = Abscissa. And Current Density/Electric field = Ordinate)
 SEMESTER: WINTER, SESSION: 2022-23
Examination & Semester: 2nd Semester M.Tech, + JRF + B.Tech., ECE DEJ
Max Marks: 100
Time: 3 Hours Subject: MOS Device Physics and Modelling (ECD569)
Instructions: Answer allthe questions from Group Aand any two from GroUp D.
(The right side numbers are representing the marks of the corresponding question.)
Use the following values: k= 1.38x10-25 J/K and E= 8.854 X10 F/m
Group A 10
1. (a) Starting from Poisson's equation, find out the expression for the depletion charge densty oa
two-terminal MOS structure with p-substrate having a uniform concentration of N, cm. Each steP
must be shown clearly. Show the corresponding band diagram.

(b) Schematically show the variation of the induced charge density (Qs) with surface potential (0s)
Tor a two-terminal MOS structure. Mark all the regions of MOS operation clearly. The diagram snould
be self-explanatory.
2
(a) lf the Fermi potential is 0.4 V and thethermal yoltage is 0.025 Vat T=300 K, display the output
characteristicsof the MOSFET showingvarious inversion modes (weak strong). Mark the starting
points of the different modes of operation.

(b)Atthe onset of inversion, the depletion width stops increasing eventually. Justify this using an 5
appropriate diagram. Also, mention the relation of maximum depletion width with surface potential.
(C) Consider a MOS structure at T=300 K, with a p-type semiconductor. The doping concentration in 5
the semiconductor is 1016 cm and the intrinsic carrier concentration is 1.5 x 1010 cm3. The
maximum depletion width at a certain gate voltage is 440nm. Find therelative permittivity of the
semiconductor.

3
(a) The n+ Source (S) and Drain (D) each have an area of 200 × 200 um'. The substrate doping is 10
10cm-3 and the S/D doping is 1020 cm-3.The measured zero bias depletion cápacitance is 100
aF/um for the inner side wall, 150 aF/um for the outer side wall, and 200 aF/um for the bottom
wall. The grading coefficient is 0.33 andthe intrinsic carrier concentration is nË= 1.5x 1010 cmn-3
at 300 K. The depth of the S/D junction is 1 pm and the applied bias Vás is 0.8 V. Find the total
junction capacitance of the MOS if the curved surface area for both side walls is equal.

(b) Application of a potential difference between the source and drain allows the transportation of 5
charge carriers (electrons). Show this with the help of suitable energy band diagrams.
4. (a) For the n-type semiconductor with doping concentration 2 x 101 cm-a, the band gap of 1.12 eV 3
and electron affinity of 4.05 eV at 300K, find the work function of the senmiconductor if the intrinsic
carrier concentration is 1.5 x 10" cm.Sketch the energy band diagram of the semiconductor.
Mark all the necessary points and values.
(b) Show the large signal model of MOSFET.

(c) Suppose there is a MOS structure with an Al gate and a Si substrate doped with NA= 1016 cm-3 7
The structure uses the HfO:-SiO2 combination as an insulator. The relative permittivity ofHfO2 and
Sio: is 25 and 3.9 respectively. The thickness of HfO2 and Sio:is 64.1 nm and 40 nm respectively.
Assuming the oxide as asingle layer,draw the energy band diagram ofthe given structure under zero
bias if the intrinsic carrier concentration is nj= 1010 cm- at T=300 K, the work function of Al is
4.1eV and the electron affinity of the semiconductor is 4.05 ev. Calculate the flat band voltage /fthe
interface trapped charges are 10 electronic charges/cm. The band gap of Si is 1.12 eV.
 END SEMESTFD

Group B condition. Ine0

structure shown below under the flat band
(4Qoalnthe energy band diagram of the
OXIde layers (thickness at both sides
is tox) voltage heWeen the metal and the substrate are Si02. AISO,So
the band bending if positive with respect to the p-substrate is applied at Vg.
Vg
TOPGATE
-Metal
SIO,

Si (p-type)

-Metal
BOTTOM GATE

substrate for all the regions O

(b) Sketch the energy band diagrams of the MOS structure with an n-type regions: the
of operation (i.e. Accumulation, depletion, and inversion). State the following for all the
the surface potential, and the induced charge in the substrate. Give a brief
applied gate voltage,
description of each region.
poly-silicon gate. The oxide thickness 20
6. A two-terminal MOS structure has a p-type substrate and n+ trapped
The interface
is 500 and the silicon substrate has a doping concentration of 10gm-3,
charge is 10 electronic charges/cm. Calculate the capacitance of the given MOS structure (in
Mention all necessary steps with
Flcm?) if zero voltage is applied the gate at room temperature. Consider the band gap of silicon to be
justification for the mode of operation of the MOS structure.
carrier concentration to be 1.4 x 10m$, Eoy= 3.9 and E_i= 11.7.
1.12 eV, the intrinsic conduction
Assume that the Fermi level of the poly-silicon gate is approximately coinciding with the
band. [The expressions for Cs and Xd. are as fol!ows]
EEst |1+
2(Vgb - Vfb) Cox? -1|
Xa = EoEs1 qNb
Cox
EEsi sinh(U;)- sinh(U, - U)
VZLa [cosh(U,- U) +U,sinh(U;)-cos(U;)]2
geometry
Table 1 lists the different parameters for a 4-terminal n-channel enhancement-type short
20

linear region, with W=20 um and L =1 um. Calculate the current Ids (in
MOSFET. biased inthe electrors as
for surface mobility of
mA) at Vas = 1V, Vgs =4 V, and Vsb =0V. [Take the expression
s = uo/[l+0(Vgs -Vth + 2y(2r+ Vsb))].Use the relation s(y)= 2¢r +Veb(y) + 6V; for evaluating
the average surface potential (i.e. at the middle of the channel) at the onset of strong inversion for
Vsby41
utilizationin computing the maximum depletion width (Xám). Also §-0.5/(2¢r +
Table 1

Parameter Value Parameter Value

2x 1016 cm-3 Vsat 8 x 106 cm/s
Nb
0.2 um 8,854 × 10-14 F/cm
200 ¢ 3.9
tox
0.04 V-1 &Si 11.7
670 cmN.sec ni 1.4 x 1010 cm-3
Vth 0.35 V
 END WINTER SEMESTER EXAMINATION 2022-2023

Examination & Semester: M. Tech, Electronics and Communication Engineering,

2nd Semester

Date: 09/05/2023 Subject: Analog IC Design (ECD560) Max Marks: 100

Time:3-6 PM

Instructions: Answer all the questions

(The right side numbers indicate marks, Consider parameter values of the Long-channel model in Table 1for all the
calcuiations.)
neat (6+4)
1 a) Explain the operation of a supply independent self-biased reference circuit with
diagram and derive the expression of reference current? What the startup problem in
self-biased reference circuit and how is it mitigated?
b) What is Bandgap Reference (BGR) voltage? Why is it called BGR Voltage? Explain the (2T27o)
circuit implementation of a PVT insensitive Bandgap current reference circuit?
10
2 a) The Differential pair in Fig. 1 has mismatches in load resistances and transconductance
of input transistors. Find the expression for the differential offset voltage in terms of
mismatch parameters. Assume input transistors are operating in saturation.
b) Fig. 2 shows a matched differential amplifier with diode connected loads. Using the
simplified small signal models (i.e. representing Mi to M4 by transconductance models 10
CMRR.
and Ms by itsoutput resistance, Ios)., verify the following and also find
Differential gain, |ApMgmi/gmsl
Common mode gain, |AcM1/2gm3Iosl
amplifier with a suitable circuit (6+3+8)
3. a) Explain the operation of aFolded Cascode differential DC voltage
diagram. Draw the small signal model and find Rout (output impedance),
zeroes?
gain, output voltage swing and location of poles and
differential amplifier over 3
b) What are the merits and demerits of Folded Cascode
Telescopic Cascode differential amplifier?
20
4 Design a Miller compensated, two-stage Operational amplifier using the model
channel length as 1 um, load
parameters shown in Table 1. Assume minimum
supply voltage of 5 V. Determine W, L for all devices and
capacitance of 10 pF and
following specifications:
the value of compensation capacitor (Ce) for the
Open loop gain > 60 dB
Gain Bandwidth Product > 10 MHz
Phase Margin > 600
Static power dissipation <5 mW
Slew rate > 25 V/us
VDD=5V, Vss-0V
ICMR: 1.5 V to 4.5 V
4.5 V
Qutput voltage swing: 0.5 V to
(2+6+2)
expression of total output thermal noise in a PMOS
5 a) What is KT/C noise? Derive the
capacitance, CL?
driving a load
current source load common source amplifier
 What is 1/f noise corner frequency?
method to
error in switched capacitor circuits? Explain a (2+2+6)
0) What is charge injection operation of a stray insensitive inverting integrator with the
Initngate the error? Explain the
help of a neat circuit diagram?
VoD
VoD
M; M,
Ri1 RL2
ld2
Vout

Vin2 M M,
Vini

Lo V1

Figure 1 ir Figure 2

Table 1: Typical parameters for analog design using the long-channel CMOS process

Parameter Parameter Description Typical Parameter Value Units

Symbol n-Channel P-Channel
VTI Threshold voltage 0.7 -0.7
(VBs =0V)
K Transconductance 110 50 uA/V?
parameter (in saturation)
Bulk threshold 0.4 0.57 yl2
parameter
Ciarnel length 0 04 (L=1 um) 0.05 (L=l um)
modulation parameter i01 (L2 um) 0.01 (L=2 um)
Surface potential at 0.7 0.8
2 or|
strong inversion

Vssg
 SEMESTER: WINTER, SESSION: 2022-2023
Examination & Semester: End Semester Exam- 2nd Sem
Subject: CAD for VLSI Subject Code: ECD505
Time: 3 Hours
MaxMarks:100

Instructions: Answer all the questions

The right-hand side numbering indicates the marks allotted for each
question.
Q. I Answer the following briefly and to the point.
(a) () How does a hardware description language like 3 +2
Verilog differ from an ordinary
programnming language?
(ii) What is the hardware
obtained
if the following code is synthesized?
module reg3
input
input
A;
CLK;
(Ql,Q2,Q3,A,CLK) ;
output Q1,Q2,Q3;
reg
Q1,02,Q3:
al ways
begin @(posedge CLK)
Q3 Q2; // statement 1
Q2 a Q1; // statement 2
Q1 = A; Statement 3
end

endmodule
(b) Write a Verilog code for the following circuit. Assume that 2+3
negligible. the gate delays are
() Using concurrent statement
(ii) Using an always block with sequential
statement

(c) An M-N flip-flop responds to the falling clock edge as follows: 3+ 2

If M=N=0, the flip flop changes state.
If M=0 and N=1, the flip-flop output is set to I.
If M=l and N=0, the flip-flop output is set to 0.
If M-Nl, no change of the flip-flop state occurs.
The flip-flop is cleared asynchronously if CLR=0
(i) Write a complete Verilog module that implements an M-N flip-flop.
(ii) What are the advantages of using a hardware description language as compared
with schematic capture in thedesign process?

(d) Construct a simplified structure of a CLB. With the help of only one CLB implement a 2+3
4-input AND gate.
 1+4
(e) Consider the following Verilog code:
module Q3(A,B,C,F,C1k,¬);
input A,B,C,F.Clk;
output reg E;
reg D,G:
initial
begin
E = 'b0:
D 1' b0;
G= 1'bo;
end

always Q(posedge C1k)

begin
D <= A & B & C;
G <= ~A & ~B;
E < D | G | F:
end
endmodule
() Draw a block diagram for the circuit (no gates and a block level only)
(i) Give the circuit generated by the preceding code (at the gate level). 2+8
Q. 2. What do understand by the term programming technology in FPGA? Explain in detail
the general programming methods adopte: in FPGAs.
Q. 3. () Design a full subtractor and write down its Verilog description using dataflow 5+5
modeling.
(ii) What is the difference between aCPLD and an FPGA? In which application should
a designer use CPLD rather than an FPGA?

Q.4. (i) Write a Verilog user-defined primitive for generating odd parity for a 4-bit input data. 5 +5
(ii) Write a Verilog user-defined primitive for a2:1 MUX using (?).
Q.5. (i) Write a Verilog description of an SR latch using an always block. 3+7
(ii) Write down the Verilog code for an 8-bit Up-Down counter and draw its hardware
model.
Q.6. () Withthe helg of an exaple explan the "Forever loop in Verilog. 5+5
(ii) What do you mean by Verilog race condition?
Q.7. (i) Write down a Verilog code for afalling edge triggered Dflip-flop with asynchronous 2+8
active high clear and set.
(i)Given
Reg [7:0] C;
Reg signed [7:0] D;
Reg signed [7:0] A= 8'hD5;
Evaluate (a) C=A>>4 (b) C=A>>>4 (c) C=A<<4 (d) C=A<<<4 (e) D=A>4
() D=A>>4 (g) D-A<<4 (h) D=A<<<4
Q.8. (i) Implement a Verilog code for the synchronous D flip-flop with reset and set. 5+6+4
(ii) A DD flip-flop is like D flip-flop. except that the flip-flop can change state (Q=D)
on both rising and falling edge of the clock input. The flip-flop has a direct reset input R
and R=0 resets the flip-flop to Q=0 independent of clock. Similarly, it has direct set
input, S, that sets the flip flop to I independent of the clock. Write a Verilog description
of a DD flip-flop. FPGAs?
(iii) What are the disadvantages and advantages of anti-fuse