Sheet (1,2)
Sheet (1,2)
sheet 2
1. Program-visible registers are registers that can be
directly accessed and manipulated by the program running
on the processor.
2. The 80286 addresses registers that are 8 and 16 bits
wide.
3. The extended registers are addressable by 32-bit
microprocessors such as the Intel 386 and later.
4. The extended BX register is addressed as EBX in 32-bit
mode.
5. The CX register (Counter register) holds a count for
some instructions.
6. The purpose of the IP/EIP register is to hold the
instruction pointer, which points to the memory address
of the next instruction to be executed.
7. The carry flag bit is not modified by logical
operations like NOT, AND, OR, and XOR.
8. No overflow will occur if a signed FFH (−1) is added
to a signed 01H (1).
9. A number that contains 3 one bits is said to have odd
parity.
10. The IF (Interrupt Flag) controls the INTR pin on the
microprocessor.
11. Microprocessors such as the Intel 80386 and later
contain an FS segment register.
12. In real mode operation of the microprocessor, segment
registers are used to calculate physical addresses by
multiplying the segment value by 16 and adding the offset
value.
13. In real mode, the starting and ending addresses of
each segment located by the segment register values are
as follows:
(a) 1000H: Starting Address = 10000H, Ending Address =
10FFFH
(b) 1234H: Starting Address = 12340H, Ending Address =
1243FH
(c) 2300H: Starting Address = 23000H, Ending Address =
23FFFH
(d) E000H: Starting Address = E0000H, Ending Address =
EFFFFH
(e) ABOOH: Starting Address = A0000H, Ending Address =
ABFFFH
14. The memory address of the next instruction executed
by the microprocessor, when operated in real mode, for
the given CS:IP combinations are as follows:
(a) CS = 1000H, IP = 2000H: Next Instruction Address =
12000H
(b) CS = 2000H, IP = 1000H: Next Instruction Address =
21000H
(c) CS = 2300H, IP = 1A00H: Next Instruction Address =
24A00H
(d) CS = 1A00H, IP = B000H: Next Instruction Address =
25000H
(e) CS = 3456H, IP = ABCDH: Next Instruction Address =
3AFCCH
15. Real mode memory addresses allow access to memory
below the 1 MB memory address.
16. The SI (Source Index) and DI (Destination Index)
registers are used as offset addresses for the string
instruction destination in the microprocessor.
17. In the Pentium 4 microprocessor, the 32-bit register
ESI (Extended Source Index) is used to hold an offset
address for data segment data.
18. The stack memory is addressed by a combination of the
SS (Stack Segment) register plus the SP (Stack Pointer)
offset.
19. If the base pointer (BP) addresses memory, the stack
segment (SS) contains the data.
20. The memory location addressed by the following real
mode 80286 register combinations are:
(a) DS = 1000H, DI = 2000H: Memory Address = 12000H
(b) DS = 2000H, SI = 1002H: Memory Address = 21002H
(c) SS = 2300H, BP = 3200H: Memory Address = 55200H
(d) DS = A000H, BX = 1000H: Memory Address = A1000H
(e) SS = 2900H, SP = 3A00H: Memory Address = 5D00H
21. The memory location addressed by the following real
mode Core2 register combinations are:
(a) DS = 2000H, EAX = 00003000H: Memory Address =
20000H
(b) DS = 1A00H, ECX = 00002000H: Memory Address =
1C000H
(c) DS = C000H, ESI = 0000A000H: Memory Address =
D0000H
(d) SS = 8000H, ESP = 00009000H: Memory Address =
89000H
(e) DS = 1239H, EDX = 0000A900H: Memory Address =
1239A900H