CAD for VLSI

Debdeep Mukhopadhyay
IIT Madras
 Tentative Syllabus
– Overall perspective of VLSI Design
– MOS switch and CMOS, MOS based logic design, the
CMOS logic styles, Pass Transistors
– Introduction to Verilog HDL
– Combinational logic Design: Simplification of
switching functions, K-map based reductions of
switching circuits, complex designs using
multiplexers/demultiplexers, decoders
– PLAs and their use in standard combinational logic
design.
 Tentative Syllabus
– Memory elements: flip-flops, latches, registers.
– Sequential logic Design: Concepts and state
diagrams.
– VLSI Design Issues:
• Timing in Digital Circuits
• Power Issues
• and Parasitics
– Data Path Design: Realizations of Computational
blocks, like adders, multipliers, CORDIC
 Laboratory Work
• This is an Engineering Course. So, we
shall have assignments and lab works
integrated with this course. Please be
sincere about them.
• Assignments shall encompass:
– Verilog Coding
– Developing knowledge of Standard CAD flow
• ASIC Flow
• FPGA Flow
The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
ENIAC - The first electronic computer
(1946)
The Transistor Revolution

First transistor
Bell Labs, 1948
The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966
Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation
Intel Pentium (IV) microprocessor
 Computer-Aided Design
• 1967: Fairchild develops the
“Micromosaic” IC using CAD

• 1968: Noyce, Moore leave Fairchild, start

Intel
 Moore’s Law

zIn 1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.
zHe made a prediction that
semiconductor technology will double its
effectiveness every 18 months
 LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1959
1960
1961
1962

Electronics, April 19, 1965.

1963
1964
1965
1966
1967
1968
1969
1970
1971
Moore’s Law

1972
1973
1974
1975
Evolution in Complexity
 Transistor Counts
1 Billion
K
Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

Courtesy, Intel
 Evolution of Micro-electronics
Year 1947-> 1950-> 1961-> 1966-> 1971-> 1980-> 1990-> 2000->

No of 1 1 10 100- 1000- 20,000- 1 M- >10M

trans 1000 20,000 1M 10M
Per
chip
Typical - Junction Planar Count 8 bit 16 bit Special
product Transist Devices, ers, uP, uP, proces
or Logic mux, ROM, DRAM sors,
gates, adders RAM virtual
FFs reality
m/cs
Techno Transi- Discrete SSI MSI LSI VLSI ULSI GSI
logy stor Compon
ents
Moore’s law in Microprocessors
1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Courtesy, Intel
 Die Size Growth
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year

Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel
 Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel
 Power Dissipation
100
P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

Courtesy, Intel
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

Courtesy, Intel
 Power density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

Courtesy, Intel
 Not Only Microprocessors
Cell
Phone

Small Power
Signal RF RF

Digital Cellular Market

(Phones Shipped) Power
Management

1996 1997 1998 1999 2000

Analog
Units 48M 86M 162M 260M 435M Baseband

Digital Baseband
(DSP + MCU)

(data from Texas Instruments)

 Challenges in Digital Design

∝ DSM ∝ 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • etc.
• Clock distribution.

Everything Looks a Little Different …and There’s a Lot of Them!

?
24
 Productivity Trends
Logic Transistor per Chip (M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000

(K) Trans./Staff - Mo.

Tr./Staff Month.
100 1,000
Complexity

100,000 1,000,000

Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100

0.001
1 0.01
10
1981
1983
1985
1987

1991
1993

1997
1999
2001
2003

2007
1989

1995

2005

2009
Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

 Why Scaling?
• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
• Cost of a function decreases by 2x
• But …
– How to design chips with more and more functions?
– Design engineering population does not double every
two years…
• Hence, a need for more efficient design methods
– Exploit different levels of abstraction
Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
 But Reality is complex!
• Advancement of technology requires
designing and implementing module
libraries.
• Require to understand critical paths of
design to evaluate its performance.
• Library based design is fine for Application
specific designs. But not so for high
performance designs: Full custom…
 But Reality is complex!
• Interconnect parasitics: capacitances,
resistances and inductances.
• Clock distribution and power supply
distribution.
• Power constraint as a design issue.
• Murphy's law : "Whatever can go wrong,
will go wrong“. So, troubleshooting has to
be learnt.
 Examples
• Clocks Defy Hierarchy
– Why do we require clocks?
– Clock Skews.
– Effect of clock skews on a hierarchically designed
system
• Power dissipation networks defy hierarchy:
– planning a power distribution requires estimation of
loading, direction of current, information about total
peak power drawn from the supply etc…
– have to defy the boundaries of hierarchical design,
plan dedicated area for the power network.
 Design Metrics
• How to evaluate performance of a
digital circuit (gate, block, …)?
– Cost
– Reliability
– Scalability
– Speed (delay, operating frequency)
– Power dissipation
– Energy to perform a function
 Cost of Integrated Circuits
• NRE (non-recurrent engineering) costs
– cost of work done by ASIC vendor, mask generation
– $10,000-$3,00,000 (Mask cost: $5000-$50,000)
– production test cost
• Recurrent costs
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area
NRE Cost is Increasing
 Die Cost

Single die

Wafer

Going up to 12” (30cm)

From http://www.amd.com
 Cost per Transistor

cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
 Yield
No. of good chips per wafer
Y= × 100%
Total number of chips per wafer
Wafer cost
Die cost =
Dies per wafer × Die yield
π × (wafer diameter/2)2 π × wafer diameter
Dies per wafer = −
die area 2 × die area
 Defects

−α
⎛ defects per unit area × die area ⎞
die yield = ⎜1 + ⎟
⎝ α ⎠
α is approximately 3

die cost = f (die area)4