Comparison of FPGA based implementation for DES and AES,

two cryptographic algorithms

Pooja Singh, Student

Rajkumar Goel Institute of Technology for Women

Delhi- Meerut Road, 5th km Stone, Ghaziabad, U.P., INDIA

E-mail: [email protected]

Chetna Aggarwal, Student

Rajkumar Goel Institute of Technology for Women

Delhi- Meerut Road, 5th km Stone, Ghaziabad, U.P., INDIA

E-mail: [email protected]

Reshu Gupta, HOD

Rajkumar Goel Institute of Technology for Women

Delhi- Meerut Road, 5th km Stone, Ghaziabad, U.P., INDIA

E-mail: [email protected]

Kunal Lala, Lecturer

Rajkumar Goel Institute of Technology for Women

Delhi- Meerut Road, 5th km Stone, Ghaziabad, U.P., INDIA

E-mail: [email protected]

ABSTRACT

With the rapid development of various multimedia technologies, more and more multimedia data are
generated and transmitted in the medical, also the internet allows for wide distribution of digital
media data. It becomes much easier to edit, modify and duplicate digital information .This paper
reviews the comparison between the most common and used cryptographic algorithms in the data
encryption field. The two main characteristics that identify and differentiate one encryption algorithm
from another are its ability to secure the protected data against attacks and its speed and efficiency in
doing so.
Keywords: DES (Data encryption standard), AES (Advanced encryption standard), cryptography,
FPGA (Field programmable gate array)

1. Introduction

In 1997, the National Institute of Standards and Technology (NIST) initiated a process to select a
symmetric key encryption algorithm to be used to protect sensitive information in furtherance of
NIST’s statutory responsibilities. In 1998, NIST announced the acceptance of fifteen candidate
algorithms and requested the assistance of the cryptographic research community in analyzing the
candidates. This analysis included an initial examination of the security and efficiency characteristics
for each algorithm. NIST reviewed the results of this preliminary research and selected MARS, RC6,
Rijndael, Serpent and Twofish as finalists. On October 2000 and having reviewed further public
analysis of the finalists, NIST decided to propose Rijndael as the Advanced Encryption Standard
(AES). Rijndael, designed by Joan Daemen (Proton World International Inc.) and Vincent Rijmen
(Katholieke Univeriteit Leuven) of Belgium, is a block cipher with a simple and elegant structure.
The Advanced Encryption Standard (AES), also known as the Rijndael algorithm, is asymmetric
block cipher that can encrypt data blocks of 128 bits using symmetric keys of 128, 192 or 256 bits.
AES was introduced to replace the DES algorithm used for a good amount of time universally.
Though, if security were the only consideration, then DES would be an appropriate choice for a
standardized encryption algorithm for decades to come. The main drawback was its slow software
implementation. For reasons of both efficiency and security, a larger block size is desirable. Due to its
high level security, speed, ease of implementation and flexibility, Rijndael was chosen for AES
standard in the year 2001.

2. DES Algorithm

The DES algorithm is a private-key encryption algorithm, which was developed by IBM and has been
a federal standard since 1977. Presently replaced by the Advanced Encryption Standard (AES)
algorithm, but still used widely in the public domain and provides a basis for comparison for new
algorithms. A 16-stage pipelined DES Algorithm hardware implementation is outlined in this paper. It
allows16 data blocks to be processed simultaneously resulting in an impressive gain in speed. It also
supports the use of different keys every clock cycle, thus improving overall security since users are
not restricted to using the same key during any one session of data transfer. The design is
implemented on Xilinx Spartan FPGA technology. Implementing cryptographic algorithms on
reconfigurable hardware provides major benefits over VLSI (very large scale integrated circuits) and
software platforms since they offer high speed similar to VLSI and high flexibility similar to
software. VLSI implementations are fast but must be designed all the way from behavioural
description to the physical layout. They have to follow an expensive and time consuming fabrication
process. Software implementations offer high flexibility but they are not fast enough for the
applications where time factor is vital. On the other hand, reconfigurable devices are attractive since
the time and costs of VLSI design and fabrication can be reduced. Moreover, they offer high potential
for reprogramming and experimenting on multiple architectures or several revisions of the same
architecture.
2.1 DES ALGORITHM DESCRIPTION

Figure 1 : DES Algorithm

It is a block cipher operating on 64- bits blocks of plaintext utilizing a 64-bits key. Every bit of the
64-bits key is used for parity checking and otherwise ignored. After an initial permutation, the 64-bits
input is split into a right and left half, each 32 bits in length. DES has 16 iterations or rounds. In each
round a function f is performed in which the data is combined with a 48-bits permutation of the key.
After the 16th iteration, the right and left halves are concatenated and a final permutation, which is the
inverse of the initial permutation, completes the algorithm.

2.2 CIPHER FUNCTION

The function f of the DES algorithm is made up of four operations. Firstly, the 32-bits right half of the
plaintext is expanded to 48-bits and then XORed with a 48-bits sub-key K1. The result is fed into
eight substitution boxes (s-boxes), which transform the 48-bits input to a 32-bits output. Finally, a
straight permutation (P-permutation) is performed, the output of which is XORed with the initial left
half, to obtain the new right half R. The original right half becomes the new left half L.
 Figure 2 : Cipher Function

2.3 PIPELINING THE DES ALGORITHM

Pipelining is wildly use method in large design for speed enhancement. The iterative nature of the
DES algorithm makes it ideally suited to pipelining and that can be 4, 6, 8 or 16 stages. The DES
algorithm implementation presented in this paper is based on the ECB mode with 16 stages
pipelining. Although the ECB mode is less secure than other modes of operation, it is commonly used
and its operation can be pipelined.

Figure 3 : DES Pipeline Architecture

3. AES Algorithm

Advanced Encryption Standard (AES) is a specification for the encryption of electronic data. It has
been adopted by the U.S. government and is now used worldwide. It supersedes DES. The algorithm
described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting
and decrypting the data. In the United States, AES was announced by National Institute of Standards
and Technology (NIST) as U.S. FIPS PUB 197 (FIPS 197) on November 26, 2001 after a five-year
standardization process in which fifteen competing designs were presented and evaluated before it
was selected as the most suitable . It became effective as a Federal government standard on May 26,
2002 after approval by the Secretary of Commerce. It is available in many different encryption
packages. AES is the first publicly accessible and open cipher approved by the National Security
Agency (NSA) for top secret information. Originally called Rijndael, the cipher was developed by
two Belgian cryptographers, Joan Daemen and Vincent Rijmen, and submitted by them to the AES
selection process. The name Rijndael is a play on the names of the two inventors.

Figure 4 : AES Algorithm

3.1 DESCRIPTION OF ALGORITHM

a. Key Expansion—round keys are derived from the cipher key using Rijndael's key schedule
b. Initial Round
1. AddRoundKey—each byte of the state is combined with the round key using bitwise
xor
c. Rounds
 1. SubBytes—a non-linear substitution step where each byte is replaced with another
according to a lookup table.
2. ShiftRows—a transposition step where each row of the state is shifted cyclically a
certain number of steps.
3. MixColumns—a mixing operation which operates on the columns of the state,
combining the four bytes in each column.
4. AddRoundKey
d. Final Round (no MixColumns)
1. SubBytes
2. ShiftRows
3. AddRoundKey

FIPS 197 gives the complete mathematical explanation of the AES Algorithm . In this section we only
explain the Mix columns phase, because this is the critical part of the algorithm. Mix columns
transformation operates on the State column-by-column , relating each column as a four-term
polynomial. The columns are considered as polynomials over GF(28) and multiplied modulo x4+1 by
a fixed polynomial a(x).
a(x) = {03}x3 + {01}x2 + {01}x + {02}

In the MixColumns step, each column of the state is multiplied with a fixed polynomial c(x).

In the MixColumns step, the four bytes of each column of the state are combined using an
invertible linear transformation. The MixColumns function takes four bytes as input and outputs four
bytes, where each input byte affects all four output bytes. Together
with ShiftRows, MixColumns provides diffusion in the cipher.
During this operation, each column is multiplied by the known matrix that for the 128 bit key is
3.2 PIPELINING THE AES ALGORITHM

Besides the inner pipelining we use an operation pipelining. This pipelining is done among all
simple operations like (adders or XORs) of all the phases of the AES algorithm. The pipelining
done is very fine grain pipelining which reduces the clock frequency a lot. This fact causes that
we have a high latency, but if we are speaking about encrypting a great number of blocks, the
benefit achieved by the high clock frequency clearly overcomes the disadvantage of the latency.
In AES algorithm all the operations of a phase are done at same time, actually it is a phase level
pipelining.

Figure 5: The phase level pipelining of AES Algorithm

4. DES performance and AES performance comparison with FPGA

Advance Encryption Standard (AES) and DES are commonly used block ciphers. Whether you
choose AES or DES depend on your needs. In this section it would like to highlight their differences
in terms of security and performance (Seleborg, 2004). DES was developed in 1977 and it was
carefully designed to work better in hardware than software. DES performs lots of bit manipulation in
substitution and permutation boxes in each of 16 rounds. For example, switching bit 30 with 16 is
much simpler in hardware than software. DES encrypts data in 64 bit block size and uses effectively a
56 bit key. 56 bit key space amounts to approximately 72 quadrillion possibilities. Even though it
seems large but according to today’s computing power it is not sufficient and vulnerable to brute
force attack. Therefore, DES could not keep up with advancement in technology and it is no longer
appropriate for security. The Rijndael algorithm has been selected as the Advance Encryption
Standard (AES) to replace DES. AES is modified version of Rijndael algorithm. Advance Encryption
Standard.
• Security

• Software & Hardware performance

• Suitability in restricted-space environments

• Resistance to power analysis and other implementation attacks.

Rijndael was submitted by Joan Daemen and Vincent Rijmen. When considered together Rijndael’s
combination of security, performance, efficiency, implementability, and flexibility made it an
appropriate selection for the AES. By design AES is faster in software and works efficiently in
hardware. It works fast even on small devices such as smart phones; smart cards etc.AES provides
more security due to larger block size and longer keys.AES uses 128 bit fixed block size and works
with 128, 192 and 256 bit keys. Rigndael algorithm in general is flexible enough to work with key and
block size of any multiple of 32 bit with minimum of128 bits and maximum of 256 bits.AES is
replacement for DES according to NIST both ciphers will coexist until the year2030 allowing for
gradual transition to AES. Even though AES has theoretical advantage over DES for speed and
efficiency in some hardware implementation DES may be faster where support for DES is mature.

Table 1

Comparative results of DES Algorithm

DEVICE NUMBEROF FREQUENCY THROUGHPUT

SLICES
XC4020E 438 10MHz 26.7Mbit/s
Alpha 8400 --- 300 MHz 127 Mbit/s
XC4028EX 741 25.18 MHz 402.7 Mbit/s
XCV400 5263 47.7 MHz 3052 Mbit/s
XCV1000 6446 59.5 MHz 3808 Mbit/s
ASIC --- --- 9280 Mbit/s
XCV150 1584 168 MHz 10752 Mbit/s
XC3S500E 2814 111.882 MHz 7160 Mbit/s

Table 2
Comparative results of AES algorithm
DEVICE NUMBEROF FREQUENCY THROUGHPUT
SLICES
XC2VP70 -7 5408 232.6MHz 29.77Gbit/s
XCV1000e -8 11022 168.4MHz 21.56Gbit/s
XC2VP20 -7 9446 169.1MHz 21.64Gbit/s
XC2VP2 - 7 12450 168.3MHz 21.54Gbit/s
XC2V3000 -6 139357 222.2MHz 28.4Gbit/s

5. Conclusion

In this paper a new comparative study between DES, and AES were presented in to three factors,
which are number of slices, frequency, throughput, these eligible’s proved the AES is better than
DES. In general, hardware implementations of encryption algorithms and their associated keys are
physically secure, as they cannot easily be modified by an outside attacker. At a clock frequency of
111.882 MHz, the 16-stage pipelined design can encrypt or decrypt data blocks at a rate of 7.16
Gbit/sec and should prove very useful in applications where speed is vital as with real-time
communications such as satellite communications and electronic financial transactions etc.
In our proposed sequential AES design with both encryption and decryption, the operational
frequency can reach 75.3MHz and the throughput can be up to 0.876Gbits/s. In our full pipelined
AES design at the encryption mode, the operational frequency can process 222.2MHz and the
throughput can be up to 28.4Gbits/s. The implementation of the AES algorithm based on FPGA
devices has the advantages like potential for fast, low-cost multiple reprogramming and experimental
testing of a large number of various architectures and revised versions of the same architecture.
Higher accuracy of comparison in the absence of the physical design and fabrication.

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