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Assignment 2

The document provides instructions for an assignment involving Verilog code for a D flip flop, writing gate level Verilog code for a given circuit, inserting stuck at faults in the circuit code, and finding test vectors to identify the faults using sensitization-propagation-justification method.

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Charan Eswar
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19 views3 pages

Assignment 2

The document provides instructions for an assignment involving Verilog code for a D flip flop, writing gate level Verilog code for a given circuit, inserting stuck at faults in the circuit code, and finding test vectors to identify the faults using sensitization-propagation-justification method.

Uploaded by

Charan Eswar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 02

To be submitted as a PDF
1. A Verilog code for D Flip Flop and its Test bench is given below:-
module dff (clk, reset,
d, q, qb);
input clk;
input reset;
input d;
output q;
output qb;
reg q;
assign qb = ~q;
always @(posedge clk or posedge reset)
begin
if (reset) begin
// Asynchronous reset when reset goes high
q <= 1'b0;
end else begin
// Assign D to Q on positive clock edge
q <= d;
end
end
endmodule

module test;
reg clk;
reg reset;
reg d;
wire q;
wire qb;
// Instantiate design under test
dff DFF(.clk(clk), .reset(reset),
.d(d), .q(q), .qb(qb));
initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);

$display("Reset flop.");
clk = 0;
reset = 1;
d = 1'bx;
display;

$display("Release reset.");
d = 1;
reset = 0;
display;

$display("Toggle clk.");
clk = 1;
display;
end

task display;
#1 $display("d:%0h, q:%0h, qb:%0h",
d, q, qb);
endtask
endmodule
Task1:
Write a gate level Verilog code for the circuit show below:-
(Write the code in the assignment document)

Task2:

Insert a stuck at fault in the circuit by modifying the code :


(Write the modified code in the assignment document highlighting the inserted fault
in red colour font)

Student ID ending with Fault


0 Sa0 at F1
1 Sa0 at F2
2 Sa0 at D
3 Sa1 at F1
4 Sa1 at F2
5 Sa1 at D
6 Sa0 A
7 Sa0 B
8 Sa1 A
9 Sa1 B

Task 3:
Find the test vectors required to identify these faults using sensitization-propagation-
justification method, and verify it by running the simulation with identified test
vectors on the fault induced code.
(Paste a snap of the code and result)

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